Semiconductor device structure, method of making the same, and semiconductor device array

Abstract

The application provides a semiconductor device structure, a preparation method thereof and a semiconductor device array, and relates to the technical field of semiconductor packaging. The semiconductor device structure comprises a substrate, a double-layer device layer, a back re-wiring layer and a bonding pad, the substrate is configured as a ground, and a conductive silicon column penetrating through the back surface is arranged on the front surface of the substrate; the front surface of the substrate is further provided with a movable groove. The double-layer device layer comprises a first device layer, a second device layer and a micro-motion structure, the first device layer is arranged on the front surface of the substrate, the second device layer is located on the side of the first device layer away from the substrate, and the micro-motion structure is arranged in the double-layer device layer and located above the movable groove. The back re-wiring layer is arranged on the back surface of the substrate, and the bonding pad is arranged on the surface of the second device layer away from the substrate. Compared with the prior art, the embodiment of the application can meet the demand of high-density wiring, reduce the packaging reliability hidden danger, avoid the thermal stress damage caused by packaging, and guarantee the device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically, to a semiconductor device structure, a method for fabricating the same, and a semiconductor device array. Background Technology

[0002] Microelectromechanical systems (MEMS) micromirror technology plays a central role in modern fiber optic communication networks. By precisely controlling the deflection of micromirrors, beam attenuation, switching, and modulation can be achieved, leading to their widespread application in key devices such as optical switches, optical attenuators, and tunable optical filters. In particular, two-dimensional micromirror arrays are crucial components in building optical switches (OCS) for data center networks. For a long time, the optical communication industry has been committed to developing low-cost, high-port-count optical switch solutions with low switching times. To improve the channel capacity of cross-connect systems, it is necessary to increase the number of mirrors in the MEMS mirror matrix and improve the fill factor. A high fill factor is significant for improving the shape of optical channels and reducing system optical losses.

[0003] Traditional planar wiring schemes have certain spatial limitations. To overcome the density limitations of planar wiring, existing improved solutions typically employ through-silicon via (TSV) technology, vertically introducing the driving electrodes of the micromirrors to the bottom of the chip, and then directly mounting the chip onto a ceramic substrate or PCB board using a flip-chip process. Although this solution solves the wiring density problem, it introduces serious packaging reliability risks and is prone to thermal stress damage. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device structure, its fabrication method, and a semiconductor device array that can meet the requirements of high-density wiring, reduce packaging reliability risks, avoid thermal stress damage caused by packaging, and ensure device performance.

[0005] This invention is achieved through the following technical solution:

[0006] In a first aspect, embodiments of the present invention provide a semiconductor device structure, comprising:

[0007] A substrate has a conductive silicon pillar extending from the front side to the back side, the conductive silicon pillar including at least one first conductive silicon pillar and at least one second conductive silicon pillar, and the front side of the substrate also has a movable groove, the substrate being configured to be grounded;

[0008] A dual-layer device layer includes a first device layer, a second device layer, and a micro-motion structure. The first device layer is disposed on the front side of the substrate, and the second device layer is located on the side of the first device layer away from the substrate. The micro-motion structure is disposed in the dual-layer device layer and located above the movable groove, which is configured as the movable space of the micro-motion structure.

[0009] A back redistribution layer is disposed on the back side of the substrate and is electrically connected to the first conductive silicon pillar and the second conductive silicon pillar;

[0010] Bonding pads are disposed on the surface of the second device layer away from the substrate and are electrically connected to the second device layer;

[0011] The electrical signal received by the bonding pad is transmitted to the back redistribution layer via the first conductive silicon pillar, and then back to the double-layer device layer via the second conductive silicon pillar, thereby forming a U-shaped conductive loop to drive the micro-motion structure.

[0012] In an optional embodiment, the depth of the movable groove is 50-400 μm.

[0013] In an optional embodiment, the dual-layer device layer further includes an insulating layer and an interlayer conductive plug. The insulating layer is disposed at the interface between the first device layer and the second device layer, and the interlayer conductive plug penetrates the insulating layer to electrically connect the first device layer and the second device layer.

[0014] In an optional embodiment, both the first conductive silicon pillar and the second conductive silicon pillar are electrically connected to the first device layer. The first conductive silicon pillar is configured to transmit a signal from the first device layer to the back redistribution layer, and the second conductive silicon pillar is configured to transmit a signal from the back redistribution layer to the first device layer.

[0015] In an optional embodiment, both the first conductive silicon pillar and the second conductive silicon pillar are insulated from the substrate.

[0016] In an optional embodiment, a first filling insulating trench is provided between the first conductive silicon pillar and the substrate, and a second filling insulating trench is provided between the second conductive silicon pillar and the substrate.

[0017] In an optional embodiment, the electrical signal is transmitted from the bonding pad to the second device layer, then via the interlayer conductive plug to the first device layer, then via the first conductive silicon pillar to the back redistribution layer, then via the second conductive silicon pillar back to the first device layer, and then via the interlayer conductive plug to the second device layer, so that the bonding pad, the second device layer, the interlayer conductive plug, the first device layer, the first conductive silicon pillar, the back redistribution layer and the second conductive silicon pillar constitute the U-shaped conductive loop.

[0018] In an optional embodiment, the micro-motion structure includes a mirror and a comb tooth actuator. The comb tooth actuator includes a moving comb tooth and a fixed comb tooth. The moving comb tooth and the mirror are disposed in the first device layer, and the fixed comb tooth is disposed in the second device layer. The moving comb tooth is connected to a ground electrode for grounding, and the fixed comb tooth is connected to a drive electrode for applying a drive voltage.

[0019] In an optional embodiment, one end of the interlayer conductive plug is embedded in the first device layer, and the other end of the interlayer conductive plug is exposed on the side surface of the second device layer away from the first device layer.

[0020] In an optional embodiment, one end of the interlayer conductive plug is embedded in the second device layer, and the other end of the interlayer conductive plug is exposed on the surface of the first device layer away from the second device layer.

[0021] In an optional embodiment, one end of the interlayer conductive plug is exposed on the side surface of the second device layer away from the first device layer, and the other end of the interlayer conductive plug is exposed on the side surface of the first device layer away from the second device layer, and is electrically connected to the conductive silicon pillar.

[0022] In an optional embodiment, the first conductive silicon pillar is in electrical contact with the region corresponding to the driving electrode on the double-layer device layer and is insulated from other regions; the second conductive silicon pillar is in electrical contact with the region corresponding to the pad on the double-layer device layer and is insulated from other regions.

[0023] In an optional embodiment, the front side of the substrate is further provided with a first electrical isolation trench and a second electrical isolation trench, the first electrical isolation trench being disposed around the first conductive silicon pillar and the second electrical isolation trench being disposed around the second conductive silicon pillar.

[0024] In an optional embodiment, the micro-motion structure includes a mirror and a comb tooth actuator. The comb tooth actuator includes a moving comb tooth and a fixed comb tooth. The mirror and the moving comb tooth are disposed in the second device layer, and the fixed comb tooth is disposed in the first device layer. The moving comb tooth is connected to the ground electrode for grounding, and the fixed comb tooth is connected to the drive electrode for applying a drive voltage.

[0025] In an optional embodiment, a first isolation channel is provided on the first device layer, and a second isolation channel is provided on the second device layer. Both the first isolation channel and the second isolation channel surround the interlayer conductive plug, and the first isolation channel and the second isolation channel are connected or staggered.

[0026] Secondly, embodiments of the present invention provide a semiconductor device array, the semiconductor device array comprising an array of several of the aforementioned semiconductor device structures arranged and combined along two orthogonal directions.

[0027] Thirdly, embodiments of the present invention provide a method for fabricating a semiconductor device structure, used to fabricate the aforementioned semiconductor device structure, the method comprising:

[0028] Provide a substrate;

[0029] Conductive silicon pillars and movable grooves are formed on the front side of the substrate;

[0030] A first isolation trench is formed on the front side of a bilayer device wafer having a bilayer device layer, wherein the bilayer device layer includes a first device layer and a second device layer, and the first isolation trench is formed on the front side of the first device layer.

[0031] A dual-device wafer with dual device layers is bonded to the front side of the substrate. The first device layer is bonded to the front side of the substrate and electrically connected to the conductive silicon pillar. The second device layer is located on the side of the first device layer away from the substrate and is electrically connected to the first device layer.

[0032] Thin the back side of the substrate and expose the conductive silicon pillar so that the conductive silicon pillar extends through the back side of the substrate;

[0033] A back redistribution layer is formed on the back side of the substrate, wherein the back redistribution layer is electrically connected to the conductive silicon pillar;

[0034] A bonding pad is formed on the surface of the second device layer away from the substrate, wherein the bonding pad is electrically connected to the second device layer;

[0035] Micro-motion structures are formed in the second device layer and the first device layer, wherein the micro-motion structures correspond to the movable groove.

[0036] In an optional embodiment, the dual-layer device layer further includes an insulating layer disposed between the first device layer and the second device layer, and before the step of forming bonding pads on the surface of the second device layer away from the substrate, the method further includes:

[0037] Thin the side of the bilayer device wafer away from the substrate to expose the second device layer;

[0038] An interlayer conductive plug is formed in the second device layer, wherein one end of the interlayer conductive plug is embedded in the first device layer, and the other end of the interlayer conductive plug is exposed on the side surface of the second device layer away from the first device layer.

[0039] In an optional embodiment, the dual-layer device layer further includes an insulating layer disposed between the first device layer and the second device layer. Before the step of bonding the dual-layer device wafer with the dual-layer device layer to the front side of the substrate, the method further includes:

[0040] An interlayer conductive plug is formed in the first device layer, wherein one end of the interlayer conductive plug is embedded in the second device layer, the other end of the interlayer conductive plug is exposed on the side surface of the first device layer away from the second device layer, and the interlayer conductive plug is configured to be bonded to the conductive silicon pillar.

[0041] In an optional embodiment, the step of forming conductive silicon pillars and movable grooves on the front side of the substrate includes:

[0042] Conductive silicon pillars are formed on the front side of the substrate;

[0043] The front side of the substrate is planarized;

[0044] An electrical isolation trench is formed on the front side of the substrate, wherein the electrical isolation trench is arranged in a ring around the conductive silicon pillar;

[0045] An active groove is formed on the front side of the substrate.

[0046] The beneficial effects of the embodiments of the present invention include:

[0047] This invention provides a semiconductor device structure, its fabrication method, and a semiconductor device array. Conductive silicon pillars penetrating both surfaces are disposed in a substrate, and a movable groove is also provided on the front side of the substrate. A first device layer of a dual-layer device is disposed on the front side of the substrate and electrically connected to the conductive silicon pillars. A second device layer is located on the first device layer and electrically connected to it. A micro-motion structure is disposed between the first and second device layers, corresponding to the movable groove. A back redistribution layer is disposed on the back side of the substrate, electrically connected to the conductive silicon pillars. Bonding pads are disposed on the second device layer and electrically connected to it.

[0048] Compared to existing technologies, this invention abandons the traditional back-side flip-chip packaging structure and uses the front-side bonding pads as the sole external interface. This cuts off the transmission path of thermal mismatch stress to the micro-motion structure, significantly improving the optical flatness and long-term reliability of the micro-motion structure. It reduces packaging reliability risks, avoids thermal stress damage caused by packaging, and ensures device performance. Simultaneously, by employing a double-layer device stack and reusing the back-side space of the substrate, complex signal fan-out networks can be completely transferred from the crowded front side of the device to the back side of the substrate. This not only frees up front-side space to improve the fill factor but also supports complex electrode designs, significantly increasing device port density and thus meeting the requirements of high-density wiring. Furthermore, by using the substrate as a physical barrier, the high-voltage drive signal on the back side is naturally isolated from the sensitive micro-motion structure on the front side. This eliminates signal crosstalk and reduces parasitic capacitance without the need for an additional shielding layer, improving device response speed. Attached Figure Description

[0049] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram of a first semiconductor device structure provided in an embodiment of the present invention;

[0051] Figure 2 This is a three-dimensional schematic diagram of a first semiconductor device structure provided in an embodiment of the present invention;

[0052] Figure 3 for Figure 2 Schematic diagram of the electrical connection between the micro-motion structure and the bonding pads;

[0053] Figure 4 for Figure 2 Top view of the micro-motion structure and bonding pads;

[0054] Figure 5 This is a schematic diagram of a second semiconductor device structure provided in an embodiment of the present invention;

[0055] Figure 6 A schematic diagram of a third semiconductor device structure provided in an embodiment of the present invention;

[0056] Figure 7 This is a schematic diagram of the structure corresponding to step S1 in the method for fabricating a semiconductor device structure provided in an embodiment of the present invention.

[0057] Figure 8 and Figure 9 This is a schematic diagram of the structure corresponding to step S2 in the method for fabricating a semiconductor device structure provided in an embodiment of the present invention.

[0058] Figure 10 A schematic diagram of the structure corresponding to step S3 in the method for fabricating a semiconductor device structure provided in an embodiment of the present invention;

[0059] Figure 11 A schematic diagram of the structure corresponding to step S4 in the method for fabricating a semiconductor device structure provided in an embodiment of the present invention;

[0060] Figure 12 This is a schematic diagram of the structure corresponding to step S5 in the method for fabricating a semiconductor device structure provided in an embodiment of the present invention.

[0061] Figure 13 This is a schematic diagram of the structure corresponding to step S6 in the method for fabricating a semiconductor device structure provided in an embodiment of the present invention.

[0062] Figure 14 This is a schematic diagram of the structure corresponding to step S7 in the method for fabricating a semiconductor device structure provided in an embodiment of the present invention.

[0063] Icons: 100 - Semiconductor device structure; 110 - Substrate; 111 - Conductive silicon pillar; 111a - First conductive silicon pillar; 111b - Second conductive silicon pillar; 112 - Movable groove; 113a - First electrical isolation trench; 113b - Second electrical isolation trench; 114a - First filled insulating trench; 114b - Second filled insulating trench; 120 - Double-layer device layer; 120a - First device layer; 120b - Second device layer; 121 - Insulating layer; 122 - Interlayer conductive plug; 123 - Driving electrode; 124 - Ground electrode; 125 - First isolation channel; 126 - Second isolation channel; 130 - Micro-motion structure; 131 - Mirror; 132 - Moving comb teeth; 133 - Fixed comb teeth; 140 - Backside redistribution layer; 150 - Bonding pad. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0065] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0066] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0067] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0068] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0069] As disclosed in the background section, with the continuous expansion of the micromirror array size, how to achieve high-density signal routing within a limited chip area has become a highly challenging technical bottleneck.

[0070] Traditional planar routing schemes have certain spatial limitations. Specifically, in traditional mirror array structures, electrical interconnects are typically fabricated on the front side of the device layer. These interconnects must pass through the chip surface of the mirror array and be routed through the narrow gaps between the mirrors to the pads at the chip edge. As the array size increases, the number of electrical interconnects increases dramatically, making it extremely difficult to accommodate a massive number of traces within the limited space between the mirrors, especially for the mirror areas near the chip edge. This routing congestion not only limits further improvements in the physical size and fill factor (i.e., the ratio of mirror area to the total array area) of the mirror array, but also encroaches on the space of MEMS actuators, leading to problems such as reduced driving force, increased inter-channel driving interference, and limited tilt range.

[0071] To overcome the density limitations of planar wiring, existing solutions typically employ through-silicon vias (TSVs) to vertically introduce the driving electrodes of the micromirrors onto the bottom of the chip, followed by flip-chip mounting directly onto a ceramic substrate or PCB. While this approach solves the wiring density problem, it introduces serious packaging reliability issues. Specifically, the combination of TSVs and flip-chip packaging introduces mechanical stress and reliability problems. Because the solder balls directly contact the pads on the bottom of the micromirror, and the coefficient of thermal expansion (CTE) of the solder ball materials (Sn, AuSn, etc.) differs significantly from that of the silicon chip, enormous thermomechanical stress is generated during high-temperature processes such as reflow soldering. This stress not only easily leads to solder ball detachment, causing poor soldering or short circuits, but more seriously, it can be transmitted to the fragile MEMS structure, causing the entire micromirror chip to warp or deform. The unevenness of the chip surface directly disrupts the optical consistency of the micromirror array, severely affecting the precise adjustment of the optical path and the quality of signal transmission.

[0072] In addition, conventional TSV packaging structures have a short interlayer insulation distance, which poses a risk of electrical breakdown under high voltage drive. They must rely on a harsh low-pressure inert gas sealing environment to maintain insulation. Even with a shielding layer, the compact vertical structure still faces the risk of signal crosstalk.

[0073] Furthermore, existing technologies have also employed conductive vias to achieve electrical connections between wiring layers in order to address wiring density issues. However, these conductive vias are typically made of dielectric material and lack shielding, resulting in the compact vertical structure still facing the risk of signal crosstalk.

[0074] To address the aforementioned issues, this invention provides a novel semiconductor device structure and its fabrication method, which simultaneously meets the requirements of high-density wiring while effectively avoiding thermal stress damage caused by flip-chip fabrication, thus ensuring the optical flatness and long-term reliability of MEMS micromirrors. It should be noted that, unless otherwise specified, features in the embodiments of this invention can be combined with each other.

[0075] See Figures 1 to 3 This invention provides a semiconductor device structure 100 that can meet the requirements of high-density wiring, reduce packaging reliability risks, avoid thermal stress damage caused by packaging, and ensure device performance. Simultaneously, it can achieve natural electromagnetic shielding, improve signal integrity and device response speed, and reduce signal crosstalk.

[0076] The semiconductor device structure 100 provided in this embodiment of the invention includes a substrate 110, a double-layer device layer 120, a back redistribution layer 140, and bonding pads 150. The substrate 110 is configured to be grounded, and a conductive silicon pillar 111 extending through to the back side is provided on the front side of the substrate 110. The conductive silicon pillar 111 includes at least one first conductive silicon pillar 111a and at least one second conductive silicon pillar 111b, and a movable groove 112 is also provided on the front side of the substrate 110. The dual-layer device layer 120 includes a first device layer 120a, a second device layer 120b, and a micro-motion structure 130. The first device layer 120a is disposed on the front side of the substrate 110 and is electrically connected to conductive silicon pillars 111. The second device layer 120b is located on the side of the first device layer 120a away from the substrate 110 and is electrically connected to the first device layer 120a. The micro-motion structure 130 is disposed in the dual-layer device layer 120 and is located above a movable recess 112, which is configured as the movable space for the micro-motion structure 130. A back redistribution layer 140 is disposed on the back side of the substrate 110 and is electrically connected to the first conductive silicon pillars 111a and the second conductive silicon pillars 111b. A bonding pad 150 is disposed on the surface of the second device layer 120b away from the substrate 110 and is electrically connected to the second device layer 120b for connecting bonding wires.

[0077] The electrical signal received by the bonding pad 150 is transmitted to the back redistribution layer 140 via the first conductive silicon pillar 111a, and then back to the double-layer device layer 120 via the second conductive silicon pillar 111b, thereby forming a U-shaped conductive loop to drive the micro-motion structure 130.

[0078] It should be noted that, in this embodiment of the invention, the distribution position and form of the bonding pads 150 on the surface of the double-layer device layer 120 are not specifically limited. The bonding pads 150 can be concentrated in the edge area of ​​the overall package structure, or they can be respectively set near a single micro-motion structure 130, as long as the micro-motion structure 130 can be avoided.

[0079] This invention abandons the traditional back-side flip-chip packaging structure and uses the front-side bonding pad 150 as the sole external interface, cutting off the transmission path of thermal mismatch stress to the micro-motion structure 130. This significantly improves the optical flatness and long-term reliability of the micro-motion structure 130, reduces packaging reliability risks, avoids thermal stress damage caused by packaging, and ensures device performance. Simultaneously, by using a double-layer device stack 120 and reusing the back-side space of the substrate 110, the complex signal fan-out network can be completely transferred from the crowded front side of the device to the back side of the substrate 110. This not only frees up front-side space to improve the fill factor but also supports complex electrode designs, significantly increasing device port density and thus meeting the requirements of high-density wiring. Furthermore, using the substrate 110 as a physical barrier naturally isolates the high-voltage drive signal on the back side from the sensitive micro-motion structure 130 on the front side. Signal crosstalk and parasitic capacitance can be eliminated without the need for an additional shielding layer, improving device response speed. At the same time, a certain degree of electromagnetic shielding can be achieved between adjacent conductive silicon pillars 111, reducing signal crosstalk problems and allowing for a more compact vertical structure arrangement, which helps to reduce package size.

[0080] It should be noted that the dual-layer device layer 120 provided in this embodiment can be a dual-layer MEMS structure, and its micro-motion structure 130 can be a micromirror structure. Utilizing the grounded semiconductor substrate 110 as a physical barrier naturally isolates the high-voltage drive signal on the back side from the sensitive micro-motion structure 130 on the front side. Signal crosstalk and parasitic capacitance can be eliminated and improved by eliminating the need for an additional thin-film shielding layer, thus enhancing the device response speed.

[0081] In some embodiments, the movable groove 112 serves as the movable space for the micro-motion structure 130, and its depth can be between 50 and 300 μm, for example, it can be any value among 50 μm, 100 μm, and 300 μm, or a value between any two points. It should be noted that if the depth of the movable groove 112 exceeds the upper limit, the substrate strength at the groove will decrease, affecting the overall package structure strength; while if it is less than the lower limit, the movement of the micro-motion structure 130 within it may be restricted. By reasonably setting the depth of the movable groove, sufficient movement space for the micro-motion structure 130 is ensured while maintaining the overall structural strength. Furthermore, the width of the movable groove 112 needs to be adapted to the distribution range of the micro-motion structure 130, and the micro-motion structure 130 can move freely within the movable groove 112 without interference from the sidewalls of the movable groove 112. Preferably, the inner wall of the movable groove 112 can also be coated with an electromagnetic shielding material, which, combined with the grounding of the substrate 110, can further prevent the micro-motion structure 130 from being subjected to signal interference or electromagnetic interference when moving within the movable groove 112.

[0082] In some embodiments, the double-layer device layer 120 further includes an insulating layer 121 and an interlayer conductive plug 122. The insulating layer 121 is disposed at the interface between the first device layer 120a and the second device layer 120b, and the interlayer conductive plug 122 penetrates the insulating layer 121 to electrically connect the first device layer 120a and the second device layer 120b. Specifically, the insulating layer 121 may be a silicon dioxide layer, and the double-layer device layer 120 may be fabricated from a double-layer device insulator-on-silicon (DSOI) wafer. Both the first device layer 120a and the second device layer 120b may be silicon layers. The interlayer conductive plug 122 is a conductive pillar, which may be formed by slotting on the surface of the first device layer 120a or the second device layer 120b, and the interlayer conductive plug 122 may penetrate the insulating layer 121 to electrically connect the first device layer 120a and the second device layer 120b. The interlayer conductive plug 122 can be a polysilicon plug, which is made by deep-hole etching followed by filling with conductive polysilicon material. Using the interlayer conductive plug 122, high-density, short-distance vertical electrical interconnection between the first device layer 120a and the second device layer 120b can be achieved.

[0083] In some embodiments, both the first conductive silicon pillar 111a and the second conductive silicon pillar 111b are electrically connected to the first device layer 120a, and the first conductive silicon pillar 111a is configured to transmit signals to the back redistribution layer 140, while the second conductive silicon pillar 111b is configured to transmit signals to the first device layer 120a. Specifically, both the first conductive silicon pillar 111a and the second conductive silicon pillar 111b utilize through-silicon via (TSV) technology. Through the arrangement of the first conductive silicon pillar 111a and the second conductive silicon pillar 111b, a unique U-shaped loop principle can be achieved. That is, the signal travels from the second device layer 120b on the front side to the first conductive silicon pillar 111a, then to the back redistribution layer 140 on the back side of the substrate 110, then through the second conductive silicon pillar 111b to the first device layer 120a, and finally to the bonding pad 150 on the front side, realizing a complete closed-loop signal transmission topology, which is different from conventional unidirectional transmission technology.

[0084] It should be noted that the first conductive silicon pillar 111a is located below the MEMS chip structure within the double-layer device layer 120, and is responsible for guiding the front signal to the back. The second conductive silicon pillar 111b can be located around the MEMS chip structure or below the bonding pad 150, and is responsible for guiding the signal back to the front.

[0085] In some embodiments, both the first conductive silicon pillar 111a and the second conductive silicon pillar 111b are insulated from the substrate 110. It should be noted that the substrate 110 is grounded here, and the first conductive silicon pillar 111a and the second conductive silicon pillar 111b are insulated from the substrate 110. This ensures that the substrate 110 provides good electromagnetic shielding, avoids leakage current and short circuits, reduces local heat concentration, and better achieves thermal management of the packaged device.

[0086] Furthermore, a first filled insulating trench 114a is provided between the first conductive silicon pillar 111a and the substrate 110, and a second filled insulating trench 114b is provided between the second conductive silicon pillar 111b and the substrate 110. The filled insulating trenches are filled with insulating material. Specifically, the first filled insulating trench 114a and the second filled insulating trench 114b (hereinafter referred to as the filled insulating trenches) can be filled with a silicon dioxide layer. That is, the TSV fabrication adopts a combination of silicon dioxide insulation and silicon pillar conductivity. Moreover, the thermal expansion coefficient of the conductive silicon pillar matches that of the silicon substrate 110, enabling it to withstand the high-temperature annealing process during MEMS manufacturing and reducing the impact of thermal stress. Of course, in other preferred embodiments of the present invention, the filled insulating trenches can also be filled with a polymer layer, and the conductive silicon pillar layer can be replaced with copper pillars. Therefore, the TSV fabrication can also adopt a combination of silicon dioxide insulation and copper conductivity, a combination of polymer insulation and silicon pillar conductivity, or a combination of polymer insulation and copper conductivity. In this embodiment, the substrate 110 can be a semiconductor material, such as a silicon substrate or a glass substrate. The substrate 110 serves as the basic support for the device and has opposing front and back sides. The substrate 110 has a sufficient physical thickness, for example, between 300-700 μm, specifically any value from 300 μm, 500 μm, or 700 μm, or any value between any two points. The substrate 110 is grounded. Therefore, the substrate 110 not only serves as a mechanical support but also acts as a physical barrier, forming a natural electromagnetic shielding layer that naturally isolates the high-voltage drive signal from the back side from the sensitive micro-motion structure 130 on the front side. Signal crosstalk and parasitic capacitance are eliminated without the need for additional thin-film shielding, improving the device response speed. Simultaneously, the substrate 110 contains conductive silicon pillars 111 and movable grooves 112 for the movement of the micro-motion structure 130.

[0087] In some embodiments, the back redistribution layer 140 is disposed on the back side of the substrate 110. The back redistribution layer 140 does not have solder balls or conductive bumps designed for external interconnection, and therefore serves only as a pure signal routing layer. The surface of the back redistribution layer 140 is covered with a passivation protective layer to protect the traces and provide a mechanical bonding interface. Bonding pads 150 are disposed in the edge region of the second device layer 120b, serving as the sole electrical interface between the device and the external package or circuitry. A mature wire bonding process can be used to achieve the electrical connection.

[0088] Furthermore, the electrical signal is transmitted from the bonding pad 150 to the second device layer 120b, then via the interlayer conductive plug 122 to the first device layer 120a, then via the first conductive silicon pillar 111a to the back redistribution layer 140, then via the second conductive silicon pillar 111b back to the first device layer 120a, and then via the interlayer conductive plug 122 to the second device layer 120b, so that the bonding pad 150, the second device layer 120b, the interlayer conductive plug 122, the first device layer 120a, the first conductive silicon pillar 111a, the back redistribution layer 140 and the second conductive silicon pillar 111b form a U-shaped conductive loop.

[0089] See Figures 1 to 4 In some embodiments, the micro-motion structure 130 includes a mirror 131 and a comb tooth actuator. The comb tooth actuator includes a moving comb tooth 132 and a fixed comb tooth 133. The moving comb tooth 132 and the mirror 131 are disposed in the first device layer 120a, and the fixed comb tooth 133 is disposed in the second device layer 120b. The moving comb tooth 132 is connected to the ground electrode 124 and configured to be grounded, while the fixed comb tooth 133 is connected to the drive electrode 123 and configured to apply a drive voltage. Specifically, the micro-motion structure 130 also includes a torsion beam structure, the basic structure and driving principle of which can refer to existing micromirror structures. This structural design allows voltage to be applied only to the fixed comb tooth 133 located in the second device layer 120b, while the moving comb tooth 132 in the first device layer 120a is grounded. The upper electrode pulls the lower comb tooth electrode and the mirror 131 upwards.

[0090] Furthermore, one end of the interlayer conductive plug 122 is embedded in the second device layer 120b, and the other end of the interlayer conductive plug 122 is exposed on the side of the first device layer 120a away from the second device layer 120b. In actual fabrication, the interlayer conductive plug 122 can also be fabricated on the surface of the first device layer 120a in advance, and then the first device layer 120a is bonded to the front side of the substrate 110.

[0091] It is worth noting that the second device layer 120b contains multiple fixed comb teeth 133 located on the upper layer. The fixed comb teeth 133 are isolated from the upper second device layer 120b through the second isolation channel 126. Furthermore, the fixed comb teeth 133 can be divided into four independent electrodes through the separation of the upper isolation trench and the connection of the upper torsion beam, thereby applying a driving signal. This electrode can be the upper layer connection structure, which contains an interlayer conductive plug 122 and is electrically connected to the lower layer connection structure in the first device layer 120a. The first device layer 120a contains a moving comb tooth 132, fixed comb teeth 133 extending to the lower layer, a mirror surface 131, and a lower layer torsion beam. The lower layer connection structure is isolated from the first device layer 120a through the first isolation channel 125. The lower layer connection structure contains an interlayer conductive plug 122, which is electrically connected to the upper layer connection structure and electrically connected to the conductive silicon pillars 111 in the substrate 110 through a bonding interface.

[0092] See Figure 5 In other preferred embodiments of the present invention, one end of the interlayer conductive plug 122 is embedded in the first device layer 120a, and the other end of the interlayer conductive plug 122 is exposed on the surface of the second device layer 120b away from the first device layer 120a. At least a portion of the interlayer conductive plug 122 is electrically connected to bonding pads 150. In actual fabrication, the first device layer 120a can be bonded to the front side of the substrate 110 first, and then the interlayer conductive plug 122 can be fabricated. For details, please refer to the fabrication steps described below.

[0093] Please continue reading Figure 1 and Figure 5 In some embodiments, the first conductive silicon pillar 111a is electrically contacted with the corresponding region of the driving electrode 123 on the double-layer device layer 120 and is insulated from other regions; the second conductive silicon pillar 111b is electrically contacted with the corresponding region of the bonding pad 150 on the double-layer device layer 120 and is insulated from other regions. Both the first conductive silicon pillar 111a and the second conductive silicon pillar 111b are in contact with the first device layer 120a and can correspondingly contact predetermined electrode positions, thereby forming a U-shaped conductive loop and avoiding leakage current and short circuits.

[0094] Furthermore, the front side of the substrate 110 is also provided with a first electrical isolation trench 113a and a second electrical isolation trench 113b. The first electrical isolation trench 113a is arranged around the first conductive silicon pillar 111a, and the second electrical isolation trench 113b is arranged around the second conductive silicon pillar 111b. Specifically, the first electrical isolation trench 113a is located at the top end of the first filled insulating trench 114a, and the second electrical isolation trench 113b is located at the top end of the second filled insulating trench 114b. The electrical isolation trenches enable electrical isolation between the electrical connection points of the conductive silicon pillar 111 and the substrate 110, while preventing short circuits between the first conductive silicon pillar 111a and the second conductive silicon pillar 111b. Of course, in other preferred embodiments of the present invention, insulation of the top end of the conductive silicon pillar 111 can also be achieved by other electrical isolation means, such as adding an insulating material layer, etc., which are not specifically limited here.

[0095] See Figure 6 In other preferred embodiments of the present invention, one end of the interlayer conductive plug 122 is exposed on the surface of the second device layer 120b away from the first device layer 120a, and the other end of the interlayer conductive plug 122 is exposed on the surface of the first device layer 120a away from the second device layer 120b, and is electrically connected to the conductive silicon pillar 111. Specifically, an insulating material is also disposed between the first device layer 120a and the substrate 110. This insulating material is the same as the material of the insulating layer 121 between the first device layer 120a and the second device layer 120b. In actual fabrication, a slot can be cut through the first device layer 120a, the insulating layer 121, and the second device layer 120b, and the insulating material can be passed through as well. Then, the interlayer conductive plug 122 is fabricated. The interlayer conductive plug 122 passes through the first device layer 120a and the second device layer 120b and is directly electrically connected to the conductive silicon pillar 111, thus achieving a good electrical connection effect. Meanwhile, since the interlayer conductive plug 122 is directly electrically connected to the conductive silicon pillar 111, the fabrication of isolation trenches can be eliminated, simplifying the process steps and improving the electrical connection effect. Furthermore, the increased bonding area results in better bonding performance.

[0096] In some embodiments, a first isolation channel 125 is provided on the first device layer 120a, and a second isolation channel 126 is provided on the second device layer 120b. Both the first isolation channel 125 and the second isolation channel 126 surround the interlayer conductive plug 122, and are either connected or staggered to form a conductive electrode. The first isolation channel 125 on the first device layer 120a is also connected to an insulating trench, thereby better achieving electrical connection between the electrode and the conductive silicon pillar 111 and achieving peripheral insulation.

[0097] It should be noted that the embodiments of the present invention construct a unique hierarchical vertical signal transmission path, with the driving signal flowing as follows: comb electrode - first conductive silicon pillar 111a - back redistribution layer 140 - second conductive silicon pillar 111b - bonding pad 150. Specifically, the signal originates first at the comb driver, with a driving voltage applied to the comb electrode located in the second device layer 120b or the first device layer 120a. Then, through the interlayer interconnect section, the signal is transmitted between the first device layer 120a and the second device layer 120b via the interlayer conductive plug 122, and converges to the electrical connection point of the first device layer 120a. Then, through the downlink penetration section, the signal enters the first conductive silicon pillar 111a from the first device layer 120a, vertically penetrating the entire substrate 110 to reach the back side of the substrate 110. After passing through the back routing section, the signal enters the back redistribution layer 140, where complex signal crossing, fan-out, and rearrangement are performed using the vast space on the back side, avoiding the crowded areas of the front MEMS structure. Finally, after passing through the uplink backhaul section, the signal reaches the endpoint and is rearranged to connect to the second conductive silicon pillar 111b. It penetrates vertically upward through the entire substrate 110 and returns to the surface of the second device layer 120b, that is, back to the front side of the chip. Then the signal reaches the bonding pad 150 on the front side and is finally connected to the external package pins through gold or aluminum wires.

[0098] The present invention also provides a semiconductor device array, comprising an array of several of the aforementioned semiconductor device structures arranged in two orthogonal directions.

[0099] This invention also provides a method for fabricating a semiconductor device structure 100. To achieve the aforementioned device structure based on dual-layer stacking and U-shaped vertical interconnects, this invention integrates a wafer-level manufacturing process route for TSVs. The method specifically includes the following steps:

[0100] S1: Provide a substrate 110.

[0101] See also Figure 7 First, a substrate wafer is provided, which can be a double-sided polished substrate 110, such as a single-crystal silicon wafer, as a support layer for the device and a carrier for the conductive silicon pillars 111.

[0102] S2: Conductive silicon pillars 111 and movable grooves 112 are formed on the front side of substrate 110.

[0103] See also Figure 8First, a first conductive silicon pillar 111a and a second conductive silicon pillar 111b can be formed on the front side of the substrate 110. For example, a first filled insulating trench 114a and a second filled insulating trench 114b can be formed on the front side of the substrate 110 using a deep reactive ion etching process. Then, an insulating dielectric material is deposited in the filled insulating trench, thereby forming the conductive silicon pillar 111. It should be noted that at this time, the TSV structure does not completely penetrate the substrate 110.

[0104] Then, the front side of the substrate 110 can be planarized. Specifically, chemical mechanical polishing (CMP) can be used to remove excess filler material from the surface, thereby achieving global planarization of the front side of the substrate 110 and providing a flat interface for subsequent photolithography and bonding processes.

[0105] See also Figure 9 Then, a first electrical isolation trench 113a and a second electrical isolation trench 113b are formed on the front side of the substrate 110, and a movable groove 112 is formed on the front side of the substrate 110. Specifically, photolithography and etching can be performed on the front side of the substrate 110 to form isolation trenches for defining the TSV electrical isolation region and movable groove 112 located below the preset micro-motion structure 130 region. The movable groove 112 is used to provide the mechanical space required for the deflection of the micromirror structure.

[0106] S3: A first isolation trench 125 is formed on the front side of a double-layer device wafer having a double-layer device layer 120.

[0107] See Figure 10 Interlayer conductive plugs 122 and first isolation channels 125 can be formed in advance. The double-layer device layer 120 includes a first device layer 120a, a second device layer 120b, and an insulating layer 121, with the insulating layer 121 located between the first device layer 120a and the second device layer 120b. The first isolation channel 125 can be formed on the front side of the first device layer 120a by an etching process. Furthermore, the first device layer 120a can also be provided with interlayer conductive plugs 122 to achieve electrical connection between the first device layer 120a and the second device layer 120b.

[0108] Specifically, an interlayer conductive plug 122 may be formed in the first device layer 120a, wherein one end of the interlayer conductive plug 122 is embedded in the second device layer 120b, and the other end of the interlayer conductive plug 122 is exposed on the side surface of the first device layer 120a away from the second device layer 120b, and the interlayer conductive plug 122 is configured to be bonded to the conductive silicon pillar 111.

[0109] S4: Bond the double-layer device wafer with double-layer device layer 120 to the front side of substrate 110.

[0110] See also Figure 11The double-layer device layer 120 includes a first device layer 120a and a second device layer 120b. The first device layer 120a is bonded to the front side of the substrate 110 and electrically connected to the conductive silicon pillar 111. The second device layer 120b is located on the side of the first device layer 120a away from the substrate 110 and is electrically connected to the first device layer 120a. Specifically, another double silicon-on-insulator (DSOI) wafer can be provided. This SOI wafer preferably has a double-layer device structure, namely, including a first device layer 120a, an intermediate insulating layer 121, and a second device layer 120b. Then, the surface of the first device layer 120a is etched to form the lower isolation channel. Finally, the first device layer 120a side of the SOI wafer is precisely aligned with the front side of the substrate 110, and a wafer-level bonding process, such as silicon-silicon fused bonding, is used to permanently bond the first device layer 120a and the substrate 110 to form a composite wafer stack structure. At this point, the first device layer 120a in the SOI wafer establishes an electrical connection with the conductive silicon pillar 111 through a bonding interface.

[0111] S5: Thin the back side of the substrate 110 and expose the conductive silicon pillars 111 so that the conductive silicon pillars 111 penetrate to the back side of the substrate 110.

[0112] See also Figure 12 Specifically, the back side of the substrate 110 can be mechanically ground and polished until the bottom of the conductive silicon pillar 111 is exposed, so that the conductive silicon pillar 111 can become a conductive path through the substrate 110. This step achieves physical continuity from the front device layer to the back side.

[0113] Furthermore, after thinning the back side of the substrate 110, the double-layer device wafer can be thinned further using a thinning process to expose the second device layer 120b. Specifically, the handle layer of the SOI wafer can be removed to expose the second device layer 120b.

[0114] Of course, in other preferred embodiments of the present invention, the interlayer conductive plug 122 may not be formed in step S3. After the second device layer 120b is exposed, the interlayer conductive plug 122 may be formed in the second device layer 120b. In this case, one end of the interlayer conductive plug 122 is embedded in the first device layer 120a, and the other end of the interlayer conductive plug 122 is exposed on the side surface of the second device layer 120b away from the first device layer 120a.

[0115] S6: A back redistribution layer 140 is formed on the back side of the substrate 110.

[0116] See also Figure 13The back redistribution layer 140 is electrically connected to the conductive silicon pillars 111. Specifically, a dielectric material and a conductive layer are deposited on the back side of the substrate 110 and photolithographically patterned to form a redistribution layer (RDL). Different electrical connection points of this layer connect the first conductive silicon pillar 111a and the second conductive silicon pillar 111b, enabling spatial routing and rearrangement of signals. The dielectric material can be silicon dioxide or a polymer, and the conductive layer can be a conductive metal (e.g., copper) or conductive polysilicon. The conductive polysilicon can be fabricated by physical deposition or using SOI device layers. The RDL fabrication can be a combination of silicon dioxide insulation and conductive metal wires, a combination of polymer insulation and conductive metal wires, a combination of polymer insulation and conductive polysilicon wires, or a combination of silicon dioxide insulation and conductive polysilicon wires.

[0117] S7: A bonding pad 150 is formed on the surface of the second device layer 120b away from the substrate 110.

[0118] Please see Figure 14 The bonding pad 150 is electrically connected to the second device layer 120b. Specifically, metal can be deposited and patterned in a predetermined area (typically a peripheral area) on the surface of the second device layer 120b to form the bonding pad 150, and a ground pad is formed simultaneously. The bonding pad 150 is electrically connected to the conductive silicon pillar 111 and the back redistribution layer 140 via internal interlayer conductive plugs 122.

[0119] S8: A micro-motion structure 130 is formed in the second device layer 120b and the first device layer 120a.

[0120] Please continue reading Figure 1 The micro-motion structure 130 corresponds to the movable groove 112. Specifically, the second device layer 120b and the first device layer 120a are patterned and etched using processes such as deep reactive ion etching to release the mechanical structure, thereby forming the movable micro-motion structure 130. Simultaneously, a second isolation channel 126 can be formed at the same time as the micro-motion structure 130. The second isolation channel 126 and the first isolation channel 125 can be staggered to form multiple conductive electrodes.

[0121] The method for fabricating the semiconductor device structure 100 provided in this embodiment of the invention has strong process compatibility and controllable yield. Moreover, it only requires a single wafer-level bonding between a single SOI wafer and the substrate 110, avoiding the multiple bonding and thinning processes required for traditional multilayer stacked structures, significantly reducing accumulated alignment errors and manufacturing costs, and greatly improving device yield.

[0122] In summary, this invention provides a semiconductor device structure 100 and its fabrication method. A conductive silicon pillar 111 penetrating both surfaces is disposed in a substrate 110, and a movable groove 112 is also provided on the front side of the substrate 110. A first device layer 120a of the double-layer device layer 120 is disposed on the front side of the substrate 110 and electrically connected to the conductive silicon pillar 111. A second device layer 120b is located on and electrically connected to the first device layer 120a. A micro-motion structure 130 is disposed in both the first and second device layers 120a and corresponds to the movable groove 112. A back redistribution layer 140 is disposed on the back side of the substrate 110, and this back redistribution layer 140 is electrically connected to the conductive silicon pillar 111. A bonding pad 150 is disposed on and electrically connected to the second device layer 120b. Compared to existing technologies, the embodiments of this invention can avoid packaging stress and ensure optical performance. This invention abandons the traditional back-side flip-chip packaging structure, using the front-side bonding pad 150 as the sole external interface, cutting off the transmission path of thermal mismatch stress to the micro-motion structure 130. This significantly improves the optical flatness and long-term reliability of the micro-motion structure 130, reduces packaging reliability risks, avoids thermal stress damage caused by packaging, and ensures device performance. Simultaneously, it overcomes wiring bottlenecks and achieves ultra-high-density integration. Specifically, it uses a double-layer device stack 120 and reuses the back-side space of the substrate 110, allowing complex signal fan-out networks to be completely transferred from the crowded front side of the device to the back side of the substrate 110. This not only frees up front-side space to improve the fill factor but also supports complex electrode designs, significantly increasing device port density and thus meeting the requirements of high-density wiring. Furthermore, this embodiment of the invention can achieve natural electromagnetic shielding, improving signal integrity. It utilizes a substrate 110 several hundred micrometers thick as a physical barrier, naturally isolating the high-voltage drive signal on the back side from the sensitive micro-motion structure 130 on the front side. This eliminates signal crosstalk and reduces parasitic capacitance without the need for an additional shielding layer, thus improving device response speed. Finally, this embodiment of the invention offers strong process compatibility, controllable yield, and requires only a single wafer-level bonding process between a single SOI wafer and the substrate 110. This avoids the multiple bonding and thinning processes required by traditional multilayer stacked structures, significantly reducing accumulated alignment errors and manufacturing costs, and greatly improving device yield.

[0123] Compared to existing technologies, this invention abandons the traditional back-side flip-chip packaging structure and uses the front-side bonding pad 150 as the sole external interface. This cuts off the transmission path of thermal mismatch stress to the micro-motion structure 130, significantly improving the optical flatness and long-term reliability of the micro-motion structure 130. It reduces potential packaging reliability issues, avoids thermal stress damage caused by packaging, and ensures device performance. Simultaneously, by using a double-layer device stack 120 and reusing the back-side space of the substrate 110, complex signal fan-out networks can be completely transferred from the crowded front side of the device to the back side of the substrate 110. This not only frees up front-side space to improve the fill factor but also supports complex electrode designs, significantly increasing device port density and thus meeting the requirements of high-density wiring.

[0124] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device structure, characterized in that, include: The substrate (110) has a conductive silicon pillar (111) extending from the front to the back side. The conductive silicon pillar (111) includes at least one first conductive silicon pillar (111a) and at least one second conductive silicon pillar (111b). The front side of the substrate (110) also has a movable groove (112). The substrate (110) is configured to be grounded. A dual-layer device layer (120) includes a first device layer (120a), a second device layer (120b), and a micro-motion structure (130). The first device layer (120a) is disposed on the front side of the substrate (110), and the second device layer (120b) is located on the side of the first device layer (120a) away from the substrate (110). The micro-motion structure (130) is disposed in the dual-layer device layer (120) and located above the movable groove (112). The movable groove (112) is configured as the movable space of the micro-motion structure (130). A back redistribution layer (140) is disposed on the back side of the substrate (110) and electrically connected to the first conductive silicon pillar (111a) and the second conductive silicon pillar (111b); A bonding pad (150) is disposed on the side surface of the second device layer (120b) away from the substrate (110) and is electrically connected to the second device layer (120b); The electrical signal received by the bonding pad (150) is transmitted to the back redistribution layer (140) via the first conductive silicon pillar (111a), and then back to the double-layer device layer (120) via the second conductive silicon pillar (111b), thereby forming a U-shaped conductive loop to drive the micro-motion structure (130).

2. The semiconductor device structure according to claim 1, characterized in that, The depth of the movable groove (112) is 50-400 μm.

3. The semiconductor device structure according to claim 1 or 2, characterized in that, The dual-layer device layer (120) further includes an insulating layer (121) and an interlayer conductive plug (122). The insulating layer (121) is disposed at the interface between the first device layer (120a) and the second device layer (120b). The interlayer conductive plug (122) penetrates the insulating layer (121) to make the first device layer (120a) and the second device layer (120b) electrically connected.

4. The semiconductor device structure according to claim 3, characterized in that, Both the first conductive silicon pillar (111a) and the second conductive silicon pillar (111b) are electrically connected to the first device layer (120a). The first conductive silicon pillar (111a) is configured to transmit a signal from the first device layer (120a) to the back redistribution layer (140), and the second conductive silicon pillar (111b) is configured to transmit a signal from the back redistribution layer (140) to the first device layer (120a).

5. The semiconductor device structure according to claim 3, characterized in that, Both the first conductive silicon pillar (111a) and the second conductive silicon pillar (111b) are insulated from the substrate (110).

6. The semiconductor device structure according to claim 5, characterized in that, A first filled insulating trench (114a) is provided between the first conductive silicon pillar (111a) and the substrate (110), and a second filled insulating trench (114b) is provided between the second conductive silicon pillar (111b) and the substrate (110).

7. The semiconductor device structure according to claim 3, characterized in that, The electrical signal is transmitted from the bonding pad (150) to the second device layer (120b), then via the interlayer conductive plug (122) to the first device layer (120a), then via the first conductive silicon pillar (111a) to the back redistribution layer (140), then via the second conductive silicon pillar (111b) back to the first device layer (120a), and then via the interlayer conductive plug (122) to the second device layer (120b), so that the bonding pad (150), the second device layer (120b), the interlayer conductive plug (122), the first device layer (120a), the first conductive silicon pillar (111a), the back redistribution layer (140) and the second conductive silicon pillar (111b) constitute the U-shaped conductive loop.

8. The semiconductor device structure according to claim 3, characterized in that, The micro-motion structure (130) includes a mirror (131) and a comb driver. The comb driver includes a moving comb tooth (132) and a fixed comb tooth (133). The moving comb tooth (132) and the mirror (131) are disposed in the first device layer (120a), and the fixed comb tooth (133) is disposed in the second device layer (120b). The moving comb tooth (132) is connected to the ground electrode (124) for grounding, and the fixed comb tooth (133) is connected to the drive electrode (123) for applying a drive voltage.

9. The semiconductor device structure according to claim 8, characterized in that, One end of the interlayer conductive plug (122) is embedded in the first device layer (120a), and the other end of the interlayer conductive plug (122) is exposed on the side surface of the second device layer (120b) away from the first device layer (120a).

10. The semiconductor device structure according to claim 8, characterized in that, One end of the interlayer conductive plug (122) is embedded in the second device layer (120b), and the other end of the interlayer conductive plug (122) is exposed on the side surface of the first device layer (120a) away from the second device layer (120b).

11. The semiconductor device structure according to claim 8, characterized in that, One end of the interlayer conductive plug (122) is exposed on the side surface of the second device layer (120b) away from the first device layer (120a), and the other end of the interlayer conductive plug (122) is exposed on the side surface of the first device layer (120a) away from the second device layer (120b), and is electrically connected to the conductive silicon pillar (111).

12. The semiconductor device structure according to claim 8, characterized in that, The first conductive silicon pillar (111a) is electrically contacted with the corresponding area of ​​the driving electrode (123) on the double-layer device layer (120) and is insulated from other areas; the second conductive silicon pillar (111b) is electrically contacted with the corresponding area of ​​the bonding pad (150) on the double-layer device layer (120) and is insulated from other areas.

13. The semiconductor device structure according to claim 12, characterized in that, The front side of the substrate (110) is also provided with a first electrical isolation trench (113a) and a second electrical isolation trench (113b), the first electrical isolation trench (113a) being arranged around the first conductive silicon pillar (111a), and the second electrical isolation trench (113b) being arranged around the second conductive silicon pillar (111b).

14. The semiconductor device structure according to claim 3, characterized in that, The micro-motion structure (130) includes a mirror (131) and a comb driver. The comb driver includes a moving comb tooth (132) and a fixed comb tooth (133). The mirror (131) and the moving comb tooth (132) are disposed in the second device layer (120b). The fixed comb tooth (133) is disposed in the first device layer (120a). The moving comb tooth (132) is connected to the ground electrode (124) for grounding. The fixed comb tooth (133) is connected to the driving electrode (123) for applying a driving voltage.

15. The semiconductor device structure according to claim 3, characterized in that, A first isolation channel (125) is provided on the first device layer (120a), and a second isolation channel (126) is provided on the second device layer (120b). The first isolation channel (125) and the second isolation channel (126) are both arranged around the interlayer conductive plug (122), and the first isolation channel (125) and the second isolation channel (126) are connected or staggered.

16. A semiconductor device array, characterized in that, It includes an array of several semiconductor device structures as described in any one of claims 1 to 15 arranged in two orthogonal directions.

17. A method for fabricating a semiconductor device structure, used to fabricate the semiconductor device structure as described in claim 1, characterized in that, The method includes: Provide a substrate (110); Conductive silicon pillars (111) and movable grooves (112) are formed on the front side of the substrate (110). A first isolation trench (125) is formed on the front side of a double-layer device wafer having a double-layer device layer (120), wherein the double-layer device layer (120) includes a first device layer (120a) and a second device layer (120b), and the first isolation trench (125) is formed on the front side of the first device layer (120a); A bilayer device wafer with a bilayer device layer (120) is bonded to the front side of the substrate (110). The first device layer (120a) is bonded to the front side of the substrate (110) and electrically connected to the conductive silicon pillar (111). The second device layer (120b) is located on the side of the first device layer (120a) away from the substrate (110) and is electrically connected to the first device layer (120a). Thin the back side of the substrate (110) and expose the conductive silicon pillar (111) so that the conductive silicon pillar (111) extends through the back side of the substrate (110); A back redistribution layer (140) is formed on the back side of the substrate (110), wherein the back redistribution layer (140) is electrically connected to the conductive silicon pillar (111); A bonding pad (150) is formed on the surface of the second device layer (120b) away from the substrate (110), wherein the bonding pad (150) is electrically connected to the second device layer (120b); A micro-motion structure (130) is formed in the second device layer (120b) and the first device layer (120a), wherein the micro-motion structure (130) corresponds to the movable groove (112).

18. The method for fabricating a semiconductor device structure according to claim 17, wherein the double-layer device layer (120) further comprises an insulating layer (121) disposed between the first device layer (120a) and the second device layer (120b), characterized in that, Prior to the step of forming bonding pads (150) on the surface of the second device layer (120b) away from the substrate (110), the method further includes: Thin the side of the bilayer device wafer away from the substrate (110) to expose the second device layer (120b). An interlayer conductive plug (122) is formed in the second device layer (120b), wherein one end of the interlayer conductive plug (122) is embedded in the first device layer (120a), and the other end of the interlayer conductive plug (122) is exposed on the side surface of the second device layer (120b) away from the first device layer (120a).

19. The method for fabricating a semiconductor device structure according to claim 17, wherein the double-layer device layer (120) further comprises an insulating layer (121) disposed between the first device layer (120a) and the second device layer (120b), characterized in that, Prior to the step of bonding a bilayer device wafer with a bilayer device layer (120) to the front side of the substrate (110), the method further includes: An interlayer conductive plug (122) is formed in the first device layer (120a), wherein one end of the interlayer conductive plug (122) is embedded in the second device layer (120b), the other end of the interlayer conductive plug (122) is exposed on the side surface of the first device layer (120a) away from the second device layer (120b), and the interlayer conductive plug (122) is configured to be bonded to the conductive silicon pillar (111).

20. The method for fabricating a semiconductor device structure according to claim 17, characterized in that, The step of forming conductive silicon pillars (111) and movable grooves (112) on the front side of the substrate (110) includes: Conductive silicon pillars (111) are formed on the front side of the substrate (110). The front side of the substrate (110) is planarized; An electrical isolation trench is formed on the front side of the substrate (110), wherein the electrical isolation trench is arranged in a ring around the conductive silicon pillar (111). An active groove (112) is formed on the front side of the substrate (110).

Images