Test and measurement instrument with built-in advanced data pattern generator

Abstract

A test and measurement instrument with a built-in advanced data pattern generator. A test and measurement instrument includes a display, one or more transmitters, one or more receivers, one or more channels configured to transmit and receive signals, a data pattern generator, and a high speed serial flip-flop (HSST) circuit operating at a speed of 1 gigabit per second or faster, connected to the one or more receivers, a high-speed serial flip-flop circuit is provided to receive a data pattern from a data pattern generator to operate the high-speed serial flip-flop circuit.

Description

[0001] Cross-reference to related applications This disclosure is a non-provisional application filed on November 11, 2024, entitled “TEST AND MEASUREMENT INSTRUMENT WITH BUILT-IN ADVANCED DATA PATTERN GENERATOR”, and claims the benefit thereof, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to test and measurement instruments, and more particularly to test and measurement instruments with built-in advanced data pattern generators, such as oscilloscopes. Background Technology

[0003] Arbitrary waveform generators (AWGs) are a type of test and measurement instrument that provides signals for testing a device under test (DUT). Typically, users also utilize these AWGs in addition to the measurement types of test and measurement instruments.

[0004] Some test and measurement instruments, such as oscilloscopes, have integrated or built-in arbitrary function generators (AFGs). AFGs can generate functions, but typically in the analog domain. Currently, there is no option to feed high-speed serial data back to the instrument's analog channel.

[0005] Being able to use the same instruments used to perform tests and measurements on the DUT for data pattern generation will eliminate a great deal of complexity in the test environment. Attached Figure Description

[0006] Figure 1 An embodiment of a test and measurement instrument with an advanced data pattern generator is shown.

[0007] Figure 2 An example of a user interface is shown that allows users to select a scrambler and encoder to generate the corresponding waveform.

[0008] Figure 3 A flowchart illustrating an embodiment of a method for generating advanced data pattern waveforms is shown. Detailed Implementation

[0009] Embodiments of this disclosure generally include, for example, advanced data pattern generators integrated within test and measurement instruments (such as oscilloscopes) used for signal analysis. The output signal of the advanced data pattern generator can be used externally to the instrument or routed internally to a channel front end for direct acquisition. For example, according to some embodiments of this disclosure, an oscilloscope with a built-in advanced high-speed serial data pattern generator can feed high-speed serial data back to the oscilloscope's analog channels. This makes it easier for the user to exercise the oscilloscope's high-speed triggering capabilities or any other features. Furthermore, according to some embodiments, there will be the ability to create or load waveforms of different protocols based on scrambling and encoding mechanisms.

[0010] The embodiments disclosed herein are not necessarily limited to implementation in an oscilloscope. The built-in advanced data pattern generator can also utilize the features of any test equipment or device under test (DUT). It does not necessarily have to be an oscilloscope. One embodiment includes an oscilloscope with or without an advanced data pattern generator and high-speed serial trigger circuitry.

[0011] Figure 1 An embodiment of a test and measurement instrument 10 with an Advanced Data Pattern Generator (ADPG) is illustrated. The ADPG allows for the verification of any high-speed serial flip-flop or other instrument feature. The ADPG can be used in the quality control phase of any instrument or other product to verify high-speed serial flip-flops (HSSTs). Users will have the ability to generate customizable waveforms, such as inserting error bits or loading any waveform of interest from memory. The ADPG can generate high-speed waveforms based on the instrument's available bandwidth, which in some embodiments exceeds 25 gigabits per second (Gbps). The ADPG allows users to utilize any instrument, other test equipment, or device under test (DUT). The presence of the ADPG within another instrument, such as an oscilloscope, eliminates the need for an additional piece of equipment such as an arbitrary waveform generator.

[0012] As used in this article, the term "high-speed" refers to a speed of 1 gigabits per second (Gbps) or higher.

[0013] exist Figure 1 In this design, instrument 10 has one or more transmitters and one or more receivers, and instrument 10 may include one or more transceivers having both. The following discussion will refer to the transmitters and receivers associated with channels 1 and 2 of the instrument; it should be understood that the instrument may include many more transmitters, receivers, and channels. The numbers 1 and 2 are used to distinguish between two different channels and do not imply that only two channels exist. Figure 1In the illustrated embodiment, the instrument has a receiver 12 connected to channel 1 of the instrument and a receiver 14 connected to a second channel (channel 2). The instrument also has one or more transmitters, such as transmitter 16 on channel 1 and transmitter 18 on channel 2. The input channels connected to receivers 12 and 14 may include some type of interface (I / F) circuitry or chip, such as an application-specific integrated circuit (ASIC), for receiving incoming signal 20 for receiver 12 and incoming signal 22 for receiver 14. A receiver multiplexer (RxMUX) 24 controls which channel receiving data is connected to a high-speed serial flip-flop (HSST) circuit 26. Transmitters 16 and 18 may have built-in pre-emphasis capabilities to compensate for signal loss in the network where they are driving signals into.

[0014] Two receivers, 12 and 14, act as deserializers, converting high-speed serial data into low-speed parallel data. In most instances, receivers (such as 12 and 14) serve as clock data recovery (CDR) modules. As an example, receivers may include Intel H-tiles, but this is not intended to limit them to any particular high-speed circuit, nor should it imply any limitations. The HSST circuit 26 receives parallel low-speed data from the RxMUX 24, which contains data from the selected high-speed receiver, and is the primary flexible serial flip-flop logic / state machine, typically housed within the instrument to allow the user to trigger the instrument in desired modes, errors, sequences, etc. The output of HSST 26 typically triggers the instrument's master flip-flop 28, but can also stimulate the ADPG state machine 30.

[0015] On the transmission side, ADPG receives input from ADPG user interface 38 displayed on display 36. Display 36 may include a touchscreen or have adjacent user controls; combinations thereof include a user interface. The user interacts with instrument 10 via display / user interface 36 and selects, enters, or otherwise provides data patterns to be generated. Some of these may involve executable code or software running on one or more processors (such as 34). This information is passed to one or more processors, which then create or access (if stored) the pattern to be generated and send it to waveform generator 33. Waveform generator 33 may include a number of components (not shown here). These components may include, but are not limited to, oscillators, waveform generator / shaping circuitry, modulators, and signal conditioning stages.

[0016] Waveform generator 33 then sends waveform data through interface 32, such as a PCIe (Peripheral Component Interface Fast) interface. State machine 30 can respond to different stimuli. State machine 30 can control which mode to play back, step between different modes in memory, etc. It can receive modes received through receivers 12 and 14, and change the mode or otherwise modify the mode transmitted through interface 32.

[0017] Block 40 contains a PRBS generator (pseudo-random binary sequence) 42 and a block RAM 44. In one embodiment, a field-programmable gate array (FPGA) may contain components for the receiver and transmitter from interface 32 to block 11. This is just one example, and other configurations are possible. The output of block 40 goes to an encoder / scrambler 45, which is discussed below. Figure 2 The user interface is described in more detail in [the document / document].

[0018] In one embodiment, the transmitter multiplexer (TxMUX) 46 does not actually act as a multiplexer. Instead of selecting which channel receives the output, the TxMUX sends the same output signal to both the internal channel and the external connector interface. In another embodiment, the TxMUX 46 can select which channel receives the generated data pattern. In one embodiment, the transmitter connected to channel 2 outputs a signal to the outside of instrument 10 via the external connector interface 48. Interface 48 is external because it passes the data pattern to the outside of instrument 10, not because interface 48 is outside the instrument. It can be part of instrument 10. Providing the data pattern to the outside of the instrument can achieve many different uses, including applying the data pattern to the device under test 52. The external connector interface 48 can include one of many different types of interfaces, such as an RF (radio frequency) interface including an ultra-small type A (SMA) interface.

[0019] In another embodiment, the TxMUX 46 can selectively output a data mode via path 50, which can then be internally rerouted to one or more of the instrument channel inputs I / F 20 and 22 to reach receivers 12 and 14, without using external cables to instrument 10. The ability to route output data modes to incoming instrument channels allows for the application, testing, and demonstration of the high-speed serial data triggering capabilities of the instruments discussed above.

[0020] To allow users to select the desired pattern to generate, ADPG U / I 38 can provide users with a list of possible scramblers and encoders. Figure 2 This is illustrated in more detail below. For high-speed protocols, when generating known waveforms for the HSST data path to establish any trigger of interest, the user generally needs to consider two blocks: scrambler 60 and encoder 62. Figure 2Different protocols, such as NRZ and 8b10b, are shown, along with associated scramblers and encoder schemes. PCIe12 in the interface refers to PCIe Gen 1 and Gen 2, while PCIe345 refers to PCIe Gen 3, Gen 4, and Gen 5. USBG1 and USBG2 refer to USB3 Gen 1 and Gen 2.

[0021] like Figure 2 As shown, users can select options from each S and E drop-down menu 60, 62 based on the waveform type of interest. For better visibility, the user interface can include the polynomials and encoding types required for each protocol to generate the waveform. These selections are just some of the options shown. Selections may also include PAM (Pulse Amplitude Modulation) to support PCIe 6 and USB (Universal Serial Bus) version 4.

[0022] The user configures the system via U / I 38. The client provides high-level or low-level descriptions via U / I 38, and waveform generator 33 receives those inputs and generates waveforms. Waveform generator 33 can modify the inputs as needed to generate waveforms, and then sends the waveforms to block RAM 44. The waveforms can be... Figure 1 The waveform is generated by the waveform generator 33, or it can be "generated" by accessing a predefined waveform in the memory represented by block RAM 44. An example of low-level control might involve the user manually entering a bit pattern, including any error bits or other exceptions the user wants to include. When the user enters a pattern of 0s and 1s, state machine 30 uses this segment of memory in block RAM 44 to bypass encoder / scrambler 45 and send out the user's pattern without alteration.

[0023] Advanced control might involve the user selecting a PCIe compliance mode only on repeating loops, or a mode with a similar generic label. Waveform generator 33 knows what the compliance mode is, so it can obtain the raw compliance mode and pass it to encoder / scrambler 45 to generate data to be stored in block RAM 44. Since the data has been encoded / scrambled, the state machine again sends out the raw data stored in block RAM 44.

[0024] In another example of advanced control, as an example, the user might want an infinite series of scrambled PCIe packets. The pattern length is too long to be pre-calculated and placed into block RAM 44. Waveform generator 33 simply loads 0s into block RAM 44, enabling encoder / scrambler 45 to continuously scramble the 0 payload and transmit it indefinitely.

[0025] The data mode used for waveform generation is changeable. Conditions that may change the data mode include, but are not limited to, a second user input following the user input that selects or enters the data mode, a trigger occurring at the HSST circuit, and a specific state of the instrument (such as after each acquisition if the instrument is an oscilloscope). Other changes may occur.

[0026] Figure 3 A flowchart illustrating the process of generating a waveform based on user input is shown. The process begins at 70, where the instrument displays the ADPG user interface. The user makes their selection, which is received by the instrument at 72. At 74, the instrument generates a waveform corresponding to the user-defined pattern. Pattern generation can use a scrambler, an encoder, both, or neither. Without using one or both of the scrambler and encoder, data will only be transmitted through the encoder / scrambler at 45. (Reference) Figure 1 The instrument loads the waveform into a memory represented by block RAM 44 for reading the waveform once a transmission path is selected. As mentioned above, waveform generation also includes accessing the previous waveform from memory. In one embodiment, at 76, the process may determine whether the instrument will send a signal to either an internal or external path, and if so, complete at 78 as discussed above. In an alternative embodiment, the instrument may select an internal path at 82 or an external interface at 80.

[0027] In one embodiment, receiver 12 or 14 acts as a deserializer, a function that uses a single receiver. When the transmitter and receiver are part of the same transceiver, the transmitter channel associated with the receiver being used remains unused. The ability to internally route high-speed signals using this unused transmitter channel does not increase the instrument's hardware requirements.

[0028] The above discussion demonstrates that an Advanced Data Pattern Generator (ADPG) can be provided to existing instruments, eliminating the need for additional equipment, as is required when using an arbitrary waveform generator.

[0029] The external path through which the signal will be routed to the external interface will allow users to pass the transmitted test signal through any channel they can design (such as long coaxial cables, PCB loss traces, crosstalk injection, etc.) to degrade the signal and then run it back to the input channel to further utilize the capabilities of HSST. Most of the limitations on the amount of test signal the receiver can tolerate will be set by the receiver itself. The receiver plus HSST logic enables the instrument to be triggered in the non-ideal domain (meaning the degraded signal) based on the application signal from the customer or from ADPG. Because users are typically interested in their signals, ADPG may not play a significant role in this embodiment. ADPG adds a stimulus that would otherwise require another instrument to generate the signal, which can be used to drive the user's DUT to perform some function on that data. Its output can be acquired and analyzed on an oscilloscope and HSST combination.

[0030] Various aspects of this disclosure can operate on specially created hardware, firmware, digital signal processors, or specially programmed general-purpose computers, including processors that operate according to programmed instructions. As used herein, the term controller or processor is intended to include microprocessors, microcomputers, application-specific integrated circuits (ASICs), and special-purpose hardware controllers. One or more aspects of this disclosure can be embodied in computer-usable data and computer-executable instructions, such as one or more program modules executed by one or more computers (including monitoring modules) or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc., which perform specific tasks or implement specific abstract data types when executed by a processor in a computer or other device. Computer-executable instructions can be stored on non-transitory computer-readable media, such as hard disks, optical disks, removable storage media, solid-state memory, random access memory (RAM), etc. As those skilled in the art will appreciate, the functionality of program modules can be combined or distributed in various aspects as desired. Furthermore, functionality can be wholly or partially embodied in firmware or hardware equivalents, such as integrated circuits, FPGAs, and the like. Specific data structures can be used to more efficiently implement one or more aspects of this disclosure, and such data structures are considered within the scope of the computer-executable instructions and computer-available data described herein.

[0031] In some cases, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried or stored on one or more non-transitory computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As discussed herein, a computer-readable medium means any medium that can be accessed by a computing device. By way of example and not limitation, a computer-readable medium may include computer storage media and communication media.

[0032] Computer storage media means any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital video optical disc (DVD) or other optical disc storage devices, magnetic tape cassettes, magnetic tape, disk storage devices or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable media implemented in any technology. Computer storage media excludes signals themselves and temporary forms of signal transmission.

[0033] Communication medium means any medium that can be used to transmit computer-readable information. By way of example and not limitation, communication medium may include coaxial cable, fiber optic cable, air, or any other medium suitable for transmitting electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0034] Example Illustrative examples of the disclosed techniques are provided below. Embodiments of these techniques may include one or more of the examples described below, as well as any combination thereof.

[0035] Example 1 is a test and measurement instrument comprising: a display; one or more transmitters; one or more receivers; one or more channels configured to transmit and receive signals; a data pattern generator; and a high-speed serial flip-flop (HSST) circuit operating at 1 gigabits per second or faster, connected to one or more receivers to receive data patterns from the data pattern generator, thereby utilizing the high-speed serial flip-flop circuit.

[0036] Example 2 is a test and measurement instrument of Example 1, wherein the output of one or more transmitters is connected to the input channel of the test and measurement instrument.

[0037] Example 3 is a test and measurement instrument of either Example 1 or 2, wherein the output of one or more transmitters is connected to an external connector interface of the test and measurement instrument.

[0038] Example 4 is a test and measurement instrument of any of Examples 1 to 3, further including one or more processors, and the data pattern generator includes code executed by one or more processors to cause one or more processors to generate data patterns.

[0039] Example 5 is a test and measurement instrument of Example 4, wherein one or more processors are further configured to execute code to cause one or more processors to display a user interface on a display.

[0040] Example 6 is a test and measurement instrument of Example 5, wherein the code that causes one or more processors to display a user interface includes code that causes one or more processors to receive user input to specify the pattern to be generated.

[0041] Example 7 is a test and measurement instrument of Example 6, wherein user input may include one of the following: training mode, stored mode, manually entered mode, or changed mode.

[0042] Example 8 is the test and measurement instrument of Example 6, wherein the generated data pattern can be modified by one or more of the following: user input via user interface, trigger events from HSST circuit, and changes in the state of the test and measurement instrument.

[0043] Example 9 is a test and measurement instrument of any of Examples 1 to 8, further including a scrambler and an encoder.

[0044] Example 10 is a test and measurement instrument of Example 9, wherein the generated data pattern is produced by a scrambler, an encoder, or both a scrambler and an encoder.

[0045] Example 11 is a method for generating a data pattern from a test and measurement instrument, comprising: displaying a user interface that provides options to allow a user to define a data pattern; receiving the user-defined data pattern through the user interface; generating a waveform based on the user-defined data pattern; and selectively routing the waveform to at least one of an input channel of the test and measurement instrument and an external interface of the test and measurement instrument.

[0046] Example 12 is a method of Example 11, wherein generating the waveform includes generating a new waveform based on a user-defined data pattern.

[0047] Example 13 is a method of either Example 11 or 12, wherein generating a waveform includes accessing memory to retrieve data corresponding to a user-defined data pattern.

[0048] Example 14 is a method of any of Examples 11 to 13, further including receiving the selection of the waveform route via a user interface.

[0049] Example 15 is a method of any of Examples 11 to 14, wherein generating a waveform involves generating a waveform at a rate of 1 gigabits per second or faster.

[0050] Example 16 is a method of any of Examples 11 to 15, wherein generating a waveform includes changing the waveform based on one or more of a second user input received through a user interface.

[0051] Example 17 is a method of any one of Examples 11 to 16, wherein the generated waveform includes one of the following: using a scrambler, using an encoder, using both a scrambler and an encoder, or not using either a scrambler or an encoder.

[0052] Example 18 is an oscilloscope comprising: a display; one or more transmitters; one or more receivers; one or more channels configured to transmit and receive signals; a data pattern generator for generating waveforms according to user-defined data patterns; and a path selector for selectively routing waveforms to at least one of the oscilloscope's input channels and the oscilloscope's external connector interfaces.

[0053] Example 19 is an oscilloscope of Example 18, in which the data pattern generator operates at a rate of 1 gigabits per second or faster.

[0054] Example 20 is an oscilloscope of either Example 18 or 19, and further includes one or more processors, the data pattern generator including code executed by one or more processors to cause one or more processors to generate data patterns.

[0055] Example 21 is an oscilloscope of Example 20, wherein one or more processors are further configured to execute code to cause one or more processors to display a user interface on a display.

[0056] Example 22 is an oscilloscope of Example 21, wherein the code that causes one or more processors to display the user interface includes code that causes one or more processors to receive user input to specify the data pattern to be generated.

[0057] Example 23 is an oscilloscope of Example 22, wherein user input may include one of the following: training mode, stored mode, manually entered mode, or changed mode.

[0058] Example 24 is an oscilloscope of Example 22, wherein the generated data pattern can be changed by one or more of the following: user input via the user interface and changes in the state of the oscilloscope.

[0059] Example 25 is an oscilloscope of Example 18, further including a scrambler and an encoder.

[0060] Example 26 is an oscilloscope of Example 25, in which the generated data pattern is produced by a scrambler, an encoder, or both a scrambler and an encoder.

[0061] All features disclosed in the specification (including claims, abstract, and drawings), and all steps in any disclosed method or process, may be combined in any combination, except for at least some mutually exclusive combinations of such features and / or steps. Unless expressly stated otherwise, each feature disclosed in the specification (including claims, abstract, and drawings) may be replaced by an alternative feature for the same, equivalent, or similar purpose.

[0062] Additionally, this written description refers to specific features. It should be understood that the disclosure in this specification includes all possible combinations of those specific features. For example, where a specific feature is disclosed in the context of a particular aspect, that feature can also be used in the context of other aspects to the greatest extent possible.

[0063] Furthermore, when a method with two or more defined steps or operations is referenced in this application, the defined steps or operations may be performed in any order or simultaneously unless the context excludes those probabilities.

[0064] Although specific aspects of this disclosure have been illustrated and described for illustrative purposes, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Therefore, the invention should not be limited except for the appended claims.

Claims

1. A testing and measuring instrument, comprising: monitor; One or more transmitters; One or more receivers; One or more channels are configured to transmit and receive signals; Data pattern generator; as well as A high-speed serial flip-flop (HSST) circuit, which operates at 1 gigabits per second or faster, is connected to one or more receivers to receive data patterns from a data pattern generator, thereby employing the high-speed serial flip-flop circuit.

2. The test and measurement instrument of claim 1, wherein the output of one or more of the transmitters is connected to the input channel of the test and measurement instrument.

3. The test and measurement instrument of claim 1, wherein the output of one or more transmitters is connected to an external connector interface of the test and measurement instrument.

4. The test and measurement instrument of claim 1, further comprising one or more processors, wherein the data pattern generator includes code executed by the one or more processors to cause the one or more processors to generate data patterns.

5. The test and measurement instrument of claim 4, wherein the one or more processors are further configured to execute code to display a user interface on a display.

6. The test and measurement instrument of claim 5, wherein the code that causes the one or more processors to display a user interface includes code that causes the one or more processors to receive user input specifying a pattern to be generated.

7. The test and measurement instrument according to claim 6, wherein the user input may include one of the following: training mode, stored mode, manually entered mode, or modified mode.

8. The test and measurement instrument of claim 6, wherein the generated data pattern is modifiable by one or more of the following: user input via a user interface, trigger events from the HSST circuit, and changes in the state of the test and measurement instrument.

9. The test and measurement instrument according to claim 1, further comprising a scrambler and an encoder.

10. The test and measurement instrument of claim 9, wherein the generated data pattern originates from a scrambler, an encoder, or both a scrambler and an encoder.

11. A method for generating data patterns from test and measurement instruments, comprising: The display provides a user interface that allows users to define data patterns; Receive user-defined data patterns through the user interface; Generate waveforms based on user-defined data patterns; as well as The waveform is selectively routed to at least one of the input channels of the test and measurement instrument and the external interface of the test and measurement instrument.

12. The method of claim 11, wherein generating the waveform includes generating a new waveform according to a user-defined data pattern.

13. The method of claim 11, wherein generating the waveform includes accessing a memory to retrieve data corresponding to a user-defined data pattern.

14. The method of claim 11, further comprising receiving a selection of a route for the waveform via a user interface.

15. The method of claim 11, wherein generating the waveform comprises generating the waveform at a rate of 1 gigabits per second or faster.

16. The method of claim 11, wherein generating the waveform includes changing the waveform based on one or more of second user inputs received through a user interface.

17. The method of claim 11, wherein generating the waveform comprises one of the following: using a scrambler, using an encoder, using both a scrambler and an encoder, or not using either a scrambler or an encoder.

18. An oscilloscope, comprising: monitor; One or more transmitters; One or more receivers; One or more channels are configured to transmit and receive signals; A data pattern generator is used to generate waveforms based on user-defined data patterns. as well as A path selector is used to selectively route waveforms to at least one of the oscilloscope's input channels and the oscilloscope's external connector interfaces.

19. The oscilloscope of claim 18, wherein the data pattern generator operates at a speed of 1 gigabits per second or faster.

20. The oscilloscope of claim 18, further comprising one or more processors, the data pattern generator comprising code executed by the one or more processors to cause the one or more processors to generate data patterns.

21. The oscilloscope of claim 20, wherein the one or more processors are further configured to execute code to cause the one or more processors to display a user interface on a display.

22. The oscilloscope of claim 21, wherein the code causing the one or more processors to display the user interface includes code causing the one or more processors to receive user input specifying a data pattern to be generated.

23. The oscilloscope of claim 22, wherein the user input may include one of the following: training mode, stored mode, manually entered mode, or changed mode.

24. The oscilloscope of claim 22, wherein the generated data mode is modifiable by one or more of the following: user input via a user interface and changes in the state of the oscilloscope.

25. The oscilloscope of claim 18, further comprising a scrambler and an encoder.

26. The oscilloscope of claim 25, wherein the generated data pattern originates from a scrambler, an encoder, or both a scrambler and an encoder.

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