Single pin impedance measurement system and phase offset compensation for single pin impedance measurement system

Abstract

Embodiments of the invention relate to a single pin impedance measurement system and phase offset compensation for a single pin impedance measurement system. An impedance measurement system comprising: a signal generator comprising a memory and arranged to generate a digital test signal and at least one digital demodulation signal based on the memory, where the digital test signal has a first frequency and the at least one digital demodulation signal has a first frequency; a single pin for providing an analog test signal based on the digital test signal to a device under test (DUT) and measuring an analog input signal in response to providing the analog test signal to the DUT; and a demodulator configured to obtain a first filtered digital signal based on the input signal to generate at least one digital demodulated signal indicative of the impedance; and at least one digital demodulation signal.

Description

Cross-references to related applications

[0001] This application claims priority to UK Patent Application No. 2416584.7, filed on 11 November 2024. The entire disclosure of UK Patent Application No. 2416584.7 is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a single-pin impedance measurement system and phase offset compensation for the single-pin impedance measurement system, and more particularly, but not limited to, a single-pin impedance measurement system including a phase offset compensator configured to introduce an address offset to compensate for unknown phase offsets. This single-pin impedance measurement system can be used with a vehicle's steering equipment to implement a gesture-based human-machine interface system. Background Technology

[0003] To measure or calculate the impedance of a Device Under Test (DUT), the system can generate measurements representing the amplitude and phase (or real and imaginary components) of the impedance. To reduce the number of signal pins, each DUT should only use one connector to provide the "test signal" and measure the result.

[0004] A voltage can be applied to the DUT, and the system can determine the impedance of the DUT by measuring the amplitude and phase of the current flowing through the DUT. Alternatively, a current can be applied to the DUT, and the voltage across the DUT can then be measured to determine the amplitude and phase of the voltage signal.

[0005] In order to measure the real and imaginary components of a signal affected by a complex DUT, the test signal must be a time-varying signal, such as a signal pulse or a sine wave.

[0006] Typically, a sine wave is used because it has both amplitude and phase (real and imaginary components: “Re” and “Im”).

[0007] A known system typically implements an I / Q demodulator to derive Re and Im. The amplitude and phase of the current are measured by demodulating the signal across the DUT (current through the DUT or voltage across the DUT) using the I / Q demodulator. This measurement is performed by multiplying the measured signal by a sine and a cosine signal of the same frequency. The output of the I / Q demodulator (after filtering) yields in-phase quadrature signals on DC. The output is complex, including both real and imaginary components. The amplitude is determined by... Given, and the phase is given by arctan( (This is given.)

[0008] The known system has limited sensitivity, making it more susceptible to noise and parasitic effects, which reduces the accuracy and reliability of the measurement results.

[0009] Furthermore, internal signal delays can be introduced, independent of the DUT, due to propagation delays in frequency-dependent signal processing or digital processing of the analog amplifiers (which function similarly to filters) used in impedance measurement systems. For example, delays created by mixed-signal devices (such as analog-to-digital converters aligned with the signal processing path). Therefore, the output from the I / Q demodulator can have a phase shift independent of the DUT.

[0010] One object of this disclosure is to provide a single-pin impedance measurement system for measuring the impedance of an external DUT, which has increased sensitivity, thereby reducing noise sensitivity and increasing measurement accuracy. Furthermore, it is desirable to develop a system capable of addressing phase shift, as correcting phase shift increases accuracy. Summary of the Invention

[0011] According to a first aspect of this disclosure, an impedance measurement system is provided, the impedance measurement system including a signal generator comprising a memory, a single pin, and a demodulator, and arranged to generate a digital test signal and at least one digital demodulated signal based on the memory, wherein the digital test signal has a first frequency, and the at least one digital demodulated signal has a first frequency, the single pin being configured to provide an analog test signal based on the digital test signal to a device under test (DUT), and to measure an analog input signal in response to providing the analog test signal to the DUT; the demodulator being configured to obtain signals to generate at least one digital demodulated signal indicating impedance: a first filtered digital signal based on the input signal, and at least one digital demodulated signal.

[0012] According to a second aspect of this disclosure, a single-pin impedance measurement system is provided, comprising: an oversampling analog-to-digital converter; a digital demodulator coupled to the analog-to-digital converter; and a memory configured to generate a test signal and one or more demodulated signals; wherein the test signal and the one or more demodulated signals are coherent, enabling the single-pin impedance measurement system to simultaneously perform phase and amplitude measurements of the impedance signal.

[0013] According to a third aspect of the invention, a single-pin impedance measurement system is provided, the single-pin impedance measurement system comprising: an oversampling analog-to-digital converter; a digital demodulator coupled to the analog-to-digital converter; a memory configured to generate a test signal and one or more demodulated signals; and a phase offset compensator; wherein the phase offset compensator is configured to introduce an address offset to one or more demodulated signals and / or the test signal, thereby compensating for an unknown phase offset between the test signal and one or more demodulated signals.

[0014] It should be understood that the single-pin impedance measurement system of the third aspect may include providing and / or using the features set forth in the second aspect, and may be combined with other features described herein. Attached Figure Description

[0015] The present disclosure will now be described in further detail by way of example only with reference to the accompanying drawings, wherein:

[0016] Figure 1 It is an impedance measurement system based on existing technology;

[0017] Figure 2 This is an example embodiment of the single-pin impedance measurement system according to the present disclosure.

[0018] Figure 3 This is another example embodiment of a single-pin impedance measurement system according to the present disclosure;

[0019] Figure 4 This is an example embodiment of a single-pin impedance measurement system arranged to compensate for phase shift according to the present disclosure;

[0020] Figure 5 This is an example embodiment of a steering device using the single-pin impedance measurement system of this disclosure; and

[0021] Figure 6 This is a table comparing the performance of the single-pin impedance measurement system disclosed herein with the prior art.

[0022] Figure 7 This is another embodiment of single-pin impedance measurement according to the present disclosure. Detailed Implementation

[0023] Figure 1 This is a circuit diagram of an impedance measurement system 100 according to the prior art. System 100 includes a sine wave generation digital-to-analog converter (TX-DAC) 110 coupled to a filter 120. The TX-DAC 110 and the filter 120 are configured to generate a sine wave signal at pin 130 connected to the DUT.

[0024] System 100 also includes a voltage buffer amplifier IV buffer 140 coupled to a bandpass filter 150. The IV buffer 140 is configured to measure the current through the DUT, and the current signal is then filtered by the bandpass filter 150 before being passed to the I / Q demodulation block 160. The I / Q demodulation block 160 is configured to generate an I / Q demodulated signal by multiplying the sinusoidal signal input(f) measured at pin 130 by a sine (SIN) signal and a cosine (COS) signal. This results in the generation of two signals: input(f) x SIN(f) and input(f) x COS(f), which represent the real and imaginary components of the sinusoidal signal input(f). By measuring the real and imaginary components of the sinusoidal signal, the amplitude and phase of the signal can be calculated. These two signals (the real and imaginary signals) are then passed to a multiplexer (MUX) 170, which is configured to time-interleave the signals. Finally, the time-interleaved signal is passed to the analog-to-digital converter ADC 180.

[0025] The existing system 100 has several drawbacks. First, the I / Q demodulation process is highly sensitive to the matching between SIN and COS signals. Due to process variations, any analog component in system 100 can affect the matching. Second, the I / Q demodulation process is also sensitive to phase shift (i.e., delay) variations and the sinusoidal signal from DAC 110. Any variation in the amplitude of the analog components of the SIN and COS signals will affect the output of I / Q demodulation block 160. Third, the real and imaginary components are sent to ADC 180 via MUX 170, which time-interleaves the signals. Therefore, the acquisition time is doubled, and the signal must be maintained at a constant level (allowing only small variations) between acquisition times to reduce errors in impedance measurements. Finally, the bandpass filter 150 preceding the I / Q demodulation block 160 requires stable bandpass characteristics in the analog domain. Furthermore, any change in the signal frequency supplied to filter 150 requires a corresponding change in the bandpass filter. All these drawbacks result in limited sensitivity of system 100. Therefore, attempting to measure minute changes in impedance using System 100 becomes complex and expensive.

[0026] The purpose of this disclosure is to overcome the limitations of the prior art.

[0027] Figure 2 This is an example embodiment of the pin impedance measurement system 200 according to the present disclosure. The impedance measurement system 200 can be coupled to an external system to obtain a pin impedance measurement system with a system frequency f. s The clock signal (not shown). For example, the system frequency f s It can be 32 MHz.

[0028] System 200 includes a signal generator 201, and the signal generator 201 includes a memory 202. The signal generator 201 is arranged to generate a test signal 203 based on the contents of the memory 202.

[0029] The memory 202 includes a lookup table (LUT) that stores a set of predefined values ​​at corresponding memory addresses for generating digital test signals 203.

[0030] exist Figure 2 In the example embodiment, the test signal 203 is a digital signal, and therefore it will be referred to as digital test signal 203. In other embodiments, the signal generator 201 may include an integrated digital-to-analog converter such that after the test signal is generated, the output of the signal generator 201 is an analog signal. The digital test signal 203 has a first frequency.

[0031] exist Figure 2 In an example embodiment, the impedance measurement system 200 further includes a digital-to-analog converter (DAC) 209, which is coupled to a signal generator 201 to obtain a digital test signal 203 and generate at least one analog test signal 206. The at least one analog test signal 206 may be referred to as an excitation signal. In some embodiments, the DAC 209 can operate at a frequency less than the system frequency f. s It operates at a second frequency (e.g., 4 MHz). In some embodiments, the DAC 209 may have a sampling frequency equal to the second frequency, such that the DAC 209 has a sampling rate less than the system frequency fs.

[0032] In some embodiments, at least one analog test signal 207 has a frequency f that is related to the system frequency f. s Coherent frequency. In some embodiments, at least one analog test signal 206 has a frequency f that is determined by the system frequency f. s The frequency is set by multiplying by a prime number. In some embodiments, the frequency of at least one analog test signal 206 can be based on a prime number and the system frequency f. s The product of the numbers. Prime numbers can be, for example, 7, 11, 13, 17, 19, ... etc. In some embodiments, the frequency of at least one analog test signal 206 can be based on the length of the acquisition period of DAC 206. In some embodiments, the frequency of at least one analog test signal 206 can be given by the following formula:

[0033] in:

[0034] f ex It is the frequency of the analog test signal 206, i.e., the excitation signal;

[0035] N is a prime number; and

[0036] K is the length of the acquisition period of the DAC 209, measured in system clock cycles.

[0037] As an example to facilitate understanding of this disclosure, Table 1 shows that if a data acquisition period has 4096 system clock cycles and the system frequency f s Equal to 30.72 MHz, then for the frequency of the analog test signal 206 for various prime numbers... Table 1

[0038] Advantageously, reducing the sampling rate of the DAC 209 allows for a reduction in the number of samples in the LUT, thus requiring a smaller LUT. This, in turn, results in a corresponding reduction in memory size and power consumption, leading to a more efficient system.

[0039] Impedance measurement system 200 is arranged to provide at least one analog test signal 206 to DUT 205 via a single pin 220 to measure the impedance of DUT 205.

[0040] The signal generator 201 is also arranged to generate at least one digital demodulated signal 204 based on the contents of the memory 202. The at least one digital demodulated signal 204 may have the same frequency as the digital test signal 203. In some embodiments, the at least one digital demodulated signal 204 may be coherent with the digital test signal 203.

[0041] The memory 202 includes a lookup table (LUT) that stores a set of predefined values ​​at corresponding memory addresses for generating at least one digital demodulated signal 204. In other words, the LUT contains multiple samples of the amplitude values ​​of the digital demodulated signal.

[0042] The at least one demodulated signal may include a first sine signal and a second sine signal (not shown), wherein the second sine signal is generated by filtering the phase of the first sine signal by 90 degrees.

[0043] The impedance measurement system 200 also includes a single pin 220 for providing an analog test signal SIG 206 to the DUT 205 based on the digital test signal 203. In some embodiments, there are no other connections or couplings between the DUT 205 and the impedance measurement system 200. In some embodiments, a ground plane may be coupled to the DUT 205 and the impedance measurement system 200.

[0044] Impedance measurement system 200 is configured to supply or provide at least one analog test signal 206 to DUT 205, and to measure the effect of DUT on at least one analog test signal 206 via pin 220 and input processing stage 211. Input processing stage 211 is coupled to pin 220 and configured to receive an analog input signal 207, and to generate a first filtered digital signal 208 based on the analog input signal 207.

[0045] The impedance measurement system 200 also includes a demodulator 270. The demodulator 270 is configured to obtain a first filtered digital signal 208 based on the analog input signal 207, and at least one digital demodulated signal 204 to generate at least one digital demodulated signal indicating the impedance of the DUT 205.

[0046] Figure 3 This is an example embodiment of the single-pin impedance measurement system 200' according to the present disclosure. System 200" further details possible implementations of System 200. System 200" includes additional implementation details of, for example, input processing stage 211 and demodulator 270.

[0047] System 200" includes a memory LUT configured to generate a digital base signal DSIG (also referred to as digital test signal 203). DSIG provides a test signal input to the system and can be an AC signal. In this embodiment, DSIG can be a sinusoidal signal. The frequency of the DSIG signal can be adjusted based on system parameters. DSIG can be considered a modulated signal.

[0048] The memory LUT can also generate a first signal S1, which can be a sine wave, and a second signal S2, which can be a cosine wave. Signals S1 and S2 can be AC ​​signals. Figure 2 In the example embodiments, these are sinusoidal signals, although in other embodiments they can be other types of signals, such as pulse signals. Signals S1 and S2 can be considered demodulated signals. Any one of signals S1, S2, or a combination of signals S1 and S2 can be considered digital demodulated signal 204. In some embodiments, the DSIG, S1, and S2 signals can be synchronized.

[0049] System 200 also includes a digital-to-analog converter (DAC), similar to Figure 2The DAC 209 acquires the base signal DSIG and converts it into an analog signal. The DAC is coupled to one or more filters and buffers 210. The combination of the DAC and one or more filters and buffers 210 is used to generate one or more time-varying signals, which may also be referred to as test signals SIG, SIG'. The time-varying signals SIG, SIG'(s) obtained from pin 220 represent the DUT. Any of the signals SIG, SIG'(s) or combinations thereof may also be referred to in this disclosure as analog input signal 207.

[0050] System 200 may also include a multiplexer 230 configured to combine one or more time-varying signals SIG, SIG' into a single signal. In some embodiments, multiplexer 230 is part of input processing stage 211. In some embodiments, analog input signal 207 may be a single signal, and therefore in these embodiments, system 200 may not include multiplexer 230. The single signal then passes through amplifier 240.

[0051] Amplifier 240 is arranged to provide an amplified version of analog input signal 207 to oversampled ADC 250. In some embodiments, amplifier 240 may be considered part of input processing stage 211.

[0052] System 200 includes an analog-to-digital converter (ADC) 250, which is configured to convert a signal received from amplifier 240 into a digital signal, which may be referred to as digital input signal 251. ADC 250 is also configured to oversample the signal during conversion. In some embodiments, ADC 250 is part of input processing stage 211.

[0053] Coupled to the ADC 250 is a filter 260, which may be, for example, a comb filter. The filter 260 is configured to filter the digital input signal 251 to generate a first filtered digital signal 208. In some embodiments, the filter 260 is part of the input processing stage 211.

[0054] The filtered digital signal then passes through demodulator 270. The demodulator can be, for example, an I / Q demodulator 271. Figure 3 In the example embodiment, the input of the I / Q demodulator 271 is coupled to the output of the filter 260, although in other embodiments without the filter 260, the I / Q demodulator 271 may be directly coupled to the output of the ADC 250. Figure 3In an example embodiment, the demodulator is configured to multiply the filtered digital signal by a first signal to generate a real signal and by a second signal to generate a virtual signal. In other words, the I / Q demodulator is configured to multiply the first filtered digital signal 208 by a first sine wave signal 204a to generate a real component signal 271a indicating the real component of the analog input signal 207, and to multiply the first filtered digital signal 208 by a second sine wave signal to generate a virtual component signal 271b indicating the virtual component of the analog input signal 207. These signals pass through an integrator 280, which is coupled to the output of the I / Q demodulator. The real and virtual component signals are then used to calculate the amplitude and phase of the DUT. Therefore, at least one digital demodulated signal indicating the impedance of the DUT 205 is based on the real component signal 271a and / or the virtual component signal 271b.

[0055] In some embodiments, the integrator 280 may have a frequency response with a notch at the frequency of at least one harmonic of at least one demodulated signal, such that the integrator filters the real component signal 271a and the imaginary component signal 271b to generate at least one digital demodulated signal.

[0056] In some embodiments, the memory may be, for example, a lookup table. A lookup table is a hardware table that stores data. Data from the lookup table can be used directly in the DAC 209 to generate test signals, such as digital test signal 203, or to generate a first signal S1 and a second signal S2, i.e., digital demodulated signal 204. In other embodiments, as understood by those skilled in the art, the memory may be other forms of hardware table.

[0057] Since demodulation is performed in the digital domain, the matching between the first signal S1 and the second signal S2 is given by structure, which is a technique known in the art. However, for system 200, the multiplication with the first signal S1 and the second signal S2 occurs simultaneously with the same signal, so each result is acquired only once. Figure 1 Compared to existing technology systems, this improves system performance. Figure 1 In existing systems, two samples are required to process I and Q data (i.e., one for I and one for Q).

[0058] ADC 250 is an oversampling ADC; in this example embodiment, ADC 250 is a Σ-Δ ADC (sigma-delta ADC), such as a 1-bit second-order sigma-delta ADC. Figure 3 In an example embodiment, the ADC 250 operates at a system frequency f s The following operation, although in other embodiments, can be performed at frequencies below the system frequency f. sThe system operates at a frequency that allows it to operate at. In an alternative embodiment, other types of oversampling ADCs may be used, as understood by those skilled in the art. Since system 200 uses oversampling ADC 250, a bandpass filter is no longer needed before ADC conversion. Instead, due to the oversampling method, only a small anti-aliasing low-pass filter is required.

[0059] The test signals used for I / Q demodulation, the first signal S1 and the second signal S2, are based on the same digital signal DSIG generated by the memory LUT. Therefore, the phase difference is constant and independent of the analog matching between the three signals.

[0060] The frequency of the test signal is coherent with the first signal S1 and the second signal S2 (demodulated signal), and the number of signal time periods is a prime number of the sampled signal. Therefore, all harmonics of the demodulated signal will be completely filtered out by the integrator 280. In this example embodiment, the integrator 280 is formed as a comb filter with notch filtering at all harmonics. Therefore, a high-precision analog filter is not required before the ADC 250. Furthermore, the demodulated signal requires a smaller number of samples per time period, which reduces the workload of the memory LUT. Fewer samples result in increased harmonics, but the system 200 is insensitive to harmonics due to the comb filter.

[0061] Similarly, for test signals generated by a DAC, the sampling rate of the DAC can be reduced. This reduces the number of samples in the memory LUT, and thus reduces the area and power consumption of system 200. System 200 of this disclosure is less sensitive to harmonics.

[0062] The digital base signal DSIG can also be called the modulation signal or digital test signal. The first signal S1 and the second signal S2 can also be collectively referred to as the demodulation signal or digital demodulation signal.

[0063] The modulation signal DSIG and demodulation signals S1 and S2 provided by the LUT can be in phase. However, when the modulation signal DSIG passes through the system 200 from the LUT to the demodulator 270, a lot of processing delay is introduced, causing a phase shift between the modulation and demodulation signals.

[0064] Depending on the cause of the phase shift, several known methods exist in the art for correcting or eliminating it. For example, if the phase shift is known, it can be eliminated during external I / Q processing. However, the phase shift is not always known, and therefore errors can still be introduced. Alternatively, the phase shift can be due to digital processing. If this is the case, the phase shift (delay) is caused by multiple z-factors. -1 The level is defined, so it can be improved by adding more z. -1 The phase shift is compensated for at different stages to obtain a total phase shift of 360°. However, this type of method increases response time and repetition rate.

[0065] If phase shift is introduced into analog signal processing, a filter with sufficiently high bandwidth must be used so that the phase shift is negligible. For example, the resulting error is less than 0.02%. This approach yields a wide signal bandwidth, and therefore the signal is highly sensitive to noise. Conversely, if the phase shift is due to variations in analog properties (e.g., due to process or temperature), it can be eliminated by implementing time constant bandwidth fine-tuning. Such solutions are complex, resulting in larger system sizes and longer development times. Alternatively, this type of phase shift can be adjusted by fine-tuning the delay between the phases of the test signal and the sine and cosine (demodulated) signals. However, the amplitudes of the test and / or demodulated signals must remain constant, requiring tunable all-pass filters, which are expensive to implement and occupy significant space in the system.

[0066] Therefore, a new method is needed to compensate for the phase shift of the input signal (the signal that will enter the demodulator from the DAC), which can be introduced by other factors such as signal processing delays of cable bundles and measurement circuits, thus overcoming the shortcomings of the prior art.

[0067] In this disclosure, the phase offset is compensated by introducing offset compensation into the demodulated signals S1, S2, or the digital test signal 203. Thus, in some embodiments, the signal generator 201 is configured to adjust the phase of at least one digital demodulated signal 204 and / or the digital test signal 203 to correct the phase offset between the first filtered digital signal 208 and at least one digital demodulated signal 204.

[0068] Figure 4 This is an example embodiment of phase offset compensation of the single-pin impedance measurement system 200” according to the present disclosure. Figure 4 System 200 and Figure 3 The system is the same as 200', except that some features have been removed to make the system easier to read / understand. Figure 3 and Figure 4 All features that are identical between them are assigned the same label and are considered to have the same characteristics as those between them. Figure 3 Same meaning and functionality.

[0069] Figure 4 The LUT in the diagram is shown as two separate elements, one for modulating the signal DSIG and the other for demodulating the signals S1 and S2. This is done for ease of understanding. Figure 4 In the example embodiment, phase offset compensation is only added to the demodulated signals S1 and S2, therefore... Figure 4 This can be seen by splitting the LUT in this way.

[0070] Phase offset compensation is achieved by adding an address offset to the LUT portion that generates the demodulated signals S1 and S2.

[0071] The demodulation 270 in system 200 is implemented in the digital domain. The modulation and demodulation signals are based on a memory LUT. In the LUT, a first signal (or a second signal) is implemented. The LUT output is connected to a DAC that generates a test signal, also known as an analog test signal. The LUT output is also connected to demodulator 270. The values ​​of the modulation signal DSIG and the demodulation signals S1 and S2 are read from the memory LUT by rotating the address. Phase offset compensation is achieved by adding an "address offset" to the LUT address of the demodulated signal (S1, S2). Therefore, the "address offset" is directly translated into the phase offset of any signal generated by signal generator 201. In this way, signal generator 201 can adjust the phase of at least one digital demodulated signal 204 and / or digital test signal 203 by adding an address offset to a portion of the LUT that generates at least one digital demodulated signal and / or digital test signal.

[0072] For example, if the LUT contains N samples of the amplitude of the demodulated signals S1 and S2, the "address counter" will end at the end, thus generating consecutive demodulated signals S1 and S2. When the LUT for the modulated signal DSIG and the demodulated signals S1 and S2 starts at address "0", the phase between the modulated signal DSIG and the first signal S1 is 0. For address "0", the phase between the modulated signal DSIG and the second signal S2 is 90° because the second signal S2 is generated by phase-shifting S1 by 90 degrees, or in other words, by using a later or earlier address in the LUT corresponding to a 90-degree phase shift. The address offset defines how much additional phase offset will be added between the modulated signal DSIG and the demodulated signals S1 and S2.

[0073] Address offsets can be generated in a variety of different ways. Several methods for generating address offsets are given below, but this is not an exhaustive list. As those skilled in the art will understand, there are other methods as well.

[0074] The address offset can be provided by an external system (such as an external microcontroller unit) and can be updated at any time during the use of the single-pin impedance measurement system 200.

[0075] Alternatively, the impedance measurement system 200 can be configured to internally determine the address offset during the calibration phase. During the calibration phase, the single-pin impedance measurement system 200 must be connected to the DUT, which consists only of a capacitive load. When this condition is met, the expected phase between voltage and current is defined (90°). Demodulated I / Q data is processed, and the address offset changes as the processing continues during the calibration phase, such that the measured phase difference between voltage and current represented by the output of demodulator 270 becomes equal to 90°. This can be accomplished, for example, with a simple counter or an algorithm such as the CORDIC algorithm. When the I output of the demodulator becomes minimum, the corresponding address offset is the value required to compensate for the phase offset during signal processing.

[0076] As described above, phase shift can be caused by changes in the analog properties of system 200, such as due to process or temperature. In some embodiments, impedance measurements 200, 200', and / or 200" may include a temperature sensor (not shown) communicatively coupled to signal generator 201. In such embodiments, memory 202 may include a set of predefined address offset values ​​for corresponding temperature values. Thus, the signal generator can obtain temperature measurements and generate digital test signals 203 and / or digital demodulated signals 204 based on the corresponding temperature values ​​stored in the LUT.

[0077] As mentioned above, address offset can also be implemented in the LUT of the modulated signal, rather than in the demodulated signal. However, the second-order effect of address offset in the demodulated signal is more reliable because the analog settling time is irrelevant when the signal starts with different phases. Therefore, it is preferable to implement address offset in the demodulated signal.

[0078] The phase offset compensation described above can be used with the single-pin impedance measurement system, which will be described in further detail below.

[0079] Figure 5 According to an example embodiment of the steering device 400 of this disclosure, a system 200'" for measuring impedance can be used in the steering device 400. The system 200'" has... Figure 2 The system has the same architecture as System 200, although it can have in some cases... Figure 3 System 200' or Figure 4 The system 200 has an architecture. The steering device 400 includes one or more sensors 410. The steering device 400 may be, for example, a steering wheel for a car. In other embodiments, as understood by those skilled in the art, the steering device 400 may be integrated with other types of vehicles.

[0080] In an example embodiment of the steering device 400, one or more sensors are one or more conductive foils (not shown). As described below, a single pin of an impedance measurement system is coupled to one or more sensors 410 integrated into the vehicle steering wheel 400, wherein the impedance measurement system is configured to drive one or more sensors to detect operator contact with the steering wheel. Each conductive foil is driven by a sinusoidal signal generated by an integrated circuit 420. System 200'" is configured to measure the current and phase shift across the conductive coil to measure impedance.

[0081] During operation, the pressure applied by the operator's hand increases the ground capacitance across the conductive foil, thereby increasing the resistance Z of sensor 410. An example application includes sensors located at different positions on the steering device 400. This allows the operator to input various commands via gestures and hand position while maintaining contact with the steering device 400. Examples of control functions may include cruise control settings and infotainment functions.

[0082] In an exemplary embodiment of a steering device 400 including a system 200'" for measuring impedance, the following setup can be used. The system 200'" and ADC 250 have a frequency fs, for example, 32 MHz. ADC 250 is a 1-bit ADC implemented as an oversampled sigma-delta ADC. ADC 250 operates at the system frequency fs. The output of ADC 250 is decimated by a decimation filter to provide a sampling rate of 1 MHz (1:32). In this exemplary embodiment, 128 decimated samples are integrated (accumulated) after demodulation.

[0083] In this exemplary embodiment, the DAC can operate at one-eighth of the system frequency fs. For example, if the system frequency is 32 MHz, the DAC will operate at 4 MHz. In this exemplary embodiment, the DAC is configured to generate test signals up to ~150 kHz. The exemplary system 200” uses five memories (in this particular example, they are lookup tables), and thus, five different frequencies can be selected. Due to the oversampling method, the low-pass filter 240 for the DAC output can be relaxed. The low-pass filter 240 preceding the ADC 250 can be generated with a relatively simple architecture because, due to ~200x oversampling, only very stray tones need to be filtered out. The bandwidth can be relatively high, and therefore the effects of delay variations caused by using a low-frequency filter are reduced.

[0084] In this exemplary embodiment, the test signal frequency is coherent with the system clock frequency. The test signal frequency is set by a prime number of the divided system clock. For example, if a sampling period has 4096 system clock cycles, the test signal frequency (stored in memory) will be fs / 4096 × Prime, where Prime can be one of 7, 11, 13, 17, 19, etc.

[0085] The exemplary system 200'” described above for measuring impedance has a 16-bit resolution, requires no signal averaging, and has a fast acquisition time (<200µs).

[0086] Figure 6 Table 500 compares the performance of the exemplary system 200” with that of a prior art system. Column 510 lists the number of features of the two systems to be compared, column 520 contains data for the exemplary system 200” of this disclosure, and column 530 contains data for the prior art system.

[0087] As can be seen from the table, the exemplary system 200'" of this disclosure has 16 times higher sensitivity at comparable power consumption and comparable chip cost (chip size). The exemplary system 200 also has a 4.5 times faster acquisition time than prior art systems. Finally, the exemplary system 200'" has a 16-bit resolution, requiring no further averaging (averaging is possible to reduce noise), while prior art systems have a 10-bit resolution, requiring no averaging.

[0088] It should be understood that the single-pin impedance measurement system of this disclosure can be a system for measuring the impedance of vehicle steering equipment in order to implement a gesture-based human-machine interface system for the vehicle. However, as will be understood by those skilled in the art, the single-pin impedance measurement system can be implemented in other types of devices or architectures that require impedance measurement.

[0089] Figure 7This is another embodiment of the single-pin impedance measurement system 200A according to the present disclosure. System 200A includes a memory LUT_A configured to generate a digital base signal DSIGA. DSIGA provides a test signal input to the system and can be an AC signal. In this embodiment, it can be a sinusoidal signal. The frequency of the DSIGA signal can be adjusted based on system parameters. DSIGA can be considered a modulated signal. Signal S1A can be a sinusoidal signal, and a second signal S2A can be a cosine signal. Signals S1A and S2A can be AC ​​signals. In this embodiment, they can be sinusoidal signals. Signals S1A and S2A can be considered demodulated signals. In some embodiments, DSIGA and the S1A and S2A signals can be synchronized. As described above, in some embodiments, a phase delay can be added to the S1A and S2A signals to correct for signal processing delays independent of DUT_A. For example, signal processing delays introduced by the analog-to-digital converter (ADC) 250A. System 200A also includes a digital-to-analog converter (DAC_A) that acquires the base signal DSIGA and converts it into an analog signal. DAC_A is coupled to one or more filters and buffers 210A. The combination of DAC_A and one or more filters and buffers 210A is used to generate one or more time-varying signals, which may also be referred to as test signals SIGA, SIGA'. The (one or more) time-varying signals SIGA, SIGA' represent DUT_A at pin 220A.

[0090] System 200A may also include a multiplexer 230A configured to combine one or more time-varying signals SIGA, SIGA' into a single signal. This single signal then passes through amplifier 240A.

[0091] System 200A includes an analog-to-digital converter (ADC) 250A, which is configured to convert a signal received from amplifier 240A into a digital signal. ADC 250A is also configured to oversample the signal during the conversion. Coupled to ADC 250A is a filter 260A, which may be, for example, a comb filter. The filtered digital signal then passes through demodulator 270A. For example, the demodulator may be an I / Q demodulator. The demodulator is configured to multiply the filtered digital signal by a first signal to generate a real signal and by a second signal to generate an imaginary signal. These signals pass through integrator 280A. The real and imaginary components are then used to calculate the amplitude and phase of DUT_A.

[0092] In some embodiments, the memory may be, for example, a lookup table. A lookup table is a hardware table that stores data. Data from the lookup table may be used directly in DAC_A to generate a test signal, or in the demodulator to generate a first signal S1A and a second signal S2A. In other embodiments, as understood by those skilled in the art, the memory may be other forms of hardware table.

[0093] Since demodulation is performed in the digital domain, the matching between the first signal S1A and the second signal S2A is given by structure, which is a technique known in the art. However, for system 200A, the multiplication with the first signal S1A and the second signal S2A occurs simultaneously with the same signal, so that each result is acquired only once.

[0094] ADC 250A is an oversampled ADC; in this example embodiment, ADC 250A is a sigma-delta ADC, such as a 1-bit second-order sigma-delta ADC. In alternative embodiments, other types of oversampled ADCs may be used, as understood by those skilled in the art. Since system 200A uses the oversampled ADC 250A, a bandpass filter is no longer needed before ADC conversion. Instead, due to the oversampling method, only a small anti-aliasing low-pass filter is required.

[0095] The test signals used for I / Q demodulation, the first signal S1A and the second signal S2A, are based on the same digital signal DSIGA generated by the memory LUT_A. Therefore, the phase difference is constant and is independent of the analog matching of the three signals.

[0096] The frequency of the test signal is coherent with the first signal S1A and the second signal S2A (demodulated signal), and the number of signal time periods is a prime multiple of the sampled signal. Therefore, all harmonics of the demodulated signal will be completely filtered out by the integrator 280A. In this example embodiment, the integrator 280A is formed as a comb filter with notch filtering at all harmonics. Therefore, a high-precision analog filter is not required before the ADC 250A. Furthermore, the demodulated signal requires a smaller number of samples per time period, which reduces the workload of the memory LUT_A. Fewer samples result in increased harmonics, but due to the comb filter, the system 200A is insensitive to harmonics.

[0097] Similarly, for the test signal generated using DAC_A, the sampling rate of DAC_A can be reduced. This reduces the number of samples in the memory LUT_A, and thus reduces the system area and power consumption by 200A.

[0098] The disclosed system 200A is not very sensitive to harmonics.

[0099] Those skilled in the art will understand that variations in the disclosed arrangement are possible without departing from this disclosure. Therefore, the above description of specific embodiments is merely by way of example and is not intended to be limiting. It will be apparent to those skilled in the art that minor modifications can be made without significantly altering the described operation.

Claims

1. An impedance measurement system, comprising: A signal generator includes a memory and is arranged to generate a digital test signal and at least one digital demodulated signal based on the memory, wherein the digital test signal has a first frequency and the at least one digital demodulated signal has the first frequency; A single pin is provided for supplying an analog test signal based on the digital test signal to the device under test (DUT), and for measuring an analog input signal in response to supplying the analog test signal to the DUT; and A demodulator, configured to receive signals to generate at least one digital demodulated signal indicating the impedance: A first filtered digital signal based on the input signal; and The at least one digital demodulated signal.

2. The impedance measurement system according to claim 1, wherein the at least one demodulated signal comprises a first sine signal and a second sine signal, wherein the second sine signal is generated by phase-shifting the first sine signal by 90 degrees.

3. The impedance measurement system of claim 1 further includes an input processing stage coupled to the single pin and the demodulator, and configured to acquire the analog input signal and generate the first filtered digital signal based on the analog input signal.

4. The impedance measurement system of claim 3, wherein the input processing stage includes an oversampling ADC configured to generate a digital input signal based on the analog input signal.

5. The impedance measurement system according to claim 4, wherein the oversampling ADC is a 1-bit Σ-Δ ADC operating at the system frequency fs.

6. The impedance measurement system of claim 4, wherein the input processing stage includes a filter configured to filter the digital input signal to generate the first filtered digital signal.

7. The impedance measurement system of claim 4, wherein the input processing stage includes an amplifier configured to provide an amplified version of the analog input signal to the oversampled ADC.

8. The impedance measurement system of claim 4, wherein the demodulator includes an I / Q demodulator coupled to the output of the oversampled ADC, the I / Q demodulator being configured to: Multiply the first filtered digital signal by the first sine signal to generate a real component signal indicating the real component of the analog input signal; and The first filtered digital signal is multiplied by the second sine signal to generate a virtual component signal that indicates the virtual components of the analog input signal. The at least one digital demodulated signal is based on the real component signal and / or the imaginary component signal.

9. The impedance measurement system according to claim 8, further comprising: An integrator, coupled to the output of the I / Q demodulator, wherein the integrator includes a frequency response having a notch filter at the frequency of at least one harmonic of the at least one demodulated signal. The integrator is configured to filter the real component signal and the imaginary component signal to generate the at least one digital demodulated signal.

10. The impedance measurement system of claim 1, further comprising a digital-to-analog converter (DAC) coupled to the signal generator to obtain the digital test signal and generate the at least one analog test signal.

11. The impedance measurement system of claim 10, wherein the DAC has a sampling rate smaller than the system frequency fs.

12. The impedance measurement system of claim 11, wherein the at least one analog test signal has a frequency set by multiplying a fraction of the system frequency fs by a prime number.

13. The impedance measurement system of claim 12, wherein the DAC is coupled to one or more filters and / or one or more buffers, the one or more filters and / or the one or more buffers being configured to obtain an output from the DAC and generate the at least one analog test signal.

14. The impedance measurement system according to claim 1, wherein the memory includes a LUT lookup table, the LUT lookup table storing a set of predefined values ​​at corresponding storage addresses for generating the digital test signal and the at least one digital demodulation signal.

15. The impedance measurement system of claim 14, wherein the signal generator is configured to adjust the phase of the at least one digital demodulated signal and / or the digital test signal to correct the phase offset between the first filtered digital signal and the at least one digital demodulated signal.

16. The impedance measurement system of claim 15, wherein the signal generator adjusts the phase of the at least one digital demodulated signal and / or the digital test signal by adding an address offset to a portion of the LUT that generates the at least one digital demodulated signal and / or the digital test signal.

17. The impedance measurement system of claim 16, wherein the signal generator is configured to obtain the address offset from the external system to the impedance measurement system.

18. The impedance measurement system of claim 16 is further configured to determine the address offset during a calibration phase, wherein the calibration phase includes coupling a DUT comprising only capacitive loads to the single pin.

19. The impedance measurement system of claim 16, wherein the memory includes a set of predefined address offset values ​​for corresponding temperature values.

20. The impedance measurement system of claim 1, wherein the single pin is coupled to one or more sensors integrated in the steering wheel of a vehicle, wherein the impedance measurement system is configured to drive the one or more sensors to detect contact between the operator and the steering wheel.

Images