Chip testing method and device, electronic equipment and storage medium

Abstract

The invention provides a chip testing method, which comprises the following steps: carrying out image acquisition on a chip according to preset detection data to obtain a first chip image; and controlling the at least two probes to be in contact with the chip according to the first chip image, and performing image acquisition on the chip and the at least two probes in response to the fact that the pressure detected by the at least two probes reaches a preset pressure threshold value to obtain a second chip image. And identifying the second chip image, and determining whether the at least two probes are in contact with the detection position of the chip or not. And in response to successful contact between the at least two probes and the detection position, outputting a detection signal to the at least one probe, and detecting an output signal of the at least one probe to obtain a chip detection result. Therefore, accurate testing of the chip is realized.

Description

Technical Field

[0001] This application relates to the field of chip validity testing technology, and in particular to a chip testing method. Background Technology

[0002] With the miniaturization and intelligentization demands of communication and microelectronic technologies, bare chips, with their advantages of small size and low cost, are increasingly replacing traditional packaged products and are being used more and more widely in microwave, radio frequency, and power device fields. Before using bare chips, users send them to professional testing institutions for identification and screening. This often requires the use of probe stations and related instruments to test the bare chips to ensure their reliability.

[0003] Currently, in bare chip testing, the determination of test validity mainly involves assessing the effectiveness of probe insertion and the results of electrical parameter tests. This largely relies on manual judgment, making the results highly dependent on the experience of professional testers. There are no clear and strict judgment standards, and it is significantly influenced by human subjectivity. Regarding the assessment of probe insertion effectiveness, different operators have inconsistent standards for judging the location of probe marks, leading to unstable test validity results. In large-scale testing, prolonged visual strain can cause eye fatigue, resulting in misjudgments and missed judgments. Furthermore, manual visual inspection is inefficient and cannot meet the needs of batch testing; minute probe mark misalignments or poor contact are difficult to detect with the naked eye, easily leading to misjudgments of test validity. For the determination of electrical parameter test results, relying solely on instrument feedback is insufficient to fully reflect the physical contact state during testing. When electrical parameter test results are unqualified, it is difficult to quickly pinpoint whether the problem is due to probe contact issues or chip defects. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a chip testing method, apparatus, electronic device and storage medium.

[0005] To achieve the above objectives, this application provides a chip testing method, comprising: acquiring an image of the chip based on preset detection data to obtain a first chip image; controlling at least two probes to contact the chip based on the first chip image; acquiring images of the chip and the at least two probes to obtain a second chip image in response to the pressure detected by the at least two probes reaching a preset pressure threshold; identifying the second chip image to determine whether the at least two probes are in contact with the detection position of the chip; and outputting a detection signal to at least one probe and detecting the output signal of the at least one probe to obtain a chip detection result in response to the successful contact of the at least two probes with the detection position.

[0006] In some embodiments, before acquiring images of the chip based on preset detection data, the method further includes: determining the detection data based on preset chip basic parameters. These basic parameters include at least the chip's external dimensions, number of pads, pad distribution, pin piercing qualification standards, and electrical parameter qualification thresholds. The detection location of the chip is then determined based on the detection data.

[0007] In some embodiments, after acquiring an image of the chip based on preset detection data to obtain a first chip image, the method further includes: determining first position information based on the first chip image, and comparing the first position information with the detection data. In response to a deviation between the first position information and the detection data exceeding a preset first deviation threshold, the positions of at least two probes are fine-tuned to align the at least two probes with the detection position of the chip.

[0008] In some embodiments, recognizing the second chip image to determine whether at least two probes are in contact with the detection location of the chip specifically includes: extracting the second chip image according to a preset image segmentation algorithm to obtain the probe mark contours of at least two probes; calculating the deviation value between the probe mark and the center of the chip pad based on the probe mark contours; and calculating the coverage area of ​​the probe mark on the chip pad. If the deviation value meets a preset deviation threshold and the coverage area meets a preset area threshold, then at least two probes have successfully made contact with the detection location of the chip.

[0009] In some embodiments, the method further includes: in response to the deviation value not meeting the deviation threshold and / or the coverage area not meeting the area threshold, controlling at least two probes to move away from the chip and re-contact the chip, acquiring images of the chip and at least two probes to obtain an updated second chip image.

[0010] In some embodiments, after acquiring an updated second chip image by image acquisition of the chip and at least two probes, the method further includes: setting a retry count; in response to the updated second chip image's deviation value failing to meet a deviation threshold and / or its coverage area failing to meet an area threshold, re-moving the at least two probes away from the chip and re-contacting the chip to update the second chip image; and in response to the number of times the second chip image's deviation value fails to meet the deviation threshold and / or its coverage area fails to meet the area threshold exceeding the retry count, marking the current chip as a chip to be re-inspected.

[0011] In some embodiments, after obtaining the chip detection result, the method further includes: determining whether the chip detection result meets preset chip parameters. In response to the chip detection result not meeting the preset chip parameters, at least two probes are controlled to move away from the chip and re-contact the chip, and images of the chip and at least two probes are acquired to obtain an updated second chip image. The updated second chip image is then identified to determine whether at least two probes are in contact with the detection position of the chip. In response to at least two probes successfully contacting the detection position, a detection signal is output to at least one probe, and the output signal of at least one probe is detected to obtain an updated chip detection result. A detection count is set, and in response to the chip detection result continuously failing to meet the chip parameters more than the detection count is exceeded, the current chip is marked as a defective chip.

[0012] A chip testing apparatus for performing the method as described in any one of claims 1-7, the apparatus comprising: a vision recognition module for acquiring a first chip image and a second chip image; a probe station module for driving probe movement and monitoring contact pressure; a testing instrument module for outputting detection signals to at least one probe and acquiring the output signals of at least one probe; and a host computer module for controlling the vision recognition module, the probe station module, and the testing instrument module.

[0013] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method described in any one of the preceding methods.

[0014] A non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform any of the methods described above.

[0015] As can be seen from the above, the chip testing method provided in this application acquires an image of the chip to obtain a first chip image, enabling the probe to accurately contact the chip based on the first chip image. The method then determines whether the probe is in contact with the chip based on the pressure detected by the probe. After the probe detects that the pressure has reached a pressure threshold, the method acquires an image of the chip to obtain a second chip image. This second chip image allows for further confirmation of whether the probe has successfully contacted the chip, ensuring that the probe and the chip to be tested are in close contact before the test begins. This avoids deviations in the chip testing results due to poor contact. Finally, the test is performed on the premise that the probe and the chip are in good contact, thereby achieving accurate chip testing. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic flowchart of a chip testing method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a chip testing device provided in an embodiment of this application; Figure 3 This is a schematic diagram of a more specific electronic device hardware structure provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0019] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0020] like Figure 1 As shown, this application provides a chip testing method, including: Step S1: Acquire images of the chip based on preset detection data to obtain the first chip image.

[0021] Step S2: Control at least two probes to contact the chip according to the first chip image. In response to the pressure detected by at least two probes reaching a preset pressure threshold, perform image acquisition on the chip and at least two probes to obtain a second chip image.

[0022] Step S3: Identify the second chip image to determine whether at least two probes are in contact with the detection position of the chip.

[0023] In step S4, in response to at least two probes successfully contacting the detection position, a detection signal is output to at least one probe, and the output signal of at least one probe is detected to obtain the chip detection result.

[0024] In this embodiment, the chip to be tested can be a bare chip die that has not undergone the packaging process. The detection location is the metal pad area on the surface of the bare chip. The probe moves in four axes through the electric probe holder of the probe station module. The pressure threshold is monitored by the pressure sensor integrated into the probe station module. The chip detection result is electrical performance data including S-parameters.

[0025] In some embodiments, prior to step S1, the method further includes: Step S101: Determine the test data based on the preset chip basic parameters. These basic parameters include at least the chip's external dimensions, number of pads, pad distribution, pin piercing qualification standards, and electrical parameter qualification thresholds.

[0026] Step S102: Determine the detection position of the chip based on the detection data.

[0027] In this embodiment, the basic chip parameters are pre-imported by the tester through the host computer module. The external dimensions include the length, width, and thickness data of the bare chip. The pad distribution refers to the coordinate position and arrangement of the pads on the chip surface. The pin puncture qualification criteria include the offset threshold between the pin mark center and the pad center and the probe pressure threshold. The electrical parameter qualification thresholds are specifically the qualified range of RF characteristic indicators such as loss S21, VSWR S11, and S22.

[0028] In some embodiments, after step S1, the method further includes: Step S11: Determine the first position information based on the first chip image, and compare the first position information with the detection data.

[0029] Step S12: In response to the deviation between the first position information and the detection data being greater than a preset first deviation threshold, the positions of at least two probes are fine-tuned so that the at least two probes are aligned with the detection position of the chip.

[0030] In this embodiment, the first position information is obtained by the visual recognition module after acquiring the image of the first chip. The size and position feature data of the bare chip are extracted by a dedicated algorithm and converted. The preset first deviation threshold is 0.02mm. The fine adjustment is achieved by the probe station module driving the test vehicle to perform micron-level position correction according to the position adjustment command sent by the host computer.

[0031] In some embodiments, step S3 specifically includes: Step S31: Extract the image from the second chip image according to the preset image segmentation algorithm to obtain the needle mark contours of at least two probes.

[0032] Step S32: Calculate the deviation value between the pin mark and the center of the chip pad based on the pin mark contour, and calculate the coverage area of ​​the pin mark on the chip pad.

[0033] In step S33, in response to the deviation value meeting the preset deviation threshold and the coverage area meeting the preset area threshold, at least two probes successfully contact the detection position of the chip.

[0034] In this embodiment, the image segmentation algorithm is a bare chip-specific algorithm built into the visual recognition module, used to separate the pin mark contour from the second chip image. The deviation value is the Euclidean distance between the geometric center of the pin mark and the geometric center of the pad, and the coverage area is the area ratio of the overlapping area of ​​the pin mark contour and the pad contour. The deviation threshold and the area threshold are determined by the pin puncture qualification standard preset in the host computer module.

[0035] In some embodiments, the method further includes: In step S33, in response to the deviation value not meeting the deviation threshold and / or the coverage area not meeting the area threshold, at least two probes are controlled to move away from the chip and re-contact the chip, and an image is acquired of the chip and at least two probes to obtain an updated second chip image.

[0036] In this embodiment, controlling at least two probes to move away from the chip specifically involves the host computer sending a lift command to the probe station module, the electric probe holder driving the probe to move upward along the Z-axis to detach from the pad surface and re-contact the chip, and the host computer re-sending a needle insertion command to drive the probe to execute the needle insertion process again.

[0037] In some embodiments, after step S33, the method further includes: Step S331: Set the number of retries. In response to the updated second chip image's deviation value failing to meet the deviation threshold and / or its coverage area failing to meet the area threshold, move at least two probes away from the chip and re-engage with the chip to update the second chip image.

[0038] Step S332: In response to the number of times the deviation value corresponding to the second chip image fails to meet the deviation threshold and / or the coverage area fails to meet the area threshold exceeds the number of retries, the current chip is marked as a chip to be re-inspected.

[0039] In this embodiment, the number of retries is set by the tester during the system initialization phase of the host computer module. The chip to be retested is marked as the chip number recorded by the host computer in the test report and marked as "to be retested". At the same time, the probe station module is controlled to automatically move the chip to a dedicated storage area.

[0040] In some embodiments, after step S4, the method further includes: Step S51: Determine whether the chip detection result meets the preset chip parameters.

[0041] In step S52, in response to the chip detection result not meeting the preset chip parameters, at least two probes are controlled to move away from the chip and re-contact the chip, and images of the chip and at least two probes are acquired to obtain an updated second chip image.

[0042] Step S53: Identify the updated second chip image to determine whether at least two probes are in contact with the detection position of the chip.

[0043] In step S54, in response to at least two probes successfully contacting the detection position, a detection signal is output to at least one probe, and the output signal of at least one probe is detected to obtain the updated chip detection result.

[0044] Step S55: Set the number of tests. In response to the number of times the chip test results continuously fail to meet the chip parameters exceeding the number of tests, mark the current chip as a defective chip.

[0045] In this embodiment, the number of tests is preset by the host computer module during the parameter configuration stage. A defective chip is marked as defective by the host computer, and the number of defective chips is counted in the batch test report. The number of tests is used to limit the upper limit of continuous electrical parameter test failures for the same chip. If the limit is exceeded, it is determined that the chip has an inherent defect rather than a contact problem.

[0046] As can be seen from the above embodiments of this application, the chip testing method provided by this application acquires an image of the chip to obtain a first chip image, thereby enabling the probe to accurately contact the chip based on the first chip image. The method also determines whether the probe is in contact with the chip based on the pressure detected by the probe. After the probe detects that the pressure has reached the pressure threshold, the method acquires an image of the chip to obtain a second chip image, thereby confirming whether the probe has successfully contacted the chip based on the second chip image. This ensures that the probe and the chip to be tested are in close contact before the test begins, avoiding deviations in the chip test results due to poor contact. Finally, the test is performed on the premise that the probe and the chip are in good contact, thereby achieving accurate chip testing.

[0047] As an optional implementation, this application can also be implemented by the following steps: Step S10, System Initialization and Parameter Configuration Testers import the basic parameters of the bare chip under test into the host computer: external dimensions, number and distribution type of pads, pin test qualification criteria (including the offset threshold between the pin mark center and the pad center, and the probe pressure threshold), and electrical parameter qualification thresholds (such as loss S21, standing wave ratio S11, S22, etc.).

[0048] The host computer controls the probe station to move the probe and the bare chip to the preset initial position. The vision module automatically calibrates the camera focal length and light source brightness. The vector network analyzer, spectrum analyzer and other test instruments complete the power-on self-test and parameter preset values.

[0049] Step S20: Bare chip positioning and information acquisition The host computer sends an image acquisition command to the vision module, and the camera acquires an image of the bare chip. The bare chip's external dimensions are extracted using an edge detection algorithm, and a dedicated bare chip positioning algorithm (combining template matching and feature point extraction) is used to identify the type and coordinates of the bare chip's pads. Then, based on preset pad topology rules, spacing rules, and symmetry rules, the pad type of each candidate pad region is further verified, and the final pad positioning result is output.

[0050] The host computer compares the actual detected bare chip information with preset parameters. If the deviation is ≤0.02 mm, it is determined to be "positioning qualified" and proceeds to the needle insertion stage. If the deviation is >0.02 mm, the probe station module sends a "position adjustment command" to drive the carrier to perform micron-level correction until the positioning deviation meets the requirements.

[0051] Step S30: Verification of probe insertion and needle insertion effects. Based on the detected actual coordinates of the solder pads, the host computer sends a probe insertion command to the probe station module. The electric probe holder drives the probe to move its X / Y axes above the target solder pads, and the Z-axis adjuster controls the probe to descend at a speed of 0.1 mm / s. Simultaneously, a pressure sensor collects the contact pressure in real time. When the pressure reaches a set threshold, the probe stops descending to prevent damage to the solder pads due to excessive pressure or poor contact due to insufficient pressure.

[0052] The vision module captures contact images between the probe and the pad, and extracts the probe trace contour using an image segmentation algorithm. First, the contact image is analyzed to obtain an image of the bare chip after probe insertion, and the probe trace contour is extracted using the image segmentation algorithm. Next, the probe placement deviation, i.e., the distance between the center of the probe trace and the center of the pad, is analyzed; if it is less than a preset threshold, the position is considered acceptable. Then, the contact integrity is analyzed; if the area of ​​the pad covered by the probe trace is within the acceptable range and there is no obvious loose connection, the contact is considered acceptable.

[0053] If both the position and contact parameters are qualified, the host computer determines that the pin insertion is "valid" and proceeds to the electrical parameter testing stage. If either parameter is unqualified, a pin lifting command is sent and the pin is inserted again. If the pin insertion process is repeated and still unqualified, the chip is marked as a "pending retest" chip and automatically moved to the next bare chip to be tested.

[0054] Step S40: Electrical parameter testing and result determination The host computer sends test commands to the test instrument module, the vector network analyzer outputs radio frequency signals, the spectrum analyzer acquires the chip output signals, and calculates the S-parameters (S11, S21).

[0055] The testing instrument calculates the electrical parameter data and sends it to the host computer. The host computer compares the data with preset pass / fail thresholds. If all electrical parameters are within the threshold range, the test is considered passable, the test data (including test time, chip number, and test result) is recorded, and the process proceeds to the next chip test stage. If any electrical parameter fails, the chip is considered failable, its status is marked, and the data is stored.

[0056] Step S50: Batch test loop and end After completing the single-chip test, the host computer queries the chip number sequence to determine if it is the last chip.

[0057] If it is not the last chip, a carrier movement command is sent to the probe station module to move the next bare chip to the testing station, and steps S20-S40 are repeated. If it is the last chip, the host computer generates a batch test report, including the total number of tests, the number of qualified chips, the number of unqualified chips, and the test time, and automatically stores it in the designated location.

[0058] It should be noted that the method in this embodiment can be executed by a single device, such as a computer or server. The method can also be applied in a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method in this embodiment, and the multiple devices will interact with each other to complete the method.

[0059] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0060] Based on the same inventive concept, corresponding to any of the above embodiments, this application also provides a chip testing device.

[0061] refer to Figure 2 The chip testing apparatus includes: The visual recognition module 100 is used to acquire the first chip image and the second chip image; Probe station module 200 is used to drive the probe to move and monitor the contact pressure; The test instrument module 300 is used to output a detection signal to at least one of the probes and to acquire the output signal of at least one of the probes; The host computer module 400 is used to control the vision recognition module, the probe station module and the test instrument module.

[0062] In some optional embodiments, the host computer module consists of an industrial computer and control software. It is responsible for controlling the entire testing process, storing basic data such as bare chip shape parameters, pad coordinates, and pass / fail criteria, receiving data from the vision module and the test instrument module and comparing and analyzing them, and finally generating a test report containing the reasons for pass / fail. It also issues instructions to other modules and receives status data and test results from each module.

[0063] In some optional embodiments, the visual recognition module includes a high-resolution industrial CCD, an image processor, and a ring light source system. Its core function is to acquire images of the bare chip and extract the chip's size and position using a dedicated algorithm. All image feature data is then converted into digital signals and sent to a host computer.

[0064] In some optional embodiments, the probe station module consists of the probe station itself, an electric probe holder with X, Y, Z, and Theta four-axis adjusters, a test carrier, and a pressure sensor. It can move the bare chip to the test station according to instructions from the host computer and drive the probe holder to precisely insert the probe. Simultaneously, the pressure sensor monitors the probe contact pressure in real time and coordinates with the host computer to complete feedback commands.

[0065] In some optional embodiments, the test instrument module integrates a vector network analyzer, a spectrum analyzer, a signal source, and a DC power supply. It can collect data such as the S-parameters of the bare chip based on the test signals such as the DC output radio frequency signal and DC voltage from the host computer, and send the calculated data to the host computer.

[0066] For ease of description, the above devices are described in terms of function, divided into various modules. Of course, in implementing this application, the functions of each module can be implemented in one or more software and / or hardware.

[0067] The apparatus of the above embodiments is used to implement the corresponding chip testing method in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0068] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the XX method described in any of the above embodiments.

[0069] Figure 3 This embodiment illustrates a more specific hardware structure of an electronic device. The device may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0070] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0071] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0072] The input / output interface 1030 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.

[0073] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0074] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0075] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0076] The electronic devices described above are used to implement the corresponding chip testing methods in any of the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0077] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a non-transitory computer-readable storage medium that stores computer instructions for causing the computer to execute the chip testing method as described in any of the above embodiments.

[0078] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0079] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute the chip testing method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0080] It should be noted that the embodiments of this application can also be further described in the following ways: A chip testing method, comprising: The chip is imaged based on preset detection data to obtain the first chip image; Based on the first chip image, at least two probes are controlled to contact the chip. In response to the pressure detected by the at least two probes reaching a preset pressure threshold, images of the chip and the at least two probes are acquired to obtain a second chip image. The second chip image is identified to determine whether the at least two probes are in contact with the detection location of the chip; In response to the successful contact between the at least two probes and the detection position, a detection signal is output to at least one of the probes, and the output signal of at least one probe is detected to obtain the chip detection result.

[0081] Optionally, before performing image acquisition on the chip based on preset detection data, the method further includes: The test data is determined based on the preset basic parameters of the chip; wherein, the basic parameters include at least the chip's external dimensions, number of pads, pad distribution, pin piercing qualification standards, and electrical parameter qualification thresholds; The detection location of the chip is determined based on the detection data.

[0082] Optionally, after acquiring an image of the chip based on preset detection data to obtain a first chip image, the method further includes: The first location information is determined based on the first chip image, and the first location information is compared with the detection data; In response to the deviation between the first position information and the detection data being greater than a preset first deviation threshold, the positions of the at least two probes are fine-tuned so that the at least two probes are aligned with the detection position of the chip.

[0083] Optionally, the step of identifying the second chip image to determine whether the at least two probes are in contact with the detection location of the chip specifically includes: The image of the second chip is extracted according to a preset image segmentation algorithm to obtain the pin mark contours of the at least two probes; The deviation value between the pin mark and the center of the chip pad is calculated based on the pin mark contour, and the coverage area of ​​the pin mark on the chip pad is calculated. If the deviation value meets a preset deviation threshold and the coverage area meets a preset area threshold, then the at least two probes successfully contact the detection position of the chip.

[0084] Optionally, the method further includes: In response to the deviation value failing to meet the deviation threshold and / or the coverage area failing to meet the area threshold, the at least two probes are controlled to move away from the chip and re-contact the chip to acquire an image of the chip and the at least two probes, thereby obtaining an updated image of the second chip.

[0085] Optionally, after acquiring images of the chip and the at least two probes to obtain an updated image of the second chip, the method further includes: Set the number of retries. In response to the deviation value corresponding to the updated second chip image not meeting the deviation threshold and / or the coverage area not meeting the area threshold, move the at least two probes away from the chip and re-contact the chip to update the second chip image. In response to the number of times the deviation value corresponding to the second chip image fails to meet the deviation threshold and / or the number of times the coverage area fails to meet the area threshold exceeds the number of retries, the current chip is marked as a chip to be re-inspected.

[0086] Optionally, after obtaining the chip detection result, the method further includes: Determine whether the chip detection result meets the preset chip parameters; In response to the chip detection result not meeting the preset chip parameters, the at least two probes are controlled to move away from the chip and re-contact the chip to acquire an image of the chip and the at least two probes, thereby obtaining an updated image of the second chip. The updated image of the second chip is identified to determine whether the at least two probes are in contact with the detection location of the chip; In response to the successful contact between at least two probes and the detection position, a detection signal is output to at least one of the probes, and the output signal of at least one probe is detected to obtain an updated chip detection result; The number of tests is set, and if the number of times the chip test result fails to meet the chip parameters exceeds the number of tests, the current chip is marked as a defective chip.

[0087] A chip testing apparatus for performing the method as described in any one of the preceding methods, the apparatus comprising: A visual recognition module is used to acquire images of the first chip and the second chip; The probe station module is used to drive the probe to move and monitor the contact pressure. A test instrument module is used to output a detection signal to at least one of the probes and to acquire the output signal of at least one of the probes; The host computer module is used to control the vision recognition module, the probe station module, and the test instrument module.

[0088] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method as described in any of the preceding descriptions.

[0089] A non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform any of the methods described above.

[0090] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0091] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0092] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0093] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A chip testing method, comprising: The chip is imaged based on preset detection data to obtain the first chip image; Based on the first chip image, at least two probes are controlled to contact the chip. In response to the pressure detected by the at least two probes reaching a preset pressure threshold, images of the chip and the at least two probes are acquired to obtain a second chip image. The second chip image is identified to determine whether the at least two probes are in contact with the detection location of the chip; In response to the successful contact between the at least two probes and the detection position, a detection signal is output to at least one of the probes, and the output signal of at least one probe is detected to obtain the chip detection result.

2. The chip testing method according to claim 1, wherein, Before performing image acquisition on the chip based on preset detection data, the method further includes: The test data is determined based on the preset basic parameters of the chip; wherein, the basic parameters include at least the chip's external dimensions, number of pads, pad distribution, pin puncture qualification standards, and electrical parameter qualification thresholds; The detection location of the chip is determined based on the detection data.

3. The chip testing method according to claim 1, wherein, After acquiring an image of the chip based on preset detection data to obtain a first chip image, the method further includes: The first location information is determined based on the first chip image, and the first location information is compared with the detection data; In response to the deviation between the first position information and the detection data being greater than a preset first deviation threshold, the positions of the at least two probes are fine-tuned so that the at least two probes are aligned with the detection position of the chip.

4. The chip testing method according to claim 1, wherein, The step of identifying the second chip image and determining whether the at least two probes are in contact with the detection location of the chip specifically includes: The image of the second chip is extracted according to a preset image segmentation algorithm to obtain the pin mark contours of the at least two probes; The deviation value between the pin mark and the center of the chip pad is calculated based on the pin mark contour, and the coverage area of ​​the pin mark on the chip pad is calculated. If the deviation value meets a preset deviation threshold and the coverage area meets a preset area threshold, then the at least two probes successfully contact the detection position of the chip.

5. The chip testing method according to claim 4, wherein, The method further includes: In response to the deviation value failing to meet the deviation threshold and / or the coverage area failing to meet the area threshold, the at least two probes are controlled to move away from the chip and re-contact the chip to acquire an image of the chip and the at least two probes, thereby obtaining an updated image of the second chip.

6. The chip testing method according to claim 5, wherein, After acquiring images of the chip and the at least two probes to obtain an updated image of the second chip, the method further includes: Set the number of retries. In response to the deviation value corresponding to the updated second chip image not meeting the deviation threshold and / or the coverage area not meeting the area threshold, move the at least two probes away from the chip and re-contact the chip to update the second chip image. In response to the number of times the deviation value corresponding to the second chip image fails to meet the deviation threshold and / or the number of times the coverage area fails to meet the area threshold exceeds the number of retries, the current chip is marked as a chip to be re-inspected.

7. The chip testing method according to claim 1, wherein, After obtaining the chip detection results, the process also includes: Determine whether the chip detection result meets the preset chip parameters; In response to the chip detection result not meeting the preset chip parameters, the at least two probes are controlled to move away from the chip and re-contact the chip to acquire an image of the chip and the at least two probes, thereby obtaining an updated second chip image. The updated image of the second chip is identified to determine whether the at least two probes are in contact with the detection location of the chip; In response to the successful contact between the at least two probes and the detection position, a detection signal is output to at least one of the probes, and the output signal of at least one probe is detected to obtain an updated chip detection result; The number of tests is set, and if the number of times the chip test result fails to meet the chip parameters exceeds the number of tests, the current chip is marked as a defective chip.

8. A chip testing apparatus for performing the method as described in any one of claims 1-7, the apparatus comprising: A visual recognition module is used to acquire images of the first chip and the second chip; The probe station module is used to drive the probe to move and monitor the contact pressure. A test instrument module is used to output a detection signal to at least one of the probes and to acquire the output signal of at least one of the probes; The host computer module is used to control the vision recognition module, the probe station module, and the test instrument module.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method as claimed in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1 to 7.

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