PCB electrical performance test system based on multi-channel signal feedback

Abstract

The invention relates to the technical field of electrical measurement, in particular to a PCB (printed circuit board) electrical performance test system based on multichannel signal feedback, which comprises a data acquisition unit used for acquiring impedance deviation of a plurality of differential wire pairs on a printed circuit board through multichannel time domain reflection test. And the data screening unit is used for screening effective impedance deviation related to dielectric layer thickness fluctuation from the impedance deviation of the plurality of differential line pairs. And the model construction unit is used for constructing a lamination alignment error model based on the effective impedance deviation and the spatial position information of the differential line pair corresponding to the effective impedance deviation on the printed circuit board. And the process optimization unit is used for determining process compensation parameters according to the lamination alignment error model and the newly obtained impedance deviation of the printed circuit board, and outputting adjustment guidance for subsequent design or manufacturing of the printed circuit board according to the process compensation parameters. According to the method, the impedance change of the PCB caused by the thickness fluctuation of the dielectric layer can be accurately identified, and a basis is provided for process optimization.

Description

Technical Field

[0001] This invention relates to the field of electrical measurement technology, and more specifically to a PCB board electrical performance testing system based on multi-channel signal feedback. Background Technology

[0002] Printed circuit boards (PCBs) are the core basic components for achieving electrical interconnection in electronic devices, and their electrical performance directly affects signal transmission quality and system reliability. In high-speed digital circuits, differential signal transmission is widely used due to its advantages such as strong anti-interference capability. The impedance matching of differential pairs is a key parameter to ensure signal integrity and usually needs to be evaluated through testing methods such as time-domain reflection.

[0003] In existing technologies, multi-channel testing equipment is commonly used to measure the impedance of differential pairs on PCBs, and the degree of matching is evaluated by comparing the deviation between the measured impedance and the design target impedance. However, process steps such as lamination in PCB manufacturing introduce systematic errors such as dielectric layer thickness fluctuations. These physical changes are directly and complexly reflected in the electrical impedance characteristics. Existing testing and evaluation methods often struggle to effectively distinguish and quantify these impedance changes caused by specific process deviations. This results in test results lacking sufficient accuracy and specificity in guiding subsequent process optimization, thus hindering further improvements in PCB impedance control and product yield. Summary of the Invention

[0004] To address the technical problems of inaccurate PCB impedance matching assessment and lack of precise basis for process optimization caused by dielectric layer thickness fluctuations, the present invention aims to provide a PCB electrical performance testing system based on multi-channel signal feedback. The specific technical solution adopted is as follows: Firstly, a PCB electrical performance testing system based on multi-channel signal feedback is provided, comprising: a data acquisition unit for acquiring impedance deviations of multiple differential pairs on the printed circuit board through multi-channel time-domain reflectometry, wherein the impedance deviation characterizes the degree of deviation between the measured impedance of the differential pairs and a preset reference impedance; a data filtering unit for filtering effective impedance deviations related to dielectric layer thickness fluctuations from the impedance deviations of multiple differential pairs; a model building unit for constructing a lamination alignment error model based on the effective impedance deviations and the spatial position information of the corresponding differential pairs on the printed circuit board, wherein the lamination alignment error model characterizes the mapping relationship between dielectric layer thickness fluctuations and impedance deviations; and a process optimization unit for determining process compensation parameters based on the lamination alignment error model and the newly acquired impedance deviations of the printed circuit board, and outputting adjustment guidance for subsequent printed circuit board design or manufacturing based on the process compensation parameters.

[0005] In one possible design, the data acquisition unit is specifically used to: for each differential line pair on the printed circuit board, control a multi-channel time-domain reflectometer to test the two signal lines of the differential line pair in synchronous trigger mode, obtain the single-ended impedance curves of the two signal lines respectively, and use the single-ended impedance curves to characterize the impedance change characteristics of a single signal line at different transmission line positions; determine the differential impedance curve of the differential line pair based on the single-ended impedance curves of the two signal lines of the differential line pair; and determine the impedance deviation of the differential line pair based on the difference between the differential impedance curve of the differential line pair and the preset reference impedance.

[0006] In one possible design, the data filtering unit is specifically used to: for each differential pair, determine a single-ended impedance symmetry index based on the single-ended impedance curves of the two signal lines of the differential pair; determine an impedance smoothness index based on the impedance variation data of the differential pair with the transmission line position; and determine the impedance deviation of the differential pair as an effective impedance deviation if the single-ended impedance symmetry index is greater than a first preset threshold and the impedance smoothness index is greater than a second preset threshold.

[0007] In one possible design, determining the single-ended impedance symmetry index includes: determining an impedance difference sequence based on the impedance values ​​of the two signal lines in the differential pair at each sampling point, and generating a first quantized value as the single-ended impedance symmetry index by performing exponential decay mapping processing based on the impedance difference sequence; determining the impedance smoothness index includes: determining a first-order differential sequence based on the impedance change of adjacent sampling points on the single-ended impedance curve of one signal line in the differential pair, and generating a second quantized value as the impedance smoothness index by performing exponential decay mapping processing based on the standard deviation of the first-order differential sequence.

[0008] In one possible design, the model building unit includes a spatial interpolation module. This module is used to: determine the bias influence weights of the printed circuit board in the first and second axes based on all effective impedance biases. These bias influence weights characterize the overall strength of the dielectric layer thickness fluctuation's influence on impedance in different axes; for interpolation locations on the printed circuit board other than those corresponding to effective impedance biases, where differential line pairs are not arranged but impedance biases need to be obtained, determine the adjusted distance between the interpolation location and the corresponding location of each effective impedance bias based on the bias influence weights. The adjusted distance is a spatial distance weighted by the axial bias strength; and based on the adjusted distance, use an inverse distance weighted interpolation algorithm to determine the estimated impedance bias value at the interpolation location, thereby generating spatial distribution data of impedance bias covering the test area of ​​the printed circuit board.

[0009] In one possible design, determining the bias influence weights includes: for each effective impedance bias, decomposing the effective impedance bias value into a projection component in a first axis and a projection component in a second axis based on the direction of the line connecting the start and end points of the differential pair corresponding to the effective impedance bias on the printed circuit board plane; determining the bias influence weight corresponding to the first axis based on the projection components of all effective impedance biases in the first axis; and determining the bias influence weight corresponding to the second axis based on the projection components of all effective impedance biases in the second axis.

[0010] In one possible design, the model building unit further includes a model fitting module, which is used to: convert the spatial distribution data of impedance deviation into the distribution data of dielectric layer thickness fluctuation according to a preset conversion coefficient, the preset conversion coefficient being used to characterize the change in dielectric layer thickness corresponding to a unit impedance deviation; fit the dielectric layer thickness fluctuation distribution data using a quadratic surface function; and determine the coefficients of the quadratic surface function using the least squares method to obtain the lamination alignment error model, the least squares method being used to minimize the sum of squared residuals between the theoretical predicted value of the quadratic surface function and the dielectric layer thickness fluctuation distribution data.

[0011] In one possible design, the process optimization unit includes: an error back-calculation module, used to input the impedance deviation of the newly acquired printed circuit board into the lamination alignment error model to determine the dielectric layer thickness fluctuation distribution of the newly acquired printed circuit board; and a compensation determination module, used to determine process compensation parameters based on the statistical characteristics of the dielectric layer thickness fluctuation distribution and a preset process capability boundary, wherein the preset process capability boundary is used to define the limit range of dielectric layer thickness fluctuation that the current production process can control.

[0012] In one possible design, the process optimization unit further includes a design adjustment module, which is used to: determine the adjustment amount for subsequent printed circuit board design based on process compensation parameters. The adjustment amount includes compensation values ​​for at least one of trace width, trace spacing, or preset dielectric layer thickness.

[0013] In one possible design, the process optimization unit also includes a closed-loop control unit, which is used to: continuously collect impedance deviations and corresponding process parameters of each batch of printed circuit boards, update and maintain the process parameter database, monitor the stability of the lamination process through statistical process control methods, and periodically update the lamination alignment error model based on the new batch data accumulated in the process parameter database.

[0014] The present invention has the following beneficial effects: In the PCB electrical performance testing system based on multi-channel signal feedback provided by this invention, the impedance deviation of differential line pairs is accurately obtained by multi-channel time-domain reflection testing. Then, interference factors such as local defects are eliminated through effective impedance deviation screening, ensuring that the data used for modeling only reflects the core process deviation of dielectric layer thickness fluctuation, avoiding the influence of invalid data on the analysis results. The lamination alignment error model constructed based on effective impedance deviation and spatial location information realizes a quantitative mapping between impedance deviation and dielectric layer thickness fluctuation, solving the problem of difficulty in establishing the correlation between electrical parameter deviation and physical process deviation in traditional testing, and accurately characterizing the global process deviation pattern. Simultaneously, based on this model and combined with test data from a new batch of PCB boards, process compensation parameters are determined, and targeted design or manufacturing adjustment guidance can be output, effectively offsetting the adverse effects of lamination alignment errors, improving the impedance matching accuracy and signal integrity of subsequent PCB differential line pairs, and reducing the product defect rate caused by impedance deviation. The entire system forms a closed-loop control from data acquisition and model construction to process optimization, continuously adapting to dynamic process fluctuations, ensuring the stability and consistency of PCB board production quality, and meeting the stringent electrical performance requirements of high-speed electronic equipment. Attached Figure Description

[0015] To more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a PCB board electrical performance testing system based on multi-channel signal feedback, provided in one embodiment of the present invention. Figure 2 This is a schematic diagram of the impedance curves corresponding to two signal lines of a differential line pair provided in an embodiment of the present invention. Detailed Implementation

[0017] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of a PCB board electrical performance testing system based on multi-channel signal feedback proposed according to the present invention. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.

[0018] In embodiments of the present invention, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in embodiments of the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0019] In the description of this invention, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" and "more than one" refer to two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0021] The following description, in conjunction with the accompanying drawings, details a specific solution for a PCB board electrical performance testing system based on multi-channel signal feedback provided by the present invention.

[0022] Please see Figure 1 The diagram illustrates a structural schematic of a PCB board electrical performance testing system based on multi-channel signal feedback, according to an embodiment of the present invention. Figure 1 As shown, the PCB board electrical performance testing system 10 based on multi-channel signal feedback includes a data acquisition unit 11, a data filtering unit 12, a model building unit 13, and a process optimization unit 14.

[0023] The data acquisition unit 11 is used to acquire the impedance deviation of multiple differential line pairs on the printed circuit board through multi-channel time-domain reflectometry. The impedance deviation is used to characterize the degree of deviation between the measured impedance of the differential line pair and the preset reference impedance.

[0024] In some embodiments, for each differential line pair on the printed circuit board, the data acquisition unit 11 is specifically used to first configure the test channels of the multi-channel time domain reflectometer, pairing the test channels in pairs according to the number of differential line pairs, so that each differential line pair corresponds to an independent set of test channel combinations, ensuring that the test data of the two signal lines do not interfere with each other. A Sub-Miniature Version A (SMA) differential probe is used as the signal acquisition element. The P-terminal of the differential probe is connected to the test terminal of the first signal line in the differential line pair, and the N-terminal is connected to the test terminal of the second signal line in the differential line pair. Simultaneously, the ground wire of the differential probe is reliably connected to the reference ground plane of the printed circuit board to reduce the influence of external electromagnetic interference on the acquired signal.

[0025] Subsequently, the multi-channel time-domain reflectometer is controlled to activate the synchronous trigger mode. This mode ensures that the two paired test channels begin acquiring signals at the same time, avoiding measurement errors introduced by differences in time delay between channels. Simultaneously, preset test parameters are configured, including signal rise time, number of sampling points, and time base range. The signal rise time is set to 45 ps to meet the test resolution requirements of high-speed signals; the number of sampling points is set to 2000-5000 to ensure sufficient capture of impedance changes; and the time base range must completely cover the entire transmission line length of the differential pair so that the single-ended impedance curve reflects the impedance characteristics of the entire signal line. After the test is started, the reflected signals of the two signal lines of the differential pair are acquired through two independent test channels. Based on the time-amplitude relationship of the reflected signals, the single-ended impedance curve of each signal line is automatically generated, as exemplified below. Figure 2 The differential line pair shown represents the impedance curves corresponding to the two signal lines. The single-ended impedance curve is used to characterize the impedance variation characteristics of a single signal line at different transmission line positions. Each data point on the curve corresponds to the impedance value at a specific position on the transmission line at a specific time.

[0026] Furthermore, based on the single-ended impedance curves of the two signal lines of the differential pair, and combined with the electromagnetic coupling characteristics of the two signal lines, the differential impedance curve of the differential pair is derived using transmission line theory. The differential impedance is calculated according to the following formula: In the formula, The differential impedance of the differential line pair is the core parameter characterizing the overall impedance characteristics of the differential line pair. The single-ended impedance is the average impedance value at corresponding positions on the single-ended impedance curves of the two signal lines, i.e. ,in The single-ended impedance of the first signal line. This is the single-ended impedance of the second signal line; The coupling coefficient is used to characterize the electromagnetic coupling strength between two signal lines. Its value is obtained by analyzing the correlation between the two single-ended impedance curves. The range is 0-1, when When it indicates that the two signal lines are not coupled, when This indicates that the two signal lines are fully coupled. The differential impedance values ​​of the differential pair at various locations on the transmission line are calculated point-by-point using the above formula. All differential impedance values ​​are then arranged in order of transmission line location to form the differential impedance curve of the differential pair. The differential impedance curve is used to characterize the impedance variation characteristics of the differential pair as a whole at different transmission line locations.

[0027] Finally, based on the difference between the differential impedance curve of the differential pair and the preset reference impedance, the average deviation between the two is calculated, and this average deviation is determined as the impedance deviation of the differential pair. The preset reference impedance is a standard impedance value pre-set during the printed circuit board design phase; its value is determined according to the requirements of high-speed signal transmission and is typically set to 50Ω or 100Ω (e.g., ...). Figure 2 As shown in the embodiment of the invention, taking a preset reference impedance of 50Ω as an example, the calculation process of the average deviation value is as follows: First, calculate the absolute difference between the differential impedance value at each position on the differential impedance curve and the preset reference impedance to obtain several impedance deviation values. Then, perform an arithmetic mean calculation on all impedance deviation values, and the average value obtained is the impedance deviation of the differential pair. impedance deviation It is used to characterize the degree of deviation between the measured impedance of the differential pair and the preset reference impedance. The larger the value, the worse the impedance matching of the differential pair.

[0028] Based on the above steps, the data acquisition unit 11 completes the acquisition of impedance deviations of all differential line pairs on the printed circuit board, and sends the acquired impedance deviations of each differential line pair to the data filtering unit 12 as the original data basis for screening candidate effective impedance deviations.

[0029] The data filtering unit 12 is used to filter out effective impedance deviations related to dielectric layer thickness fluctuations from multiple differential line pairs.

[0030] In some embodiments, firstly, for each differential line pair, based on the single-ended impedance curves of the two signal lines of the differential line pair generated by the data acquisition unit 11, a single-ended impedance symmetry index is determined. This index is used to characterize the consistency of the two signal lines under the influence of global system errors. Its core is to eliminate invalid impedance deviations caused by local asymmetry defects by quantifying the relative stability of the single-ended impedances of the two signal lines. The calculation formula for the single-ended impedance symmetry index is as follows: In the formula, For the first The single-ended impedance symmetry index of each differential line pair has a value range of (0,1]. The closer the value is to 1, the better the relative stability of the single-ended impedance of the two signal lines and the stronger the consistency affected by global system errors. Represented by natural constant An exponential function with base 0 is used to normalize the cumulative difference in single-ended impedance between two signal lines to the (0,1] interval, which facilitates threshold determination. This represents the sampling time number of the single-ended impedance curve, with values ​​ranging from 1 to... , The total number of sampling points for the single-ended impedance curve is consistent with the number of sampling points set in the data acquisition unit 11; For the first The first signal line in the differential pair is at the... The single-ended impedance value at the sampling time is directly extracted from the single-ended impedance curve of the first signal line generated by the data acquisition unit 11. For the first The second signal line in the differential pair is at the... The single-ended impedance value at the sampling time is also extracted from the single-ended impedance curve of the second signal line generated by the data acquisition unit 11; This indicates that the two signal lines are at the 1st... The absolute difference in single-ended impedance values ​​at each sampling moment is used to quantify the impedance deviation between the two signal lines at that moment. The single-ended impedance symmetry index for each differential pair is calculated using the formula above. After that, a quantitative assessment of the single-ended impedance symmetry of the differential line can be completed.

[0031] It should be noted that the change in dielectric thickness caused by fluctuations is gradual, reflected in the impedance curve as a low-order continuous function with a smooth change in its first derivative (the difference between adjacent impedances) and low volatility. In contrast, local defects (such as line breaks or dielectric bubbles) exhibit a step-like change, causing a sudden change in impedance at the defect point. This leads to a sharp increase in the absolute value of the first derivative, abnormal peaks in the difference between adjacent impedances, and significantly increased volatility. If the volatility is small, it indicates a smooth and continuous impedance curve, consistent with the characteristics of dielectric thickness fluctuations, and the impedance data of this differential pair can be used for subsequent modeling. If the volatility is large, a local defect exists, and the data should be discarded.

[0032] Therefore, for each differential pair, based on the impedance variation data of the differential pair with the transmission line position (i.e., the differential impedance curve or single-ended impedance curve generated by the data acquisition unit 11), an impedance smoothness index is determined. This index is used to characterize the continuous variation trend of the impedance curve. Its core function is to eliminate invalid impedance deviations caused by local abrupt defects by quantifying the degree of impedance curve fluctuation. Considering that the consistency of the two signal lines has been verified by the single-ended impedance symmetry, to simplify the calculation and avoid redundancy, the single-ended impedance curve of any one signal line in the differential pair is selected as the calculation basis. The formula for calculating the impedance smoothness index is as follows: In the formula, For the first The impedance smoothness index of each differential line pair has a value range of (0,1]. The closer the value is to 1, the better the smoothness and continuity of the impedance curve, and the absence of obvious impedance abrupt changes. It is an exponential function with the natural constant e as the base, used to normalize the standard deviation of impedance fluctuations to the (0,1] interval, and to adapt to the threshold judgment logic. For the first Selected signal lines in the differential line pairs are at the _th The single-ended impedance value at the sampling time. For this signal line at the 1st The single-ended impedance value at the sampling time, and the absolute difference between the two values. Used to characterize the impedance change magnitude between adjacent sampling times; The value ranges from 2 to This corresponds to all combinations of adjacent sampling points starting from the second sampling time. The standard deviation is calculated from the first-order difference sequence of impedance change amplitudes over all adjacent sampling times. This standard deviation is used to quantify the degree of fluctuation of the impedance curve. The smaller the standard deviation, the smoother the impedance change. The total number of sampling points for the single-ended impedance curve, and the number of sampling points used in the calculation of the single-ended impedance symmetry index. Maintain consistency For the first The single-ended impedance symmetry index of each differential pair is calculated using the formula above. Afterwards, a quantitative assessment of the smoothness and continuity of the differential line impedance curve was completed.

[0033] Finally, based on the single-ended impedance symmetry index calculated above... and impedance smoothness index The effective impedance deviation is then determined. First, a first preset threshold is set. Second preset threshold First preset threshold The second preset threshold is used to define the qualification standard for single-ended impedance symmetry. Both the standard used to define the acceptance criteria for impedance smoothness and continuity are preset based on the PCB board's process requirements, the stability requirements of high-speed signal transmission, and the test accuracy target, with a value range of (0,1]. For example, according to conventional high-speed PCB board test standards, A suitable empirical value is set to 0.85. A suitable empirical value is set to 0.80. When the... Single-ended impedance symmetry index of each differential line pair Greater than the first preset threshold And its impedance smoothness index Greater than the second preset threshold When the impedance deviation of the differential line pair is not affected by local asymmetric defects or local abrupt defects, it only reflects the influence of the global systematic error of dielectric layer thickness fluctuation. Therefore, the impedance deviation corresponding to the differential line pair is determined as the effective impedance deviation.

[0034] Through the above steps, the data filtering unit 12 completes the effective filtering of impedance deviations of all differential line pairs. The effective impedance deviations obtained by filtering will be associated with the spatial position information of the corresponding differential line pairs on the printed circuit board and sent together to the model building unit 13. This provides clean and reliable data support for the accurate construction of the subsequent lamination alignment error model, and avoids invalid data from interfering with the model fitting accuracy and the targeting of process optimization.

[0035] Model building unit 13 is used to build a lamination alignment error model based on the effective impedance deviation and the spatial position information of the differential line pairs corresponding to the effective impedance deviation on the printed circuit board. The lamination alignment error model is used to characterize the mapping relationship between dielectric layer thickness fluctuation and impedance deviation.

[0036] In some embodiments, the model building unit 13 includes a spatial interpolation module.

[0037] The spatial difference module is used to determine the deviation influence weight of the printed circuit board in the first and second axes based on all effective impedance deviations. The deviation influence weight is used to characterize the overall strength of the dielectric layer thickness fluctuation on impedance in different axes. By decomposing the axial components of the effective impedance deviation, the directional characteristics of the global systematic deviation are extracted.

[0038] First, the spatial location information of the differential pair corresponding to each effective impedance deviation on the printed circuit board is obtained. This information includes the coordinates of the starting point of the differential pair. , ) and endpoint coordinates ( , )(in This is the serial number of the effective impedance deviation. Corresponding to the first axis, (corresponding to the second axis), and calculate the orientation angle of the differential line pair on the printed circuit board plane based on the line connecting the start and end points. Direction angle The angle between the line and the first axis is [0, π].

[0039] Subsequently, each effective impedance deviation By direction angle Decomposed into projection components along the first axis and projection components along the second axis, respectively denoted as... , In the formula, For the first An effective impedance deviation is used to characterize the degree of impedance deviation at this location due to fluctuations in the dielectric layer thickness; For the first Each effective impedance deviation corresponds to the direction angle of the differential line pair; Direction angle cosine value, Direction angle The sine value is taken as an absolute value because the weight of the axial deviation only considers the intensity of the deviation and is independent of its direction. For the first The projection component of the effective impedance deviation in the first axis For the first The projection component of the effective impedance deviation in the second axis, and the two components respectively reflect the contribution of the effective impedance deviation to the global deviation in the corresponding axis.

[0040] Based on the axial projection components of all effective impedance deviations, calculate the unnormalized deviation weights for the first and second axial directions. and Then, the bias influence weights are obtained through normalization. (First axial direction) and (Second axial direction), the calculation formula is as follows: In the above formula, This represents the total number of effective impedance deviations. For the first Availability factor of effective impedance deviation ( , For the first The single-ended impedance symmetry index of each differential line pair For the first The impedance smoothness index of each differential line pair has a value range of (0,1]. The closer the value is to 1, the higher the reliability of the effective impedance deviation. This represents the summation of availability factors over all effective impedance deviations; For the first The weighting percentage of each effective impedance deviation is used to assign a larger calculation weight to the effective impedance deviation with higher reliability. The unnormalized deviation weight for the first axis. The unnormalized deviation weights for the second axis are the two values, which respectively reflect the total deviation contribution of the corresponding axis. The value range is (0,1], not zero, and the effective impedance deviation is not zero. Each effective impedance deviation has a non-zero projection on at least one axis. The denominator is not zero; and The normalized bias influence weights have values ​​in the range (0,1) and satisfy the following conditions: The larger the value, the stronger the influence of the dielectric layer thickness fluctuation on the impedance in the corresponding axis.

[0041] Secondly, for the interpolation locations on the printed circuit board (PCB) that, excluding the locations corresponding to effective impedance deviations, do not have differential line pairs but require impedance deviation acquisition, the adjusted distance between the interpolation location and each location corresponding to an effective impedance deviation is calculated based on the determined deviation influence weights. This adjusted distance reflects the anisotropic deviation influence, making the distance calculation more closely match the actual distribution characteristics of dielectric layer thickness fluctuations. Specifically, the test area of ​​the PCB is first divided into grids, with the center point of each grid representing an interpolation location. Its coordinates are ( , ); then extract the first The coordinates of the positions corresponding to each effective impedance deviation ( , (Usually, the coordinates of the midpoint of the difference line pair are taken, i.e.) , ), calculate the position to be interpolated The physical distance from the position corresponding to this effective impedance deviation in the first axial direction and the physical distance along the second axis. .

[0042] Further, based on the influence weights of axial physical distance and deviation, the adjusted distance is calculated. The calculation formula is as follows: In the formula, Position to be interpolated With the The adjusted distance corresponding to each effective impedance deviation; The weighting is determined by the deviation in the first axial direction. The weighting is determined by the deviation in the second axis. The physical distance along the first axis. This represents the physical distance along the second axis. By weighting the physical distance according to the bias influence, the "effective distance" of the axis with a stronger bias influence is lengthened, thereby reducing interference from distant points in subsequent interpolation and improving interpolation accuracy.

[0043] Finally, based on the adjusted distance, an interpolation method based on spatial autocorrelation and distance attenuation effect is used to determine the impedance deviation estimate for each interpolation location, thereby generating spatial distribution data of impedance deviation covering the area under test on the printed circuit board. In practice, based on the principle of spatial autocorrelation (impedance deviations at adjacent locations are strongly correlated), the closer the effective impedance deviation, the greater its influence on the unknown point. The interpolation weight is inversely proportional to the square of the adjusted distance, ensuring that the effective impedance deviation at close range plays a dominant role. The calculation formula for determining the impedance deviation estimate for each interpolation location is as follows: In the formula, Position to be interpolated The estimated impedance deviation; This represents the total number of effective impedance deviations. Position to be interpolated With the The adjusted distance corresponding to each effective impedance deviation; For the first The interpolation weight of each effective impedance deviation at the position to be interpolated is adjusted such that the smaller the distance, the greater the weight. For the first The numerator is the sum of the products of all effective impedance deviations and their corresponding interpolation weights, and the denominator is the sum of all interpolation weights. This weighted average calculation yields the estimated impedance deviation at the position to be interpolated, ensuring spatial continuity while avoiding overfitting.

[0044] It should be noted that, due to the position to be interpolated This refers to the location on the printed circuit board other than the position corresponding to the effective impedance deviation, i.e. It must not be 0. Therefore, it is not 0, so the above formula does not have the problem of calculation abnormality caused by division by zero.

[0045] The above calculations are performed one by one at all interpolation locations within the test area of ​​the printed circuit board to obtain the estimated impedance deviation value for each interpolation location. Combined with the actual effective impedance deviation value, these values ​​are arranged according to coordinate positions to form complete spatial distribution data of impedance deviation. This data, in a continuous spatial distribution form, intuitively presents the global impact trend of dielectric layer thickness fluctuations on the printed circuit board.

[0046] In some embodiments, the model building unit 13 further includes a model fitting module.

[0047] The model fitting module first converts the spatial distribution data of impedance deviation into the distribution data of dielectric layer thickness fluctuation based on preset conversion coefficients, thereby achieving a quantitative mapping from electrical parameter deviations to physical lamination errors. The preset conversion coefficients are the sensitivity coefficients of impedance to dielectric thickness. It is derived based on transmission line theory. Specifically, it is obtained by differentiating the characteristic impedance formula of the transmission line with respect to the dielectric layer thickness, and calibrating it in conjunction with design parameters such as the dielectric constant of the PCB board and the geometric dimensions of the signal lines. The value is taken as a constant and is used to characterize the change in dielectric layer thickness corresponding to a unit impedance deviation. The unit is usually μm / Ω. The formula for calculating the dielectric layer thickness fluctuation value is as follows: In the formula, This is the dielectric layer thickness fluctuation value, used to characterize the degree of deviation between the actual thickness of the dielectric layer and the design target thickness. A positive value indicates that the actual thickness is greater than the design thickness, and a negative value indicates that the actual thickness is less than the design thickness. The preset conversion factor, whose value is determined through the aforementioned calibration process, reflects the sensitivity of impedance to changes in dielectric thickness. This represents the impedance deviation value in the spatial distribution data of impedance deviation.

[0048] Furthermore, for each impedance deviation value in the spatial distribution data of impedance deviation... Perform the above calculations one by one to obtain the dielectric layer thickness fluctuation value at each corresponding location. Combined with the spatial coordinates of each location ( , This generates dielectric layer thickness fluctuation distribution data covering the tested area of ​​the printed circuit board. Presented in the form of "coordinate-thickness fluctuation value," this data fully reflects the global continuous distribution characteristics of dielectric layer thickness fluctuation on the PCB board, providing fundamental data for subsequent function fitting.

[0049] In the formula, coordinates on the PCB board The predicted value of the dielectric layer thickness fluctuation at that location, i.e., the output of the quadratic surface function; and These are the first and second axial coordinates on the PCB board, respectively, consistent with the axial definition in the spatial interpolation module 131, and their value range covers the entire coordinate interval of the area to be measured on the PCB board. , , , , , Let be the unknown coefficients of the quadratic surface function, where For constant terms, , These are the coefficients of the first and second linear terms, respectively. , These are the coefficients of the quadratic terms in the first and second axes, respectively. These are the coefficients of the cross terms; all coefficients together determine the shape and position of the quadratic surface. The term representing the square of the first axial coordinate. The term representing the square of the second axial coordinate. This is the cross product term of the coordinates of the first and second axes, used to characterize the coupling effect between the axes.

[0050] Further, the dielectric layer thickness fluctuation distribution data (i.e., the coordinates of each location and the corresponding dielectric layer thickness fluctuation values) are substituted into the quadratic surface function to construct an overdetermined system of equations. Parameter estimation is performed using the least squares method; the parameters can be obtained by minimizing the sum of the squares of the errors between the measured residuals and the model residuals. , , , , , The optimal solution is obtained to derive the lamination alignment error model. This lamination alignment error model can determine the lamination alignment error based on the coordinates of any position on the PCB board. It outputs the corresponding predicted value of dielectric layer thickness fluctuation, accurately characterizing the mapping relationship between dielectric layer thickness fluctuation and impedance deviation.

[0051] The process optimization unit 14 is used to determine process compensation parameters based on the lamination alignment error model and the impedance deviation of the newly acquired printed circuit board, and output adjustment guidance for subsequent printed circuit board design or manufacturing based on the process compensation parameters.

[0052] In some embodiments, the process optimization unit includes an error back-calculation module and a compensation determination module.

[0053] The error back-calculation module is used to input the impedance deviation of newly acquired printed circuit boards into the lamination alignment error model to determine the dielectric layer thickness fluctuation distribution of this batch of printed circuit boards. The impedance deviation of the newly acquired printed circuit boards needs to be obtained through the same test process as the data acquisition unit 11 (i.e., controlling a multi-channel time domain reflectometer to test multiple differential line pairs on the new batch of PCBs in synchronous trigger mode, generating single-ended impedance curves and differential impedance curves, and finally calculating the impedance deviation of each differential line pair); at the same time, it needs to be filtered by the data filtering unit 12 to remove invalid data affected by local defects, retaining only the effective impedance deviation related to dielectric layer thickness fluctuation, to ensure the reliability of the data input to the model.

[0054] This will further reduce the effective impedance deviation after screening. and its corresponding spatial coordinates ( , The lamination alignment error model is constructed by inputting each input into model building unit 13. Combined with preset conversion coefficients (Consistent with model fitting module 132, representing the change in dielectric layer thickness corresponding to a unit impedance deviation), the formula for calculating the dielectric layer thickness fluctuation value at each effective impedance deviation position is as follows: Then, based on the measured effective impedance deviation at each corresponding position of the effective impedance deviation, the result is processed by a preset conversion factor. And the lamination alignment error model output based on this position Optimization algorithms such as the least squares method are used to find an optimal scaling factor. The goal is to minimize the overall difference between the two. , For the first The dielectric layer thickness fluctuation value corresponding to each effective impedance deviation For the first The position corresponding to each effective impedance deviation This represents the total number of effective impedance deviations. The scaling factor is then obtained. Then, the dielectric layer thickness fluctuation value at any location on the current printed circuit board can be output. After traversing all points, output the current dielectric layer thickness fluctuation distribution of the printed circuit board.

[0055] The compensation determination module is used to perform statistical analysis on the dielectric layer thickness fluctuation distribution of newly acquired printed circuit boards, calculate its statistical characteristics (such as standard deviation), and calculate the maximum compensable lamination alignment error range based on the principles of Statistical Process Control (SPC) and preset process capability boundaries (such as 3 times the standard deviation). As a process compensation parameter In subsequent PCB design iterations, symmetrical reserves will be made based on the design target values ​​of key parameters (such as trace width and preset dielectric layer thickness). The process margin is sufficient to cover the dielectric layer thickness in future production near its expected value (which can be approximated by process adjustments to approach the design target). Random fluctuations within a certain range are mitigated to ensure impedance stability.

[0056] In some embodiments, the process optimization unit 14 further includes a design adjustment module. The design adjustment module is used to determine the adjustment amount for subsequent printed circuit board design based on process compensation parameters. The adjustment amount includes compensation values ​​for at least one of trace width, trace spacing, or preset dielectric layer thickness.

[0057] The formula for determining the design adjustment amount is as follows: In the formula, For design parameters The adjustment amount (compensation value), if For the trace width, then This is the adjustment value for the trace width, in micrometers. A positive value increases the trace width, and a negative value decreases the trace width. For the trace spacing, then This is the adjustment value for trace spacing, in micrometers. A positive value increases the trace spacing, and a negative value decreases the trace spacing. If a predetermined thickness is set for the dielectric layer, then... The adjustment value for the preset thickness of the dielectric layer, in micrometers. A positive value indicates an increase in the preset thickness of the dielectric layer, and a negative value indicates a decrease in the preset thickness of the dielectric layer. The parameter sensitivity coefficient is a dimensionless constant that characterizes the design parameters through theoretical calculations or simulation calibration. Effectiveness of compensating for thickness fluctuations; For design parameters The original design target value; These are process compensation parameters; This is the original design thickness of the dielectric layer, and is not zero.

[0058] Furthermore, the design adjustment module outputs one or more design adjustment instructions, such as adjusting the trace width of the critical differential pair from the design value. Adjusted to , Based on the above formula Calculated when the trace width is ; Adjust the trace spacing of the critical differential pairs from the design value Adjusted to , Based on the above formula Calculated when the trace spacing is The preset thickness of the dielectric layer is adjusted from the design value. Adjusted to , Based on the above formula Calculated when the thickness of the dielectric layer is preset. These adjustment instructions will be directly input into the computer-aided design system or as part of the design specifications to guide the design of the next version of the printed circuit board. This allows for the quantitative incorporation of process fluctuations from manufacturing measurements into the design in advance, enabling feedback-based preventative design optimization and improving product yield and consistency.

[0059] In some embodiments, the process optimization unit 14 further includes a closed-loop control unit. The closed-loop control unit is used to continuously collect the impedance deviations and corresponding process parameters of each batch of printed circuit boards, update and maintain the process parameter database, monitor the stability of the lamination process through statistical process control methods, and periodically update the lamination alignment error model based on the new batch data accumulated in the process parameter database.

[0060] The closed-loop control module is specifically used to continuously collect data from the entire production and testing chain of each batch of printed circuit boards and store it in a structured manner in the process parameter database. Each database record is associated with a unique production batch number and includes, but is not limited to, the following fields: Measured data: Impedance deviation of all valid differential pairs in this batch. and its position coordinates ( , Model output: Thickness fluctuation distribution of this batch generated by the error back-calculation module. and its statistical characteristics (mean) Standard deviation Process parameters: Key production parameters used in this batch (such as press pressure, lamination temperature, resin type, etc.) and the final determined process compensation parameters. Timestamp: The time when the data was collected.

[0061] The closed-loop control module is also used to employ statistical process control methods, using the average value of the dielectric layer thickness fluctuation across batches. and standard deviation As the core monitoring indicator, XR control charts are used to achieve real-time monitoring of process stability. First, based on data from historical stable batches (typically 20 consecutive qualified batches) in the database, the upper control limit (UCL), lower control limit (LCL), and centerline (CL) of the control chart are calculated. For each new batch, the average value of that batch is calculated. and standard deviation If the data points are marked on the XR control chart and fall within the control limits without continuous (e.g., 5 data points) deviations from the center line or continuous upward / downward trends, the process is considered stable. If the data points exceed the control limits or show abnormal trends, an early warning is immediately triggered, prompting operators to check for potential problems such as lamination equipment and material batches, and the results are entered into the database.

[0062] The closed-loop control module is also used to periodically update the lamination alignment error model based on new batch data accumulated in the process parameter database. For example, every five new batches of data are accumulated, an automatic model update is triggered. The model update process includes first selecting data from the process parameter database from multiple recent and complete batches, merging all effective thickness fluctuation data points from all batches to form an expanded training dataset; then, using the new training dataset as input, sending it to the model building unit 13, completely re-executing the model building process, and fitting a new set of optimal model parameters based on the new training dataset using the least squares method. Finally, the new model replaces the old model. Before or after the replacement, historical data or retained test batch data can be used to verify the prediction accuracy of the new model, and the update record (time, data batch used, comparison of new and old parameters) is saved to the database.

[0063] Understandably, in the PCB electrical performance testing system based on multi-channel signal feedback provided in this embodiment of the invention, multi-channel time-domain reflection testing is used to accurately obtain the impedance deviation of differential line pairs. Then, interference factors such as local defects are eliminated through effective impedance deviation screening, ensuring that the data used for modeling only reflects the core process deviation of dielectric layer thickness fluctuation, thus avoiding the influence of invalid data on the analysis results. The lamination alignment error model constructed based on effective impedance deviation and spatial location information realizes a quantitative mapping between impedance deviation and dielectric layer thickness fluctuation, solving the problem of difficulty in establishing the correlation between electrical parameter deviation and physical process deviation in traditional testing, and accurately characterizing the global process deviation pattern. Simultaneously, relying on this model and combining it with test data from a new batch of PCB boards to determine process compensation parameters, targeted design or manufacturing adjustment guidance can be output, effectively offsetting the adverse effects of lamination alignment errors, improving the impedance matching accuracy and signal integrity of subsequent PCB differential line pairs, and reducing product defect rates caused by impedance deviation. The entire system forms a closed-loop control from data acquisition and model construction to process optimization, continuously adapting to dynamic process fluctuations, ensuring the stability and consistency of PCB board production quality, and meeting the stringent electrical performance requirements of high-speed electronic equipment.

[0064] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0065] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

Claims

1. A PCB board electrical performance testing system based on multi-channel signal feedback, characterized in that, include: The data acquisition unit is used to acquire the impedance deviation of multiple differential line pairs on the printed circuit board through multi-channel time-domain reflectometry. The impedance deviation is used to characterize the degree of deviation between the measured impedance of the differential line pair and the preset reference impedance. The data filtering unit is used to filter out effective impedance deviations related to dielectric layer thickness fluctuations from the impedance deviations of the plurality of differential line pairs. The model building unit is used to build a lamination alignment error model based on the effective impedance deviation and the spatial position information of the differential line pairs corresponding to the effective impedance deviation on the printed circuit board. The lamination alignment error model is used to characterize the mapping relationship between dielectric layer thickness fluctuation and impedance deviation. The process optimization unit is used to determine process compensation parameters based on the lamination alignment error model and the impedance deviation of the newly acquired printed circuit board, and output adjustment guidance for subsequent printed circuit board design or manufacturing based on the process compensation parameters.

2. The PCB board electrical performance testing system based on multi-channel signal feedback according to claim 1, characterized in that, The data acquisition unit is specifically used for: For each differential line pair on the printed circuit board, the multi-channel time domain reflectometer is controlled to test the two signal lines of the differential line pair in synchronous trigger mode to obtain the single-ended impedance curves of the two signal lines respectively. The single-ended impedance curves are used to characterize the impedance change characteristics of a single signal line at different transmission line positions. The differential impedance curve of the differential line pair is determined based on the single-ended impedance curves of the two signal lines of the differential line pair. The impedance deviation of the differential line pair is determined based on the difference between the differential impedance curve of the differential line pair and the preset reference impedance.

3. The PCB board electrical performance testing system based on multi-channel signal feedback according to claim 1, characterized in that, The data filtering unit is specifically used for: For each differential line pair, the single-ended impedance symmetry index is determined based on the single-ended impedance curves of the two signal lines of the differential line pair. Based on the impedance variation data of the differential pair with the transmission line position, an impedance smoothness index is determined. When the single-ended impedance symmetry index is greater than a first preset threshold and the impedance smoothness index is greater than a second preset threshold, the impedance deviation of the differential pair is determined as the effective impedance deviation.

4. The PCB board electrical performance testing system based on multi-channel signal feedback according to claim 3, characterized in that, Determining the single-ended impedance symmetry index includes: determining the impedance difference sequence based on the impedance values ​​of the two signal lines at each sampling point of the differential line pair, and generating a first quantization value as the single-ended impedance symmetry index by performing exponential decay mapping processing based on the impedance difference sequence. Determining the impedance smoothness index includes: determining a first-order differential sequence based on the impedance change of adjacent sampling points on the single-ended impedance curve of one signal line in the differential line pair, and performing exponential decay mapping processing based on the standard deviation of the first-order differential sequence to generate a second quantization value as the impedance smoothness index.

5. The PCB board electrical performance testing system based on multi-channel signal feedback according to claim 1, characterized in that, The model building unit includes a spatial interpolation module, which is used for: Based on all effective impedance deviations, the deviation influence weights of the printed circuit board in the first and second axes are determined. These deviation influence weights are used to characterize the overall strength of the impedance effect of dielectric layer thickness fluctuations in different axes. For the interpolation positions on the printed circuit board that are not equipped with differential line pairs but for which impedance deviation needs to be obtained, except for the positions corresponding to the effective impedance deviation, the adjusted distance between the interpolation positions and the positions corresponding to each effective impedance deviation is determined according to the deviation influence weight. The adjusted distance is the spatial distance after weighting by the axial deviation intensity. Based on the adjusted distance, an inverse distance weighted interpolation algorithm is used to determine the impedance deviation estimate of the location to be interpolated, so as to generate impedance deviation spatial distribution data covering the area to be tested on the printed circuit board.

6. The PCB board electrical performance testing system based on multi-channel signal feedback according to claim 5, characterized in that, Determine the weight of the impact of the bias, including: For each effective impedance deviation, the value of the effective impedance deviation is decomposed into a projection component in the first axis and a projection component in the second axis according to the direction of the line connecting the start and end points of the differential line pair corresponding to the effective impedance deviation on the plane of the printed circuit board. The deviation influence weight corresponding to the first axis is determined based on the projection components of all effective impedance deviations on the first axis. The deviation influence weight corresponding to the second axis is determined based on the projection components of all effective impedance deviations onto the second axis.

7. The PCB board electrical performance testing system based on multi-channel signal feedback according to claim 5, characterized in that, The model building unit further includes a model fitting module, which is used for: The impedance deviation spatial distribution data is converted into dielectric layer thickness fluctuation distribution data according to a preset conversion coefficient, and the preset conversion coefficient is used to characterize the amount of dielectric layer thickness change corresponding to a unit impedance deviation. The thickness fluctuation distribution data of the dielectric layer is fitted using a quadratic surface function; The coefficients of the quadratic surface function are determined by the least squares method to obtain the lamination alignment error model. The least squares method is used to minimize the sum of squared residuals between the theoretical predicted value of the quadratic surface function and the thickness fluctuation distribution data of the medium layer.

8. The PCB board electrical performance testing system based on multi-channel signal feedback according to claim 1, characterized in that, The process optimization unit includes: The error back-calculation module is used to input the impedance deviation of the newly acquired printed circuit board into the lamination alignment error model to determine the dielectric layer thickness fluctuation distribution of the newly acquired printed circuit board. The compensation determination module is used to determine the process compensation parameters based on the statistical characteristics of the dielectric layer thickness fluctuation distribution and the preset process capability boundary. The preset process capability boundary is used to define the limit range of dielectric layer thickness fluctuation that the current production process can control.

9. The PCB board electrical performance testing system based on multi-channel signal feedback according to claim 8, characterized in that, The process optimization unit further includes a design adjustment module, which is used for: Based on the process compensation parameters, the adjustment amount for subsequent printed circuit board design is determined, and the adjustment amount includes compensation values ​​for at least one of trace width, trace spacing, or preset dielectric layer thickness.

10. The PCB board electrical performance testing system based on multi-channel signal feedback according to claim 8, characterized in that, The process optimization unit further includes a closed-loop control unit, which is used for: We continuously collect impedance deviations and corresponding process parameters for each batch of printed circuit boards, update and maintain the process parameter database, and monitor the stability of the lamination process through statistical process control methods. Based on the new batch data accumulated in the process parameter database, the lamination alignment error model is periodically updated.

Images