Data processing method and device, electronic equipment and storage medium

Abstract

The invention provides a data processing method which comprises the steps that data of a sparse matrix is divided into a plurality of first data blocks, each first data block comprises a first number of elements, and the first number is determined according to the bit width of a register; zero elements in the multiple first data blocks are marked and compressed, multiple second data blocks are obtained, each second data block comprises an index head and non-zero elements, and the index heads are used for representing position information of the zero elements and the non-zero elements in the first data blocks; loading the plurality of second data blocks into a memory; and when the calculation task is executed, performing decompression processing on the plurality of second data blocks to obtain a plurality of first data blocks, and scheduling the plurality of first data blocks into the register. The zero elements in the sparse matrix are subjected to lossless compression, waste of storage space is reduced, and therefore storage efficiency is improved.

Description

Technical Field

[0001] This disclosure relates to the field of artificial intelligence technology, and more specifically, to a data processing method and apparatus, electronic device and storage medium. Background Technology

[0002] With the development of artificial intelligence (AI) technology, deep learning models have achieved great success in fields such as computer vision and natural language processing. However, as deep learning models become increasingly large, the number of parameters and computational demands increase, limiting their use on resource-constrained hardware platforms, such as edge computing and mobile devices. Therefore, it is necessary to compress deep learning models to reduce computational and storage requirements and accelerate model training and inference.

[0003] In related technologies, model parameters can be compressed through pruning, quantization, and other methods. Quantization converts model parameters from floating-point numbers to integers; however, the quantized matrix is ​​sparse, meaning it contains a large number of zero elements. Since zero and non-zero elements occupy the same amount of memory resources, this leads to a waste of memory. Summary of the Invention

[0004] In view of the above problems, the purpose of this disclosure is to provide a data processing method and apparatus, electronic device and storage medium that reduces the waste of storage space by losslessly compressing the zero elements in a sparse matrix.

[0005] According to a first aspect of this disclosure, a data processing method is provided, comprising: dividing the data of a sparse matrix into a plurality of first data blocks, each first data block including a first number of elements, wherein the first number is determined according to the bit width of a register; marking and compressing the zero elements in the plurality of first data blocks to obtain a plurality of second data blocks, each second data block including an index header and non-zero elements, the index header being used to characterize the position information of the zero and non-zero elements in the first data blocks; loading the plurality of second data blocks into a memory; and, when performing a computation task, decompressing the plurality of second data blocks to obtain a plurality of first data blocks, and scheduling the plurality of first data blocks into a register.

[0006] Optionally, marking and compressing zero elements in multiple first data blocks to obtain multiple second data blocks includes: identifying zero and non-zero elements in the first data blocks; generating an index header based on the positions of the zero and non-zero elements in the first data blocks, wherein each bit of the index header corresponds one-to-one with an element in the first data block and is used to indicate the position status of the corresponding element; determining whether the number of zero elements in the first data blocks is greater than a preset value; and when the number of zero elements in the first data blocks is greater than the preset value, combining the index header and the non-zero elements in the first data blocks into a second data block.

[0007] Optionally, marking and compressing zero elements in multiple first data blocks to obtain multiple second data blocks includes: when the number of zero elements in the first data block is less than or equal to a preset value, the first data block is not compressed, and the index header and the first data block are combined into a second data block.

[0008] Optionally, decompressing multiple second data blocks includes restoring the non-zero and zero elements in the second data blocks to their corresponding positions in the sparse matrix based on the index header.

[0009] Optionally, the data processing method further includes: dividing a plurality of second data blocks into a plurality of first data packets, each data packet including a second number of second data blocks, wherein the second number is determined based on the bit width of the register; marking and compressing the second data blocks with all-zero elements in each first data packet to obtain a plurality of second data packets, each second data packet including metadata and second data blocks with non-all-zero elements, wherein the metadata is used to characterize the element type of each second data block in the second data packet; loading the plurality of second data packets into memory; and decompressing the plurality of second data packets to obtain a plurality of first data blocks when performing a computation task, and scheduling the plurality of first data blocks into registers.

[0010] Optionally, marking and compressing the second data blocks containing all-zero elements in each first data packet to obtain multiple second data packets includes: identifying the element type of the second data blocks in the first data packet, wherein the element type includes all-element, all-zero, and non-all-zero elements; generating metadata based on the element type of the second data blocks, wherein each two bits of the metadata correspond to each second data block in the first data packet and are used to indicate the element type of the corresponding second data block; compressing the second data blocks containing all-element and all-zero elements; and combining the metadata, the second data blocks containing all-element and non-all-zero elements into a second data packet.

[0011] Optionally, decompressing multiple second data packets includes: decompressing the second data packets according to metadata to recover the original second data block; and restoring the non-zero elements and zero elements in the second data block to their corresponding positions in the sparse matrix according to the index header of the second data block.

[0012] Optionally, the data processing method further includes: determining the size of each second data block based on the index header of the second data block; accumulating the sizes of all second data blocks preceding the second data block as the offset address of the second data block; and creating a corresponding mapping entry for each second data block to form an address mapping table, wherein the mapping entry includes a first offset address.

[0013] Optionally, the non-zero elements in the second data block are arranged closely together to form the data body; the index header and data body of the second data block are stored together, the source address points to the starting address of the index header of the first second data block, and the first offset address points to the starting address of the index header of the corresponding second data block; or, the index header and the first offset address of the second data block are stored together contiguously, and the data body is stored separately, the source address points to the starting address of the index header of the first second data block, and the first offset address points to the starting address of the data body of the corresponding second data block.

[0014] Optionally, the data processing method further includes: determining the size of each second data packet based on the metadata of the second data packet and the index header of the second data block in the second data packet; accumulating the sizes of all second data packets preceding the second data packet as the offset address of the second data packet; and creating a corresponding mapping entry for each second data packet to form an address mapping table, wherein the mapping entry includes at least the second offset address.

[0015] Optionally, the non-zero elements in the second data block are arranged closely to form the data body; the index header of the second data block is stored together with the data body, the source address points to the starting address of the metadata of the first second data packet, and the second offset address points to the starting address of the index header of the first second data block in each second data packet; or, the source address points to the starting address of the metadata of the first second data packet, the second offset address points to the starting address of the index header of the first second data block in each second data packet, and the first offset address points to the starting address of the data body of each second data block in each second data packet.

[0016] According to one aspect of this disclosure, a data processing apparatus is provided, comprising a compression unit, a scheduling unit, a memory, a decompression unit, and a register. The compression unit is configured to divide sparse matrix data into multiple first data blocks, each first data block comprising a first number of elements, wherein the first number is determined according to the bit width of the register; to mark and compress zero elements in the multiple first data blocks to obtain multiple second data blocks, each second data block comprising an index header and non-zero elements, the index header representing the position information of zero and non-zero elements in the first data blocks; the scheduling unit is configured to load the multiple second data blocks into the memory and to schedule the multiple second data blocks to the decompression unit during computational tasks; the decompression unit is configured to decompress the multiple second data blocks to obtain multiple first data blocks and schedule the multiple first data blocks to the register.

[0017] Optionally, the compression unit is further configured to divide the multiple second data blocks into multiple first data packets, each data packet including a second number of second data blocks, wherein the second number is determined based on the bit width of the register; to mark and compress the second data blocks of all elements and all zero elements in each first data packet to obtain multiple second data packets, each second data packet including metadata, second data blocks of all elements and non-all zero elements, wherein the metadata is used to characterize the element type of the second data block; the scheduling unit is configured to load the multiple second data packets into the memory and to schedule the multiple second data packets to the decompression unit when performing a computation task; the decompression unit is configured to decompress the multiple second data packets to obtain multiple first data blocks and schedule the multiple first data blocks into the register.

[0018] According to one aspect of this disclosure, an electronic device is provided, the electronic device including a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for implementing connection communication between the processor and the memory, wherein the program is executed by the processor to implement the data processing method described above.

[0019] According to one aspect of this disclosure, a computer-readable storage medium is provided that stores one or more programs, which can be executed by one or more processors to implement the data processing method described above.

[0020] The data processing method, apparatus, electronic device, and storage medium disclosed herein divide the data of a sparse matrix into multiple first data blocks, each first data block comprising a first number of elements, wherein the first number is determined according to the bit width of a register; zero elements in the multiple first data blocks are marked and compressed to obtain multiple second data blocks, each second data block comprising an index header and non-zero elements, wherein the index header is used to characterize the position information of zero elements and non-zero elements in the first data blocks; by performing lossless compression on zero elements in the sparse matrix, storage space waste is reduced, thereby improving storage efficiency.

[0021] Furthermore, each bit of the index header corresponds one-to-one with an element in the first data block, indicating the position status of the corresponding element. Here, 0 indicates that the position is a zero element, and 1 indicates that the position is a non-zero element. This allows for rapid compression and decompression of data, improving data read and write efficiency.

[0022] Furthermore, by compressing the second data block containing all elements and all zero elements, storage space waste can be further reduced and storage efficiency improved, especially for large-scale sparse matrix data.

[0023] Furthermore, by accurately calculating the size and offset address of each second data block or second data packet, memory resources can be utilized more effectively, memory fragmentation can be avoided, and memory usage efficiency can be improved.

[0024] Furthermore, by constructing an address mapping table, data blocks or data packets can be quickly located, improving decompression efficiency. Attached Figure Description

[0025] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0026] Figure 1 This is a system architecture diagram of a data processing method applied according to an embodiment of the present disclosure;

[0027] Figure 2 This is a schematic diagram of a data processing apparatus according to an embodiment of the present disclosure;

[0028] Figure 3 This is a general flowchart of a data processing method according to an embodiment of the present disclosure;

[0029] Figure 4 This is a flowchart of step S320 according to an embodiment of the present disclosure;

[0030] Figures 5a-5c This is a schematic diagram of a first data block being compressed into a second data block according to an embodiment of the present disclosure;

[0031] Figure 6 This is a schematic diagram of the address mapping table of a second data block according to an embodiment of the present disclosure;

[0032] Figure 7 This is a flowchart of step S406 according to an embodiment of the present disclosure;

[0033] Figure 8 This is a schematic diagram of the address mapping table of a second data block according to an embodiment of the present disclosure;

[0034] Figure 9 This is a general flowchart of a data processing method according to another embodiment of the present disclosure;

[0035] Figure 10 This is a flowchart of step S940 according to another embodiment of the present disclosure;

[0036] Figure 11 This is a schematic diagram of a second data packet according to an embodiment of the present disclosure;

[0037] Figure 12 This is a schematic diagram of the address mapping table of the second data packet according to an embodiment of the present disclosure;

[0038] Figure 13 This is a flowchart of step S1006 according to another embodiment of the present disclosure;

[0039] Figure 14 This is a schematic diagram of the address mapping table of the second data packet according to an embodiment of the present disclosure;

[0040] Figure 15 This is a flowchart of step 960 according to another embodiment of the present disclosure;

[0041] Figure 16 This is a schematic diagram of a data processing apparatus according to an embodiment of the present disclosure.

[0042] Figure 17 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0043] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various portions in the drawings are not drawn to scale.

[0044] The specific embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and examples.

[0045] A Compute Unit (CU) is a processing module in electronic devices such as GPUs. A GPU can include multiple Compute Units, which contain multiple execution units. A Compute Unit can be viewed as a processing core within a GPU, and each Compute Unit can independently execute instructions and process data in parallel.

[0046] Shared memory refers to a certain amount of memory within a processor that can be accessed by different computing units.

[0047] Global memory refers to the memory within a processor that can be accessed by all computing units.

[0048] Tensor Core: A tensor processor in a Computational Unit (CU) is used to perform tensor matrix operations, such as multiplying two tensor matrices (using the Matmul function).

[0049] In existing technologies, quantization converts model parameters from floating-point numbers to integers. However, the quantized matrix is ​​sparsity, meaning it contains a large number of zero values. Zero and non-zero values ​​occupy the same memory resources, leading to memory waste. For example, if the quantized data type is int8, representing zero values ​​with int8 would require 8 bits of memory, resulting in wasted memory.

[0050] Based on this, this disclosure proposes a data processing method and apparatus. The data processing method and apparatus provided in the embodiments of this disclosure can reduce the waste of storage space and improve storage efficiency by performing lossless compression on the zero elements in the sparse matrix.

[0051] Figure 1 This is a system architecture diagram of the data processing method applied according to embodiments of the present disclosure. It mainly consists of computing components, which include multiple computing units.

[0052] A computing component is a computer processing device with a certain computing capability. Computing components can be graphics processing units (GPUs), general-purpose graphics processing units (GPGPUs), neural processing units (NPUs), tensor processing units (TPUs), etc.

[0053] The computing component includes multiple computing units (CUs) and global memory. Each CU includes an instruction scheduling unit, a tensor processor 110, and execution units (EUs). The instruction scheduling unit can schedule computing tasks corresponding to a computing unit to either the tensor processor 110 or the execution unit (EU). The computing unit also includes shared memory, which can be accessed by the tensor processor 110 or different execution units (EUs) and has a large capacity.

[0054] See Figure 2Tensor processor 110 is a unit for performing matrix multiplication operations. Tensor processor 110 includes a first buffer 111 and a second buffer 114, a matrix multiplication unit 112, and an accumulator buffer 113. The first buffer 111 and the second buffer 114 read matrix data from shared memory or global memory. The matrix multiplication unit 112 is dedicated hardware for performing matrix multiplication operations. The matrix multiplication unit 112 is connected to the first buffer 111 and the second buffer 114, and reads the matrices from the first buffer 111 and the second buffer 114 for matrix multiplication. The accumulator buffer 113 is used to accumulate the matrix output by the matrix multiplication unit 112 or to buffer the matrix output by the matrix multiplication unit 112. The first buffer 111 and the second buffer 114 are registers.

[0055] Compression units are used to perform lossless compression of zero elements in a sparse matrix. It should be understood that a sparse matrix can be a quantized weight matrix or a weight matrix obtained through pruning. A sparse matrix has a large number of zero elements.

[0056] It is understandable that the compression unit can run as an independent software module or service, compressing the sparse matrix offline and then loading the compressed data onto memory, such as global memory or shared memory.

[0057] The decompression unit can be the hardware inside the computing unit (CU) used to decompress matrix data.

[0058] Overall Implementation of the Data Processing Method in the Embodiments of this Disclosure

[0059] This disclosure provides a data processing method applied to a data processing apparatus, with reference to... Figure 3 The data processing method includes:

[0060] Step S310: Divide the data of the sparse matrix into multiple first data blocks, each first data block including a first number of elements, wherein the first number is determined according to the bit width of the register.

[0061] Step S320: The zero elements in the multiple first data blocks are marked and compressed to obtain multiple second data blocks. Each second data block includes an index header and non-zero elements. The index header is used to characterize the position information of the zero elements and non-zero elements in the first data blocks.

[0062] Step S330: Load multiple second data blocks into memory;

[0063] Step S340: When performing the computation task, the multiple second data blocks are decompressed to obtain multiple first data blocks, and the multiple first data blocks are scheduled into the register.

[0064] Steps S310 to S340 are described in detail below.

[0065] In step S310, the sparse matrix is ​​a parameter of the large model. It can be a quantized weight matrix, and the data type of the quantized weight matrix is, for example, int8, int4, int16, or int32. Correspondingly, the bit width of the elements in the weight matrix is ​​8 bits, 4 bits, 16 bits, or int32, but it is not limited to these. The following embodiment uses a register with a bit width of 32 bits as an example. The sparse matrix has a large number of zero elements. Every consecutive first number of elements in the sparse matrix is ​​divided into a first data block. For example, if the sparse matrix is ​​read in row-major or column-major order, the data of the sparse matrix is ​​divided into multiple first data blocks in row-major or column-major order. The first number represents the number of elements contained in the first data block. The first number is determined according to the bit width of the register. For example, when the register bit width is 32 bits, the first number is 32, that is, the first data block includes 32 elements. In the subsequent decompression process, the decompression unit needs to load the index header into the register; therefore, the size of the index header is the same as the bit width of the register. Since each element uses "0" and "1" to represent a zero element and a non-zero element respectively, each bit of the index header corresponds to one element, and the number of bits in the index header corresponds to the first number. Therefore, the first number is determined based on the bit width of the register.

[0066] In step S320, the index header is a binary number of a first number of bits, used to represent the position information of zero elements and non-zero elements in the first data block; each bit of the index header corresponds one-to-one with each element of the first data block, used to indicate the position status of the corresponding element.

[0067] Specifically, see Figure 4 In one embodiment, step S320 includes steps S401-S405.

[0068] In step S401, zero elements and non-zero elements in the first data block are identified.

[0069] In this embodiment, all elements in the first data block can be traversed to identify zero elements and non-zero elements.

[0070] In step S402, an index header is generated based on the positions of zero and non-zero elements in the first data block.

[0071] In this embodiment, the index header is a binary number of a first number of bits, used to characterize the position information of zero elements and non-zero elements in the first data block; each bit of the index header corresponds one-to-one with each element of the first data block, used to indicate the position status of the corresponding element, wherein "0" indicates that the position is a zero element, and "1" indicates that the position is a non-zero element.

[0072] In step S403, it is determined whether the number of zero elements in the first data block is greater than a preset value.

[0073] In this embodiment, the number of identified zero elements can be counted using a counter, or the number of zero elements represented in the index header can be counted. The preset value can be determined based on the size of the index header and the bit width of the elements in the first data block. For example, if the index header size is 32 bits and the bit width of the elements in the first data block is 8 bits, then the preset value is 4; see [link to previous section]. Figure 5a When the number of zero elements is less than or equal to 4, the storage space saved is less than 32 bits. However, the index header occupies 32 bits of storage space, so compressing the first data block will not reduce the storage space usage. See also... Figure 5b When the number of zero elements is greater than 4, the storage space that can be saved is greater than 32 bits. However, the index header occupies 32 bits of storage space. Therefore, compressing the first data block will reduce the storage space occupied.

[0074] In step S404, when the number of zero elements in the first data block is greater than a preset value, the index header and the non-zero elements in the first data block are combined into a second data block.

[0075] In this embodiment, the index header and the non-zero elements in the first data block are combined to form the second data block, wherein the non-zero elements are arranged closely together as the data body (data) of the second data block. See also Figure 5b The second data block, obtained by compressing the first data block which includes non-zero elements, includes the index header and the non-zero elements from the first data block. See also... Figure 5c The second data block, obtained by compressing the first data block containing all zero elements, only includes the index header. Each zero element is represented by 1 bit in the index header, which can greatly reduce the waste of storage space.

[0076] In step S405, when the zero element in the first data block is less than or equal to a preset value, the first data block is not compressed, and the index header and the first data block are combined into a second data block.

[0077] In this embodiment, the first data block is not compressed, and the index header and the first data block are combined into the second data block. See also Figure 5aThe first data block, which includes non-zero elements, is not compressed. The second data block includes an index header and the original first data block. The first data block serves as the data body of the second data block.

[0078] In an optional embodiment, each second data block is stored as a whole in the memory, and the storage locations of multiple second data blocks are arranged contiguously. During decompression, the index header (head) and data body (data) of each second data block can be read sequentially according to the data placement order, and then decompressed to restore the original first data block. For example, see... Figure 6 The process involves sequentially storing the head0 and data0 of block0, the head1 and data1 of block1, ..., the headM-2 and dataM-2 of blockM-2, and the headM-1 and dataM-1 of blockM-1 in memory. During decompression, the source address src is the starting address of the index header head0 in block0. The head0 of block0 is read, and since the index header head has a fixed size, the offset address and size of data0 can be obtained from head0, and data0 is restored to its original position in the first data block. Similarly, the offset address of head1 of block1 is obtained from the offset address and size of data0 in block0, and the head1 of block1 is read. The offset address and size of data1 are obtained from head1, and data1 is restored to its original position in the first data block. This process continues until the heads and data of all blocks have been read. In an optional embodiment, each second data block is stored as a whole in memory, and the storage locations of multiple second data blocks are arranged consecutively. The data processing method further includes step S406, in which an address mapping table of multiple second data blocks is constructed. This allows for quick location of the second data blocks during computational tasks and enables random reading of the corresponding second data blocks, thereby improving data access efficiency. Specifically, step S406 includes the following steps.

[0079] In step S701, the size of each second data block is determined based on the index header of the second data block.

[0080] In this embodiment, the size of the second data block is determined based on the number of non-zero elements in the index header of each second data block and the size of the index header. For example, the index header size is 32 bits, and the bit width of the elements in the first data block is 8 bits. See [link to documentation]. Figure 5b The index header of the second data block contains 18 "1"s, so the space occupied by the non-zero elements is 18 * 8 bits = 144 bits. The size of the second data block is 144 bits + 32 bits = 176 bits.

[0081] In step S702, the size of all the second data blocks preceding the second data block is accumulated as the first offset address of the second data block.

[0082] In this embodiment, the sparse matrix is ​​divided into M first data blocks, which are then compressed into M second data blocks, namely block0-blockM-1. The first offset address of block0 is offset-b0, the first offset address of block1 is offset1, which is the size of block0, i.e., offset-b1 = size-b0. The first offset address of block2 is offset-b2, which is the sum of the sizes of block0 and block1, i.e., offset2 = size-b0 + size-b1. And so on, the first offset address of blockM-1 is offset-bM-1, which is the sum of the sizes of block0 and blockM-2, i.e., offset-bM-1 = size-b0 + size-b1 + ... + size-bM-2.

[0083] In step S703, a corresponding mapping entry is created for each second data block to form an address mapping table, wherein the mapping entry includes a first offset address.

[0084] In this embodiment, see Figure 6 Each second data block corresponds to a mapping entry, which includes a first offset address, offset-b. The source address, src, points to the starting address of the header (head0) of the first second data block, block0, and the first offset address, offset-b, points to the starting address of the header (head) of the corresponding second data block. During decompression, any second data block can be randomly read according to the address mapping table; that is, the header (head) and data body (data) of the corresponding second data block can be obtained based on the source address, src, and the first offset address, offset-b.

[0085] In an optional embodiment, the index headers (head) of the multiple second data blocks are stored separately and an address mapping table is constructed, and the data bodies (data) of the multiple second data blocks are stored separately. The data processing method further includes step S406, in which an address mapping table is constructed for the multiple second data blocks. This allows for quick location of the second data blocks during computational tasks and enables random reading of the corresponding second data blocks, improving data access efficiency. Specifically, step S406 includes the following steps.

[0086] In step S701, the size of each second data block is determined based on the index header of the second data block.

[0087] In this embodiment, the size of the second data block is determined based on the number of non-zero elements in the index header of each second data block. For example, the bit width of an element in the first data block is 8 bits. See [link to documentation]. Figure 5b The index header of the second data block contains 18 "1"s, so the space occupied by the non-zero elements is 18 * 8 bits = 144 bits, and the size of the second data block is 144 bits.

[0088] In step S702, the size of all the second data blocks preceding the second data block is accumulated as the first offset address of the second data block.

[0089] In this embodiment, the sparse matrix is ​​divided into M first data blocks, which are then compressed into M second data blocks, namely block0-blockM-1. The first offset address of block0 is offset-b0, the first offset address of block1 is offset1, which is the size of block0, i.e., offset-b1 = size-b0. The first offset address of block2 is offset-b2, which is the sum of the sizes of block0 and block1, i.e., offset2 = size-b0 + size-b1. And so on, the first offset address of blockM-1 is offset-bM-1, which is the sum of the sizes of block0 and blockM-2, i.e., offset-bM-1 = size-b0 + size-b1 + ... + size-bM-2.

[0090] In step S703, a corresponding mapping entry is created for each second data block to form an address mapping table, wherein the mapping entry includes a first offset address.

[0091] In this embodiment, see Figure 8 Each second data block corresponds to a mapping entry, which includes a first offset address (offset-b), a source address (src) pointing to the starting address of the index header (head0) of the first second data block (block0), and the first offset address (offset-b) pointing to the starting address of the data body (data) of the corresponding second data block. During decompression, the index header (head) and the corresponding first offset address (offset-b) of each second data block are obtained based on the source address and the second data block number, and the data body (data) of each second data block is obtained based on the source address (src) and the corresponding first offset address (offset-b).

[0092] Specifically, during the decompression process, any second data block can be randomly read according to the address mapping table. The source address src points to the starting address of the index header head0 in the second data block, and the first offset address offset-b0 points to the storage address of the data body data0 in the second data block. Since the size of head and the first offset address offset-b are fixed, the starting address of the index header head and the first offset address offset-b of the data body can be determined according to the number of the second data block. Therefore, any second data block can be randomly read, and the corresponding data body can be restored to the corresponding first data block according to the index header of the second data block.

[0093] In step S330, during large model inference, the preprocessed weight matrix is ​​pre-loaded into memory for subsequent computation. For example, the weight matrix is ​​quantized to obtain a sparse matrix, and the sparse matrix is ​​compressed to obtain multiple second data blocks. The memory can be global memory accessible to different computational units within the computational component, or shared memory accessible to different execution units or tensor processors within the computational unit. In step S340, during computation, the multiple second data blocks are decompressed to obtain multiple first data blocks, and these first data blocks are scheduled into registers.

[0094] In this embodiment, the computation task is, for example, matrix multiplication, which can be performed by a tensor processor. Therefore, when performing the computation task, the tensor processor reads weight data from global memory or shared memory. This requires decompressing multiple second data blocks to obtain multiple first data blocks, and then scheduling these first data blocks into the corresponding second buffer 114 in the tensor processor 110. Specifically, the non-zero and zero elements in the second data blocks can be restored to their corresponding positions in the sparse matrix based on the index header of the second data blocks.

[0095] The data processing method provided in this embodiment divides the data of a sparse matrix into multiple first data blocks, each first data block including a first number of elements, wherein the first number is determined according to the bit width of a register; zero elements in the multiple first data blocks are marked and compressed to obtain multiple second data blocks, each second data block including an index header and non-zero elements, wherein the index header is used to characterize the position information of zero elements and non-zero elements in the first data blocks; by performing lossless compression on zero elements in the sparse matrix, the waste of storage space is reduced, thereby improving storage efficiency.

[0096] Furthermore, each bit of the index header corresponds one-to-one with an element in the first data block, indicating the position status of the corresponding element. Here, 0 indicates that the position is a zero element, and 1 indicates that the position is a non-zero element. This allows for rapid compression and decompression of data, improving data read and write efficiency.

[0097] Furthermore, by accurately calculating the size and offset address of each second data block or second data packet, memory resources can be utilized more effectively, memory fragmentation can be avoided, and memory usage efficiency can be improved.

[0098] Furthermore, by constructing an address mapping table, data blocks can be quickly located, improving decompression efficiency.

[0099] Another embodiment of this disclosure provides a data processing method applied to a data processing apparatus, with reference to... Figure 9 The data processing method includes:

[0100] Step S910: Divide the data of the sparse matrix into multiple first data blocks, each first data block including a first number of elements, wherein the first number is determined according to the bit width of the register.

[0101] Step S920: Zero elements in multiple first data blocks are marked and compressed to obtain multiple second data blocks. Each second data block includes an index header and non-zero elements. The index header is used to characterize the position information of zero elements and non-zero elements in the first data blocks.

[0102] Step S930: Divide the multiple second data blocks into multiple first data packets, each data packet including a second number of second data blocks, wherein the second number is determined based on the bit width of the register;

[0103] Step S940: Mark and compress the second data block with all zero elements in each first data packet to obtain multiple second data packets. The second data packet includes metadata and second data blocks with non-all zero elements. The metadata is used to characterize the element type of each second data block in the second data packet.

[0104] Step S950: Load multiple second data packets into the memory;

[0105] In step S960, when performing the computation task, multiple second data packets are decompressed to obtain multiple first data blocks, and the multiple first data blocks are scheduled into registers.

[0106] Steps S910 and S920 are the same as steps S310 and S320 in the above embodiments, and will not be described again here.

[0107] In step S930, since the second data block with all-zero elements only includes an index header, it can be further compressed to use fewer bits to mark it. The second data block includes three element types: all-zero elements, non-all-zero elements, and all-zero elements. All-zero elements refer to the uncompressed second data block, non-all-zero elements refer to the compressed second data block including an index header and non-zero elements, and all-zero elements refer to the compressed second data block containing only an index header. Two bits are needed to distinguish the three element types. The second number represents the number of second data blocks contained in the first data packet. The second number is determined based on the register's bit width. For example, when the register's bit width is 32 bits, the second number is 16, meaning the first data packet includes 16 second data blocks.

[0108] In step S940, the metadata Meta is used to characterize the element type of the second data block in the second data packet; each two bits of the metadata correspond to each second data block in the first data packet and are used to indicate the element type of the corresponding second data block.

[0109] Specifically, see Figure 10 In one embodiment, step S840 includes steps S1001-S1003.

[0110] In step S1001, the element type of the second data block in the first data packet is identified, and the element type includes all elements, all zero elements and non-all zero elements.

[0111] In this embodiment, the index headers of all second data blocks in the first data packet are traversed to identify the element type of the second data block. If all bits in the index header of the second data block represent zero elements, for example, all bits in the index header are "0", the second data block is marked as an all-zero element; if the number of bits representing zero elements in the index header of the second data block is greater than a preset value, for example, the number of "0"s in the index header is greater than a preset value, the second data block is marked as a non-all-zero element; if the number of bits representing zero elements in the index header of the second data block is less than or equal to a preset value, for example, the number of "0"s in the index header is less than or equal to a preset value, the second data block is marked as a full element. For example, "00" is used to mark second data blocks with all-zero elements, "01" is used to mark second data blocks with non-all-zero elements, and "11" is used to mark second data blocks with full elements.

[0112] In step S1002, metadata is generated based on the element type of the second data block.

[0113] In this embodiment, each two bits of the metadata Meta corresponds to each second data block in the first data packet, and is used to indicate the element type of the corresponding second data block. For example, "00" represents a second data block with all zeros at that position, "01" represents a second data block with non-all zeros at that position, and "11" represents a second data block with all elements at that position.

[0114] In step S1003, the second data block containing all elements and all zero elements is compressed.

[0115] In this embodiment, the second data block containing all elements includes an index header (head) and an uncompressed data body (data). After compression, the second data block only includes the uncompressed data body (data), which is achieved by removing the index header (head) from the second data block containing all elements. Similarly, the second data block containing all zero elements only includes an index header (head), and this is also achieved by removing the index header from the second data block containing all zero elements. Replacing the index header (head) in the second data block with two bits from the metadata (Meta) further reduces the size of the sparse matrix data, thereby further reducing storage space usage.

[0116] In step S1004, the metadata, the second data block containing all elements and non-zero elements are combined into a second data packet.

[0117] In this embodiment, see Figure 11 Each second data packet includes metadata and a second data block with non-zero elements, as well as a second data block with all elements. The second data block with all elements only includes the data body.

[0118] In an optional embodiment, the metadata (Meta) of multiple second data packets is stored separately and an address mapping table is constructed. Second data blocks containing non-all-zero elements and second data blocks containing all elements from the multiple second data packets are stored separately. The index header (head) and data body (data) of the second data block are stored together as a whole and contiguously. The data processing method further includes step S1005, in which the address mapping table of multiple second data packets is constructed. This allows for rapid location of the second data packets during computational tasks and enables random reading of corresponding second data packets, improving data access efficiency. Specifically, see [link to documentation]. Figure 13 Step S1005 includes the following steps.

[0119] In step S1301, the size of each second data packet is determined based on the metadata of the second data packet and the index header of the second data block in the second data packet.

[0120] In this embodiment, the size of the second data packet is determined based on the metadata of the second data packet and the index header of the second data block in the second data packet. For example, the size of the second data packet is the sum of the sizes of all non-zero elements and the sizes of all-zero elements in the second data block; the size of the second data block is determined based on the number of non-zero elements in the index header of each second data block.

[0121] In step S1302, the size of all the second data packets preceding the second data packet is accumulated as the second offset address of the second data packet.

[0122] In this embodiment, multiple second data blocks are divided into N first data packets, which are compressed into N second data packets, namely package0-packageN-1. The second offset address offset-p0 of package0 is 0, the second offset address offset1 of package1 is the size of package0, that is, offset-p1=size-p0, the second offset address offset-p2 of package2 is the sum of the sizes of package0-package1, that is, offset2=size-p0+size-p1, and so on. The second offset address offset-pM-1 of packageM-1 is the sum of the sizes of package0-packageM-2, that is, offset-pM-1=size-p0+size-p1+……+size-pM-2.

[0123] In step S1303, a corresponding mapping entry is created for each second data packet to form an address mapping table, wherein the mapping entry includes a second offset address.

[0124] See Figure 14 Each second data packet corresponds to a mapping entry, which includes a second offset address, offset-p. The source address, src, points to the starting address of the metadata, Meta0, of the first second data packet, package0. The second offset address, offset-p, points to the starting address of the index header, head0, of the first second data block, block0, within each second data packet package. Based on the source address, src, and the number of each second data packet package, the metadata, Meta, and the corresponding second offset address, offset-p, are obtained. Then, multiple second data blocks within each second data packet are read sequentially based on the source address, src, and the corresponding second offset address, offset-p.

[0125] During decompression, any second data packet can be randomly read according to the address mapping table. The source address src points to the starting address of the metadata Meta0 in the first second data packet package0. The second offset address offset-p0 of package0 points to the starting address of the index header head0 of the first second data block block0 in the second data packet. Since the size of the second offset address offset-p of the second data packet package is fixed, the starting address of the metadata Meta of the corresponding second data packet and the starting address of the index header head0 of the first second data block block0 in the second data packet can be determined according to the number of the second data packet package. Any second data packet can be randomly read, and then the index header head and data body of multiple second data blocks in the corresponding second data packet package can be read in sequence. The data body data of the second data block is restored to the corresponding first data block according to the index header head of the second data block.

[0126] In an optional embodiment, the metadata (Meta) of multiple second data packets is stored separately and a first-level address mapping table is constructed. The index header (head) of each second data packet is stored separately and a second-level address mapping table is constructed. The data body (data) of each second data packet is stored separately and contiguously. The data processing method further includes step S1005, in which the address mapping table of multiple second data packets is constructed. This allows for quick location of the second data packets during computational tasks and enables random reading of corresponding second data packets, improving data access efficiency. See [link to specific documentation]. Figure 13 Step S1005 includes the following steps.

[0127] In step S1301, the size of each second data packet is determined based on the metadata of the second data packet and the index header of the second data block in the second data packet.

[0128] In this embodiment, the size of the second data packet is determined based on the metadata of the second data packet and the index header of the second data block in the second data packet. For example, the size of the second data packet is the sum of the sizes of all non-zero elements and the sizes of all-zero elements in the second data block; the size of the second data block is determined based on the number of non-zero elements in the index header of each second data block and the size of the index header.

[0129] In step S1302, the size of all the second data packets preceding the second data packet is accumulated as the second offset address of the second data packet.

[0130] In this embodiment, multiple second data blocks are divided into N first data packets, which are compressed into N second data packets, namely package0-packageN-1. The second offset address offset-p0 of package0 is 0, the second offset address offset1 of package1 is the size of package0, that is, offset-p1=size-p0, the second offset address offset-p2 of package2 is the sum of the sizes of package0-package1, that is, offset2=size-p0+size-p1, and so on. The second offset address offset-pM-1 of packageM-1 is the sum of the sizes of package0-packageM-2, that is, offset-pM-1=size-p0+size-p1+……+size-pM-2.

[0131] In step S1303, a corresponding mapping entry is created for each second data packet to form an address mapping table, wherein the mapping entry includes a second offset address and a first offset address.

[0132] See Figure 12 Each second data packet corresponds to a mapping entry, which includes a second offset address (offset-p) and a first offset address (offset-b). The source address (src) points to the starting address of the metadata (Meta0) of the first second data packet (package0). The second offset address (offset-p) points to the starting address of the index header (head0) of the first second data block (block0) in each second data packet (package). The first offset address (offset-b) points to the starting address of the data body (data) of each second data block (block) in each second data packet. Based on the source address (src) and the package number, the metadata (Meta) and corresponding second offset address (offset-p) of each second data packet (package) are obtained. Based on the source address (src) and the corresponding second offset address (offset-p), the starting address of the index header (head) of the first second data block (block) in the second data packet is obtained. Based on the source address (src) and the corresponding second offset address (offset-b), the data body (data) of any second data block in the second data packet is read.

[0133] Specifically, during decompression, any second data packet can be randomly read according to the address mapping table. The source address `src` in the instruction points to the starting address of the metadata `Meta0` in the first second data packet `package0`, the second offset address `offset-p0` of `package0` points to the starting address of the index header `head0` of the first second data block `block0` in the second data packet, and the first offset address `offset-b` of the block points to the starting address of the data body `data` of the corresponding block. Since the sizes of the metadata `Meta`, the second offset address `offset-p` of `package`, and the first offset address `offset-b` of `block` are fixed, the starting address of the metadata `Meta` and the starting address of the index header `head0` of the corresponding second data packet can be determined according to the number of the second data packet `package`, and the starting address of the data body `data` of the corresponding block can be determined according to the number of the block in the second data packet. Any second data block in any second data packet can be randomly read, and the corresponding data body can be restored to the corresponding first data block according to the index header of the second data block.

[0134] In step S950, during large model inference, the preprocessed weight matrix is ​​pre-loaded into memory for subsequent computation. For example, the weight matrix is ​​quantized to obtain a sparse matrix, and the sparse matrix is ​​compressed to obtain multiple second data packets. The memory can be global memory within the computing component that can be accessed by different computing units, or it can be shared memory within the computing unit that can be accessed by different execution units or tensor processors.

[0135] In step S960, when performing the computation task, multiple second data packets are decompressed to obtain multiple first data blocks, and the multiple first data blocks are scheduled into registers.

[0136] In this embodiment, the computation task is, for example, matrix multiplication, which can be performed by the tensor processor. Therefore, when performing the computation task, the tensor processor reads weight data from global memory or shared memory, and needs to decompress multiple second data blocks to obtain multiple first data blocks. Then, the multiple first data blocks are scheduled to the corresponding second cache 114 in the tensor processor 110.

[0137] Specifically, see Figure 15 The decompression process for multiple second data packets includes the following steps.

[0138] In step S1501, the second data packet is decompressed according to the metadata to recover the original second data block.

[0139] In this embodiment, the second data packet containing all zero elements in the second data packet is restored to the original second data block based on the meta information Meta.

[0140] In step S1502, the non-zero elements and zero elements in the second data block are restored to their corresponding positions in the sparse matrix according to the index header of the second data block.

[0141] This embodiment further reduces storage space waste and improves storage efficiency, especially for large-scale sparse matrix data, by compressing the second data block with all elements and all zero elements and using meta-information to characterize the element type of the second data block.

[0142] Furthermore, by constructing an address mapping table, data packets and / or data blocks can be quickly located, improving decompression efficiency.

[0143] Description of apparatus and devices according to embodiments of this disclosure

[0144] See Figure 16 The present disclosure also proposes a data processing device 1600, which includes a compression unit 1610 and a computing unit 1620. The computing unit 1620 includes a memory 1621, a scheduling unit 1622, a decompression unit 1623, and a register 1624.

[0145] The compression unit 1610 is used to divide the data of the sparse matrix into multiple first data blocks, each first data block including a first number of elements, wherein the first number is determined according to the bit width of the register; and to mark and compress the zero elements in the multiple first data blocks to obtain multiple second data blocks, each second data block including an index header and non-zero elements, wherein the index header is used to characterize the position information of the zero elements and non-zero elements in the first data block.

[0146] The scheduling unit 1622 is used to load multiple second data blocks into the memory 1621 and to schedule multiple second data blocks to the decompression unit 1623 when performing computing tasks.

[0147] The decompression unit 1623 is used to decompress multiple second data blocks to obtain multiple first data blocks, and schedule the multiple first data blocks into register 1624. Register 1624 may be a cache in a tensor processor.

[0148] In an optional embodiment, the compression unit 1610 is further configured to divide a plurality of second data blocks into a plurality of first data packets, each data packet including a second number of second data blocks, wherein the second number is determined based on the bit width of the register; and to mark and compress the second data blocks of all elements and all zero elements in each first data packet to obtain a plurality of second data packets, wherein the second data packets include metadata, second data blocks of all elements and non-all zero elements, wherein the metadata is used to characterize the element type of the second data block.

[0149] The scheduling unit 1622 is used to load multiple second data packets into the memory 1621 and to schedule multiple second data packets to the decompression unit 1623 when performing computing tasks;

[0150] The decompression unit 1623 is used to decompress multiple second data packets to obtain multiple first data blocks, and schedule the multiple first data blocks into register 1624.

[0151] The data processing apparatus disclosed herein is used to execute the data processing method as described in the above embodiments. Its specific processing procedure is the same as the data operation and processing method described in the above embodiments, and will not be repeated here.

[0152] This disclosure also provides an electronic device 1700, comprising:

[0153] At least one processor, and,

[0154] A memory that is communicatively connected to at least one processor; wherein,

[0155] The memory stores instructions that are executed by at least one processor to cause the at least one processor to perform the method as described in any of the above embodiments of this application when executing the instructions.

[0156] The following is combined Figure 17 The hardware structure of the electronic device is described in detail. The electronic device includes: a processor 1710, a memory 1720, an input / output interface 1730, a communication interface 1740, and a bus 1750.

[0157] The processor 1710 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this disclosure.

[0158] The memory 1720 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1720 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1720 and is called and executed by the processor 1710 using the data processing method of the embodiments of this disclosure.

[0159] The input / output interface 1730 is used to implement information input and output;

[0160] The communication interface 1740 is used to enable communication and interaction between this device and other devices. Communication can be achieved via wired means (e.g., USB, Ethernet cable) or wireless means (e.g., mobile network, Wi-Fi, Bluetooth).

[0161] Bus 1750 transmits information between various components of the device (e.g., processor 1710, memory 1720, input / output interface 1730, and communication interface 1740);

[0162] The processor 1710, memory 1720, input / output interface 1730 and communication interface 1740 are connected to each other within the device via bus 1750.

[0163] This application also provides a computer-readable storage medium that stores one or more programs, which can be executed by one or more processors to implement the data processing method of the above embodiments, which will not be described again here.

[0164] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in this disclosure and the foregoing drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “including,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0165] It should be understood that in this disclosure, "at least one item" means one or more, and "more than one" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0166] It should be understood that in the description of the embodiments of this disclosure, "multiple" means two or more, "greater than", "less than", "exceeding" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself.

[0167] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0168] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0169] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0170] It should also be understood that the various implementation methods provided in this disclosure can be combined arbitrarily to achieve different technical effects.

[0171] The above is a detailed description of the embodiments of this disclosure. However, this disclosure is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this disclosure. All such equivalent modifications or substitutions are included within the scope defined by the claims of this disclosure.

Claims

1. A data processing method, characterized in that, include: The data of the sparse matrix is ​​divided into multiple first data blocks, each first data block including a first number of elements, wherein the first number is determined according to the bit width of the register. Zero elements in multiple first data blocks are marked and compressed to obtain multiple second data blocks. Each second data block includes an index header and non-zero elements. The index header is used to characterize the position information of zero and non-zero elements in the first data blocks. Load multiple second data blocks into memory; When performing computational tasks, multiple second data blocks are decompressed to obtain multiple first data blocks, and these first data blocks are then scheduled into registers.

2. The data processing method according to claim 1, characterized in that, Zero elements in multiple first data blocks are marked and compressed to obtain multiple second data blocks, including: Identify zero and non-zero elements in the first data block; An index header is generated based on the positions of zero and non-zero elements in the first data block. Each bit of the index header corresponds one-to-one with an element in the first data block and is used to indicate the position status of the corresponding element. Determine whether the number of zero elements in the first data block is greater than a preset value; When the number of zero elements in the first data block is greater than a preset value, the index header and the non-zero elements in the first data block are combined into a second data block.

3. The data processing method according to claim 2, characterized in that, Zero elements in multiple first data blocks are marked and compressed to obtain multiple second data blocks, including: When the number of zero elements in the first data block is less than or equal to a preset value, the first data block is not compressed, and the index header and the first data block are combined into the second data block.

4. The data processing method according to claim 1, characterized in that, Decompressing multiple second data blocks includes: The non-zero and zero elements in the second data block are restored to their corresponding positions in the sparse matrix based on the index header.

5. The data processing method according to claim 1, characterized in that, Also includes: The multiple second data blocks are divided into multiple first data packets, each data packet including a second number of second data blocks, wherein the second number is determined based on the bit width of the register; The second data blocks containing all zero elements in each first data packet are marked and compressed to obtain multiple second data packets. Each second data packet includes metadata and second data blocks containing non-all zero elements. The metadata is used to characterize the element type of each second data block in the second data packet. Load multiple second data packets into memory; When performing computational tasks, multiple second data packets are decompressed to obtain multiple first data blocks, and these first data blocks are scheduled into registers.

6. The data processing method according to claim 5, characterized in that, Each second data block containing all zero elements in the first data packet is marked and compressed to obtain multiple second data packets, including: Identify the element type of the second data block in the first data packet, wherein the element type includes all elements, all zero elements, and non-all zero elements; Meta-information is generated based on the element type of the second data block, wherein each two bits of the meta-information correspond to each second data block in the first data packet and are used to indicate the element type of the corresponding second data block; Compress the second data block containing all elements and all zero elements; The second data packet is composed of metadata, full elements, and non-full zero elements.

7. The data processing method according to claim 5, characterized in that, Decompressing multiple second data packets includes: The second data packet is decompressed based on the metadata to recover the original second data block; Based on the index header of the second data block, restore the non-zero and zero elements in the second data block to their corresponding positions in the sparse matrix.

8. The data processing method according to claim 1, characterized in that, Also includes: The size of each second data block is determined based on the index header of the second data block; The offset address of the second data block is obtained by summing the sizes of all previous second data blocks. A corresponding mapping entry is created for each second data block to form an address mapping table, wherein the mapping entry includes a first offset address.

9. The data processing method according to claim 8, characterized in that, In the second data block, non-zero elements are arranged closely together to form the data body; The index header and data body of the second data block are stored together. The source address points to the starting address of the index header of the first second data block, and the first offset address points to the starting address of the index header of the corresponding second data block. Alternatively, the index header and the first offset address of the second data block are stored together contiguously, while the data body is stored separately. The source address points to the starting address of the index header of the first second data block, and the first offset address points to the starting address of the data body of the corresponding second data block.

10. The data processing method according to claim 5, characterized in that, Also includes: The size of each second data packet is determined based on the metadata of the second data packet and the index header of the second data block in the second data packet; The offset address of the second data packet is obtained by summing the sizes of all previous second data packets. A corresponding mapping entry is created for each second data packet to form an address mapping table, and the mapping entry includes at least the second offset address.

11. The data processing method according to claim 10, characterized in that, In the second data block, non-zero elements are arranged closely together to form the data body; The index header and data body of the second data block are stored together. The source address points to the starting address of the metadata of the first second data packet, and the second offset address points to the starting address of the index header of the first second data block in each second data packet. Alternatively, the source address points to the starting address of the metadata of the first second data packet, the second offset address points to the starting address of the index header of the first second data block in each second data packet, and the first offset address points to the starting address of the data body of each second data block in each second data packet.

12. A data processing apparatus, characterized in that, It includes a compression unit, a scheduling unit, a memory, a decompression unit, and registers. The compression unit is used to divide the data of the sparse matrix into multiple first data blocks, each first data block including a first number of elements, wherein the first number is determined according to the bit width of the register; and to mark and compress the zero elements in the multiple first data blocks to obtain multiple second data blocks, each second data block including an index header and non-zero elements, wherein the index header is used to characterize the position information of the zero elements and non-zero elements in the first data block. The scheduling unit is used to load multiple second data blocks into the memory and to schedule multiple second data blocks to the decompression unit when performing computing tasks; The decompression unit is used to decompress multiple second data blocks to obtain multiple first data blocks, and schedule the multiple first data blocks into a register.

13. The data processing apparatus according to claim 11, characterized in that, The compression unit is further configured to divide multiple second data blocks into multiple first data packets, each data packet including a second number of second data blocks, wherein the second number is determined based on the bit width of the register; and to mark and compress the second data blocks of all elements and all zero elements in each first data packet to obtain multiple second data packets, wherein the second data packets include metadata, second data blocks of all elements and non-all zero elements, wherein the metadata is used to characterize the element type of the second data block; The scheduling unit is used to load multiple second data packets into the memory and to schedule multiple second data packets to the decompression unit when performing computing tasks; The decompression unit is used to decompress multiple second data packets to obtain multiple first data blocks, and schedule the multiple first data blocks into a register.

14. An electronic device, characterized in that, The electronic device includes a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for establishing communication between the processor and the memory. The program is executed by the processor to implement the data processing method as described in any one of claims 1 to 11.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the data processing method as described in any one of claims 1 to 11.

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