MCU (Microprogrammed Control Unit) caching device, memory access method and electronic equipment
By introducing a jump buffer unit and a last-in-first-out (LIFO) strategy into the MCU, the cache miss problem during function jumps and returns in the MCU is solved, improving execution performance and reducing storage costs, and supporting complex jump logic and nested jumps.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU SHUOTIAN TECH CO LTD
- Filing Date
- 2025-12-31
- Publication Date
- 2026-05-12
AI Technical Summary
In existing technologies, MCUs are prone to cache misses when jumping and returning from functions, leading to performance degradation. Existing solutions cannot effectively solve the waiting delay during jumps and returns.
A jump buffer unit is introduced between the processor unit and the flash memory unit, using a 128-bit storage structure and a last-in-first-out strategy to cache the instruction block when a jump occurs, and directly read the return address instruction from the jump buffer when the jump returns.
It significantly reduces the probability of cache misses when jumping back, improves the execution performance of the MCU in jump scenarios, reduces the demand for cache space, reduces storage device costs, and supports cache full hits for multiple nested jumps.
Smart Images
Figure CN122018981A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of microcontroller unit technology, specifically to an MCU cache device, memory access method, and electronic device. Background Technology
[0002] In modern embedded systems, the performance of a microcontroller unit (MCU) largely depends on its instruction fetch efficiency. EFLASH, as the program memory, often becomes a bottleneck in system performance due to its access speed. Existing technologies typically employ instruction caches and prefetch buffers to improve instruction fetch efficiency.
[0003] However, traditional caching mechanisms often experience cache misses when encountering function calls and return instructions during program execution. This is especially true in scenarios with deeply nested jumps, where the instruction at the return address may have already been replaced from the cache, forcing the processor to wait to fetch the instruction from main memory again, resulting in performance degradation.
[0004] Existing solutions mainly include: initiating jump return target prefetching during the jump instruction decoding or execution phase. Although this can reduce waiting time, the FLASH waiting period cannot be fully covered due to the late start time of prefetching, making it difficult to avoid waiting delays.
[0005] Writing all CPU memory access requests to the cache achieves zero-wait instruction response during jumps and returns, but it requires a large cache size and is easily replaced when the cache capacity is insufficient, thus limiting its effectiveness.
[0006] Therefore, there is an urgent need for an effective method to solve the problem of jump return cache miss and improve MCU execution performance.
[0007] It should be noted that the information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0008] In view of this, this application provides an MCU cache device to help solve the problem of instruction jump return cache miss in the prior art.
[0009] In a first aspect, embodiments of this application provide an MCU cache device, including:
[0010] Processor unit;
[0011] Flash memory cells;
[0012] A jump buffer unit is provided between the processor unit and the flash memory unit;
[0013] The jump buffer unit is configured to cache the instruction block whose address is aligned with the address where the jump occurs.
[0014] In conjunction with the first aspect of the present invention, in one possible embodiment, the present application also provides an MCU cache device, wherein the jump buffer unit has a D×N bits storage structure, where D is the depth and N is the data bit width, and in particular, the data bit width N of the jump buffer unit is 128 bits.
[0015] In conjunction with the first aspect of the present invention, in one possible embodiment, the present application also provides an MCU cache device, wherein the jump buffer unit adopts a last-in-first-out data replacement strategy.
[0016] In conjunction with the first aspect of the present invention, in one possible embodiment, the present application also provides an MCU caching device, wherein the jump buffer unit directly deletes the read data after it is read, and subsequent data is shifted forward sequentially.
[0017] In a second aspect, the present invention also provides a memory access method, comprising the following steps:
[0018] Detect jump instructions during processor unit execution;
[0019] When a function jump is detected, the instruction block aligned with the address where the jump occurred is stored in the jump buffer;
[0020] When a jump return instruction is detected, the instruction to return to the destination address is read directly from the jump buffer;
[0021] Execute the instruction to return the destination address.
[0022] In conjunction with the second aspect of the invention, in one possibility, the step of "stored the instruction block aligned with the address where the jump occurred into the jump buffer" includes:
[0023] Determine if the current instruction is a function jump instruction;
[0024] If it is a function jump instruction, the instruction block aligned to the current address is stored in the jump buffer, and the jump instruction is executed;
[0025] Otherwise, execute sequentially.
[0026] In conjunction with a second aspect of the invention, in one possibility, the step of "reading the return destination address instruction directly from the jump buffer" includes:
[0027] Determine if the current instruction is a jump / return instruction;
[0028] If it is a jump return instruction, the required return destination address instruction is read from the top layer of the jump buffer;
[0029] If the read is successful, execute the instruction to return to the destination address;
[0030] If the read fails, the instruction is read from main memory and then executed.
[0031] In conjunction with the second aspect of the invention, in one possibility,
[0032] When nested jumps occur, the instruction caching process is repeated to store the return address instructions of each jump level into the jump buffer in sequence;
[0033] When jumping back, the corresponding return destination address instruction is read from the jump buffer in a last-in-first-out (LIFO) order.
[0034] Thirdly, the present invention also provides an electronic device including a processor and flash memory, wherein the processor and flash memory access each other via the method described in the second aspect.
[0035] This invention significantly reduces the probability of cache misses during jump return by adding a jump buffer, thereby improving the execution performance of the MCU in jump scenarios. The dedicated jump buffer reduces the use of conventional cache space and lowers the requirement for cache SRAM size, thus reducing the storage device cost of the MCU. By storing the jump return address instruction in a dedicated jump buffer, the probability of code being replaced in the cache is reduced, thereby reducing the probability of cache misses in other scenarios and improving the overall execution performance of the MCU. Furthermore, it supports multiple jump nesting, achieving a full cache hit during jump return within a set number of jump nesting levels. Attached Figure Description
[0036] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0037] Figure 1 This is a schematic diagram of the processor unit accessing FLASH according to an embodiment of the present invention;
[0038] Figure 2 This is a flowchart illustrating the logic of writing to the JUMP Buffer when a jump occurs, according to an embodiment of the present invention.
[0039] Figure 3 This is a flowchart illustrating the logic of reading the JUMP Buffer during a jump return in an embodiment of the present invention.
[0040] Figure 4This is a schematic diagram of a two-level jump nesting and return in an embodiment of the present invention. Detailed Implementation
[0041] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0042] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.
[0043] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.
[0044] In the field of microcontroller units (MCUs), due to cost considerations, code often runs on a storage combination consisting of embedded flash memory (FLASH) and small-capacity static random access memory (SRAM). FLASH read speeds are typically around 30MHz. With a comparable CPU frequency, data can be read at the CPU frequency. However, as the CPU frequency increases, a speed difference exists between the CPU and FLASH. Direct CPU access to FLASH requires additional CPU cycles to wait for data to be returned from FLASH, increasing the time spent on CPU read instructions and reducing the performance of embedded systems. In more complex or high-performance MCUs, acceleration units such as caches and prefetch buffers are typically provided. The cache stores data requested by the CPU that is not in the cache or prefetch buffer, while the prefetch initiates a prefetch of the next N-bit aligned data block after each access to the prefetch buffer. Both significantly improve the speed of frequently accessed data, instructions, and sequential execution.
[0045] In general, the cache mechanism commonly used by MCUs is jump caching, meaning that caching only occurs after a cache miss, and sequentially executed instructions are generally not cached. Embedded system application code typically contains numerous function jumps. In function jump scenarios, the cache only caches the N bits of instructions at the target address after the jump; the N bits of the jump instruction itself are generally not cached, but only exist in the prefetch buffer. However, the prefetch buffer is replaced by the sequentially prefetched data block after the jump. Therefore, upon returning from the jump, the CPU cannot read the required instructions from the cache or prefetch buffer and needs to reread them from the FLASH, resulting in a cache miss problem upon jump return. Currently, this problem usually has the following solutions.
[0046] One solution is to use a mechanism where the cache only caches CPU-requested instructions not in the cache or prefetch buffer. When a jump return occurs, the jump signal status is checked during instruction decoding or execution. If it is a valid jump, the CPU will start prefetching instructions aligned to the jump return destination address (N bits). This can reduce CPU waiting time to some extent. However, prefetching during decoding or execution cannot meet the FLASH time wait cycle, and prefetching usually cannot be completed. This cannot solve the problem of the CPU consuming wait cycles to directly read instructions from main memory FLASH during jump return.
[0047] Another solution is to write all CPU memory access requests into the cache for faster access later. In this case, if the cache is large enough, the instruction at the jump address can be directly read from the cache during the jump return, achieving zero-wait execution for the CPU during the jump return. While this technique achieves zero-wait execution during the jump return, it has certain requirements on cache size; if the cache size is insufficient, the instruction at the return address is more likely to be replaced.
[0048] like Figure 1As shown, the MCU cache device includes a processor unit (CPU), a flash memory unit (FLASH), and an acceleration unit disposed between the two. Commonly used acceleration units in existing MCUs typically include an instruction cache (I-CACHE) to load and cache the requested address from FLASH when the CPU's requested instruction is not in the cache; a data cache (D-CACHE) to load and cache the requested address from FLASH or RAM when the CPU's requested data is not in the cache; a data buffer for temporary data storage; and two instruction buffers for instruction prefetching. Prefetching is initiated after each access to the prefetch buffer. After the CPU fetches an instruction from the prefetch buffer, the prefetch mechanism prefetches subsequent instructions into another buffer to hide FLASH access latency. The acceleration unit of the MCU cache device of this invention also includes a jump buffer.
[0049] The jump buffer employs a last-in, first-out (LIFO) data replacement strategy. When the buffer is full, the first cached instruction is deleted. Furthermore, after data is read, the jump buffer immediately deletes the read data, and the second layer of data becomes the first layer of data. The same applies to other layers, ensuring that each time a jump instruction is retrieved, it can be directly accessed from the first layer of the buffer.
[0050] The jump buffer has a data width of N bits and a depth of D. Typically, the data width N can be designed as 128 bits or 256 bits. Of course, the buffer size can be flexibly adjusted according to the application scenario, and the depth and width can be optimized according to actual needs to improve the utilization efficiency of hardware resources.
[0051] When multi-level nested jumps occur, the jump buffer unit stores the instruction blocks aligned with the address where the jump occurred in sequence. Data will not be lost within the storage depth of the jump buffer unit, thus improving data security. When returning from a jump, the processor unit reads the return destination address instruction from the jump buffer unit in a last-in-first-out order, avoiding the problem of a jump miss.
[0052] Example 1, such as Figure 2 As shown, the processing flow for a JUMP Buffer write scenario when a jump occurs includes:
[0053] Step S201: Determine if the current action is a function jump;
[0054] The system checks whether the current instruction is a jump instruction using hardware logic or software instructions. There are no restrictions on this. If it is a jump instruction, the system proceeds to the next step and triggers subsequent cache operations to ensure that the instruction can be quickly retrieved when the jump returns. If it is not a jump instruction, the system continues to execute subsequent code.
[0055] Step S202: If the current jump is a function jump, store the instruction block aligned to the current address of the jump instruction (N bits) into the JUMP Buffer;
[0056] Store the instruction block aligned to the current address (N bits) into the JUMP Buffer. The JUMP Buffer follows the Last-In-First-Out (LIFO) principle to ensure that the cached instructions can be accessed in sequence. At the same time, to ensure that the complete instruction sequence can be directly retrieved from the JUMP Buffer when jumping back, the instructions stored are aligned to the current address (N bits).
[0057] Step S203: After the current instruction is stored in the JUMP Buffer, execute the jump instruction;
[0058] The current jump instruction is stored in the JUMP Buffer, and then the jump instruction is executed to jump to the target address. The processor then begins executing the code at the target address.
[0059] Step S204: If the current step is not a function jump, continue executing the code.
[0060] If the current instruction is not a function jump instruction, skip the JUMP Buffer buffering operation and continue executing subsequent instructions directly.
[0061] As can be seen from the above embodiments, compared with traditional cache, the advantages of the present invention are:
[0062] Specifically designed for function jump and return scenarios, it can efficiently cache jump instructions and related instructions. At the same time, it adopts a last-in-first-out strategy to ensure that the most recent jump instructions are always kept at the top level of the cache, significantly reducing cache misses when jumping and returning. Working together with traditional cache and prefetch buffer, it can further improve the overall performance of the system.
[0063] Example 2, as Figure 3 As shown, the processing flow for reading the JUMP Buffer during a jump return includes:
[0064] Step S301: Determine whether the current instruction is a jump return instruction;
[0065] The system checks whether the current instruction is a jump / return instruction using hardware logic or software instructions. If it is, it triggers the operation of reading the cached instruction from the JUMP Buffer; otherwise, it reads the instruction directly from the cache or prefetch buffer and continues normal execution.
[0066] Step S302: If it is a jump return instruction, then directly read the required return destination address instruction from the JUMP Buffer;
[0067] Reading cached instructions directly from the JUMP Buffer avoids the latency of reading instructions from main memory and reduces waiting cycles.
[0068] Step S303: If it is not a jump return instruction, then read the instruction at the required address from the cache or prefetch buffer;
[0069] If the current instruction is not a jump / return instruction, the instruction is read from the traditional cache structure, ensuring the normal execution of non-jump / return instructions without affecting the overall operation of the system.
[0070] Step S304: Determine whether the returned destination address instruction has been read;
[0071] Step S305: If the return destination address instruction is read, then start executing the instruction after the jump return;
[0072] Step S306: If the instruction at the returned destination address is not read, then the instruction is read from the main memory and executed.
[0073] Check if the instruction read from the JUMP Buffer is the instruction at the jump return address. If the read is successful, continue execution; if not, trigger the operation to read the instruction from main memory to ensure instruction continuity.
[0074] As can be seen from the above embodiments, compared with traditional cache, the advantages of the present invention are:
[0075] By caching jump instructions, main memory access caused by jump returns is reduced, thus lowering access latency. Furthermore, due to its efficient caching mechanism, the memory bandwidth requirement is low, and the jump pointer storage and lookup hit rate is high.
[0076] Example 3: Handling nested jumps:
[0077] Firstly, if a function jump occurs again, the processing flow of cached instructions during the jump is repeated. Instructions stored in the JUMP Buffer are replaced according to the last-in-first-out (LIFO) replacement rule, and the last instruction block stored is the top-level data. The JUMP Buffer depth is set to D, meaning that a full cache hit can be achieved when returning from a jump with a jump depth of D or less.
[0078] Secondly, if nested jumps occur, the top layer of the JUMP Buffer is accessed when the first jump returns. After access, the data is deleted, and the second layer of data in the JUMP Buffer becomes the top layer data. When the second jump returns, the top layer of the JUMP Buffer is still accessed to obtain the destination address instruction of the second jump return in the nested jump.
[0079] like Figure 4 The diagram illustrating a two-level nested jump and return mechanism uses a JUMP Buffer with a data width N of 128 bits and a depth D of 4 as an example. In this embodiment, multiple instructions aligned to their respective 128-bit addresses are collectively referred to as an instruction block. Instruction block B is executed sequentially following instruction block A. It achieves zero CPU access wait through prefetching, and instruction block B is not stored in the cache. The same applies to instruction block E. When the code reaches the jump return point of instruction block H, the instructions in the prefetch buffer have been replaced. Therefore, neither the cache nor the prefetch buffer contains instruction blocks B and E. In traditional cache schemes, instructions need to be read from main memory before execution, which greatly reduces system efficiency.
[0080] The JUMP Buffer provided by this invention caches instruction blocks B and E when a jump occurs. Therefore, when a jump return occurs, the jump return destination address instruction can be directly obtained from the JUMP Buffer without consuming a waiting cycle.
[0081] As can be seen from the above embodiments, compared with traditional cache, the advantages of the present invention are:
[0082] The JUMP Buffer scheme of this invention is highly adaptable to jump instructions and can effectively handle complex jump logic and nested jumps.
[0083] Corresponding to the above embodiments, this application also provides an electronic device, including a processor and flash memory, wherein the processor and flash memory access each other through the memory access method described above.
[0084] Those skilled in the art will recognize that the units and algorithm steps described in the embodiments disclosed herein can be implemented using electronic hardware, computer software, or a combination of electronic hardware and software. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0085] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0086] In the several embodiments provided in this application, any function, if implemented as a software functional unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0087] The above description is merely a specific embodiment of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application. The protection scope of this application should be determined by the protection scope of the claims.
Claims
1. An MCU cache device, characterized in that, include: Processor unit; Flash memory cells; A jump buffer unit is provided between the processor unit and the flash memory unit, and the jump buffer unit is configured to cache the instruction block whose address is aligned when the jump occurs.
2. The MCU cache device according to claim 1, characterized in that: The jump buffer unit has a D×Nbits storage structure, where D is the depth and N is the data bit width.
3. The MCU cache device according to claim 2, characterized in that: The data width N of the jump buffer unit is 128 bits.
4. The MCU cache device according to claim 1, characterized in that: The jump buffer unit adopts a last-in-first-out data replacement strategy.
5. The MCU cache device according to any one of claims 1-4, characterized in that: When a nested jump occurs, the jump buffer unit will store the instruction block aligned with the address where the jump occurred in sequence. When returning from a jump, the processor unit reads the return destination address instruction from the jump buffer unit in a last-in-first-out order.
6. A memory access method, characterized in that, Includes the following steps: Detect jump instructions during processor unit execution; When a function jump is detected, the instruction block aligned with the address where the jump occurred is stored in the jump buffer; When a jump return instruction is detected, the instruction to return to the destination address is read directly from the jump buffer; Execute the instruction to return the destination address.
7. The method according to claim 6, characterized in that, The step of "stores the instruction block aligned with the address where the jump occurs into the jump buffer" includes: Determine if the current instruction is a function jump instruction; If it is a function jump instruction, the instruction block aligned to the current address is stored in the jump buffer, and the jump instruction is executed; Otherwise, execute sequentially.
8. The method according to claim 6, characterized in that, The step of "reading the return destination address instruction directly from the jump buffer" includes: Determine if the current instruction is a jump / return instruction; If it is a jump return instruction, the required return destination address instruction is read from the top layer of the jump buffer; If the read is successful, execute the instruction to return to the destination address; If the read fails, the instruction is read from main memory and then executed.
9. The method according to claim 6, characterized in that, include: When nested jumps occur, the instruction caching process is repeated to store the return address instructions of each jump level into the jump buffer in sequence; When jumping back, the corresponding return destination address instruction is read from the jump buffer in a last-in-first-out (LIFO) order.
10. An electronic device, characterized in that, It includes a processor and flash memory, characterized in that: the processor and flash memory access each other via the method described in claims 6-9.