Branch prediction system and method
By using a two-level buffer cascade design and a dynamic splitting strategy in the branch prediction system, the problems of lag and hardware resource waste in predicting branches are solved, resulting in higher prediction accuracy and improved processor performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING YINGQI INTELLIGENT TECH CO LTD
- Filing Date
- 2026-01-20
- Publication Date
- 2026-05-12
AI Technical Summary
Existing technologies suffer from problems such as lag, insufficient accuracy, and high hardware resource consumption in speculative execution dependency chain analysis due to unpredictable branches.
A branch prediction system is adopted, including a main branch predictor, a decoupled queue, and a branch instruction stream processing unit. Through a two-level branch jump target buffer cascade design and a buffer for difficult-to-predict branch instructions, a dynamic entry splitting strategy is used to collect and analyze instruction stream information to improve prediction accuracy and hardware efficiency.
It improves the accuracy of unpredictable branches, reduces hardware resource consumption, and enhances processor performance and chip area efficiency.
Smart Images
Figure CN122018982A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of branch prediction technology, and in particular to a branch prediction system and method. Background Technology
[0002] Branch prediction errors are a major performance bottleneck in current processors. Some branches still cannot be easily predicted by mainstream high-precision branch predictors (such as TAGE-SC-L and Perceptron). These are often referred to as unpredictable branches, including data-dependent branches and branches with complex control flow patterns, which are difficult to identify during dynamic processor operation. The current common approach is to identify instructions in the dependency chains of unpredictable branches and analyze their dependencies to generate speculative instruction flows. The drawbacks of this method are: 1) Lag: It is difficult to fully meet the requirement that the computation result be completed before the branch is predicted; 2) Accuracy: Typical branch prediction unit designs only target unpredictable branches with simple or specific types of dependency chains, resulting in low flexibility and general coverage; 3) The branch predictor update mechanism is cumbersome, and the increasingly large memory units occupy a significant amount of chip area, requiring improvements in information storage density and hardware area efficiency. Summary of the Invention
[0003] Purpose of the invention: The purpose of this invention is to provide a branch prediction system and method that solves the problems of lag, insufficient accuracy, and high hardware resource consumption in speculative execution dependency chain analysis methods, which are difficult to predict branches.
[0004] Technical Solution: To achieve the above objectives, the present invention provides a branch prediction system comprising a main branch predictor, a decoupling queue, and a branch instruction stream processing unit. The main branch predictor includes a branch jump target buffer subsystem and a branch jump direction prediction subsystem. The decoupling queue generates entries containing a PC list and branch data. The branch instruction stream processing unit includes a buffer for difficult-to-predict branch instructions and a buffer for branch instruction stream information. The main branch predictor predicts branch instructions and inputs the generated prediction results into the decoupling queue. The branch instruction stream processing unit receives branch parsing information, identifies and analyzes the instruction stream of difficult-to-predict branches, and feeds back the analysis results to the main branch predictor.
[0005] Preferably, the branch jump target buffer subsystem is a two-level cascaded branch jump target buffer, wherein the first-level branch jump target buffer and the program counter generation logic are accessed in parallel at the same pipeline stage, and the second-level branch jump target buffer is accessed at the next stage of the pipeline stage where the first-level branch jump target buffer is located.
[0006] Preferably, the branch jump target buffer includes N entries, each entry including a valid field, a tag field, instruction block information, multiple branch instruction slots, entry splitting, and LRU. The instruction block information includes the number of instructions and the instruction block termination method.
[0007] Preferably, the branch jump target buffer allocation strategy is as follows: the existing entries of the branch block are indexed by the PC. If the entry exists and there is a free branch instruction slot, the corresponding branch information is added; if the entry exists but the branch instruction slot is full, the entry is split; if there is no entry, a new entry is allocated; when the branch jump target buffer is full, the least recently used entry is removed according to LRU.
[0008] Preferably, the strategy for splitting entries is as follows: add branch information, calculate the split point (the middle position of the instruction slot), create two new entries, Entry 1 and Entry 2, and assign all branches to the two new entries according to the split point: if the offset of the branch instruction in the instruction block is less than the split point, add it to Entry 1 as is; if the offset of the branch is greater than or equal to the split point, add it to Entry 2. For the branch instructions assigned to the entries, their offsets need to be adjusted. The new offset = the original offset – the split point, so that the branch offset in Entry 2 starts from 0, keeping the relative position unchanged. Further update the control flow pointer, that is, mark Entry 1 as already split, and set a target pointing to the starting position of Entry 2. When the end of Entry 1 is reached, jump to Entry 2.
[0009] Preferably, the information in the first-level branch jump target buffer is a subset of the information stored in the second-level branch jump target buffer.
[0010] Preferably, when a branch prediction error is parsed, the PC index is used to index the unpredictable branch instruction buffer. If a hit occurs, the counter is incremented; if a miss occurs, a new entry is allocated. Once the error prediction count exceeds a threshold, the branch is marked as unpredictable.
[0011] The method for applying the above-mentioned branch prediction system according to the present invention includes the following steps:
[0012] Step S1: Perform branch prediction through the main branch predictor, including the branch jump target buffer subsystem predicting the branch jump target address and the branch jump direction prediction subsystem predicting the branch jump direction;
[0013] Step S2: Decouple the queue to generate entries containing the PC list and branch data for use in the subsequent instruction extraction stage;
[0014] Step S3: When a branch prediction error is parsed, the branch instruction stream processing unit uses the PC index to index the unpredictable branch instruction buffer. If the error is hit, the counter is incremented; if the error is not hit, a new entry is allocated. When the error prediction count exceeds the threshold, the branch is marked as unpredictable.
[0015] Step S4: The branch instruction flow information buffer collects commit / exit instructions, performs backward instruction flow analysis, and provides instruction flow information for the branch predictor.
[0016] Preferably, in step S1, the method for accessing the branch jump target buffer subsystem includes:
[0017] Step S11: The first-level branch jump target buffer and the program counter generation logic are accessed in parallel at the same pipeline stage;
[0018] Step S12: The second-level branch jump target buffer is accessed in the next stage of the pipeline stage where the first-level branch jump target buffer is located;
[0019] Step S13: Update the PC value when the main branch predictor redirects the pipeline.
[0020] Preferably, in step S1, the method for allocating the branch jump target buffer includes:
[0021] If the existing entries in the PC index branch block exist and there are free branch instruction slots, then add the corresponding branch information.
[0022] If an entry exists but the branch instruction slot is full, split the entry, calculate the split point as the middle position of the instruction slot, create two new entries, and assign all branches to the two new entries according to the split point;
[0023] If there is no entry, a new entry is allocated. If the branch jump target buffer is full, the least recently used entry is removed according to LRU.
[0024] Beneficial effects: The present invention has the following advantages: 1. For unpredictable branch instructions, the present invention sets up an unpredictable branch instruction buffer and a branch instruction flow information buffer, collects commit / exit instructions and performs backward instruction flow analysis, providing instruction flow information for the branch predictor, thereby improving the accuracy of branch prediction; at the same time, it adopts a two-level branch jump target buffer cascade design, in which the first-level branch jump target buffer and the program counter generation logic are accessed in parallel at the same pipeline stage, effectively avoiding the lag problem existing in the speculative execution dependency chain analysis method.
[0025] 2. By adopting a dynamic splitting strategy for branch jump target buffer entries, entries are dynamically split when the branch slot capacity exceeds the limit. This optimizes the branch jump target buffer subsystem, which consumes the most hardware area in the branch predictor. Combined with the comprehensive increase in instruction stream information, this improves both performance and chip area efficiency. Attached Figure Description
[0026] Figure 1 A top-level view of the processor front end of the branch prediction system;
[0027] Figure 2 A structural diagram of the branch jump target buffer;
[0028] Figure 3 A flowchart for accessing the target buffer subsystem for branch jumps;
[0029] Figure 4 Storing information graphs for buffer entries of unpredictable branch instructions;
[0030] Figure 5 Flowchart for detecting data flow in unpredictable branch instruction buffers;
[0031] Figure 6 Store information graphs for entries in the branch instruction stream information buffer;
[0032] Figure 7 The flowchart for the backward instruction flow analysis process is shown in the branch instruction flow information buffer. Detailed Implementation
[0033] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.
[0034] Example 1
[0035] like Figure 1 As shown, a branch prediction system includes a main branch predictor, a decoupling queue, and a branch instruction stream processing unit.
[0036] The main branch predictor includes a branch jump target buffer subsystem and a branch jump direction prediction subsystem, which are used to predict the branch instruction jump target address and jump direction (whether to jump) respectively.
[0037] The decoupled queue generates entries containing a list of PCs and branch data.
[0038] The branch instruction flow information processing unit includes a buffer for unpredictable branch instructions and a buffer for branch instruction flow information. The branch instruction prediction buffer is used to quickly identify unpredictable branch instructions and provide fine-grained branch behavior tracking. The branch instruction flow information buffer is a circular queue of N entries (the larger N is, the more complete the instruction flow information is recorded, and the better it can support the prediction of branch instructions that are difficult to predict accurately), used to collect commit / exit instructions and perform backward instruction flow analysis.
[0039] like Figure 1 As shown, the information flow processing relationship between the main branch predictor, the decoupling queue, and the branch instruction stream processing unit is as follows: The main branch predictor predicts branch instructions through the branch jump target buffer subsystem and the branch jump direction prediction subsystem. The prediction results are input into the decoupling queue to generate entries containing PC lists and branch data for use in the subsequent instruction extraction stage. The branch instruction stream processing unit receives branch parsing information from the instruction execution stage, identifies unpredictable branches through the unpredictable branch instruction buffer, performs backward instruction stream analysis through the branch instruction stream information buffer, and feeds the analysis results back to the main branch predictor to dynamically update the prediction model.
[0040] Example 2
[0041] The branch jump direction prediction subsystem can employ commonly used prediction algorithm hardware architectures, such as TAGE-SC-L and Perceptron. Considering performance and area overhead efficiency, the branch jump target buffer subsystem consists of two cascaded branch target buffers (BTBs). The first-level branch target buffer (Level 1 BTB) and the program counter (PC) generation logic are accessed in parallel at the same pipeline stage, ensuring that the main branch predictor's redirection of the pipeline (i.e., updating the PC value) does not incur pipeline flushing cycle overhead. The second-level branch target buffer (Level 2 BTB) is accessed at the next level in the pipeline stage where the first-level branch target buffer is located.
[0042] The two-level branch jump target buffer design is optimized for different access latencies. Each entry in the branch jump target buffer can cache multiple sequential instruction blocks. Entries can be dynamically split when the branch slot capacity is exceeded. The validity field indicates the availability of the entry; the tag field is the high-order PC address used for entry identification; the instruction block information includes the instruction count and the instruction block termination method (sequential fetch, direct branch jump, indirect branch jump, function return); the entry splitting indicator shows whether the entry was split due to branch instruction slot overflow; LRU (Least Recently Used) is used to evict entries when the buffer is full. Each entry can contain N branch instruction slots (the specific number can be determined according to the instruction flow requirements of the covered application scenario), and the information stored in the branch instruction slots is as follows: Figure 2 As shown in the figure, the branch stability count represents the stability of the indirect jump branch instruction, and the in-entry jump indicator indicates whether to continue jumping within the current entry (if not, directly return to the branch jump target of the current slot).
[0043] The second-level branch jump target buffer has a similar general structure to the first-level branch jump target buffer. The main differences are: 1) The second-level branch jump target buffer is designed to have a larger capacity and stores more branch instruction information; 2) It does not store branch stability counts; 3) The information in the first-level branch jump target buffer is a subset of the information stored in the second-level branch jump target buffer.
[0044] The branch jump target buffer allocation strategy is as follows:
[0045] If the existing entries in the PC index branch block exist and there are free branch instruction slots, then add the corresponding branch information.
[0046] If an entry exists but the branch instruction slot is full, the entry is split: add branch information, then calculate the split point (the middle position of the instruction slot), create two new entries (the original entry is not reused), and assign all branches to the two new entries (e.g., entry 1 and entry 2) based on the split point: if the branch instruction's offset in the instruction block is less than the split point, add it to entry 1 as is; if the branch's offset is greater than or equal to the split point, add it to entry 2. For branch instructions assigned to an entry, their offsets need to be adjusted: new offset = original offset – split point. This way, the branch offsets in entry 2 start from 0, maintaining their relative positions. Then, the control flow pointer needs to be updated, marking entry 1 as split and setting a target pointing to the beginning of entry 2. When the end of entry 1 is reached, a jump to entry 2 is initiated.
[0047] If no entry is available, a new entry is allocated. If the branch jump target buffer is full, the least recently used entry is removed according to LRU.
[0048] The flowchart for branch jump target buffer subsystem access is as follows: Figure 3 As shown. The specific process is as follows: First, the PC index is used to jump to the target buffer and it is determined whether a hit occurs; if a hit occurs, the branch instruction information in the entry is read and the jump target address is obtained according to the branch type; if a hit occurs, the instruction fetching continues sequentially; after the branch parsing is completed, the branch jump target buffer is updated according to the parsing result, including adding new entries or updating existing entry information.
[0049] Example 3
[0050] In the branch instruction stream information processing unit, it is difficult to predict the information stored in the branch instruction buffer entries, such as... Figure 4 As shown, its entry storage information includes fields such as valid fields, branch instruction PC, and error prediction count. When a branch prediction error is parsed, the branch instruction buffer is difficult to predict using the PC index. If a hit occurs, the counter is incremented; otherwise, a new entry is allocated. Branches are marked as difficult to predict when the error prediction count exceeds a threshold. The detection data stream is as follows: Figure 5 As shown, this process demonstrates the complete data flow processing from branch parsing error detection to unpredictable branch markers.
[0051] In the branch instruction stream information processing unit, the branch instruction stream information buffer entries store information such as... Figure 6 As shown, its entry storage information includes fields such as valid fields, instruction PC, instruction type, and register dependency information, used to record detailed information about commit / exit instructions. The backward instruction flow analysis process of the branch instruction flow information buffer is as follows: Figure 7 As shown, the process begins with the identification of branches that are difficult to predict, then iterates backward through the historical instructions in the branch instruction flow information buffer, analyzes data dependencies, and extracts instruction flow information related to the branch, providing more comprehensive contextual information for subsequent branch prediction.
[0052] Example 4
[0053] This embodiment provides a branch prediction method based on the branch prediction system described in embodiments 1-3. The method includes the following steps:
[0054] Step S1: Perform branch prediction through the main branch predictor. The branch jump target buffer subsystem in the main branch predictor predicts the branch jump target address, and the branch jump direction prediction subsystem predicts the branch jump direction.
[0055] Step S2: Decouple the queue to generate entries containing the PC list and branch data for use in the subsequent instruction extraction stage;
[0056] Step S3: When a branch prediction error is parsed, the branch instruction stream processing unit uses the PC index to index the unpredictable branch instruction buffer. If the error is hit, the counter is incremented; if the error is not hit, a new entry is allocated. When the error prediction count exceeds the threshold, the branch is marked as unpredictable.
[0057] Step S4: The branch instruction flow information buffer collects commit / exit instructions, performs backward instruction flow analysis, and provides instruction flow information for the branch predictor.
[0058] Further, in step S1, the method for accessing the branch jump target buffer subsystem includes:
[0059] Step S11: The first-level branch jump target buffer and the program counter generation logic are accessed in parallel at the same pipeline stage;
[0060] Step S12: The second-level branch jump target buffer is accessed in the next stage of the pipeline stage where the first-level branch jump target buffer is located;
[0061] Step S13: Update the PC value when the predictor redirects the pipeline.
[0062] Furthermore, the allocation method for the branch jump target buffer includes:
[0063] If the existing entries in the PC index branch block exist and there are free branch instruction slots, then add the corresponding branch information.
[0064] If an entry exists but the branch instruction slot is full, split the entry, calculate the split point as the middle position of the instruction slot, create two new entries, and assign all branches to the two new entries according to the split point;
[0065] If there is no entry, a new entry is allocated. If the branch jump target buffer is full, the least recently used entry is removed according to LRU.
[0066] The branch prediction method provided in this embodiment achieves targeted optimization of difficult-to-predict branch instructions through the collaborative work of the main branch predictor, the decoupled queue, and the branch instruction stream processing unit. It comprehensively increases the instruction stream information provided to the branch predictor, thereby improving the accuracy of branch prediction and processor performance.
Claims
1. A branch prediction system, characterized in that, The system includes a main branch predictor, a decoupling queue, and a branch instruction stream processing unit. The main branch predictor comprises a branch jump target buffer subsystem and a branch jump direction prediction subsystem. The decoupling queue generates entries containing a PC list and branch data. The branch instruction stream information processing unit includes a buffer for difficult-to-predict branch instructions and a buffer for branch instruction stream information. The main branch predictor predicts branch instructions and inputs the prediction results to the decoupling queue. The branch instruction stream processing unit receives branch parsing information, identifies and analyzes the instruction stream of difficult-to-predict branches, and feeds back the analysis results to the main branch predictor.
2. The branch prediction system according to claim 1, characterized in that, The branch jump target buffer subsystem is a two-level cascaded branch jump target buffer. The first-level branch jump target buffer is accessed in parallel with the program counter generation logic in the same pipeline stage, and the second-level branch jump target buffer is accessed in the next stage of the pipeline stage where the first-level branch jump target buffer is located.
3. The branch prediction system according to claim 2, characterized in that, The branch jump target buffer includes N entries. Each entry includes a valid field, a tag field, instruction block information, multiple branch instruction slots, entry splitting, and LRU. The instruction block information includes the number of instructions and the instruction block termination method.
4. The branch prediction system according to claim 2, characterized in that, The branch jump target buffer allocation strategy is as follows: the existing entries of the branch block are indexed by the PC. If the entry exists and there is a free branch instruction slot, the corresponding branch information is added; if the entry exists but the branch instruction slot is full, the entry is split; if there is no entry, a new entry is allocated. When the branch jump target buffer is full, the least recently used entry is removed according to LRU.
5. The branch prediction system according to claim 4, characterized in that, The strategy for splitting entries is as follows: Add branch information, calculate the split point (the middle position of the instruction slot), create two new entries, entry 1 and entry 2, and assign all branches to the two new entries based on the split point: if the offset of the branch instruction in the instruction block is less than the split point, add it to entry 1 as is; if the offset of the branch is greater than or equal to the split point, add it to entry 2. For branch instructions assigned to an entry, adjust their offsets: new offset = original offset – split point, so that the branch offsets in entry 2 start from 0, maintaining their relative positions. Further update the control flow pointer, marking entry 1 as already split, and setting a target pointing to the starting position of entry 2. When the end of entry 1 is reached, jump to entry 2.
6. The branch prediction system according to claim 2, characterized in that, The information in the first-level branch jump target buffer is a subset of the information stored in the second-level branch jump target buffer.
7. The branch prediction system according to claim 1, characterized in that, When a branch prediction error is parsed, the PC index is used to index the unpredictable branch instruction buffer. If a hit occurs, the counter is incremented; if a miss occurs, a new entry is allocated. Once the error prediction count exceeds the threshold, the branch is marked as unpredictable.
8. A method applied to the branch prediction system of claim 1, characterized in that, Includes the following steps: Step S1: Perform branch prediction through the main branch predictor, including the branch jump target buffer subsystem predicting the branch jump target address and the branch jump direction prediction subsystem predicting the branch jump direction; Step S2: Decouple the queue to generate entries containing the PC list and branch data for use in the subsequent instruction extraction stage; Step S3: When a branch prediction error is parsed, the branch instruction stream processing unit uses the PC index to index the unpredictable branch instruction buffer. If the error is hit, the counter is incremented; if the error is not hit, a new entry is allocated. When the error prediction count exceeds the threshold, the branch is marked as unpredictable. Step S4: The branch instruction flow information buffer collects commit / exit instructions, performs backward instruction flow analysis, and provides instruction flow information for the branch predictor.
9. The branch prediction method according to claim 8, characterized in that, In step S1, the access method for the branch jump target buffer subsystem includes: Step S11: The first-level branch jump target buffer and the program counter generation logic are accessed in parallel at the same pipeline stage; Step S12: The second-level branch jump target buffer is accessed in the next stage of the pipeline stage where the first-level branch jump target buffer is located; Step S13: Update the PC value when the main branch predictor redirects the pipeline.
10. The branch prediction method according to claim 8, characterized in that, In step S1, the method for allocating the branch jump target buffer includes: If the existing entries in the PC index branch block exist and there are free branch instruction slots, then add the corresponding branch information. If an entry exists but the branch instruction slot is full, split the entry, calculate the split point as the middle position of the instruction slot, create two new entries, and assign all branches to the two new entries according to the split point; If there is no entry, a new entry is allocated. If the branch jump target buffer is full, the least recently used entry is removed according to LRU.