RISC-V vector compression method and device

Abstract

The invention relates to the technical field of computers, in particular to an RISC-V vector compression method and device. The method comprises the following steps: receiving a vector compression instruction; according to the bit width of the masks, grouping the masks according to a preset sequence and a fixed interval; shifting elements in the to-be-compressed vector data corresponding to each mask group to form an intermediate compression result corresponding to the mask group; wherein the intermediate compression results corresponding to the adjacent mask groups respectively form a high-order group and a low-order group of the intermediate compression group; executing the following iteration steps: merging and compressing elements of the high-order group and the low-order group in each intermediate compression group in parallel to form the high-order group or the low-order group of the updated intermediate compression group; and the compression of the to-be-compressed vector data is completed. By utilizing the embodiment of the invention, the vector compression instruction can be executed in parallel, and the compression efficiency is improved.

Description

Technical Field

[0001] This specification relates to the field of computer technology, and in particular to a RISC-V vector compression method and apparatus. Background Technology

[0002] RISC-V stands for Reduced Instruction Set Computing, and it is currently one of the most widely used reduced instruction sets. The RISC-V vector instruction set introduces a variable-length vector instruction set. Most arithmetic instructions in the RISC-V vector instruction set have the following characteristic: for binary operations, the nth element of one vector is only operated on with the nth element of another vector.

[0003] Vector compression instructions in the RISC-V architecture enable efficient compression of vector data. However, current techniques use a traversal method, which checks the validity of each source operand sequentially and places valid source elements into the lowest element position of the destination register. The problem with this traversal method is its poor timing and long execution cycle.

[0004] How to control data operations in the cache to reduce the frequent eviction and refilling of cache lines at the same address, thereby reducing system power consumption, is an urgent problem to be solved. Summary of the Invention

[0005] To address the problems in the prior art, this specification provides a RISC-V vector compression method and apparatus, which solves the problem of low vector data compression efficiency in the prior art.

[0006] This specification provides an embodiment of a RISC-V vector compression method, which includes: Receive a vector compression instruction, the vector compression instruction including vector data to be compressed and a mask indicating the validity of each element in the vector data to be compressed; Based on the bit width of the mask, the mask is grouped in a predetermined order and at fixed intervals; The elements in the vector data to be compressed corresponding to each mask group are shifted to form an intermediate compression result corresponding to the mask group; wherein, the intermediate compression results corresponding to adjacent mask groups form the high-bit group and low-bit group of the intermediate compression group respectively. Perform the following iterative steps: merge and compress the elements of the high-order and low-order groups in each intermediate compression group in parallel to form the high-order or low-order group of the updated intermediate compression group; until the compression of the vector data to be compressed is completed.

[0007] As a further aspect of this specification, grouping the mask according to its bit width, in a predetermined order and at fixed intervals, further includes: In ascending order, adjacent masks with fixed intervals are grouped into a mask group.

[0008] As a further aspect of this specification, two adjacent masks are grouped into a mask group.

[0009] As a further aspect of this specification, shifting multiple elements in the vector data to be compressed corresponding to each mask group to form an intermediate compression result corresponding to the mask group further includes: Based on the indication of the mask in the mask group, determine the valid elements in the vector data to be compressed; The valid elements in the mask group are shifted sequentially to the lower bits of the intermediate compression result.

[0010] As a further aspect of this specification, shifting the valid element to the lower bits of the intermediate compression result further includes: The high-order bits of the intermediate compression result are padded with 0.

[0011] As a further aspect of this specification, determining the valid elements in the vector data to be compressed, based on the indication of the mask in the mask group, further includes: When the mask of the mask group is 00, it indicates that both corresponding elements are invalid. When the mask of the mask group is 01, it indicates that the first element is an invalid element and the second element is a valid element. When the mask of the mask group is 10, it indicates that the first element is a valid element and the second element is an invalid element. When the mask of the mask group is 11, it indicates that both corresponding elements are valid elements.

[0012] As a further aspect of this specification, merging and compressing the elements of the high-order and low-order groups in the intermediate compression group further includes: The number of shift bits is determined based on the number of invalid masks in the mask group corresponding to the low-order group in the intermediate compression group of the current iteration; Shift the elements of the high-order group in the intermediate compression group to the right by the shift number to form an overflow element; The overflow element is merged with the element of the low-order group in the intermediate compression group to form the high-order group or low-order group of the updated intermediate compression group.

[0013] As a further aspect of this specification, merging the overflow element with the elements of the lower-order group in the intermediate compression group to form the higher-order group or lower-order group of the updated intermediate compression group further includes: The overflow element is bitwise ORed with the elements of the low-order group in the intermediate compression group, and the high-order group in the intermediate compression group is padded with 0 to form the updated high-order or low-order group of the intermediate compression group.

[0014] As a further aspect of this specification, the parallel merging and compression of the elements of the high-order and low-order groups in each intermediate compression group to form the high-order or low-order group of the updated intermediate compression group further includes: Use the high-order and low-order groups of adjacent updated intermediate compression groups as the updated intermediate compression groups; The iterative steps are performed on the updated intermediate compression group.

[0015] As another further aspect of this specification, when the vector register group multiplier LMUL is greater than 1, the vector data to be compressed occupies multiple vector registers; Calculate the portion of compressed data in each vector register of the vector data to be compressed; Partial compressed data of each vector register is used as the intermediate compression result, and the intermediate compression results corresponding to the two vector registers are respectively used as the high-order group and low-order group of the intermediate compression group. The iterative steps are performed until the compression of the vector data to be compressed is complete.

[0016] This specification also provides an embodiment of a RISC-V vector compression device, comprising: The instruction receiving unit is configured to receive a vector compression instruction, which includes vector data to be compressed and a mask indicating the validity of each element in the vector data to be compressed. The mask grouping unit is configured to group the mask according to the bit width of the mask, in a predetermined order and at a fixed interval; The intermediate compression group unit is configured to shift the elements in the vector data to be compressed corresponding to each mask group to form an intermediate compression result corresponding to the mask group; wherein the intermediate compression results corresponding to adjacent mask groups form the high-order group and low-order group of the intermediate compression group, respectively. The iterative unit is configured to perform the following iterative steps: merging and compressing the elements of the high-order and low-order groups in each intermediate compression group in parallel to form the high-order or low-order group of the updated intermediate compression group; until the compression of the vector data to be compressed is completed.

[0017] This specification also provides a vector execution unit, which executes the above-described vector compression method.

[0018] This specification also provides a processor, including the vector execution unit described above, in its embodiments.

[0019] This specification also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is the processor described above.

[0020] This specification also provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the above-described method.

[0021] This specification also provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.

[0022] Using the embodiments of this specification, parallel processing of grouped vector data to be compressed can improve the efficiency of vector compression operations. Furthermore, due to the iterative processing in the process, shift registers of the same bit width can be reused, thereby reducing the number of shift registers, reducing the circuit area of ​​the shift registers, and thus reducing the size of the processor. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 The diagram shown is a flowchart of a RISC-V vector compression method according to an embodiment of this specification. Figure 2 The diagram shown is a schematic diagram of the grouping of the mask according to an embodiment of this specification; Figure 3 The diagram shown is a schematic diagram of vector compression for LMUL=8 in an embodiment of this specification; Figure 4 The diagram shown is a schematic of the compression method for vectors using actual data, with sew=8 as an example, as an example of an embodiment in this specification. Figure 5 The image shown is related to Figure 4 A schematic diagram of the corresponding vector data compression method; Figure 6 The diagram shown is a schematic of a vector data compression method using sew=16 as an example in this specification. Figure 7 The diagram shown is a schematic of a vector data compression method using sew=32 as an example in this specification. Figure 8The diagram shown is a schematic of a vector data compression method using sew=64 as an example in this specification. Figure 9 The diagram shown is a schematic representation of the mask generation method in an embodiment of this specification. Figure 10 The diagram shown is a multiplexing structure diagram of the shift register in an embodiment of this specification; Figure 11 The diagram shown is a schematic diagram of a RISC-V vector compression device according to an embodiment of this specification. Figure 12 This is a computer device provided as an embodiment of the present specification.

[0025] [Explanation of Labels in the Attached Image]

[0026] 1101. Command Receiving Unit; 1102, Masking Grouping Unit; 1103, Intermediate Compression Unit; 1104, Iteration Unit; 1202. Computer equipment; 1204, Processor; 1206. Memory; 1208. Drive mechanism; 1210. Input / output module; 1212. Input devices; 1214. Output devices; 1216. Presentation equipment; 1218. Graphical User Interface; 1220. Network interface; 1222. Communication link; 1224. Communication bus. Detailed Implementation

[0027] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0028] The vector compression instruction (vcompress) is a binary operation. The first source operand is treated as the data to be compressed, and each element is divided into elements with a sew width (the width of a single sew element). The second source operand acts as a valid element indicator, dividing the corresponding element into 1-bit widths. That is, if the lowest bit of the second source operand is 1, it indicates that the lowest position of the first operand is valid; if it is 0, the element is invalid. If the second lowest bit of the second source operand is 1, it indicates that the second lowest position of the first operand is valid; if it is 0, the element is invalid, and so on, essentially using a mask-like layout. The result of executing this instruction is that, based on the single-bit valid indication of the second operand, the valid elements in the first source operand are compressed towards lower positions, while the invalid elements with empty higher bits are considered tail elements, where the tail elements remain unchanged.

[0029] like Figure 1 The diagram shown is a flowchart of a RISC-V vector compression method according to an embodiment of this specification. The diagram illustrates that by grouping data into mask groups and then grouping the vector data to be compressed corresponding to each mask group into intermediate compression groups, the data in each intermediate compression group can be shifted and compressed in parallel according to the mask groups. By iteratively shifting and compressing the intermediate compression groups, the compression of the vector data to be compressed in the vector register can be completed within one clock cycle, thereby improving the efficiency of vector compression. The specific methods include: Step 101: Receive a vector compression instruction, wherein the vector compression instruction includes vector data to be compressed and a mask indicating the validity of each element in the vector data to be compressed; Step 102: Group the mask according to the bit width of the mask, in a predetermined order and at a fixed interval; Step 103: Shift the elements in the vector data to be compressed corresponding to each mask group to form an intermediate compression result corresponding to the mask group; wherein, the intermediate compression results corresponding to adjacent mask groups form the high-bit group and low-bit group of the intermediate compression group respectively. Step 104: Perform the following iterative steps: merge and compress the elements of the high-order and low-order groups in each intermediate compression group in parallel to form the high-order or low-order group of the updated intermediate compression group; until the compression of the vector data to be compressed is completed.

[0030] The method described in this specification can improve the efficiency of vector compression operations by processing the grouped vector data in parallel. Furthermore, due to the iterative processing in the process, shift registers with the same bit width can be reused, thereby reducing the number of shift registers, reducing the circuit area of ​​the shift registers, and thus reducing the size of the processor.

[0031] In the embodiments of this specification, grouping the mask according to the bit width of the mask in a predetermined order and at fixed intervals further includes: In ascending order, adjacent masks with fixed intervals are grouped into a mask group.

[0032] In this embodiment, as Figure 2 The diagram illustrates the grouping of the mask in an embodiment of this specification. In this diagram, V0 is the mask, V1 is the vector data to be compressed, V2 is the original data in the vector register, and V2' is the target compressed vector data after compressing the vector data to be compressed. Bit 0 (value 1 in the diagram) in V0 indicates that the corresponding vector data to be compressed is a valid element, and bit 1 (value 0 in the diagram) indicates that the corresponding vector data to be compressed is an invalid element. In this example, the mask width can be 8 bits, with the rightmost bit being the least significant bit and the leftmost bit being the most significant bit. The fixed interval can be 2, 4, or 8 bits, that is, the mask is grouped from least significant bit to most significant bit with an interval of 2 bits, 4 bits, or 8 bits. For example, a 2-bit mask will be used as an example. Figure 2 In the middle V0, each two bits of the mask are divided into a mask group. The right side of a mask group is the low bit and the left side is the high bit. In this example, the mask is divided into 4 mask groups with a fixed interval of 2 bits based on the 8-bit width. The masks corresponding to the mask groups are: the first mask group 01, the second mask group 01, the third mask group 10, and the fourth mask group 10.

[0033] In this embodiment of the specification, shifting multiple elements in the vector data to be compressed corresponding to each mask group to form an intermediate compression result corresponding to the mask group further includes: Based on the indication of the mask in the mask group, determine the valid elements in the vector data to be compressed; The valid elements in the mask group are shifted sequentially to the lower bits of the intermediate compression result.

[0034] In this embodiment, 0 in the mask group represents invalid elements and 1 represents valid elements. The valid elements in the vector data to be compressed indicated by mask 1 are shifted to the lower bits of the intermediate compression result, referencing... Figure 2In this embodiment, the vector data to be compressed, indicated by 1 in each mask group, is obtained in ascending order. The 01 in the first mask group of V0 indicates 10 of the vector data V1 to be compressed, and the 1 in the first mask group corresponds to the valid element 0 of the vector data V1 to be compressed, where the valid element 0 is located in the low-order bits of the vector data V1 to be compressed. The 01 in the second mask group of V0 indicates 32 of the vector data V1 to be compressed, and the 1 in the second mask group corresponds to the valid element 2 of the vector data V1 to be compressed, where the valid element 2 is located in the low-order bits of the vector data V1 to be compressed. The 10 in the third mask group of V0 indicates 54 of the vector data V1 to be compressed, and the 1 in the third mask group corresponds to the valid element 5 of the vector data V1 to be compressed, where the valid element 5 is located in the high-order bits of the vector data V1 to be compressed. The 10 in the fourth mask group of V0 indicates 76 of the vector data V1 to be compressed, and the 1 in the fourth mask group corresponds to the valid element 7 of the vector data V1 to be compressed, where the valid element 7 is located in the high-order bits of the vector data V1 to be compressed.

[0035] The valid elements corresponding to the first mask group are shifted to the low bits of the intermediate compression result, and 0 is added to the high bits of the intermediate compression result, so the intermediate compression result for the first mask group is 00; the valid elements corresponding to the second mask group are shifted to the low bits of the intermediate compression result, and 0 is added to the high bits of the intermediate compression result, so the intermediate compression result for the second mask group is 02; the valid elements corresponding to the third mask group are shifted to the low bits of the intermediate compression result, and 0 is added to the high bits of the intermediate compression result, so the intermediate compression result for the third mask group is 05; the valid elements corresponding to the fourth mask group are shifted to the low bits of the intermediate compression result, and 0 is added to the high bits of the intermediate compression result, so the intermediate compression result for the fourth mask group is 07.

[0036] In another embodiment, if the mask group is 11, the indicated vector data to be compressed is 98. The 1 in the mask group corresponds to the valid element 98 of the vector data to be compressed, the valid element 9 is located in the high-order bits of the vector data to be compressed, and the valid element 8 is located in the low-order bits of the vector data to be compressed. The valid elements corresponding to the mask group are sequentially shifted to the low-order bits of the intermediate compression result. Since there are two valid elements corresponding to the mask group, it is not necessary to pad the high-order bits of the intermediate compression result with 0s. The intermediate compression result corresponding to this mask group is 98.

[0037] In this embodiment of the specification, determining the valid elements in the vector data to be compressed based on the indication of the mask in the mask group further includes: When the mask of the mask group is 00, it indicates that both corresponding elements are invalid. When the mask of the mask group is 01, it indicates that the first element is an invalid element and the second element is a valid element. When the mask of the mask group is 10, it indicates that the first element is a valid element and the second element is an invalid element. When the mask of the mask group is 11, it indicates that both corresponding elements are valid elements.

[0038] In this embodiment, a 2-bit mask group is used as an example for illustration. In other embodiments, the mask group can also be of other lengths, such as 4 bits, 8 bits, etc.

[0039] When the mask of the mask group is 00, it indicates that both elements corresponding to the vector data to be compressed are invalid elements; When the mask of the mask group is 01, it indicates that the first element (high bit) of the vector data to be compressed is an invalid element and the second element (low bit) is a valid element; for example, if the high bit of the lowest two bits of mask V0 is 0 and the low bit is 1, the valid element of the vector data to be compressed is 0. When the mask of the mask group is 10, it indicates that the first element (high bit) is a valid element and the second element (low bit) is an invalid element; for example, if the high bit of the two highest bits of mask V0 is 1 and the low bit is 0, the valid element corresponding to the vector data to be compressed is 7. When the mask of the mask group is 11, it indicates that both corresponding elements are valid elements.

[0040] In the embodiments of this specification, merging and compressing the elements of the high-order and low-order groups in the intermediate compression group further includes: The number of shift bits is determined based on the number of invalid masks in the mask group corresponding to the low-order group in the intermediate compression group of the current iteration; Shift the elements of the high-order group in the intermediate compression group to the right by the shift number to form an overflow element; The overflow element is merged with the element of the low-order group in the intermediate compression group to form the high-order group or low-order group of the updated intermediate compression group.

[0041] In this embodiment, reference Figure 2 In the illustrated embodiment, the two mask groups formed by the low-order bits 0101 of V0 correspond to the intermediate compression result 02 and the intermediate compression result 00, respectively. The two adjacent intermediate compression results constitute the high-order group (02) and the low-order group (00) of the intermediate compression group. The shift bit (i.e., shift by 1 bit) is determined according to the number of invalid masks (i.e., the number of 0s, which is 1 in this example) in the mask group (01) corresponding to the low-order group of the intermediate compression group.

[0042] The element (02) of the high-order group in the middle compression group is shifted 1 bit to the right, forming the overflow element 2.

[0043] The overflow element 2 is merged with the element 0 of the low-order group in the intermediate compressed group (i.e., the high-order bit of the low-order group). That is, the overflow element 2 is bitwise ORed with the element 0 of the low-order group in the intermediate compressed group to obtain the low-order group element sequence 20 of the intermediate compressed group. After merging with the element sequence 00 of the high-order group shifted 1 bit to the right, the updated element sequence 0020 is formed. This element sequence 0020 serves as the low-order group of the updated intermediate compressed group.

[0044] The two mask groups formed by the high-order bits 1010 of V0 correspond to the intermediate compression results 07 and 05, respectively. The two adjacent intermediate compression results constitute the high-order group (07) and low-order group (05) of the intermediate compression group. The shift bit (i.e., shift by 1 bit) is determined according to the number of invalid masks (i.e., the number of 0s, which is 1 in this example) in the mask group (10) corresponding to the low-order group of the intermediate compression group.

[0045] The element (07) of the high-order group in the middle compression group is shifted 1 bit to the right, forming the overflow element 7.

[0046] The overflow element 7 is merged with the element 0 of the low-order group in the intermediate compression group (i.e., the high-order bit of the low-order group). That is, the overflow element 7 is bitwise ORed with the element 0 of the low-order group in the intermediate compression group to obtain the low-order group element sequence 75 of the intermediate compression group. After merging with the high-order group element sequence 00 shifted 1 bit to the right, the updated element sequence 0075 is formed. This element sequence 0075 serves as the high-order group of the updated intermediate compression group.

[0047] In the embodiments of this specification, merging and compressing the elements of the high-order and low-order groups in each intermediate compression group in parallel to form the high-order or low-order group of the updated intermediate compression group further includes: Use the high-order and low-order groups of adjacent updated intermediate compression groups as the updated intermediate compression groups; The iterative steps are performed on the updated intermediate compression group.

[0048] In this embodiment, an updated intermediate compression group is formed based on the high-order group and low-order group of the updated intermediate compression group, and the aforementioned merging and compression steps are repeated for the updated intermediate compression group.

[0049] Continuing with the foregoing embodiments, refer to Figure 2 The iterative steps include: The shift bit (i.e., shift by 2 bits) is determined based on the number of invalid masks (i.e., the number of 0s, which is 2 in this example) in the mask group (0101) corresponding to the lower bit of the updated intermediate compression group.

[0050] The element (0075) of the high-order group in the intermediate compression group is shifted 2 bits to the right, forming the overflow element 75.

[0051] The overflow element 75 is merged with the element 00 (i.e., the high bit of the low bit group) in the intermediate compression group. That is, 75 and 00 are bitwise ORed to obtain the low bit group element 75 of the intermediate compression group. After merging with the element 20 of the high bit group shifted 2 bits to the right, the updated element sequence 7520 is formed. This element sequence is written into the low bit of V2 to form the final target compressed vector data 23457520, where the high bit 2345 in V2 is the tail element.

[0052] In the embodiments described in this specification, when the vector register set multiplier (LMUL) is greater than 1, the vector data to be compressed occupies multiple vector registers; Calculate the portion of compressed data in each vector register of the vector data to be compressed; Partial compressed data of each vector register is used as the intermediate compression result, and the intermediate compression results corresponding to the two vector registers are respectively used as the high-order group and low-order group of the intermediate compression group. The iterative steps are performed until the compression of the vector data to be compressed is complete.

[0053] In this embodiment, when LMUL is greater than 1 (e.g., LMUL equals 2, 4, or 8), such as when LMUL equals 8, it can support the compression of data in 8 vector registers. First, the data in each vector register is compressed according to the method in the above embodiment to obtain the compressed data in each vector register. This is used as an intermediate compression result. The two parts of the vector data to be compressed that are sequentially adjacent and have been compressed in two vector registers are used as the high-order and low-order groups of an intermediate compression group. Then, according to the method of the aforementioned iterative steps, the compressed data involving two vector registers in the intermediate compression group can be compressed again to form an updated intermediate compression group. The sequentially adjacent updated intermediate compression groups are used to form the high-order and low-order groups of the updated intermediate compression group. Then, the process is repeated until the vector data to be compressed occupying multiple vector registers is compressed.

[0054] For details, please refer to... Figure 3 The diagram shown is a vector compression illustration for LMUL=8 in an embodiment of this specification. In this diagram, a 1024-bit vector data to be compressed is used as an example. The vector data to be compressed is divided into 8 consecutive 128-bit blocks (denoted as block 0 to block 7, where block 0 is the lowest 128 bits and block 7 is the highest 128 bits). At the same time, the corresponding mask is also divided into 8 16-bit mask groups (corresponding to 16 8-bit elements of each 128-bit block).

[0055] Processing for each block: Reusing the process of LMUL≤1 in the previous embodiment (including forming intermediate compression results corresponding to the mask group, forming the high-order and low-order groups of two adjacent intermediate compression results into an intermediate compression group, and performing iterative steps to finally complete the vector data compression of the vector register where each 128-bit block is located) yields two key outputs: zero_n (n=0-7): The total number of zeros in the mask block of the nth 128-bit block (for example, if the mask of block 0 has 5 zeros, then zero_0=5). r1_n (n=0-7): Partial compressed data after the nth 128-bit block has completed lmul=1 data compression (128 bits, the effective elements are already compactly arranged in the low bits of this block).

[0056] Two adjacent compressed data parts (e.g., r1_0 and r1_1) are formed into a low-order group and a high-order group of an intermediate compressed group. The effective elements in the high-order group of the intermediate compressed group are merged and compressed into the low-order group by the merging compression method in the aforementioned embodiment, thereby achieving compression of lmul=2.

[0057] Specifically: The intermediate compression groups are grouped as follows: r1_7 and r1_6, r1_5 and r1_4, r1_3 and r1_2, and r1_1 and r1_0 are divided into 4 intermediate compression groups.

[0058] Taking the merging of r1_1 and r1_0 into r2_0 as an example: Right shift bit calculation: Right shift bit = zero_0 × SEW (for example, when SEW = 8, if zero_0 = 3, then the right shift bit = 3 × 8 = 24 bits); Right shift operation: Shift the high-order bit (r1_1) of the middle compressed group (r1_1 and r1_0) to the right by the above right shift amount, so that the valid elements in r1_1 overflow into the empty bits of the low-order bit (r1_0) (because r1_0 has zero_0 invalid elements, corresponding to the empty bits in the high-order bits). Overflow bitwise OR: The valid elements overflowing after right shifting r1_1 are combined with the high-order free bits of r1_0 by bitwise OR (using the free bits 0 of r1_0, the original low-order valid elements of r1_0 are not destroyed after bitwise OR). We obtain a 256-bit r2_0 (the effective elements are arranged consecutively in the low bits within the 256 bits).

[0059] The same applies to other groups: r1_3 and r1_2 are merged and compressed into r2_1, r1_5 and r1_4 are merged and compressed into r2_2, and r1_7 and r1_6 are merged and compressed into r2_3, all of which result in the high-order or low-order group of the updated intermediate compressed group of 256 bits.

[0060] Iteratively merge two adjacent updated intermediate compressed groups (i.e., the element sequence identified by r2_n) (a total of 2×256=512 bits) into a new intermediate compressed group, either the high-order or low-order group (i.e., the element sequence identified by r2_n). Repeat the above merging and compression logic to extend to the larger bit-width lmul=4 scenario.

[0061] Specifically: Taking the example of merging the updated intermediate compressed group (r3_1) obtained in the previous iteration with the adjacent updated intermediate compressed group (r3_0) into the final target (r4_0) in this iteration: Right shift bit calculation: Right shift bit = (zero_1 + zero_0) × SEW (i.e., the sum of the mask group zeros corresponding to the low bit group r2_0 of the current iteration's intermediate compression group × SEW); Right shift operation: Shift the high-order bit group (r2_1) of the current iteration's middle compressed group to the right by the number of right shifts mentioned above, so that the valid elements of r2_1 overflow into the empty bits of the low-order bit group (r2_0); Overflow bitwise OR: Combines the valid elements overflowing from r2_1 with r2_0 by bitwise OR. We obtain r3_0, which is 512 bits long (the effective elements are arranged consecutively in the low bits within the 512 bits).

[0062] Iteratively merge the two adjacent updated intermediate compression groups (i.e., the low-order group and the high-order group corresponding to r3_0 and r3_1 respectively) (a total of 2×512=1024 bits) to complete the full vector data compression of lmul=8, and obtain the final compressed vector data result.

[0063] Specifically: Right shift bit calculation: Right shift bit = (zero_3 + zero_2 + zero_1 + zero_0) × SEW (that is, the sum of the mask group zeros corresponding to the low bit group r3_0 of the current iteration's intermediate compression group × SEW); Right shift operation: Shift the high-order bit group (r3_1) of the current iteration's middle compressed group to the right by the number of right shifts mentioned above, causing the valid elements in it to overflow into the empty bits of the low-order bit group (r3_0); Overflow bitwise OR: Combines the overflowing valid elements of the high-order group (r3_1) with the high-order free bits of the low-order group (r3_0) by bitwise OR. The final compressed vector data is obtained, which is a 1024-bit r4_0 (all valid elements are arranged consecutively from the least significant bit to the most significant bit within 1024 bits, which meets the compression requirements of the vcompress instruction).

[0064] The method described in the embodiments of this specification enables parallel compression of vector data by using mask grouping and grouping of vector data to be compressed. Furthermore, it allows for the iterative execution of the merging and compression steps using vector shift registers of the same bit width, improving the efficiency of vector compression while reducing the area and complexity of the vector shift register circuit. For vector data with a large bit width to be compressed, a maximum of 8 macro-operations (mops) are required, corresponding to an LMUL of 8, effectively reducing the number of macro-operations. It also allows for parallel compression of vector data in multiple vector registers in one cycle, followed by parallel compression of compressed vector data in multiple vector registers in another cycle. In other words, cross-vector register vector data compression can be completed in just two cycles.

[0065] like Figure 4 The diagram illustrates a vector data compression method using sew=8 as an example in this specification. In this illustration, sew=8 is used as an example; however, other embodiments may use sew=4, sew=16, etc. This example considers LMUL<=1, i.e., a maximum data width of 128 bits. This method is also applicable to other data widths. The specific methods in this embodiment include: Step 401: Group the masks and count the number of invalid masks.

[0066] In this step, the 16-bit mask is grouped into 2-bit groups, and the number of 0s in each mask group and the type of the mask group are counted.

[0067] Taking SEW=8 as an example, the 128-bit vector register contains 16 8-bit elements (v0_15-v0_0), corresponding to a 16-bit mask (bit15-bit0, 1 bit controls the validity of 1 element).

[0068] Mask grouping method: The 16-bit mask is split into 8 mask groups in pairs (i.e., bit1 and bit0 form a mask group, bit3 and bit2 form a mask group, ..., bit15 and bit14 form a mask group). The 2 bits of each mask group correspond to the validity of 2 elements of the vector data to be compressed.

[0069] Count the number of 0s in each mask group (0, 1, 2); The type of the statistical mask group (e.g., 01 indicates that bit1 is 0 and bit0 is 1; 10 indicates that bit0 is 0 and bit1 is 1).

[0070] For example, the number of 00:0 mask blocks is 2, and the type of the mask blocks is two bits both being 0; The mask group is 01: the number of 0s is 1, and the mask group type is high-order bits of 0 and low-order bits of 1.

[0071] Step 402: Generate intermediate compression results based on the valid bits of the mask group.

[0072] In this step, based on the type of each mask group, the valid elements in the vector data to be compressed are placed in the low bits according to the rules to generate intermediate compression results.

[0073] Specifically Figure 4 Let's take the mask group formed by the four masks on the far right as an example for explanation.

[0074] The first mask group has a mask value of 10, which contains one zero (zero_num0=1). The vector data to be compressed corresponding to the 1 is 8'h32, and the vector data to be compressed corresponding to the 0 is 8'h10. The effective vector data to be compressed corresponding to the first mask group is 8'h32. The effective vector data to be compressed is placed in the low-order bits and padded with 0s in the high-order bits to form the intermediate compression result 16'h0032. The second mask group has a mask value of 10, which contains one zero (zero_num1=1). The vector data to be compressed corresponding to the 1 is 8'h76, and the vector data to be compressed corresponding to the 0 is 8'h54. The effective vector data to be compressed corresponding to the second mask group is 8'h76. The effective vector data to be compressed is placed in the low-order bits and padded with 0s in the high-order bits to form the intermediate compression result 16'h0076. The intermediate compression result 16'h0032 corresponding to the first mask group and the intermediate compression result 16'h0076 corresponding to the second mask group constitute an intermediate compression group, wherein the intermediate compression result 16'h0032 is the low-order group of the intermediate compression group and the intermediate compression result 16'h0076 is the high-order group of the intermediate compression group.

[0075] The same steps were applied to other vector data to be compressed, resulting in intermediate compression groups corresponding to different mask groups.

[0076] Step 403: Perform compression merging between the high-order and low-order groups of the intermediate compression group.

[0077] In this step, a right shift operation is performed on the high-order group of the intermediate compressed group, causing the valid elements of the high-order group to overflow to the low-order group. Then, through bitwise OR and merging, the valid elements are compactly arranged in the low-order group of the destination register.

[0078] Specifically: The right shift of the high-order bits of the intermediate compressed group = the number of invalid mask (i.e., 0) in the mask group corresponding to the low-order bits of the intermediate compressed group × SEW (here SEW=8, so the right shift is an integer multiple of 8). Move the valid elements of the high-order bits to the empty positions of the low-order bits (because there are invalid elements in the low-order bits, the high 8 bits are filled with 0s).

[0079] When an element in the high-order group is shifted right, the valid elements that are removed from the current group's data range are removed (e.g., if a 16-bit intermediate result is shifted right by 8 bits, the valid elements of the original lower 8 bits will be removed from the high-order group and become overflow elements).

[0080] The overflow element is merged with the high-order element of the low-order group (because the empty bits of the low-order group are 0, the bitwise OR operation will not destroy the original valid elements).

[0081] Combined with appendix Figure 4 The high-order group of the intermediate compression group is v1_1=16'h0076, and the low-order group of the intermediate compression group is v1_0=16'h0032). v1_1 is the intermediate result corresponding to the mask group bit3 & bit2: corresponding elements v0_3=8'h76, v0_2=8'h54 (the mask group is "10", the high bits are valid, so v1_1={v0_3, v0_2}=16'h0076); The mask group of v1_0 is 10, corresponding to the number of 0s = 1. Therefore, the right shift of v1_1 = 1 × 8 = 8 bits. Shifting v1_1 right by 8 bits yields 16'h0000. The original 76 in the lower 8 bits overflows, and the 00 in the original higher 8 bits is shifted to the lower 8 bits, while the higher 8 bits are padded with 0. The overflow 76 is bitwise ORed with the high 8 bits (00) of v1_0 (76|00=76), and finally the low byte of the updated compressed group 32'h00007632 is obtained.

[0082] The updated high-order byte of the compressed group, 32'h000000FE, is obtained synchronously. The same processing is applied to the vector data to be compressed corresponding to other masked groups, resulting in two more 32-bit intermediate compressed groups that form the high-order and low-order bytes of the intermediate compressed group for the next iteration, for example... Figure 4 32'h0000_0098 and 32'h0000_3201.

[0083] Step 404: Compress and merge the high-order and low-order groups of the updated compressed group to obtain the high-order and low-order groups of the compressed group for subsequent iterations.

[0084] In this step, the operation of step 403 is repeated to merge two adjacent intermediate compression groups in turn, and finally a complete 128-bit compression result is obtained, which is adapted to the result bit width of different LMULs.

[0085] Specifically: Compress and merge two adjacent 32-bit intermediate compressed groups, using the processing method in step 403, compress and merge the low-order group 32'h00007632 and the high-order group 32'h000000FE of the intermediate compressed group in this iteration, to obtain a 64-bit intermediate compressed group 64'h0000_0000_00FE_7632; In parallel, compress and merge the low-order group 32'h00003201 and the high-order group 32'h00000098 of the intermediate compressed group in this iteration, to obtain a 64-bit intermediate compressed group 64'h0000_0000_0098_3201; These will respectively form the low-order group and the high-order group of the intermediate compressed group in the next iteration. In the next iteration, the 64-bit intermediate compression group 64'h0000_0000_00FE_7632 is taken as the low-order group of the intermediate compression group, and the 64-bit intermediate compression group 64'h0000_0000_0098_3201 is taken as the high-order group of the intermediate compression group. The low-order group 64'h0000_0000_00FE_7632 and the high-order group 64'h0000_0000_0098_3201 of the intermediate compression group in this iteration are compressed and merged using the processing method in step 403 to obtain the 128-bit final target compressed vector data 128'h0000_0000_0000_0000_0000_0000_0098_3201_01FE_7632.

[0086] like Figure 5 The image shown is related to Figure 4The diagram illustrates the corresponding vector data compression method. In this diagram, a 128-bit vector register is used as an example for illustration. In other embodiments, the width of the vector register can be different. In this embodiment, bit n (n=0-15) represents the mask, and the concatenated mask represents a mask group. V0_n (n=0-15) represents the original vector data to be compressed, V1_n (n=0-7) represents the intermediate compression group of the first iteration (which is also the high-bit or low-bit group of the intermediate compression group in the next iteration, for example, V1_0 is the low-bit group of the intermediate compression group V2_0 in the next iteration, and V1_1 is the high-bit group of the intermediate compression group V2_0 in the next iteration), V2_n (n=0-3) represents the intermediate compression group of the second iteration (which is also the high-bit or low-bit group of the intermediate compression group in the next iteration), V3_n (n=0-1) represents the intermediate compression group of the third iteration (which is also the high-bit or low-bit group of the intermediate compression group in the next iteration), and V4_0 represents the final target compressed vector data.

[0087] like Figure 6 The diagram illustrates a vector data compression method using sew=16 as an example in this specification. A 128-bit vector register is used as an example in this diagram; in other embodiments, the vector register width can be different. In this embodiment, bit n (n=0-7) represents the mask, and a concatenated mask represents a mask group. In this diagram, V0_n (n=0-7) represents the original vector data to be compressed, V1_n (n=0-3) represents the intermediate compression group of the first iteration (which is also the high-order or low-order group of the intermediate compression group in the next iteration; for example, V1_0 is the low-order group of intermediate compression group V2_0 in the next iteration, and V1_1 is the high-order group of intermediate compression group V2_0 in the next iteration), V2_n (n=0-1) represents the intermediate compression group of the second iteration (which is also the high-order or low-order group of the intermediate compression group in the next iteration), and V3_0 represents the final target compressed vector data.

[0088] like Figure 7The diagram illustrates a vector data compression method using sew=32 as an example in this specification. A 128-bit vector register is used as an example in this diagram; in other embodiments, the vector register width can be different. In this embodiment, bit n (n=0-3) represents the mask, and a concatenated mask represents a mask group. In this diagram, V0_n (n=0-3) represents the original vector data to be compressed, V1_n (n=0-1) represents the intermediate compression group of the first iteration (which is also the high-order or low-order group of the intermediate compression group in the next iteration; for example, V1_0 is the low-order group of intermediate compression group V2_0 in the next iteration, and V1_1 is the high-order group of intermediate compression group V2_0 in the next iteration), and V2_0 represents the final target compressed vector data.

[0089] like Figure 8 The diagram illustrates a vector data compression method using sew=64 as an example in this specification. A 128-bit vector register is used as an example in this diagram; in other embodiments, the vector register width can be different. In this embodiment, bit n (n=0-1) represents the mask, and a concatenated mask represents a mask group. In this diagram, V0_n (n=0-1) represents the original vector data to be compressed, and V1_0 represents the final target compressed vector data.

[0090] The method described in this embodiment can be used to compress vector data for cases where LMUL<=1 and LMUL>1. For example, when LMUL=8, the data of 8 vector registers is compressed, and the data width can be 1024 bits. Please refer to the foregoing embodiment.

[0091] like Figure 9 The diagram illustrates a mask generation method as described in this specification. This method controls the number of valid elements in RVV using the vector length parameter vl, ensuring the compression result contains only the valid data of the first vl elements while maintaining compatibility with the tail element retention rules. Furthermore, the entire mask processing and compression merging process requires only two execution cycles. The diagram includes: Step 901: Generate vl_mask and mark elements that exceed vl as invalid.

[0092] In this step, a mask is generated by right-shifting an all-1 vector by vl bits, where only the first vl bits are 1 and the rest are 0, which is used to define the range of valid elements.

[0093] Taking a 128-bit vector of all 1s ({1'b1}}) as an example, the vector is right-shifted by vl bits (logical right shift, high-order bits are padded with 0s); vl_mask is only 1 for the lower vl bits, and the remaining bits (those exceeding vl) are 0. For example, when vl=2, the 128-bit vector of all 1s is right-shifted by 2 bits, vl_mask=128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_fffc (lower 2 bits are 0, the rest are 1), meaning only the first 2 elements are valid.

[0094] Step 902: Generate vl_dec and mark the range of valid elements.

[0095] In this step, the vl_mask is inverted to obtain a vector where only the lower vl bits are 1 and the rest are 0, thus clarifying the positions of the elements that need to be retained. In this embodiment, vl_mask is bitwise inverted; vl_dec has only the lower vl bits 1 and the rest are 0, directly marking the range of valid element positions. For example, when vl=2, after inverting vl_mask, vl_dec=128'h0000_0000_0000_0000_0000_0000_0003 (only the lower 2 bits are 1), indicating that only the first 2 elements need to be processed.

[0096] Step 903: Generate real_mask to obtain the real and valid mask constrained by vl.

[0097] In this step, a bitwise AND operation is performed between `vl_dec` and the original mask (mask) to filter out mask bits outside the range of `vl`, resulting in a real mask that only applies within the valid range. Specifically, the bitwise AND operation is performed on `vl_dec` and `mask`; `real_mask` retains information from the original mask only in the lower `vl` bits, setting bits outside `vl` to 0. For example, when `vl=2`, the lower 4 bits of the original mask are 1011. A bitwise AND operation is performed between `vl_dec` (lower 2 bits 11) and `mask` (lower 2 bits 11), resulting in `real_mask` having lower 2 bits of 11 and the remaining bits being 0. This means that only the validity of the first two elements is determined by the original mask, and any elements outside the range are forcibly invalidated.

[0098] Step 904: Perform compression based on real_mask.

[0099] In this step, the original mask is replaced with a real_mask, and the previous compression and merging process is executed to ensure that only valid elements within the range of vl are processed, and tail elements outside vl retain their original values. The real_mask has already filtered out mask bits outside vl, so the compression and merging only applies to the first vl elements; elements outside vl (tail) are not processed and retain their original values ​​in the destination register (compliant with the RVV specification).

[0100] Using the method described in the aforementioned embodiments, cycle 1 can complete the compression and merging within vector registers with lmul≤1 (based on real_mask); cycle 2 can complete the compression and merging between multiple vector registers with lmul>1, ultimately obtaining the final target compressed vector data that conforms to the vl constraint.

[0101] like Figure 10 The diagram shown illustrates the multiplexing structure of a shift register according to an embodiment of this specification. This diagram depicts multiple iterations occurring during vector data compression for different sew bit widths. It allows operation on intermediate compression groups with the same number of bits using multiplexed shift registers, thereby reducing the number of shift registers and the corresponding circuit area. For example, when lmul ≤ 1, it can be used... Figure 10 The shift register multiplexing structure shown is illustrated; shift register multiplexing can also be implemented for the case where lmul>1.

[0102] because Figure 4 , Figure 6 , Figure 7 , Figure 8 Both methods utilize a large number of shifters, and the large shifters have a significant area. Therefore, shifters with the same bit width in data compression under different SEQ (sequence of evolution) conditions can be merged. For example, in the compression process with SEQ=8, v2_0~v2_3 each have a bit width of 32 bits, while in the compression process with SEQ=16, v1_0~v1_3 also have a bit width of 32 bits. Therefore, before the data enters the 32-bit shifter, the data to be shifted can be selected based on the different SEQ. Similarly, the data bit width obtained by sharing shifters is 64 bits, which is the same as the bit width of v1_0~v1_1 in the compression process with SEQ=32. Before the data enters the 64-bit shifter, the data to be shifted can be selected based on the different SEQ, ultimately resulting in a 128-bit compression result.

[0103] As described in the above embodiments, for 1024-bit vector data to be compressed (or other lengths), 8 uops (micro-operations) can be used, corresponding to the case of LMUL=8, to complete the reading of the vector data to be compressed. For example, the uop splitting method of the Vcompress instruction is as follows: Uop0: dst0 = vcompress(src0, src_mask, dst0); Uop1: dst1 = vcompress(src1, src_mask, dst1); Uop2: dst2 = vcompress(src2, src_mask, dst2); Uop3: dst3 = vcompress(src3, src_mask, dst3); Uop4: dst4 = vcompress(src4, src_mask, dst4); Uop5: dst5 = vcompress(src5, src_mask, dst5); Uop6: dst6 = vcompress(src6, src_mask, dst6); Uop7: dst7 = vcompress(src7, src_mask, dst7); Wherein, src n (0-7) means splitting the 1024-bit vector data to be compressed into 8 vector data of length 128 bits, and src_mask is the corresponding mask, which is sent to different vector registers (dst0-dst7) to perform the vector data compression method in the above embodiment. Then, for the partially compressed data obtained from different vector registers, the above compression merging method can still be used to complete the data compression of multiple vector registers.

[0104] like Figure 11 The diagram shown is a schematic representation of a RISC-V vector compression device according to an embodiment of this specification. The units in this diagram may be composed of circuits or machine instructions. The device specifically includes: The instruction receiving unit 1101 is configured to receive a vector compression instruction, which includes vector data to be compressed and a mask indicating the validity of each element in the vector data to be compressed. The mask grouping unit 1102 is configured to group the mask according to the bit width of the mask in a predetermined order and at a fixed interval; Intermediate compression group unit 1103 is configured to shift elements in the vector data to be compressed corresponding to each mask group to form an intermediate compression result corresponding to the mask group; wherein the intermediate compression results corresponding to adjacent mask groups form the high-bit group and low-bit group of the intermediate compression group, respectively. Iteration unit 1104 is configured to perform the following iterative steps: merging and compressing the elements of the high-order and low-order groups in each intermediate compression group in parallel to form the high-order or low-order group of the updated intermediate compression group; until the compression of the vector data to be compressed is completed.

[0105] This specification also provides a vector execution unit, which executes the RISC-V vector compression method described above.

[0106] This specification also provides a processor, including the vector execution unit described above, in its embodiments.

[0107] like Figure 12 The illustration shows a computer device provided in an embodiment of this specification. The methods described in this embodiment can be run on the computer device described above. The computer device 1202 may include one or more processors 1204, such as one or more central processing units (CPUs), each of which can implement one or more hardware threads. The computer device 1202 may also include any memory 1206 for storing information of any kind, such as code, settings, data, etc. Without limitation, for example, the memory 1206 may include any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Further, any memory can provide volatile or non-volatile retention of information. Further, any memory can represent a fixed or removable component of the computer device 1202. In one case, when the processor 1204 executes associated instructions stored in any memory or combination of memories, the computer device 1202 can perform any operation of the associated instructions. The computer device 1202 also includes one or more drive mechanisms 1208 for interacting with any memory, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.

[0108] Computer device 1202 may also include an input / output module 1210 (I / O) for receiving various inputs (via input device 1212) and providing various outputs (via output device 1214). A specific output mechanism may include a presentation device 1216 and an associated graphical user interface (GUI) 1218. In other embodiments, the input / output module 1210 (I / O), input device 1212, and output device 1214 may be omitted, and the device may function solely as a computer device within a network. Computer device 1202 may also include one or more network interfaces 1220 for exchanging data with other devices via one or more communication links 1222. One or more communication buses 1224 couple the components described above together.

[0109] Communication link 1222 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 1222 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0110] This specification also provides computer-readable instructions, wherein when a processor executes the instructions, the program therein causes the processor to perform the methods described above.

[0111] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0112] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this specification generally indicates that the preceding and following related objects have an "or" relationship.

[0113] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0114] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0115] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.

[0116] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described in this specification, depending on actual needs.

[0117] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0118] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this specification, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0119] This specification uses specific embodiments to illustrate the principles and implementation methods of this specification. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this specification. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this specification. Therefore, the content of this specification should not be construed as a limitation of this specification.

Claims

1. A RISC-V vector compression method, characterized in that, The method includes: Receive a vector compression instruction, the vector compression instruction including vector data to be compressed and a mask indicating the validity of each element in the vector data to be compressed; Based on the bit width of the mask, the mask is grouped in a predetermined order and at fixed intervals; The elements in the vector data to be compressed corresponding to each mask group are shifted to form an intermediate compression result corresponding to the mask group; wherein, the intermediate compression results corresponding to adjacent mask groups form the high-bit group and low-bit group of the intermediate compression group respectively. Perform the following iterative steps: merge and compress the elements of the high-order and low-order groups in each intermediate compression group in parallel to form the high-order or low-order group of the updated intermediate compression group; until the compression of the vector data to be compressed is completed.

2. The method according to claim 1, characterized in that, Based on the bit width of the mask, the mask is further grouped according to a predetermined order and fixed intervals, including: In ascending order, adjacent masks with fixed intervals are grouped into a mask group.

3. The method according to claim 2, characterized in that, Two adjacent masks are grouped together to form a mask group.

4. The method according to claim 1, characterized in that, Shifting multiple elements in the vector data to be compressed corresponding to each mask group to form an intermediate compression result corresponding to the mask group further includes: Based on the indication of the mask in the mask group, determine the valid elements in the vector data to be compressed; The valid elements in the mask group are shifted sequentially to the lower bits of the intermediate compression result.

5. The method according to claim 4, characterized in that, Shifting the valid elements to the lower bits of the intermediate compression result further includes: The high-order bits of the intermediate compression result are padded with 0.

6. The method according to claim 4, characterized in that, Determining the valid elements in the vector data to be compressed, based on the indication of the mask in the mask group, further includes: When the mask of the mask group is 00, it indicates that both corresponding elements are invalid. When the mask of the mask group is 01, it indicates that the first element is an invalid element and the second element is a valid element. When the mask of the mask group is 10, it indicates that the first element is a valid element and the second element is an invalid element. When the mask of the mask group is 11, it indicates that both corresponding elements are valid elements.

7. The method according to claim 4, characterized in that, The merging and compression of elements from the high-order and low-order groups in the intermediate compression group further includes: The number of shift bits is determined based on the number of invalid masks in the mask group corresponding to the low-order group in the intermediate compression group of the current iteration; Shift the elements of the high-order group in the intermediate compression group to the right by the shift number to form an overflow element; The overflow element is merged with the element of the low-order group in the intermediate compression group to form the high-order group or low-order group of the updated intermediate compression group.

8. The method according to claim 7, characterized in that, Merging the overflow element with the elements of the low-order group in the intermediate compressed group to form the high-order group or low-order group of the updated intermediate compressed group further includes: The overflow element is bitwise ORed with the elements of the low-order group in the intermediate compression group, and the high-order group in the intermediate compression group is padded with 0 to form the updated high-order or low-order group of the intermediate compression group.

9. The method according to claim 7, characterized in that, The elements of the high-order and low-order groups in each intermediate compression group are merged and compressed in parallel to form the high-order or low-order groups of the updated intermediate compression group, which further include: Use the high-order and low-order groups of adjacent updated intermediate compression groups as the updated intermediate compression groups; The iterative steps are performed on the updated intermediate compression group.

10. The method according to claim 1, characterized in that, When the vector register group multiplier LMUL is greater than 1, the vector data to be compressed occupies multiple vector registers; Calculate the portion of compressed data in each vector register of the vector data to be compressed; Partial compressed data of each vector register is used as the intermediate compression result, and the intermediate compression results corresponding to the two vector registers are respectively used as the high-order group and low-order group of the intermediate compression group. The iterative steps are performed until the compression of the vector data to be compressed is complete.

11. A RISC-V vector compression device, characterized in that... include: The instruction receiving unit is configured to receive a vector compression instruction, which includes vector data to be compressed and a mask indicating the validity of each element in the vector data to be compressed. The mask grouping unit is configured to group the mask according to the bit width of the mask, in a predetermined order and at a fixed interval; The intermediate compression group unit is configured to shift the elements in the vector data to be compressed corresponding to each mask group to form an intermediate compression result corresponding to the mask group; wherein the intermediate compression results corresponding to adjacent mask groups form the high-order group and low-order group of the intermediate compression group, respectively. The iterative unit is configured to perform the following iterative steps: merging and compressing the elements of the high-order and low-order groups in each intermediate compression group in parallel to form the high-order or low-order group of the updated intermediate compression group; until the compression of the vector data to be compressed is completed.

12. A vector execution unit, characterized in that... The vector execution unit performs the method described in any one of claims 1-10.

13. A processor, characterized in that, Includes the vector execution unit as described in claim 12.

14. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor is the processor described in claim 13.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the method of any one of claims 1-10.

16. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method according to any one of claims 1-10.

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