Microoperation result merging and buffering device, processor, chip, equipment and method
By dynamically allocating cache entries through a two-level buffer structure of a micro-operation result merging buffer, the hardware and timing overhead issues of RISC-V vector instruction write-back are solved, the out-of-order execution efficiency of the processor is maintained, and the overall write-back of complex micro-operation results is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU QUNXIN MICROELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2026-01-15
- Publication Date
- 2026-05-12
AI Technical Summary
Existing technologies, when supporting the write-back of micro-operation results of RISC-V vector instructions, lead to an increase in processor hardware area and timing overhead, and impair out-of-order execution efficiency, especially since small-granularity writes in PRFs are complex and costly.
A micro-operation result merging buffer device is adopted, including a buffer management unit and a write-back control unit. The buffer entries are dynamically allocated through a two-level buffer structure (result merging cache and score table). The write-back to the physical register file is triggered only when the progress field indicates that the intermediate results have been collected, so as to avoid resource locking and maintain out-of-order execution efficiency.
It enables the overall write-back of complex micro-operation results, reducing processor hardware area and timing overhead, while maintaining out-of-order execution capability, avoiding resource contention blocking, and improving processor performance.
Smart Images
Figure CN122018992A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of processor technology, and in particular to a micro-operation result merging buffer device, processor, chip, apparatus and method. Background Technology
[0002] With the widespread adoption of open instruction set architectures such as RISC-V (Reduced Instruction Set Computer V), its vector extension, with its high flexibility and configurability, provides powerful parallel processing capabilities for fields such as high-performance computing and artificial intelligence. The RISC-V vector architecture allows software to dynamically configure the width and number of vector elements. While this brings convenience to software development, it also poses significant challenges to processor microarchitecture design, especially the hardware implementation of critical components such as register files.
[0003] In modern high-performance out-of-order processors, the Physical Register File (PRF) is a critical component in terms of area and power consumption. To improve vector processing performance, register widths are typically designed to be 16 bytes, 32 bytes, 64 bytes, or even larger. However, RISC-V vector instructions (such as discrete-addressed strided / indexed load instructions) support byte-level element access, meaning a single instruction may generate multiple small-granularity write requests targeting different locations in the same target register. Directly writing the results of such micro-operations to the PRF requires the PRF to support complex and costly small-granularity write circuitry, significantly increasing chip area, routing complexity, and timing convergence challenges.
[0004] To alleviate the direct pressure on the PRF (Programmable Execution File), existing technologies employ two main approaches: one is to directly write the results of micro-operations derived from vector instructions back to the PRF in small granularity, but this leads to the aforementioned hardware complexity and area issues; the other is to pre-allocate dedicated merging buffer units during the instruction issue phase, and then merge and write back the results after all relevant micro-operations are completed. While the latter reduces the write pressure on the PRF, the static binding of limited buffer resources during the issue phase makes it highly susceptible to out-of-order allocation, which can cause older instructions to be blocked. Furthermore, the excessively long lifetime of buffer entries severely impairs the processor's out-of-order execution efficiency and overall performance.
[0005] Therefore, how to support the overall write-back of complex micro-operation results while avoiding excessive overhead in processor hardware area and timing, and ensuring that the processor's out-of-order execution capability is not compromised, has become a pressing technical problem to be solved in this field. Summary of the Invention
[0006] The purpose of this application is to provide a micro-operation result merging buffer device, processor, chip, device and method, so as to reduce the hardware area and timing overhead of the processor while supporting the overall write-back of complex micro-operation results and maintaining the out-of-order execution capability of the processor.
[0007] To achieve the above objectives, in one aspect, embodiments of this application provide a micro-operation result merging buffer device, disposed on the processor's write-back pipeline, the device comprising: The buffer management unit is used to store dynamically allocated buffer entries. Each buffer entry includes: an index field for storing the target register identifier; a result field for temporarily storing the intermediate results to be merged from the target register; and a progress field for recording the collection progress of the intermediate results from the target register. The write-back control unit is used to respond to the micro-operation result entering the write-back pipeline, match or allocate a corresponding storage entry according to the target register identifier it carries, merge the micro-operation result into the result field of the matched or allocated cache entry, and update the progress field of the corresponding cache entry. When the progress field indicates that the intermediate results for the corresponding target register have been collected, the complete result in the result field of the corresponding cache entry is written into the corresponding target register in the physical register file.
[0008] In the apparatus of this application embodiment, the apparatus is located between the memory management unit and the physical register file.
[0009] In the apparatus of this application embodiment, the buffer management unit includes two levels of buffering: The result merge cache serves as a first-level buffer, containing multiple first-class entries, each of which contains the index field, the result field, and the progress field. The scoring table, as a second-level buffer, contains multiple second-class entries, each of which contains the index field and the progress field; The depth of the scoring table is greater than the depth of the result merging cache.
[0010] In the apparatus of this application embodiment, the step of matching or allocating a corresponding storage entry based on the target register identifier carried by the entry includes: The results are merged into the cache to match the storage entry corresponding to the target register identifier; If a miss occurs, a storage entry is allocated for the micro-operation result carrying the identifier of the target register.
[0011] In the apparatus of this application embodiment, each first type of entry further includes an activity indicator field, which is used to indicate the activity level of the corresponding first type of entry being accessed; The allocation of a storage entry for the micro-operation result carrying the target register identifier includes: When the number of first-type entries in the result merging cache has reached its limit, and there is no first-type entry corresponding to the target register identifier in the result merging cache, a first-type entry is selected according to the activity indicator field, the intermediate result stored in the selected first-type entry is written into the corresponding target register in the physical register file, and the selected first-type entry is cleared as a first-type entry allocated for the micro-operation result carrying the target register identifier.
[0012] In the apparatus of this application embodiment, the step of selecting a first type of item according to the activity indication field includes: Select the first category of entries with the lowest activity based on the activity indicator field.
[0013] In the apparatus of this application embodiment, allocating a storage entry for the micro-operation result carrying the target register identifier further includes: If the number of first-type entries in the result merging cache has not reached the upper limit, and if there is no first-type entry corresponding to the target register identifier in the result merging cache, but there is a second-type entry corresponding to the target register identifier in the score table, then a first-type entry is allocated in the result merging cache for the micro-operation result carrying the target register identifier. Based on the target register identifier, the corresponding intermediate result is read back from the physical register file, the corresponding collection progress is read back from the score table, and the intermediate result and the collection progress are loaded into the corresponding field of the first-type entry.
[0014] In the apparatus of this application embodiment, allocating a storage entry for the micro-operation result carrying the target register identifier further includes: If there is no first-type entry corresponding to the target register identifier in the result merging cache and no second-type entry corresponding to the target register identifier in the score table, then one first-type entry and one second-type entry will be allocated to the micro-operation result carrying the target register identifier in the result merging cache and the score table, respectively.
[0015] In the apparatus of this application embodiment, updating the progress field of the corresponding cache entry includes: The corresponding progress field is accumulated based on the element width information carried in the micro-operation result; the element width information represents the element width occupied by the micro-operation result in the complete result of the corresponding target register.
[0016] In the apparatus of this application embodiment, the progress field indicating the completion of intermediate result collection for the corresponding target register includes: The cumulative element width of the progress field reaches the total element width of the complete result of the corresponding target register.
[0017] In the apparatus of this application embodiment, the write-back control unit is further configured to: After writing the complete result in the result field of the corresponding cache entry to the corresponding destination register in the physical register file, the resource occupation of the corresponding cache entry is released.
[0018] In the apparatus of this application embodiment, the write-back control unit is further configured to: When the progress field indicates that intermediate results for the corresponding target register have not been collected, the operation of writing the micro-operation results into the physical register file is invalidated.
[0019] In the apparatus of this application embodiment, the depth of the scoring table is determined according to the formula D2=D0-D1; where D2 is the depth of the scoring table, D0 is the depth of the load storage queue loaded by the memory management unit, and D1 is the depth of the result merging cache.
[0020] On the other hand, embodiments of this application also provide a processor that includes the above-described apparatus.
[0021] On the other hand, embodiments of this application also provide a chip that includes the processor described above.
[0022] On the other hand, embodiments of this application also provide an electronic device comprising the aforementioned chip.
[0023] On the other hand, embodiments of this application also provide a micro-operation result merging and buffering method, applied to the above-mentioned apparatus, the method comprising: In response to the micro-operation result entering the write-back pipeline, a corresponding memory entry is matched or allocated based on the target register identifier it carries. The micro-operation results are merged into the result field of the cache entry that is matched or assigned to them, and the progress field of the corresponding cache entry is updated. When the progress field indicates that the intermediate results for the corresponding target register have been collected, the complete result in the result field of the corresponding cached entry is written into the corresponding target register in the physical register file.
[0024] In the method of this application embodiment, the buffer management unit includes two levels of storage: The result merge cache serves as a first-level buffer, containing multiple first-class entries, each of which contains the index field, the result field, and the progress field. The scoring table, as a second-level buffer, contains multiple second-class entries, each of which contains the index field and the progress field; The depth of the scoring table is greater than the depth of the result merging cache.
[0025] In the method of this application embodiment, the step of matching or allocating a corresponding storage entry based on the target register identifier carried by the entry includes: The results are merged into the cache to match the storage entry corresponding to the target register identifier; If a miss occurs, a storage entry is allocated for the micro-operation result carrying the identifier of the target register.
[0026] In the method of this application embodiment, each first type of entry further includes an activity indicator field, which is used to indicate the activity level of the corresponding first type of entry being accessed; The allocation of a storage entry for the micro-operation result carrying the target register identifier includes: When the number of first-type entries in the result merging cache has reached its limit, and there is no first-type entry corresponding to the target register identifier in the result merging cache, the first-type entry is selected according to the activity indicator field; Write the intermediate results of the selected first type of entry into the corresponding target register in the physical register file; Clear the selected first-class entry as a first-class entry assigned to the micro-operation result carrying the target register identifier.
[0027] In the method of this application embodiment, the step of selecting a first type of item according to the activity indicator field includes: Select the first category of entries with the lowest activity based on the activity indicator field.
[0028] In the method of this application embodiment, allocating a storage entry for the micro-operation result carrying the target register identifier further includes: If the number of first-type entries in the result merging cache has not reached the upper limit, and if there is no first-type entry corresponding to the target register identifier in the result merging cache, but there is a second-type entry corresponding to the target register identifier in the score table, then a first-type entry is allocated in the result merging cache for the micro-operation result carrying the target register identifier. Based on the target register identifier, read back the corresponding intermediate results from the physical register file and read back the corresponding collection progress from the score table; The intermediate result and the collection progress are then loaded into the corresponding field of the first type of entry.
[0029] In the method of this application embodiment, allocating a storage entry for the micro-operation result carrying the target register identifier further includes: If there is no first-type entry corresponding to the target register identifier in the result merging cache and no second-type entry corresponding to the target register identifier in the score table, then one first-type entry and one second-type entry will be allocated to the micro-operation result carrying the target register identifier in the result merging cache and the score table, respectively.
[0030] In the method of this application embodiment, updating the progress field of the corresponding cache entry includes: The corresponding progress field is accumulated based on the element width information carried in the micro-operation result; the element width information represents the element width occupied by the micro-operation result in the complete result of the corresponding target register.
[0031] In the method of this application embodiment, the progress field indicating the completion of intermediate result collection for the corresponding target register includes: The cumulative element width of the progress field reaches the total element width of the complete result of the corresponding target register.
[0032] In the method of this application embodiment, the method further includes: After writing the complete result in the result field of the corresponding cache entry to the corresponding destination register in the physical register file, the resource occupation of the corresponding cache entry is released.
[0033] In the method of this application embodiment, the method further includes: When the progress field indicates that intermediate results for the corresponding target register have not been collected, the operation of writing the micro-operation results into the physical register file is invalidated.
[0034] As can be seen from the technical solutions provided in the embodiments of this application above, in these embodiments, the write-back to the PRF is triggered only when the progress field indicates that the intermediate results for the corresponding target register have been collected. This ensures that each write to the PRF is a merged complete result, achieving the overall write-back of complex micro-operation results. More importantly, since the cache entries in the buffer management unit are dynamically allocated, they are only occupied when the micro-operation is actually written back (the micro-operation result enters the write-back pipeline). Thus, the micro-operations that are executed first can apply for the use of buffer resources first. This method of decoupling resource dynamic allocation from program order avoids the serious damage to the out-of-order execution efficiency and overall performance of the processor caused by locking resources in advance, and maintains the out-of-order execution efficiency and overall performance of the processor. Moreover, by adding a micro-operation result merging buffer device to the write-back pipeline with a small hardware overhead, the huge area overhead caused by small-granularity writing in the PRF is avoided. This achieves the support for the overall write-back of complex micro-operation results while reducing hardware area and timing overhead, and maintaining the out-of-order execution capability of the processor. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 The following is a schematic diagram illustrating the application environment of the micro-operation result merging buffer device in some embodiments of this application; Figure 2 The following is a structural block diagram of a micro-operation result merging buffer device in some embodiments of this application; Figure 3 This application shows a schematic diagram of the two-level buffer structure of the buffer management unit in some embodiments; Figure 4 A schematic diagram illustrating the correspondence between registers and memory addresses in an exemplary embodiment of this application is shown; Figure 5 This illustration shows a schematic diagram of the write-back process of micro-operation results in a write-back pipeline in an example embodiment of this application; Figure 6 A flowchart of a micro-operation result merging and buffering method in some embodiments of this application is shown; Figure 7 Structural block diagrams of electronic devices in some embodiments of this application are shown.
[0036] [Explanation of Labels in the Attached Image]
[0037] 10. Load the storage queue; 20. Memory Management Unit; 30. Micro-operation result merging buffer device; 301. Buffer Management Unit; 302. Write back to the control unit; 40. Physical register file; 702. Electronic equipment; 704, Processor; 706. Memory; 708. Drive mechanism; 710. Input / output interfaces; 712. Input devices; 714. Output devices; 716. Presentation equipment; 718. Graphical User Interface; 720. Network interface; 722. Communication link; 724. Communication bus. Detailed Implementation
[0038] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.
[0039] It should be noted that in the embodiments of this application, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved are all information and data authorized and agreed upon by the user and fully authorized by all parties. That is, the acquisition, transmission, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations.
[0040] For memory load instructions (memory read / write instructions) of processors sampling the RISC-V architecture, the minimum element width of the instruction can be set to 1 byte. Taking a target register (i.e., the target physical register in the PRF) with a width of 16 bytes as an example, a target register needs to be filled with 16 elements. In vector instructions, each element of the strided and indexed load / store instructions and memory read / write instructions (applicable not only to strided / indexed instructions but also extend to other load / store instructions that need to be split) is discretely addressed, meaning the addresses between elements are not contiguous. The correspondence between the target register and the memory address can be as follows: Figure 4 As shown, the target register (i.e. Figure 4 Each element in the register corresponds to a memory address. For example, element 0 in the register corresponds to memory address x, and element 1 in the register corresponds to memory address y.
[0041] Due to the limitations of processor memory access bandwidth (typically 8 / 16 / 32 / 64 bytes in modern processors), it is virtually impossible for such complex memory load instructions to be completed in a single micro-operation. In microarchitecture design, these memory load instructions are typically broken down into micro-operations, i.e., into multiple micro-instructions. These micro-instructions can form a discrete vector; therefore, memory load instructions are also called vector instructions.
[0042] This application relates to a micro-operation result merging and buffering technique. An instruction (e.g., a memory load instruction) can be broken down into multiple micro-operations. A micro-operation is the smallest unit of processor instruction execution, and the result of a micro-operation is the execution result (operation result) of a single micro-operation. Since the multiple micro-operations derived from the same instruction are discrete, micro-operations can be called discrete vector instructions, and micro-operation results can also be called discrete vector micro-operation results. The micro-operation result merging and buffering technique provided in this application aims to achieve the overall write-back of complex micro-operation results with less area overhead, reducing the processor's hardware area and timing overhead, while avoiding damage to the processor's out-of-order processing capability. Here, complex micro-operation results refer to the situation where, after a memory load instruction is broken down into numerous micro-operations, the corresponding micro-operation results of these micro-operations become complex due to the large number of micro-operations.
[0043] Figure 1The diagram illustrates the application environment of a micro-operation result merging buffer device 30 in some embodiments of this application. This micro-operation result merging buffer device 30 is disposed on the processor's write-back pipeline and located between the memory management unit 20 and the physical register file 40. The load memory queue 10 is used to temporarily store memory load instructions that have been issued but not yet executed. The memory management unit 20 is used to split a single memory load instruction into multiple micro-operations and manage the micro-operation results generated during the memory access execution process. The micro-operation result merging buffer device 30 is used to dynamically assemble multiple out-of-order micro-operation results from the same memory load instruction into complete data, and then write it back to the physical register file 40 all at once.
[0044] Combination Figure 2 As shown, in some embodiments of this application, the micro-operation result merging buffer device 30 may include a buffer management unit 301 and a write-back control unit 302. Wherein: Buffer management unit 301 is used to store dynamically allocable cache entries, each cache entry including: The index field is used to store the destination register identifier; the index is the index for storing intermediate results in the destination register, and the index address for writing micro-operations back to the physical register file; The Result field is used to temporarily store the intermediate results to be merged from the target register. The Result field stores the result data of the micro-operations, and its width is the same as the width of the target register in the physical register file (e.g., 128 / 256 / 512 bits). The progress field (Score) is used to record the collection progress of intermediate results in the target register. The progress field is incremented every time the intermediate result corresponding to the index is written back to the corresponding Result. When the micro-operation result is written back, the micro-operation width information can be carried. For example, if the micro-operation width is 2 bytes and the target register width is 16 bytes, then the progress field is incremented by 2 each time. When the progress field reaches 16, it means that the register result collection is complete.
[0045] The write-back control unit 302 is used to respond to the micro-operation result entering the write-back pipeline, match or allocate a corresponding storage entry according to the target register identifier it carries, merge the micro-operation result into the result field of the matched or allocated cache entry, and update the progress field of the corresponding cache entry. When the progress field indicates that the intermediate results for the corresponding target register have been collected, the complete result in the result field of the corresponding cache entry is written into the corresponding target register in the physical register file.
[0046] In this embodiment, the write-back to the PRF is triggered only when the progress field indicates that the intermediate results for the corresponding target register have been collected. This ensures that each write to the PRF is a merged, complete result, achieving a complete write-back of complex micro-operation results. More importantly, since the cache entries in the buffer management unit are dynamically allocated, they are only occupied when the micro-operation is actually written back (the micro-operation result enters the write-back pipeline). Thus, micro-operations that are executed first can request to use buffer resources first. This method of decoupling resource dynamic allocation from program order avoids the serious damage to the processor's out-of-order execution efficiency and overall performance caused by locking resources in advance, maintaining the processor's out-of-order execution efficiency and overall performance. Moreover, by adding a micro-operation result merging buffer device to the write-back pipeline with minimal hardware overhead, the huge area overhead caused by small-granularity writes to the PRF is avoided. This achieves the support for the complete write-back of complex micro-operation results while reducing the processor's hardware area and timing overhead, and maintaining the processor's out-of-order execution capability.
[0047] refer to Figure 3 As shown, in some embodiments of this application, the buffer management unit may adopt a two-level buffer structure: The result merge cache, as a first-level buffer, contains multiple cache entries (first-class entries). Each cache entry includes the aforementioned index, result, score, and age fields. The age field indicates the activity level of the corresponding cache entry. The age value is a hardware counter that measures the relative activity of a cache entry, and its value is determined according to the rule of "reset on access, decay on idle time" (when a cache entry is accessed, its age value is immediately set to the maximum value, and gradually decays as the clock cycle increases; when idle, it gradually decays). Because the result merge cache stores a large amount of content and is relatively large in scale, the number of result merge cache entries is small.
[0048] The score table, serving as a second-level buffer, contains multiple score table entries (second-class entries). Each second-class entry includes the aforementioned index field and score field. The score table is deeper than the result merge cache, but due to the smaller amount of information stored, the overall area overhead is lower. The depth of the score table is determined by the formula D2 = D0 - D1; where D2 is the depth of the score table, D0 is the depth of the load-store queue loaded by the memory management unit, and D1 is the depth of the result merge cache. Thus, the depth of the score table covers the out-of-order capability of the load-store queue.
[0049] In summary, the result merge cache (shallow and complete) has fewer entries (e.g., 4-8) but stores complete data (Index, Result, Score, and Age), while the score table (deep and simple) has more entries but only stores Index and Score. This hierarchical structure achieves decoupled storage of state and data, allowing active micro-operation results to conveniently occupy valuable cache resources in the result merge cache to store the full state, while inactive micro-operation results are only stored in the score table with Index and Score at a very low cost. Because the score table is deep, the hardware can support a large number of discrete vector instructions concurrently with a small area cost (small cache), and can also reduce or avoid resource contention blocking that may occur during out-of-order execution under resource-constrained conditions.
[0050] In some embodiments of this application, when writing back the results of the multiple micro-operations (discrete vector instructions) that have been split, the element width information and the index information of the element's position in the register are additionally carried compared to the operation results of scalar instructions (simple instructions that are not split). Discrete vector micro-operations and scalar instructions can share the write-back pipeline and physical register file write port.
[0051] In some embodiments of this application, when a micro-operation result enters the write-back pipeline, the write-back control unit can match or allocate a corresponding storage entry based on the target register identifier (Index) carried by the micro-operation result. Specifically, the write-back control unit can match the storage entry (cache entry) corresponding to the target register identifier from the result merging cache; if a match is found, the micro-operation result is merged into the Result of the matched or allocated cache entry, and the Score of the corresponding cache entry is updated; when the progress field indicates that the intermediate results for the corresponding target register have not been collected, the operation of writing the micro-operation result to the physical register file can be invalidated, that is, the writing of the intermediate results to the PRF is suppressed; if a miss is found, a storage entry (including a cache entry and a score table entry) is allocated for the micro-operation result carrying the target register identifier.
[0052] In some embodiments of this application, allocating a storage entry for the micro-operation result carrying the target register identifier may include: when the number of cache entries in the result merging cache has reached its upper limit, and there is no cache entry corresponding to the target register identifier in the result merging cache, selecting a cache entry according to the activity indicator field, writing the intermediate result stored in the selected cache entry into the corresponding target register in the physical register file, and clearing the selected cache entry to serve as a cache entry allocated for the micro-operation result carrying the target register identifier; thus, resource contention blocking that may occur during out-of-order execution can be reduced or avoided under conditions of limited cache resources. In some embodiments of this application, selecting a cache entry according to the activity indicator field may be: selecting the cache entry with the lowest activity according to the activity indicator field; in other embodiments of this application, it may also be randomly selected from several cache entries with the lowest activity.
[0053] In some embodiments of this application, allocating a storage entry for the micro-operation result carrying the target register identifier may further include: when the number of cache entries in the result merging cache has not reached the upper limit, if there is no cache entry corresponding to the target register identifier in the result merging cache, and there is a score table entry corresponding to the target register identifier in the score table, then a cache entry is allocated in the result merging cache for the micro-operation result carrying the target register identifier; according to the target register identifier, the corresponding intermediate result is read back from the physical register file, the corresponding collection progress is read back from the score table, and the intermediate result and the collection progress are loaded into the corresponding field of the cache entry. It should be noted that in the embodiments of this application, since the micro-operation results corresponding to multiple micro-operations split from the same vector instruction are often written back consecutively, the cache entry hit rate is high, the additional read requests to the PRF are few, and the power consumption impact is small.
[0054] If, at this point, the index corresponding to the micro-operation result does not match a corresponding cache entry, but a corresponding score table entry is matched from the score table, it indicates that the target register corresponding to that index has previously had the micro-operation result written back, but not completely (for example, an instruction is split into four micro-operations, and currently only the micro-operation result of a portion of the micro-operations has been written back, i.e., the intermediate result has been written back), and the intermediate result has been written back to the physical register file. At this point, a Score readback request is sent to the matching entry in the score table (the read-back score table entry is invalidated after reading), and the Score is the intermediate score result that was not fully collected in the past. At the same time, a result readback request is sent to the physical register file (the result is the intermediate result that was not fully collected in the past), and in the next clock cycle, a cache entry carrying the micro-operation result of that index can be allocated in the result merging cache, and the read-back Score and intermediate result (including the index) are written back to that cache entry. Both the Score readback request and the result readback request carry the index as a reference.
[0055] In some embodiments of this application, allocating a storage entry for the micro-operation result carrying the target register identifier may further include: if there is no cache entry corresponding to the target register identifier in the result merging cache and no score table entry corresponding to the target register identifier in the score table, then one cache entry and one score table entry are allocated respectively for the micro-operation result carrying the target register identifier in the result merging cache and the score table.
[0056] In some embodiments of this application, updating the progress field of a corresponding cached entry may include: accumulating the element width of the corresponding progress field based on the element width information carried in the micro-operation result; the element width information represents the element width occupied by the micro-operation result in the complete result of the corresponding target register. In this scenario, the progress field indicating that the intermediate results for the corresponding target register have been collected means that the accumulated element width value of the progress field reaches the total element width of the complete result of the corresponding target register.
[0057] For example, in Figure 5 In the exemplary embodiment shown, a load-store instruction is split into four micro-operations: [Uop1, Uop2, Uop3, Uop4]; Uop1, Uop2, Uop3, and Uop4 can be executed out of order; if the result of each micro-operation of Uop1, Uop2, Uop3, and Uop4 is 4 bytes, and the results of each micro-operation of Uop1, Uop2, Uop3, and Uop4 correspond to A, B, C, and D respectively, then: In the first clock cycle (T1): if the micro-operation result C corresponding to Uop3 is received first, C can be written into the Result of the corresponding cache entry. At the same time, in the corresponding cache entry and the score table entry, the Score value is incremented from null to 4. Since Score=4 does not meet the trigger condition of Score=16, the writing of intermediate results to PRF is suppressed. Figure 5 The example shown defaults to matching the corresponding cache entry based on the Index carried by Uop3; In the second clock cycle (T2): if the micro-operation result A corresponding to Uop1 is received, A can be written into the Result of the corresponding cache entry. At the same time, the Score value is accumulated from 4 to 8 in the corresponding cache entry and the score table entry. Since Score=8 does not meet the trigger condition of Score=16, the writing of intermediate results to PRF is still suppressed. In the third clock cycle (T3): if the micro-operation result D corresponding to Uop4 is received, D can be written into the Result of the corresponding cache entry. At the same time, the Score value is accumulated from 8 to 12 in the corresponding cache entry and the score table entry. Since Score=12 does not meet the trigger condition of Score=16, the writing of intermediate results to PRF is still suppressed. In the fourth clock cycle (T4): if the micro-operation result B corresponding to Uop2 is received, B can be written into the Result of the corresponding cache entry. At the same time, the Score value is accumulated from 12 to 16 in the corresponding cache entry and the score table entry. Since Score=16 meets the trigger condition, the complete intermediate result is written to the PRF. That is, the complete result data [ABCD] temporarily stored in the corresponding cache entry is written to the target register pointed to by the corresponding Index in the PRF in a way that conforms to the native write width of the physical register file (16 bytes here).
[0058] In some embodiments of this application, the write-back control unit is further configured to: release the resource occupation of the corresponding cache entry after writing the complete result in the result field of the corresponding cache entry into the corresponding target register in the physical register file.
[0059] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more hardware devices.
[0060] This application also provides a micro-operation result merging and buffering method, which can be applied to the aforementioned micro-operation result merging and buffering device, processor, chip, or electronic device. (Refer to...) Figure 6As shown, in some embodiments of this application, the micro-operation result merging and buffering method may include the following steps: Step 601: In response to the micro-operation result, enter the write-back pipeline and match or allocate a corresponding memory entry based on the target register identifier it carries; Step 602: Merge the micro-operation results into the result field of the cache entry that it matches or is assigned, and update the progress field of the corresponding cache entry; Step 603: When the progress field indicates that the intermediate results for the corresponding target register have been collected, write the complete result in the result field of the corresponding cache entry into the corresponding target register in the physical register file.
[0061] In the micro-operation result merging buffering method of some embodiments of this application, the buffer management unit includes two levels of storage: The result merge cache, as a first-level buffer, contains multiple cache entries, each containing the index field, the result field, and the progress field; The score table, as a second-level buffer, contains multiple score table entries, each of which contains the index field and the progress field; The depth of the scoring table is greater than the depth of the result merging cache.
[0062] In the micro-operation result merging buffering method of some embodiments of this application, the step of matching or allocating a corresponding storage entry based on the target register identifier it carries includes: The results are merged into the cache to match the storage entry corresponding to the target register identifier; If a miss occurs, a storage entry is allocated for the micro-operation result carrying the identifier of the target register.
[0063] In the micro-operation result merging and buffering method of some embodiments of this application, each cache entry also includes an activity indicator field, which is used to indicate the activity level of the corresponding cache entry being accessed; The allocation of a storage entry for the micro-operation result carrying the target register identifier includes: When the number of cache entries in the result merging cache has reached the upper limit, and there is no cache entry corresponding to the target register identifier in the result merging cache, a cache entry is selected according to the activity indicator field; The intermediate results stored in the selected cache entry are written into the corresponding target register in the physical register file; Clear the selected cache entry as a cache entry allocated for the micro-operation result carrying the identifier of the target register.
[0064] In the micro-operation result merging and buffering method of some embodiments of this application, the step of selecting cache entries according to the activity indicator field includes: Select the cache entry with the lowest activity level based on the activity indicator field.
[0065] In the micro-operation result merging and buffering method of some embodiments of this application, allocating a storage entry for the micro-operation result carrying the target register identifier further includes: If the number of cache entries in the result merging cache has not reached the upper limit, and if there is no cache entry corresponding to the target register identifier in the result merging cache, but there is a score table entry corresponding to the target register identifier in the score table, then a cache entry is allocated in the result merging cache for the micro-operation result carrying the target register identifier. Based on the target register identifier, read back the corresponding intermediate results from the physical register file and read back the corresponding collection progress from the score table; The intermediate result and the collection progress are then loaded into the corresponding field of the cache entry.
[0066] In the micro-operation result merging and buffering method of some embodiments of this application, allocating a storage entry for the micro-operation result carrying the target register identifier further includes: If there is no cache entry corresponding to the target register identifier in the result merging cache and no score table entry corresponding to the target register identifier in the score table, then one cache entry and one score table entry will be allocated for the micro-operation result carrying the target register identifier in the result merging cache and the score table, respectively.
[0067] In the micro-operation result merging buffering method of some embodiments of this application, updating the progress field of the corresponding cache entry includes: The corresponding progress field is accumulated based on the element width information carried in the micro-operation result; the element width information represents the element width occupied by the micro-operation result in the complete result of the corresponding target register.
[0068] In the micro-operation result merging and buffering method of some embodiments of this application, the progress field indicating the completion of intermediate result collection for the corresponding target register includes: The cumulative element width of the progress field reaches the total element width of the complete result of the corresponding target register.
[0069] In the micro-operation result merging and buffering method of some embodiments of this application, the method further includes: After writing the complete result in the result field of the corresponding cache entry to the corresponding destination register in the physical register file, the resource occupation of the corresponding cache entry is released.
[0070] In the micro-operation result merging and buffering method of some embodiments of this application, the method further includes: When the progress field indicates that intermediate results for the corresponding target register have not been collected, the operation of writing the micro-operation results into the physical register file is invalidated.
[0071] Although the process described above includes multiple operations that occur in a specific order, it should be clearly understood that these processes may include more or fewer operations that can be executed sequentially or in parallel (e.g., using parallel processors or a multithreaded environment).
[0072] This application also provides a processor that may include the micro-operation result merging buffer device described above.
[0073] This application also provides a chip that may include the processor described above.
[0074] This application also provides an electronic device that may include the chip described above.
[0075] This application also provides another electronic device, such as... Figure 7As shown, in some embodiments of this application, the electronic device 702 may include one or more processors 704, such as one or more central processing units (CPUs) or graphics processing units (GPUs), each of which may implement one or more hardware threads. The electronic device 702 may also include any memory 706 for storing any kind of information such as code, settings, data, etc. In one specific embodiment, a computer program is stored on the memory 706 and can run on the processor 704. When the computer program is run by the processor 704, it can execute instructions of the micro-operation result merging buffer method described in any of the above embodiments. Non-limitingly, for example, the memory 706 may include any type of RAM, any type of ROM, flash memory device, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Further, any memory can provide volatile or non-volatile retention of information. Further, any memory can represent a fixed or removable component of the electronic device 702. In one case, when the processor 704 executes associated instructions stored in any memory or combination of memories, the electronic device 702 can perform any operation of the associated instructions. The electronic device 702 also includes one or more drive mechanisms 708 for interacting with any memory, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.
[0076] Electronic device 702 may also include an input / output interface 710 (I / O) for receiving various inputs (via input device 712) and providing various outputs (via output device 714). A specific output mechanism may include a presentation device 716 and an associated graphical user interface 718 (GUI). In other embodiments, the input / output interface 710 (I / O), input device 712, and output device 714 may be omitted, and the device may function solely as an electronic device within a network. Electronic device 702 may also include one or more network interfaces 720 for exchanging data with other devices via one or more communication links 722. One or more communication buses 724 couple the components described above together.
[0077] Communication link 722 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 722 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.
[0078] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), computer-readable storage media, and computer program products according to some embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processor to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processor, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0079] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processor to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0080] These computer program instructions may also be loaded onto a computer or other programmable data processor, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable device for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0081] In a typical configuration, an electronic device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.
[0082] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.
[0083] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by electronic devices. As defined in this application, computer-readable media does not include transient media, such as modulated data signals and carrier waves.
[0084] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, embodiments of this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0085] The embodiments of this application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. The embodiments of this application can also be practiced in distributed computing environments where tasks are performed by remote processors connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.
[0086] It should also be understood that, in the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0087] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the device embodiments, so the description is relatively simple; relevant parts can be referred to the description of the device embodiments.
[0088] In the description of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this application, as well as the features of different embodiments or examples.
[0089] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.
Claims
1. A micro-operation result merging and buffering device, characterized in that, The device, located on the processor's write-back pipeline, includes: The buffer management unit is used to store dynamically allocated buffer entries. Each buffer entry includes: an index field for storing the target register identifier; a result field for temporarily storing the intermediate results to be merged from the target register; and a progress field for recording the collection progress of the intermediate results from the target register. The write-back control unit is used to respond to the micro-operation result entering the write-back pipeline, match or allocate a corresponding storage entry according to the target register identifier it carries, merge the micro-operation result into the result field of the matched or allocated cache entry, and update the progress field of the corresponding cache entry. When the progress field indicates that the intermediate results for the corresponding target register have been collected, the complete result in the result field of the corresponding cache entry is written into the corresponding target register in the physical register file.
2. The apparatus according to claim 1, characterized in that, The device is located between the memory management unit and the physical register file.
3. The apparatus according to claim 1, characterized in that, The buffer management unit includes two levels of buffering: The result merge cache serves as a first-level buffer, containing multiple first-class entries, each of which contains the index field, the result field, and the progress field. The scoring table, as a second-level buffer, contains multiple second-class entries, each of which contains the index field and the progress field; The depth of the scoring table is greater than the depth of the result merging cache.
4. The apparatus according to claim 3, characterized in that, The step of matching or allocating a corresponding storage entry based on the target register identifier it carries includes: The results are merged into the cache to match the storage entry corresponding to the target register identifier; If a miss occurs, a storage entry is allocated for the micro-operation result carrying the identifier of the target register.
5. The apparatus according to claim 4, characterized in that, Each Category 1 entry also includes an activity indicator field, which indicates the level of activity of the corresponding Category 1 entry being accessed; The allocation of a storage entry for the micro-operation result carrying the target register identifier includes: When the number of first-type entries in the result merging cache has reached its limit, and there is no first-type entry corresponding to the target register identifier in the result merging cache, a first-type entry is selected according to the activity indicator field, the intermediate result stored in the selected first-type entry is written into the corresponding target register in the physical register file, and the selected first-type entry is cleared as a first-type entry allocated for the micro-operation result carrying the target register identifier.
6. The apparatus according to claim 5, characterized in that, The step of selecting the first type of entry based on the activity indicator field includes: Select the first category of entries with the lowest activity based on the activity indicator field.
7. The apparatus according to claim 5 or 6, characterized in that, The step of allocating a storage entry for the micro-operation result carrying the target register identifier further includes: If the number of first-type entries in the result merging cache has not reached the upper limit, and if there is no first-type entry corresponding to the target register identifier in the result merging cache, but there is a second-type entry corresponding to the target register identifier in the score table, then a first-type entry is allocated in the result merging cache for the micro-operation result carrying the target register identifier. Based on the target register identifier, the corresponding intermediate result is read back from the physical register file, the corresponding collection progress is read back from the score table, and the intermediate result and the collection progress are loaded into the corresponding field of the first-type entry.
8. The apparatus according to claim 4, characterized in that, The step of allocating a storage entry for the micro-operation result carrying the target register identifier further includes: If there is no first-type entry corresponding to the target register identifier in the result merging cache and no second-type entry corresponding to the target register identifier in the score table, then one first-type entry and one second-type entry will be allocated to the micro-operation result carrying the target register identifier in the result merging cache and the score table, respectively.
9. The apparatus according to claim 1, characterized in that, The progress field for updating the corresponding cache entry includes: The corresponding progress field is accumulated based on the element width information carried in the micro-operation result; the element width information represents the element width occupied by the micro-operation result in the complete result of the corresponding target register.
10. The apparatus according to claim 9, characterized in that, The progress field indicates that intermediate results for the corresponding target register have been collected, including: The cumulative element width of the progress field reaches the total element width of the complete result of the corresponding target register.
11. The apparatus according to claim 1, characterized in that, The write-back control unit is also used for: After writing the complete result in the result field of the corresponding cache entry to the corresponding destination register in the physical register file, the resource occupation of the corresponding cache entry is released.
12. The apparatus according to claim 1, characterized in that, The write-back control unit is also used for: When the progress field indicates that intermediate results for the corresponding target register have not been collected, the operation of writing the micro-operation results into the physical register file is invalidated.
13. The apparatus according to claim 3, characterized in that, The depth of the score table is determined according to the formula D2=D0-D1; where D2 is the depth of the score table, D0 is the depth of the load storage queue loaded by the memory management unit, and D1 is the depth of the result merging cache.
14. A processor, characterized in that, It includes the apparatus as described in any one of claims 1-13.
15. A chip, characterized in that, It includes the processor as described in claim 14.
16. An electronic device, characterized in that, It includes the chip as described in claim 15.
17. A method for merging and buffering micro-operation results, applied to the apparatus of claim 1, characterized in that, The method includes: In response to the micro-operation result entering the write-back pipeline, a corresponding memory entry is matched or allocated based on the target register identifier it carries. The micro-operation results are merged into the result field of the cache entry that is matched or assigned to them, and the progress field of the corresponding cache entry is updated. When the progress field indicates that the intermediate results for the corresponding target register have been collected, the complete result in the result field of the corresponding cached entry is written into the corresponding target register in the physical register file.
18. The method according to claim 17, characterized in that, The buffer management unit includes two levels of storage: The result merge cache serves as a first-level buffer, containing multiple first-class entries, each of which contains the index field, the result field, and the progress field. The scoring table, as a second-level buffer, contains multiple second-class entries, each of which contains the index field and the progress field; The depth of the scoring table is greater than the depth of the result merging cache.
19. The method according to claim 18, characterized in that, The step of matching or allocating a corresponding storage entry based on the target register identifier it carries includes: The results are merged into the cache to match the storage entry corresponding to the target register identifier; If a miss occurs, a storage entry is allocated for the micro-operation result carrying the identifier of the target register.
20. The method according to claim 19, characterized in that, Each Category 1 entry also includes an activity indicator field, which indicates the level of activity of the corresponding Category 1 entry being accessed; The allocation of a storage entry for the micro-operation result carrying the target register identifier includes: When the number of first-type entries in the result merging cache has reached its limit, and there is no first-type entry corresponding to the target register identifier in the result merging cache, the first-type entry is selected according to the activity indicator field; The intermediate results of the selected first type of entry are written into the corresponding target register in the physical register file; Clear the selected first-class entry as a first-class entry assigned to the micro-operation result carrying the target register identifier.
21. The method according to claim 20, characterized in that, The step of selecting the first type of entry based on the activity indicator field includes: Select the first category of entries with the lowest activity based on the activity indicator field.
22. The method according to claim 20 or 21, characterized in that, The step of allocating a storage entry for the micro-operation result carrying the target register identifier further includes: If the number of first-type entries in the result merging cache has not reached the upper limit, and if there is no first-type entry corresponding to the target register identifier in the result merging cache, but there is a second-type entry corresponding to the target register identifier in the score table, then a first-type entry is allocated in the result merging cache for the micro-operation result carrying the target register identifier. Based on the target register identifier, read back the corresponding intermediate results from the physical register file and read back the corresponding collection progress from the score table; The intermediate result and the collection progress are then loaded into the corresponding field of the first type of entry.
23. The method according to claim 19, characterized in that, The step of allocating a storage entry for the micro-operation result carrying the target register identifier further includes: If there is no first-type entry corresponding to the target register identifier in the result merging cache and no second-type entry corresponding to the target register identifier in the score table, then one first-type entry and one second-type entry will be allocated to the micro-operation result carrying the target register identifier in the result merging cache and the score table, respectively.
24. The method according to claim 17, characterized in that, The progress field for updating the corresponding cache entry includes: The corresponding progress field is accumulated based on the element width information carried in the micro-operation result; the element width information represents the element width occupied by the micro-operation result in the complete result of the corresponding target register.
25. The method according to claim 24, characterized in that, The progress field indicates that intermediate results for the corresponding target register have been collected, including: The cumulative element width of the progress field reaches the total element width of the complete result of the corresponding target register.
26. The method according to claim 17, characterized in that, The method further includes: After writing the complete result in the result field of the corresponding cache entry to the corresponding destination register in the physical register file, the resource occupation of the corresponding cache entry is released.
27. The method according to claim 17, characterized in that, The method further includes: When the progress field indicates that intermediate results for the corresponding target register have not been collected, the operation of writing the micro-operation results into the physical register file is invalidated.