Memory replacement strategy determination method and electronic equipment

Abstract

The invention provides a memory replacement strategy determination method and electronic equipment. The method comprises the following steps: acquiring memory error logs and read-write behavior data corresponding to each memory module in the electronic equipment; the read-write behavior data comprises a current data storage amount, an accumulated read-write data amount and a plurality of system available bandwidths collected every preset time in a preset time period; determining a corresponding migration duration based on the current data storage amount corresponding to each memory module and the available bandwidths of the plurality of systems; based on the migration duration corresponding to each memory module, extracting time-space distribution feature information capable of correcting errors from the corresponding memory error logs; and generating memory replacement strategies corresponding to all the memory modules in the electronic equipment based on the space-time distribution feature information corresponding to each memory module and the accumulated read-write data volume.

Description

Technical Field

[0001] This application relates to the field of memory management technology, and in particular to a method for determining a memory replacement strategy and an electronic device. Background Technology

[0002] In computer systems, memory is a critical hardware component, and its reliability directly impacts system stability and data processing capabilities. With the increasing scale of servers and the growing complexity of applications, memory failures (such as uncorrectable errors (UE)) have become a significant factor leading to node failures, service interruptions, and even cluster instability. Therefore, predicting memory failures in advance and developing appropriate replacement strategies are crucial for improving system availability and reducing operational costs.

[0003] Among related technologies, a typical approach is to statistically analyze the bitmap pattern of Correctable Errors (CEs) and combine it with expert rules to determine whether a User Experience (UE) will occur in the future. Another approach is to divide time windows based on historical error data and extract statistical features for prediction. While these methods can identify potential failure risks to some extent, they all have significant limitations. On the one hand, they are poorly adaptable to large-scale heterogeneous platforms and cannot accurately reflect the actual failure trends under different platforms. On the other hand, the predicted failure risks differ significantly from the actual risks, resulting in poor prediction accuracy. Summary of the Invention

[0004] This application provides a method for determining a memory replacement strategy and an electronic device.

[0005] The technical solution of this application embodiment is implemented as follows: This application provides a method for determining a memory replacement strategy, the method including: Acquire memory error logs and read / write behavior data corresponding to each memory module in the electronic device; the read / write behavior data includes: current data storage volume, cumulative read / write data volume, and multiple system available bandwidths collected at preset intervals within a preset time period; The corresponding migration duration is determined based on the current data storage volume of each memory module and the available bandwidth of multiple systems. Based on the migration time corresponding to each memory module, the spatiotemporal distribution characteristics of correctable errors are extracted from the corresponding memory error logs; Based on the spatiotemporal distribution characteristics and cumulative read / write data volume of each memory module, a memory replacement strategy is generated for all memory modules in the electronic device.

[0006] This application provides an electronic device, which includes: Memory, configured to store computer programs that can run on a processor; When the processor is configured to execute a computer program, it performs the following steps: acquiring memory error logs and read / write behavior data corresponding to each memory module within the electronic device; the read / write behavior data includes: current data storage volume, cumulative read / write data volume, and multiple system available bandwidths collected at preset intervals within a preset time period; determining the corresponding migration duration based on the current data storage volume and multiple system available bandwidths corresponding to each memory module; extracting the spatiotemporal distribution characteristics of correctable errors from the corresponding memory error logs based on the migration duration corresponding to each memory module; and generating memory replacement strategies corresponding to all memory modules within the electronic device based on the spatiotemporal distribution characteristics and cumulative read / write data volume corresponding to each memory module.

[0007] This application provides a computer-readable storage medium storing a computer program or computer-executable instructions, which, when executed by a processor, implements the method for determining a memory replacement strategy provided in this application.

[0008] This application provides a computer program product, including a computer program or computer executable instructions. When the computer program or computer executable instructions are executed by a processor, they implement the method for determining the memory replacement strategy provided in this application. Attached Figure Description

[0009] Figure 1 This is a flowchart illustrating a method for determining a memory replacement strategy provided in an embodiment of this application; Figure 2 This is a schematic diagram of an exemplary memory module provided in an embodiment of this application; Figure 3 This is a flowchart illustrating an exemplary method for determining spatial feature information provided in an embodiment of this application; Figure 4 This is a schematic diagram of an exemplary bit distribution type provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 1 ; Figure 6 This is a schematic diagram illustrating an exemplary process for determining a comprehensive risk index, provided in an embodiment of this application. Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 2 . Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0011] This application provides a method for determining a memory replacement strategy, implemented by an electronic device, such as... Figure 1 As shown, the process includes the following steps S101 and S104: Step S101: Obtain memory error logs and read / write behavior data corresponding to each memory module in the electronic device; the read / write behavior data includes: current data storage volume, cumulative read / write data volume, and multiple system available bandwidths collected at preset intervals within a preset time period.

[0012] In the embodiments of this application, the electronic device is a device with the function of determining the memory replacement strategy. Exemplary electronic devices may be tablet computers, laptop computers, handheld computers, personal digital assistants (PDAs), desktop computers, servers, etc. The exemplary electronic devices are not limited here.

[0013] In the embodiments of this application, electronic devices typically include multiple dual in-line memory modules (DIMMs), each DIMM having an independent hardware performance counter (such as Intel PCM) and an error logging interface.

[0014] For example, electronic devices can continuously collect memory error logs corresponding to each DIMM through the hardware error reporting mechanism built into the operating system and the Baseboard Management Controller (BMC), and periodically parse them. After parsing, these data are formatted and stored in a structured manner, which can provide complete and traceable raw error data for subsequent data processing. In the embodiments of this application, the electronic device may also collect read and write behavior data, which includes: current data storage volume, cumulative read and write data volume, and multiple system available bandwidths collected at preset intervals within a preset time period.

[0015] For example, collecting DIMM read / write behavior data may include: using hardware performance counters of the server's central processing unit (CPU) or memory controller (such as Intel Performance Counter Monitor (Intel PCM) or Intel Integrated Memory Controller Performance Monitoring Unit (Intel IMCPMU)) to record the cumulative read / write data volume of each DIMM or channel; obtaining the current data volume (current data storage volume) carried by the DIMM from the system memory management module; and obtaining the available bandwidth of the current node through hardware counters or operating system (OS) performance monitoring interfaces, and recording the bandwidth change process within a day (within a preset time period). The preset time period can be one day, 10 hours, or other time periods, and can be set based on actual needs and application scenarios; this application does not limit this.

[0016] In the embodiments of this application, the current data storage volume represents the effective data volume currently carried by the memory module; the cumulative read and write data volume reflects the access intensity of the memory module since the system started; and the available bandwidth of the system reflects the current data transmission capability of the system.

[0017] Step S102: Determine the corresponding migration duration based on the current data storage volume of each memory module and the available bandwidth of multiple systems.

[0018] In the embodiments of this application, migration time refers to the time required to migrate data from a memory module to other normal memory modules in order to ensure service continuity before an uncorrectable error (UE) occurs.

[0019] In embodiments of this application, the electronic device can calculate a reasonable migration time based on the current data storage volume of each memory module and the available bandwidth of multiple systems. For example, if the current data storage volume of a certain DIMM is 5GB and the average available bandwidth of multiple systems is 100MB / s, then the theoretical minimum migration time is approximately 50 seconds.

[0020] In the embodiments of this application, the electronic device may also take into account factors such as system load fluctuations, adjust the migration time, and introduce a certain amount of redundancy.

[0021] Step S103: Based on the migration time corresponding to each memory module, extract the spatiotemporal distribution feature information of correctable errors from the corresponding memory error log.

[0022] In the embodiments of this application, spatiotemporal distribution feature information is used to describe the distribution pattern of correctable errors (CEs) in the temporal and spatial dimensions. The electronic device can set a time window for analyzing CEs based on the migration duration, then extract error events within the time window from the memory error log, and analyze and process these correctable error events to extract their distribution feature information in the temporal and spatial dimensions.

[0023] For example, if a cell address (or row, column, or storage block) on a certain DIMM experiences multiple error corrections (CEs), the electronic device may determine that the corresponding address has a degradation trend. The electronic device can also count the number of memory errors based on the memory error log and determine whether there is a sudden clustering of errors over time. Alternatively, the electronic device can determine the bit distribution corresponding to each correctable error. The electronic device uses these spatiotemporal distribution characteristics to count correctable errors per unit time to identify early signs of memory module failure, thereby providing an important basis for subsequent risk assessment.

[0024] Step S104: Based on the spatiotemporal distribution characteristics and cumulative read / write data volume of each memory module, generate memory replacement strategies for all memory modules in the electronic device.

[0025] In the embodiments of this application, the memory replacement strategy refers to a decision-making scheme based on the risk assessment results of memory modules, determining which memory modules should be replaced first. The electronic device combines spatiotemporal distribution characteristic information with the cumulative read / write data volume to generate memory replacement strategies corresponding to all memory modules in the electronic device, thus obtaining the memory replacement strategy.

[0026] For example, electronic devices can assess the fault status of each memory module based on spatiotemporal distribution characteristics, and then combine this with the cumulative read / write data volume of the memory modules (the probability of them being accessed) to generate a final memory replacement priority order. This strategy comprehensively considers the fault risk score of the memory modules and their access probability in future operation, thereby optimizing the maintenance sequence, improving system reliability, and reducing maintenance costs.

[0027] For example, a memory module may have a high risk of failure, but if its access probability is low, it may not immediately trigger an uncorrectable error, thus its replacement can be appropriately postponed. Conversely, another memory module may have a slightly lower risk of failure, but due to frequent access, an error in this module would have a significant impact on the system, therefore it should be replaced first. In this way, electronic devices can optimize the allocation of maintenance resources and reduce unnecessary hardware replacement costs while ensuring reliability.

[0028] In this way, by collecting error logs and read / write behavior data from each memory module, combining them with migration time for feature extraction, and generating comprehensive evaluation factors, the optimal memory replacement strategy can be formulated, significantly improving the accuracy of memory fault prediction and maintenance efficiency.

[0029] In some embodiments, the memory error log includes at least one of the following: a timestamp of the error occurrence, the error type, the physical address and level of the error occurrence, error bit information, and an error count.

[0030] In the embodiments of this application, the memory error log is a detailed description of correctable or uncorrectable errors recorded during server operation. The memory error log contains information in multiple dimensions to characterize the occurrence time, spatial location, and nature of memory failures. Electronic devices use this information to support subsequent failure prediction and risk assessment.

[0031] For example, the timestamp of an error refers to the precise point in time when the system detects an error, usually recorded in milliseconds or nanoseconds, used to track the order and frequency of errors; the error type is used to distinguish whether an error can be corrected by the ECC mechanism, for example, CE indicates that the error can be corrected, while UE indicates that the error cannot be corrected and leads to a system interruption; the physical address and hierarchical location of the error are key information that maps the error to a specific hardware structure. The physical address and hierarchical location can be used to locate which DIMM, channel (memory channel), rank (independently addressed logical unit on the memory module), bank (memory bank), row (row), or column the error occurred on, which can further refine the spatial distribution of the error and help identify whether there is degradation of shared components along the path; the error bit information refers to which specific bits have been flipped, and the error bit information is crucial for determining whether the error is repetitive or locally concentrated; the error count is used to count the number of errors that occur, and the error count is one of the important indicators for measuring the trend of memory degradation.

[0032] In the embodiments of this application, by collecting the aforementioned multi-dimensional memory error log content, a more refined memory state model can be constructed, thereby improving the accuracy of fault prediction. Compared with existing methods that rely solely on the number or pattern of errors, this solution enhances the ability to identify potential faults by introducing richer spatiotemporal information and also possesses stronger cross-platform consistency.

[0033] In this way, features reflecting the health status of memory can be accurately extracted, thereby improving the reliability of the fault prediction model and providing a scientific basis for system maintenance strategies.

[0034] In some embodiments, when performing step S102, the electronic device may also perform the following steps S201 and S202: Step S201: Determine the corresponding target available bandwidth based on the multiple system available bandwidths corresponding to each memory module.

[0035] In the embodiments of this application, the target available bandwidth refers to the maximum data transfer rate that can be used for a specific memory module under the current operating conditions of the system. The target available bandwidth reflects the actual capability of the system when performing data migration operations, and the value of the target available bandwidth is affected by factors such as the current system load, network status, and CPU utilization.

[0036] In the embodiments of this application, the target available bandwidth can be selected using one of several statistical values, such as the average bandwidth, peak bandwidth, or 95th percentile of available bandwidth across multiple systems. Different statistical methods can be selected to more accurately reflect the actual available resources based on different business scenarios and operational strategies. For example, during high-load periods, selecting a bandwidth with a lower percentile can better reflect the true available resources, while during low-load periods, a higher bandwidth value can be selected to accelerate migration.

[0037] In the embodiments of this application, the target available bandwidth is determined by performing the operation using multiple system available bandwidths, which allows for dynamic adjustment of the migration plan under different system environments and load conditions. This adjustment method ensures that the migration of critical data is completed within a limited time, thereby improving the reliability and stability of the system.

[0038] Step S202: Determine the migration duration as the time corresponding to the current data storage volume under the target available bandwidth.

[0039] In the embodiments of this application, the migration time refers to the time required to complete the storage of the current amount of data in a specified memory module given a target available bandwidth.

[0040] For example, the formula for calculating the migration time is shown in formula (1): (1); in, For migration duration, This represents the current data storage volume. The available bandwidth for the target.

[0041] In the embodiments of this application, the formula for calculating migration time takes into account the actual data migration efficiency and avoids theoretical idealization assumptions, so that the formula for calculating migration time can more accurately predict the time required for data migration.

[0042] In the embodiments of this application, determining the migration duration is of great significance for subsequent risk modeling and maintenance decisions. On the one hand, the migration duration can ensure that data migration can be completed in a timely manner in the event of an uncorrectable error (UE), thereby avoiding service interruption; on the other hand, the migration duration is used as a feature input model, which helps to build a more accurate fault prediction model and improve the accuracy of lead time prediction.

[0043] In embodiments of this application, the migration duration can also be used to generate differentiated lead times, that is, to set different early warning windows according to the migration needs of different DIMMs, so that risk prediction and actual maintenance operations are more closely aligned with business needs. For example, in the case of DIMMs with longer migration durations, an early warning signal can be issued at an earlier time than for other DIMMs to ensure that sufficient processing time can be reserved for subsequent maintenance operations.

[0044] In this way, the target available bandwidth is determined based on the system's available bandwidth, and the migration time is calculated accordingly. This allows for a more accurate assessment of the time required for data migration, enabling the rational planning of memory replacement and maintenance schedules, thereby improving the overall reliability and operational efficiency of the system. Furthermore, the migration time can be used to determine the time window for extracting correctable spatiotemporal distribution characteristics, avoiding the tedious process of using data from the entire cycle.

[0045] In some embodiments, the spatiotemporal distribution feature information includes at least one of the following: temporal feature information, spatial feature information, and bi-bit feature information.

[0046] In embodiments of this application, temporal feature information is used to characterize the suddenness of error events and the closeness of their arrival intervals over time. Electronic devices can determine the temporal feature information of correctable errors based on the timestamps of error occurrences, error types, error counts, etc., included in the memory error log.

[0047] For example, a large number of correctable errors occurring within a given hour may indicate that an uncorrectable error is imminent in the DIMM. By dividing the time window, counting the number of errors (CEs), and calculating the average time interval between adjacent CEs, it is possible to identify high-risk temporal behavior patterns, thereby improving the accuracy of predicting the occurrence of uncorrectable errors.

[0048] In the embodiments of this application, spatial feature information is used to characterize the recurrence of correctable errors in the memory address hierarchy (spatial dimension). Electronic devices can determine the spatial feature information based on information such as the timestamp of the error occurrence, error type, physical address of the error, and hierarchical location included in the memory error log.

[0049] For example, if correctable errors occur frequently in a row or bank, it indicates that the row or bank may have hardware degradation or defects, which could lead to a higher likelihood of uncorrectable errors in the future. The features of the aforementioned spatial dimension can capture the degradation patterns of shared components (such as row drivers, column decoders, etc.) along the memory path, thereby improving fault location capabilities.

[0050] In the embodiments of this application, the binary bit feature information refers to the feature formed after binary classification of the bits involved in the correctable error.

[0051] In the embodiments of this application, by introducing temporal feature information, spatial feature information, and binary bit feature information, the spatiotemporal distribution pattern of correctable errors can be comprehensively characterized. This allows for a more accurate identification of the probability of potential uncorrectable errors, enabling early warning and the development of maintenance strategies, thereby significantly improving the reliability and operational efficiency of the server system.

[0052] In some embodiments, when performing step S103, the electronic device may perform the following steps S301 to S305: Step S301: Based on the migration duration, determine the target time window for extracting spatiotemporal distribution feature information.

[0053] In the embodiments of this application, the target time window is a time range set according to the migration duration. Within the target time window, the electronic device performs statistics and feature extraction on the CE logs to ensure that the extracted features can cover possible error patterns in the future.

[0054] In the embodiments of this application, by setting a target time window that matches actual maintenance needs, the trend of memory degradation can be captured more accurately, thereby improving the accuracy of the predictive model. For example, the target time window can be forward from the current data acquisition time. All the data is used to extract spatiotemporal distribution feature information. If the current time is... Therefore, the target window is [ - , ].

[0055] Step S302: Divide the target time window into multiple time windows according to the first time length; the first time length is any one of the multiple time lengths.

[0056] In the embodiments of this application, the first time length is a unit time interval used to divide the target time window, and different values ​​can be selected according to different application scenarios. The electronic device can divide the target time window into the first time window. Multiple time lengths can also include others, such as 2 hours, 10 minutes, etc., and of course, any combination thereof is allowed. This application does not limit this.

[0057] In the embodiments of this application, by dividing the target time window into multiple scales, the clustering and periodicity of errors can be analyzed at different time granularities, thereby improving the predictive model's adaptability to different failure modes.

[0058] In the embodiments of this application, this multi-scale time window partitioning method can enhance the sensitivity of the prediction model to abnormal behavior, making the prediction results more robust and generalizable.

[0059] Step S303: Within each time window, using the corresponding memory error log, determine the number of times correctable errors repeatedly occur in the same spatial location of multiple storage chips included in each memory module according to different address levels; the address level includes at least one of storage cell, row, column, and storage bank.

[0060] In the embodiments of this application, within each time window, the number of times a correctable error recurs at the same spatial location in the multiple memory chips included in each memory module is determined according to different address levels using the corresponding memory error log. For example, as... Figure 2 As shown, a DIMM 21 consists of multiple DRAM chips (memory chips) 22, which are organized into an array, where all chips in the array operate in parallel to serve memory requests; each RANK (independently addressed logical unit on a memory module) typically contains 16 data chips and 2 ECC chips. Each DRAM chip is internally divided into multiple banks 23, and each bank 23 is constructed as a two-dimensional array of cells 26 indexed by rows 24 and columns 25.

[0061] In the embodiments of this application, the relationships between address levels exhibit a certain nesting characteristic. For example, a storage unit may belong to a certain row and a certain column, and the row and column may reside within the same storage unit. Therefore, when counting the number of repeated errors, the error distribution can be gradually summarized from fine-grained to coarse-grained levels in a progressive manner, thereby forming a multi-dimensional spatial feature representation.

[0062] In the embodiments of this application, the target time window is divided into n time windows with a first time length. Within each time window, the number of times a correctable error corresponding to an address level recurs in the same spatial location of multiple storage chips included in each memory module is recorded. For example, the number of times a correctable error recurs in the same spatial location of multiple storage chips included in each memory module in the address level of n storage cells, the number of times a correctable error recurs in the same spatial location of multiple storage chips included in each memory module within each time window in the address level of n rows, the number of times a correctable error recurs in the same spatial location of multiple storage chips included in each memory module within each time window in the address level of n columns, and the number of times a correctable error recurs in the same spatial location of multiple storage chips included in each memory module within each time window in the address level of n memory banks can be obtained.

[0063] For example, such as Figure 3 As shown, within each time window, the number of times correctable errors recur in the same spatial location of multiple storage chips included in each memory module is determined according to different address levels using the corresponding memory error log.

[0064] Step S304: For each address level, determine the maximum number of repetitions in multiple time windows as the corresponding maximum number of repetitions, and determine the maximum number of repetitions corresponding to different address levels as the repetition spatial feature information corresponding to the first time length.

[0065] In the embodiments of this application, the maximum repetition count represents the highest frequency of error recurrence across all time windows at a certain address level. The maximum repetition counts at different address levels are combined to form a feature vector reflecting the spatial distribution characteristics of errors, which is named repetition space feature information. The repetition space feature information can be used to measure the degree of concentration of errors in the physical structure, thereby assessing the overall health of the memory module.

[0066] In the embodiments of this application, when the error is at the same physical cell address and occurs within a specific time window... If the error is repeated across devices at the cell level, it is considered to be a repeating pattern at the cell level. The method for determining the maximum number of repetitions across multiple time windows at the storage unit level is shown in formula (2): (2); Each level will obtain a corresponding maximum number of repetitions. Then, the maximum number of repetitions corresponding to different address levels will be determined as the repetition space feature information corresponding to the first time length.

[0067] In the embodiments of this application, by constructing repetitive spatial feature information, it is possible to achieve quantitative analysis of error spatial distribution. The constructed repetitive spatial feature information provides key input for subsequent risk scoring and helps to improve the discrimination ability of the prediction model.

[0068] Step S305: Determine the repeated spatial feature information corresponding to multiple time lengths as spatial feature information.

[0069] In the embodiments of this application, step S302 involves several time lengths. Here, the maximum number of repetitions (repetition spatial feature information) at different address levels corresponding to several time lengths will be obtained. Then, the repetition spatial feature information corresponding to multiple first time lengths will be determined as spatial feature information.

[0070] In the embodiments of this application, spatial feature information is a comprehensive expression of repeated spatial feature information extracted over multiple time periods. This spatial feature information reflects the spatial distribution characteristics of memory errors at different time scales. As a crucial input for training the predictive model, spatial feature information helps distinguish between the probability of normal aging processes and sudden failures.

[0071] Thus, by setting a target time window based on migration duration and dividing the target time window into multiple time windows, the number of error repetitions is statistically analyzed according to address level, and then the maximum repetition count is extracted to construct spatial feature information. This method accurately characterizes the spatial distribution features of memory errors, effectively identifying potential fault development trends and further improving the accuracy of memory fault prediction and system reliability.

[0072] In some embodiments, when performing step S103, the electronic device may also perform steps S401 to S405: Steps S401 and S402 here are the same as steps S301 and S302 above, and will not be repeated here.

[0073] Step S403: Determine the number of times a correctable error occurs in each of the multiple time windows, and determine the maximum number of occurrences in the multiple time windows as the error burst characteristic information corresponding to the first time length.

[0074] In the embodiments of this application, the error burstiness characteristic information reflects the density of errors occurring within a specific time period. By statistically analyzing the number of errors within each time window and taking the maximum value as the error burstiness characteristic information, abnormal error concentrations that may indicate memory failures can be effectively identified. Error burstiness characteristic information is of great significance for capturing transient failures and can help improve the sensitivity and accuracy of prediction models.

[0075] For example, if the number of correctable errors occurring in each time window within multiple time lengths is 5, 10, 3, 2, and 5 respectively, then the error burst characteristic information corresponding to the first time length is 10.

[0076] In the embodiments of this application, the maximum number of CEs in all windows is taken as the temporal clustering index. The larger the value, the more it indicates that a sudden concentration of errors has occurred in the DIMM within a certain time period.

[0077] Step S404: Determine the average time interval between adjacent correctable errors within each of the multiple time windows, and determine the minimum average time interval within the multiple time windows as the error interval feature information corresponding to the first time length.

[0078] In embodiments of this application, the average time interval between adjacent correctable errors within each of multiple time windows is determined. For example, if there are three correctable errors in a certain time window, and the intervals between each correctable error and the previous correctable error are 10 minutes, 2 minutes, and 6 minutes, then 6 minutes is the average time interval between adjacent correctable errors within that time window. Then, the minimum average time interval within the multiple time windows is determined as the error interval feature information corresponding to the first time length. That is, for each time window, the average time interval between adjacent errors (CEs) is calculated, and the minimum value is taken as the feature value across all windows. The smaller this value, the stronger the clustering effect of errors over time, indicating that abnormally dense error events occurred during that period.

[0079] Step S405: Determine the error burst characteristic information and error interval characteristic information corresponding to different time lengths among multiple time lengths as time characteristic information.

[0080] In the embodiments of this application, the target time window is dynamically determined based on the migration duration, and the time window is divided according to different time granularities. Error burstiness characteristic information and error interval characteristic information are extracted, thereby constructing more comprehensive and accurate time feature information. This better reflects the clustering characteristics of memory errors in the time dimension, thereby improving the model's ability to identify potential faults, and ultimately improving the accuracy and lead time of memory fault prediction, achieving a more efficient and reliable system maintenance strategy.

[0081] In some embodiments, when performing step S103, the electronic device may also perform steps S501 to S504: Step S501: Based on the migration duration, determine the target time window for extracting spatiotemporal distribution feature information.

[0082] Step S501 is the same as steps S401 and S301 above. For details, please refer to the discussion of step S301. It will not be repeated here.

[0083] Step S502: Based on the memory error logs corresponding to each memory module, determine the bit distribution type corresponding to each correctable error that occurs in the target time window.

[0084] In embodiments of this application, the bit distribution type describes the bit information affected by each correctable error. Since different error causes lead to different bit flipping patterns, identifying the bit distribution type can further distinguish the source or severity of the error. For example, some errors may be concentrated on a few adjacent bits, while others may be randomly distributed throughout the entire byte. Classifying the bit distribution type helps identify DIMMs with similar degradation patterns and is used for subsequent statistical modeling.

[0085] For example, such as Figure 4 As shown, bit distribution types can be as shown in (a) clustered vertical features 41 and dispersed vertical features 42, (b) clustered horizontal features 43 and dispersed horizontal features 44, and (c) unstructured bit distribution type 45.

[0086] Step S503: Based on the bit distribution type of at least one correctable error that occurs in each memory module, determine the number of errors corresponding to different bit distribution types.

[0087] In the embodiments of this application, different bit distribution types appearing in the same memory module within a target time window are statistically analyzed, and the frequency of occurrence of each type is recorded. For example, if a memory module has three correctable errors in the past 6 hours, two of which are clustered vertical features and one is a dispersed horizontal feature, then the bit distribution type of the memory module will be statistically analyzed as follows: clustered vertical feature: 2 times, dispersed horizontal feature: 1 time, dispersed vertical feature: 0 times, clustered horizontal feature: 0 times, unstructured bit distribution type: 0 times.

[0088] In the embodiments of this application, this statistical method helps to identify the repetitiveness of specific error patterns, thereby determining whether they indicate a higher risk of failure. In other words, the more frequently a certain bit distribution type occurs, the more likely that the error of that bit distribution type may have a certain regularity, and thus the error of that bit distribution type may indicate potential hardware defects or environmental interference factors.

[0089] Step S504: Determine the number of errors corresponding to different bit distribution types as the binary bit feature information corresponding to each memory module.

[0090] In the embodiments of this application, the electronic device determines the number of errors corresponding to different bit distribution types as the binary bit feature information corresponding to each memory module. That is, the above exemplary content, the clustered vertical feature: 2 times, the dispersed horizontal feature: 1 time, the dispersed vertical feature: 0 times, the clustered horizontal feature: 0 times, and the unstructured bit distribution type: 0 times, are used as binary bit feature information.

[0091] In the embodiments of this application, by determining the target time window based on the migration duration and generating binary bit feature information by combining the bit distribution type and the number of error occurrences, it is possible to more accurately capture the pattern changes of memory errors, thereby improving the reliability of risk prediction and providing more valuable decision-making basis for memory replacement strategies.

[0092] In some embodiments, when performing step S104 above, the electronic device may also perform steps S601 to S603: Step S601: Based on the spatiotemporal distribution characteristics of each memory module, determine the first evaluation factor for the occurrence of correctable errors.

[0093] In embodiments of this application, the electronic device can input spatiotemporal distribution feature information into a machine learning model to construct a first evaluation factor for the occurrence of a correctable error in the memory module. For example, the machine learning model can employ algorithms such as gradient boosting trees, random forests, and deep learning to output a risk score in the 0-1 range, representing the probability of a future UE (User Error Detection) (Risk(d), i.e., the first evaluation factor).

[0094] For example, an electronic device can select any two features from the spatiotemporal distribution feature information, such as: time feature information and spatial feature information, spatial feature information and binary bit feature information, time feature information and binary bit feature information, or select any one of the time feature information, spatial feature information, and binary bit feature information, or input all three feature information into the machine learning model.

[0095] Step S602: Based on the cumulative read / write data volume of each memory module and the total number of accesses to the memory modules in the electronic device, determine the corresponding second evaluation factor for the occurrence of correctable errors.

[0096] In the embodiments of this application, whether the UE actually triggers depends on whether the erroneous address continues to be accessed in subsequent operations. Within a given observation window (e.g., the most recent 1 hour or the most recent 24 hours), the number of accesses for each DIMM is counted and recorded as follows. And calculate the total number of visits for all DIMMs. The access frequency of a single DIMM is normalized to the access probability, which is the second evaluation factor. An exemplary method for determining this is shown in formula (3): (3); in, This represents the probability of access.

[0097] Step S603: Generate a memory replacement strategy based on the first evaluation factor and the second evaluation factor corresponding to each memory module.

[0098] In the embodiments of this application, the UE risk score output by the risk prediction module is... DIMM access probability They are all included in the priority scoring function, see formula (4): (4); in, This is the comprehensive risk index.

[0099] In the embodiments of this application, after obtaining the comprehensive risk index corresponding to all memory modules, the electronic device can proceed according to... Sort all DIMMs from top to bottom, generate a replacement sequence, and output the sorting results in the form of a list or alarm (memory replacement strategy). This supports batch replacement of memory modules or planned shutdown maintenance, thereby achieving a more efficient and controllable memory maintenance process.

[0100] In the embodiments of this application, the generated replacement priority list (memory replacement strategy) not only reflects the failure risk level of the DIMM itself, but also takes into account its access activity in actual business, thereby avoiding premature replacement of "high-risk but low-access" DIMMs, ensuring system reliability while reducing unnecessary maintenance costs and resource waste.

[0101] In some embodiments, after the electronic device performs the above-described step S104 of "generating memory replacement strategies corresponding to all memory modules within the electronic device", it may also perform the following steps S701 and S702: Step S701: Based on the memory replacement strategy, generate the replacement instruction corresponding to the memory module to be replaced.

[0102] In the embodiments of this application, the memory replacement strategy refers to a priority ranking rule formulated based on memory risk assessment results (such as failure probability (first assessment factor), access frequency (second assessment factor), etc.) to determine which memory modules should be replaced first. The memory module to be replaced refers to a memory component currently in a high-risk state and already included in the replacement sequence. By inputting this information into the system maintenance interface or automated operation and maintenance platform, specific execution commands (i.e., replacement instructions) are generated, such as: replace DIMM_SLOT_01, replace DIMM_SLOT_05, etc. The content of the replacement instruction typically includes key parameters such as the physical location of the target memory module, the expected replacement time, and whether system downtime is required.

[0103] Step S702: Output the replacement instruction corresponding to the memory module to be replaced, so that the memory can be replaced based on the replacement instruction.

[0104] In the embodiments of this application, output refers to sending the generated replacement instruction to a designated execution terminal or management system, such as an operations and maintenance console, an automatic replacement robot, or a remote management tool. Output methods can include graphical interface display, API calls, log recording, and other forms. Once the replacement instruction is received, it can trigger the subsequent hardware replacement process, such as scheduling engineers to perform manual replacement, or activating unattended replacement equipment for automatic replacement.

[0105] In the embodiments of this application, since the original memory module contains data, the replacement instruction may include not only key parameters such as the physical location of the target memory module, the expected replacement time, and whether a shutdown is required, but also parameters such as how to handle access to the memory module and how to migrate the stored data to the newly replaced memory module during the replacement process.

[0106] In the embodiments of this application, in a real production environment, after the replacement command is output, an alarm notification mechanism can also be set to push alarm messages to maintenance personnel, reminding them to promptly handle high-risk memory modules. Furthermore, the historical record function included in the replacement command facilitates subsequent auditing and optimization of maintenance strategies.

[0107] In the embodiments of this application, the memory replacement strategy determines which memory modules should be replaced, and the replacement instruction is the specific execution command generated by the memory replacement strategy. For example, if the memory replacement strategy specifies that the modules are sorted from high to low according to the comprehensive risk index, the replacement instruction will list the memory modules to be replaced in this sorting order and provide corresponding execution suggestions.

[0108] In this way, by outputting specific replacement instructions, closed-loop management from risk identification to maintenance execution can be achieved, which significantly improves the efficiency and accuracy of memory maintenance, thereby effectively reducing the probability of server downtime and data center operation and maintenance costs.

[0109] like Figure 5 As shown, the electronic device 5 may include a data acquisition module 51, a data migration time calculation module 52, a feature extraction module 53 based on migration time, a memory risk assessment module 54, and a replacement sequence generation module 55.

[0110] The data acquisition module 51 continuously collects operational data related to memory degradation in the server production environment, enabling dynamic monitoring of hardware health. This module connects to the server's log system, hardware performance counters, and memory controller interface to record DIMM operational behavior and error modes from multiple dimensions. Its main functions include: collecting data including, but not limited to: the occurrence time of CE (Error Detection); the row / column / bank / rank address information corresponding to the error; and formatting and structuring this data to provide complete and traceable raw error data for subsequent feature extraction and risk assessment modules. The hardware performance counters also collect data on the cumulative read / write bytes, stored data volume, and average system bandwidth for each DIMM.

[0111] The data migration time calculation module 52 is used to calculate the minimum reserved time required for data migration when a UE risk occurs, based on the amount of data currently stored in the DIMM and the available bandwidth of the system, and to provide time window parameters for subsequent risk modeling. This module takes the amount of data currently carried by the DIMM and the available bandwidth of the system as input and calculates the data migration time for subsequent feature extraction. The main steps include: (1) Acquisition and estimation of DIMM data volume: This module first reads the amount of data currently used by the DIMM and the range of data that can be accessed by other nodes from the system memory management unit or hardware monitoring interface, and calculates the amount of data to be migrated (corresponding to the current amount of data stored above); (2) Calculation of available bandwidth of the system (corresponding to the target available bandwidth above): Based on the records of the hardware performance counter and the OS performance monitoring interface, various statistical parameters of the available bandwidth of the system over a period of time (such as mean, peak, trough, 95th percentile) are statistically analyzed, and any one of the statistical values ​​is selected as the available bandwidth of the system; (3) Calculation is performed based on the above formula (1).

[0112] The feature extraction module 53 based on migration duration is used to extract spatiotemporal distribution features for UE prediction from CE logs, using data migration duration as a lead time: Spatial features: Statistical analysis at the address level to determine whether the same error location recurs on multiple chips, used to identify the risk propagation pattern caused by degradation of shared components along the memory path. Temporal features: Dividing the CE sequence into sliding time windows, statistically analyzing the number of burst errors within the window (maximum CE burst count) and the average CE interval, used to characterize the degree of error clustering in the time dimension. Bipartite bit feature information: The spatial distribution of error bits within the bitmap plays a crucial role in UE prediction, requiring explicit modeling of this distribution. Furthermore, unstructured multi-bit errors that do not match predefined patterns are challenging for ECC, prompting them to be included as a unique category to more comprehensively characterize bit-level fault mechanisms.

[0113] The memory risk assessment module 54 is used to build a machine learning model based on the aforementioned spatiotemporal features to quantitatively score the failure risk of the DIMM. Simultaneously, it combines the current read / write access behavior of the DIMM to predict its access probability within a future time window. The risk score and access probability together form a memory replacement priority evaluation index to guide subsequent maintenance strategies. This module further introduces the "access probability" dimension based on the traditional CE→UE prediction model, making the risk assessment closer to real-world operating scenarios and improving the consistency between alarm results and actual failure events. Figure 6 As shown. It mainly includes the following steps S801 to S806: Step S801: The CE history characteristics of the current DIMM.

[0114] Here, the spatiotemporal distribution features output by the feature extraction module 53 based on the migration duration are input into the machine learning model.

[0115] Step S802: Risk prediction using machine learning models.

[0116] Here, the spatiotemporal distribution features are input into a machine learning model to construct a failure risk score for the current DIMM. The risk score reflects the current hardware degradation trend.

[0117] Step S803, Risk Score.

[0118] Here, a risk score is output (corresponding to the first assessment factor discussed above), which represents the probability of a future UE occurring.

[0119] Step S804: Current DIMM read / write statistics.

[0120] Here, whether a UE actually triggers depends on whether the erroneous address continues to be accessed in subsequent operations. Within a given observation window (e.g., the most recent 1 hour or the most recent 24 hours), the number of accesses for each DIMM is counted.

[0121] Step S805: Calculation of access probability.

[0122] Here, the total number of visits to all DIMMs is calculated, and the access frequency of a single DIMM is normalized to the access probability (corresponding to the second evaluation factor discussed above).

[0123] Step S806, Comprehensive Risk Index.

[0124] Here, the UE risk score and DIMM access probability output by the risk prediction module are combined into the priority score to obtain the comprehensive risk index.

[0125] The replacement sequence generation module 55 is used to sort all DIMMs from highest to lowest according to the comprehensive risk index, generate a replacement sequence, and output the sorting results in the form of a list or alarm. This allows maintenance personnel to perform batch replacements or planned shutdown maintenance, thereby achieving a more efficient and controllable memory maintenance process.

[0126] The advantages of adopting the technical solution of this application are: (1) Introduce memory access behavior into risk assessment to make alarms more consistent with actual errors.

[0127] Traditional UE risk models do not consider whether the erroneous address will actually be accessed, which often leads to a mismatch between alarm time and actual fault occurrence time. This application introduces the current access behavior of DIMM into the risk scoring, enabling the model to identify high-risk errors that will actually be triggered, thereby making the alarm results more consistent with actual fault events and significantly improving the effectiveness of risk assessment.

[0128] (2) It has high prediction accuracy and strong cross-platform generalization ability.

[0129] The method for determining the memory replacement strategy in this application significantly outperforms related technologies in prediction performance across different platforms, achieving an average precision of 87.9% and a recall of 75.2% across platforms. Even in prediction scenarios with a prediction time of 48 hours in advance, it still achieves better results than related technologies when predicting with a prediction time of 1 hour in advance, thus allowing more time for data migration, backup, and maintenance, and improving the availability and reliability of the model in real production environments.

[0130] This application provides a method for determining a memory replacement strategy. The method includes: acquiring memory error logs and read / write behavior data corresponding to each memory module in an electronic device; the read / write behavior data includes: current data storage volume, cumulative read / write data volume, and multiple system available bandwidths collected at preset intervals within a preset time period; determining the corresponding migration duration based on the current data storage volume and multiple system available bandwidths corresponding to each memory module; extracting the spatiotemporal distribution feature information of correctable errors from the corresponding memory error logs based on the migration duration corresponding to each memory module; and generating a memory replacement strategy corresponding to all memory modules in the electronic device based on the spatiotemporal distribution feature information and cumulative read / write data volume corresponding to each memory module. The method for determining a memory replacement strategy provided in this application, by collecting error logs and read / write behavior data of each memory module, combining them with migration duration for feature extraction, and generating comprehensive evaluation factors, formulates the optimal memory replacement strategy, significantly improving the accuracy of memory fault prediction and maintenance efficiency.

[0131] like Figure 7 As shown, this application embodiment provides an electronic device 5, which includes: Memory 71 is configured to store computer programs that can run on the processor; When the processor 72 is configured to execute a computer program, it performs the following steps: acquiring memory error logs and read / write behavior data corresponding to each memory module in the electronic device; the read / write behavior data includes: current data storage volume, cumulative read / write data volume, and multiple system available bandwidths collected at preset intervals within a preset time period; determining the corresponding migration duration based on the current data storage volume and multiple system available bandwidths corresponding to each memory module; extracting the spatiotemporal distribution feature information of correctable errors from the corresponding memory error logs based on the migration duration corresponding to each memory module; and generating a memory replacement strategy corresponding to all memory modules in the electronic device based on the spatiotemporal distribution feature information and cumulative read / write data volume corresponding to each memory module.

[0132] In one embodiment of this application, the memory error log includes at least one of the following: a timestamp of the error occurrence, the error type, the physical address and hierarchical location of the error occurrence, error bit information, and an error count.

[0133] In one embodiment of this application, when the processor 72 is configured to execute a computer program, it can also perform the following steps: determining the corresponding target available bandwidth based on the multiple system available bandwidths corresponding to each memory module; and determining the migration duration corresponding to the current data storage volume under the target available bandwidth as the migration duration.

[0134] In one embodiment of this application, the spatiotemporal distribution feature information includes at least one of the following: time feature information, spatial feature information, and binary bit feature information.

[0135] In one embodiment of this application, the processor 72, configured to execute a computer program, may further perform the following steps: determining a target time window for extracting the spatiotemporal distribution feature information based on the migration duration; dividing the target time window into multiple time windows according to a first time length; the first time length being any of the multiple time lengths; within each time window, using the corresponding memory error log, determining the number of times correctable errors repeatedly occur at the same spatial location in the multiple storage chips included in each memory module according to different address levels; the address level including at least one of storage unit, row, column, and storage body; for each address level, determining the maximum number of repetitions in the multiple time windows as the corresponding maximum number of repetitions, determining the maximum number of repetitions corresponding to different address levels as the repetition spatial feature information corresponding to the first time length; and determining the repetition spatial feature information corresponding to the multiple time lengths as the spatial feature information.

[0136] In one embodiment of this application, the processor 72, configured to execute a computer program, may further perform the following steps: determining a target time window for extracting the spatiotemporal distribution feature information based on the migration duration; dividing the target time window into multiple time windows according to a first time length; the first time length being any one of multiple second time lengths; determining the number of times a correctable error occurs in each of the multiple time windows, and determining the maximum number of occurrences in the multiple time windows as the error burst feature information corresponding to the first time length; determining the average time interval between adjacent correctable errors within each of the multiple time windows, and determining the minimum average time interval in the multiple time windows as the error interval feature information corresponding to the first time length; and determining the error burst feature information and error interval feature information corresponding to different time lengths among the multiple time lengths as the time feature information.

[0137] In one embodiment of this application, the processor 72, when configured to execute a computer program, may further perform the following steps: determining a target time window for extracting the spatiotemporal distribution feature information based on the migration duration; determining the bit distribution type corresponding to each correctable error occurring in the target time window based on the memory error logs corresponding to each memory module; determining the number of errors corresponding to different bit distribution types based on the bit distribution type of at least one correctable error occurring in each memory module; and determining the number of errors corresponding to different bit distribution types as the binary bit feature information corresponding to each memory module.

[0138] In one embodiment of this application, the processor 72, when configured to execute a computer program, may further perform the following steps: determining a first evaluation factor for the occurrence of a correctable error based on the spatiotemporal distribution feature information corresponding to each memory module; determining a second evaluation factor for the occurrence of a correctable error based on the cumulative read / write data volume corresponding to each memory module and the total number of accesses corresponding to the memory modules in the electronic device; and generating the memory replacement strategy based on the first evaluation factor and the second evaluation factor corresponding to each memory module.

[0139] In one embodiment of this application, when the processor 72 is configured to execute a computer program, it can also perform the following steps: generating a replacement instruction corresponding to the memory module to be replaced based on the memory replacement strategy; and outputting the replacement instruction corresponding to the memory module to be replaced for memory replacement based on the replacement instruction.

[0140] This application provides a computer-readable storage medium storing one or more computer programs, which can be executed by one or more processors to implement the document tag management method described above. The computer-readable storage medium can be transient or non-transient.

[0141] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the interface generation method described above. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0142] In some embodiments, the storage medium may be a computer-readable storage medium, which may be volatile memory, such as random-access memory (RAM); or non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), ferromagnetic random access memory (FRAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic surface memory, optical disk, or compact disk-read-only memory (CD-ROM); or it may be various devices including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0143] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0144] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0145] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0146] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0147] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0148] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file containing other programs or data, for example, in one or more scripts within a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple co-located files (e.g., files storing one or more modules, subroutines, or code sections). As an example, executable instructions may be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0149] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

[0150] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0151] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not performed.

[0152] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for determining a memory replacement strategy, the method comprising: Obtain memory error logs and read / write behavior data for each memory module within the electronic device; The read / write behavior data includes: current data storage volume, cumulative read / write data volume, and multiple system available bandwidths collected at preset intervals within a preset time period; Based on the current data storage volume of each memory module and the available bandwidth of the multiple systems, the corresponding migration duration is determined; Based on the migration time corresponding to each memory module, the spatiotemporal distribution feature information of correctable errors is extracted from the corresponding memory error log; Based on the spatiotemporal distribution characteristics of each memory module and the cumulative read / write data volume, a memory replacement strategy is generated for all memory modules in the electronic device.

2. The method for determining the memory replacement strategy according to claim 1, wherein the memory error log includes: The error must include at least one of the following: timestamp of the error occurrence, error type, physical address and hierarchical location of the error occurrence, error bit information, and error count.

3. The method for determining the memory replacement strategy according to claim 1, wherein determining the corresponding migration duration based on the current data storage volume corresponding to each memory module and the available bandwidth of the multiple systems includes: Based on the available bandwidth of each memory module corresponding to the multiple systems, the corresponding target available bandwidth is determined; The migration duration is defined as the time taken to migrate the current data storage volume under the target available bandwidth.

4. The method for determining a memory replacement strategy according to claim 1, wherein the spatiotemporal distribution feature information includes: At least one of the following: time feature information, spatial feature information, and binary bit feature information.

5. The method for determining the memory replacement strategy according to claim 4, wherein extracting the spatiotemporal distribution feature information of correctable errors from the corresponding memory error log based on the migration time corresponding to each memory module includes: Based on the migration duration, a target time window for extracting the spatiotemporal distribution feature information is determined; The target time window is divided into multiple time windows according to a first time length; the first time length is any one of the multiple time lengths. Within each time window, using the corresponding memory error log, determine the number of times correctable errors recur in the same spatial location of multiple storage chips included in each memory module, according to different address levels; The address hierarchy includes at least one of storage units, rows, columns, and storage volumes; For each address level, the maximum number of repetitions in the multiple time windows is determined as the corresponding maximum number of repetitions, and the maximum number of repetitions corresponding to different address levels is determined as the repetition spatial feature information corresponding to the first time length. The repeated spatial feature information corresponding to the multiple time lengths is determined as the spatial feature information.

6. The method for determining the memory replacement strategy according to claim 4, wherein extracting the spatiotemporal distribution feature information of correctable errors from the corresponding memory error log based on the migration time corresponding to each memory module includes: Based on the migration duration, a target time window for extracting the spatiotemporal distribution feature information is determined; The target time window is divided into multiple time windows according to a first time length; the first time length is any one of multiple second time lengths. Determine the number of times a correctable error occurs in each of the multiple time windows, and determine the maximum number of occurrences in the multiple time windows as the error burst characteristic information corresponding to the first time length; The average time interval between adjacent correctable errors within each of the multiple time windows is determined, and the minimum average time interval within the multiple time windows is determined as the error interval feature information corresponding to the first time length. The error burst characteristic information and error interval characteristic information corresponding to different time lengths among the multiple time lengths are determined as the time characteristic information.

7. The method for determining a memory replacement strategy according to claim 4, wherein extracting the spatiotemporal distribution feature information of correctable errors from the corresponding memory error log based on the migration time corresponding to each memory module includes: Based on the migration duration, a target time window for extracting the spatiotemporal distribution feature information is determined; Based on the memory error logs corresponding to each memory module, determine the bit distribution type corresponding to each correctable error that occurs in the target time window; Based on the bit distribution type of at least one correctable error in each memory module, determine the number of errors corresponding to different bit distribution types; The number of errors corresponding to different bit distribution types is determined as the binary bit feature information corresponding to each memory module.

8. The method for determining a memory replacement strategy according to any one of claims 1 to 7, wherein generating a memory replacement strategy corresponding to all memory modules in the electronic device based on the spatiotemporal distribution feature information corresponding to each memory module and the cumulative read / write data volume includes: Based on the spatiotemporal distribution characteristic information corresponding to each memory module, the first evaluation factor for the occurrence of correctable errors is determined. Based on the cumulative read / write data volume corresponding to each memory module and the total number of accesses to the memory modules in the electronic device, a second evaluation factor for the occurrence of correctable errors is determined. The memory replacement strategy is generated based on the first evaluation factor and the second evaluation factor corresponding to each memory module.

9. The method for determining a memory replacement strategy according to any one of claims 1 to 7, wherein after generating the memory replacement strategy corresponding to all memory modules in the electronic device, the method further comprises: Based on the memory replacement strategy, a replacement instruction corresponding to the memory module to be replaced is generated; Output the replacement instruction corresponding to the memory module to be replaced, so that memory replacement can be performed based on the replacement instruction.

10. An electronic device, the electronic device comprising: Memory, configured to store computer programs that can run on a processor; When a processor is configured to execute the computer program, it performs the following steps: acquiring memory error logs and read / write behavior data corresponding to each memory module within the electronic device; The read / write behavior data includes: current data storage volume, cumulative read / write data volume, and multiple system available bandwidths collected at preset intervals within a preset time period; based on the current data storage volume and the multiple system available bandwidths corresponding to each memory module, the corresponding migration duration is determined; based on the migration duration corresponding to each memory module, the spatiotemporal distribution feature information of correctable errors is extracted from the corresponding memory error log; based on the spatiotemporal distribution feature information and the cumulative read / write data volume corresponding to each memory module, a memory replacement strategy corresponding to all memory modules in the electronic device is generated.

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