Signal verification method, circuit and memory

Abstract

The invention relates to the field of integrated circuits, and discloses a signal verification method and circuit and a memory. The signal verification method comprises the following steps: encoding a to-be-verified signal to obtain an encoding command; pipelined parity check is carried out on the coding command, and parity check delay is met; and decoding the coding command to obtain a to-be-verified signal.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and specifically to a signal verification method, circuit, and memory. Background Technology

[0002] DRAM (Dynamic Random Access Memory) is a type of semiconductor memory. Its main working principle is to use the charge in the storage cell to represent the stored data, that is, to represent whether a binary bit is 1 or 0.

[0003] DDR (Double Data Rate Synchronous Dynamic Random Access Memory) is DRAM with twice the data transfer rate, meaning its data transfer speed is twice the system clock frequency. Due to this increased speed, its transfer performance is superior to traditional DRAM. DDR supports two data verification methods: parity check and cyclic redundancy check (CRC). Parity check is one of the simplest verification methods, using only one bit as its checksum.

[0004] Parity checking verifies the parity of the total number of "1"s in both the data code and the check code to determine if the data code is correct. The working principle of parity checking is as follows: if an error occurs during transmission or storage, such as a bit or multiple bit flips, the previously maintained parity will be disrupted. Therefore, by counting the number of "1"s in the received data at the receiving end and comparing it with the expected parity, the occurrence of an error can be detected. If the counted number of "1"s does not match the expected number, that is, the actual number is inconsistent with the expected number, then it can be determined that an error occurred during transmission or storage.

[0005] DDR employs pipelined parity checking, while also needing to meet parity check delay specifications. However, the pipeline circuitry used for parity checking in existing technologies still has room for further optimization. Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a signal verification circuit and a memory that can reduce the number of data bits that need to be verified and reduce the number of storage elements in the parity check pipeline.

[0007] The technical solution of this disclosure embodiment is implemented as follows:

[0008] This disclosure provides a signal verification method, which includes: encoding a signal to be verified to obtain an encoding command; performing pipelined parity checking on the encoding command to satisfy parity check delay; and decoding the encoding command to obtain the signal to be verified.

[0009] In some embodiments of this disclosure, the pipelined parity check of the encoded command includes: registering each bit of data in the encoded command separately; and performing pipelined parity check on the encoded command based on the parity check delay.

[0010] In some embodiments of this disclosure, the signal to be verified includes: a command address signal; the parity check delay corresponding to the command address signal is stored in the mode register MR5.

[0011] In some embodiments of this disclosure, the number of data bits for the encoded command is n; n is greater than or equal to 1; and the sum of the number of data bits for the signal to be verified is greater than 2. n-1 and less than or equal to 2 n .

[0012] This disclosure also provides a signal verification circuit, comprising: a command encoder configured to encode a signal to be verified to obtain an encoded command; a parity check pipeline coupled to the command encoder configured to perform pipelined parity check on the encoded command to satisfy parity check delay; and a command decoder coupled to the parity check pipeline configured to decode the encoded command to obtain the signal to be verified.

[0013] In some embodiments of this disclosure, the parity check pipeline is further configured to register each bit of data in the encoding command separately; and to perform pipelined parity check on the encoding command based on the parity check delay.

[0014] In some embodiments of this disclosure, the number of storage elements in the parity pipeline is determined based on the number of data bits of the encoded command and the parity delay.

[0015] In some embodiments of this disclosure, the signal to be verified includes: a command address signal; the parity check delay corresponding to the command address signal is stored in the mode register MR5.

[0016] In some embodiments of this disclosure, the number of data bits for the encoded command is n; n is greater than or equal to 1; and the sum of the number of data bits for the signal to be verified is greater than 2. n-1 and less than or equal to 2 n .

[0017] This disclosure also provides a memory, which includes the signal verification circuit described in the above-described scheme.

[0018] In some embodiments of this disclosure, the memory includes at least dynamic random access memory (DRAM).

[0019] It is understandable that by first encoding the parity signal to obtain the encoded command, and then performing pipelined parity checking on the encoded command, the number of data bits that need to be checked is reduced, thereby effectively reducing the number of storage elements in the parity checking pipeline. This, in turn, reduces the circuit area and facilitates the miniaturization of the chip area. Attached Figure Description

[0020] Figure 1 Schematic diagram of the memory structure provided in the embodiments of this disclosure Figure 1 ;

[0021] Figure 2 This is a schematic diagram of the structure of a signal verification circuit in the prior art;

[0022] Figure 3 Schematic diagram of the implementation process of the signal verification method provided in the embodiments of this disclosure Figure 1 ;

[0023] Figure 4 Schematic diagram of the implementation process of the signal verification method provided in the embodiments of this disclosure Figure 2 ;

[0024] Figure 5 A schematic diagram of the signal verification circuit provided in the embodiments of this disclosure. Figure 1 ;

[0025] Figure 6 A schematic diagram of the signal verification circuit provided in the embodiments of this disclosure. Figure 2 ;

[0026] Figure 7 Schematic diagram of the memory structure provided in the embodiments of this disclosure Figure 2 . Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0028] In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict. The terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this disclosure.

[0030] Figure 1 This is a schematic diagram of the memory structure in an embodiment of this disclosure. (Reference) Figure 1 The host can be configured to send data to or receive data from the memory 20, wherein the host can be a processor of an electronic device, such as a central processing unit (CPU) or a graphics processing unit (GPU). The controller 10 is coupled to the memory 20 and the host and is configured to control the memory 20. The controller 10 can manage the data stored in the memory 20 and communicate with the host.

[0031] Controller 10 can be configured to control operations of memory 20, such as read, erase, write, and refresh operations. In some embodiments, controller 10 is also configured to process error correction codes (ECCs) regarding data read from or written to memory 20. Controller 10 can also perform any other suitable functions, such as formatting memory 20.

[0032] In some embodiments of this disclosure, reference is made to Figure 1 The controller 10 and one or more memories 20 can be integrated into various types of electronic devices. For example, the controller 10 can be integrated into the northbridge of a computer motherboard or directly into the computer CPU, and multiple memories 20 can be integrated into a memory module. In other words, the memory system 30 can be implemented and packaged into different types of terminal electronic products.

[0033] Controller 10 can send data to / receive data from the host (HOST) and can send commands (CMD) and addresses (ADDR) to memory 20. Controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. Host interface 140 can receive commands (CMD) and addresses (ADDR) from the host (HOST). Command generator 110 can generate access commands, row hammer refresh commands, etc., by decoding the commands (CMD) received from the host (HOST), and can provide access commands and row hammer refresh commands to memory 20 through device interface 130. An access command may be a signal instructing memory 20 to write or read data by accessing a row of the memory cell array 220 corresponding to address ADDR. A row hammer refresh command may be a signal instructing memory 20 to perform an additional refresh operation on word lines adjacent to word lines that are frequently accessed in a short period. In other words, an additional refresh operation can be performed on word lines adjacent to word lines that are accessed multiple times in a short period.

[0034] The address generator 120 in the controller 10 can generate the row and column addresses to be accessed in the memory cell array 220 by decoding the address ADDR received from the host interface 140. Furthermore, the memory 20 can generate addresses of the memory banks to be accessed when the memory cell array 220 comprises multiple banks.

[0035] Furthermore, the controller 10 can control memory operations such as writing and reading by providing various signals to the memory 20 via the device interface 130. For example, the controller 10 can provide a write command to the memory 20. The write command is used to instruct the memory 20 to perform a write operation to store data in the memory 20.

[0036] In some embodiments of this disclosure, reference is made to Figure 1The memory 20 includes a memory cell array 220 and peripheral circuitry 210. The memory cell array 220 includes multiple banks, each bank includes multiple blocks, each block includes multiple rows and columns of memory cells, each row is coupled to a corresponding word line, and each column is coupled to a corresponding bit line. The peripheral circuitry 210 can write data DATA to or read data DATA from the memory cell array 220 and send it to the controller 10 based on commands CMD and addresses ADDR received from the controller 10. Alternatively, it can provide control signals CTRL to the row decoding and column decoding circuits to refresh the memory cells included in the memory cell array 220. In other words, the peripheral circuitry 210 can perform all operations to process the data in the memory cell array 220. The peripheral circuit 210 may include: control circuits corresponding to each memory block, such as sensing amplifier (SA) circuits and word-line driver (WLD) circuits; control circuits corresponding to each memory bank, such as row decoding circuits and column decoding circuits; and control circuits corresponding to all memory banks, such as command buffers, command decoders, address buffers, data input / output buffers, and mode registers.

[0037] It should be noted that pipeline technology refers to a quasi-parallel processing technique in which multiple instructions overlap during program execution. For example, a command processing pipeline consists of n circuit units; then, the processing of a single command is divided into n steps, which are executed separately by the n circuit units; in this way, the processing of a single command can be completed in one clock cycle, thus improving processing speed.

[0038] It should also be noted that the command address signal C / A is transmitted from the controller to the DDR internally. Before the command address signal C / A is executed internally by the DDR, it must be ensured that there are no parity errors in the command address signal C / A. Therefore, the JEDEC standard defines the specification for the C / A parity mode. In C / A parity mode, all upcoming commands need to be latched and pipelined within the parity delay time before internal execution. This C / A parity mode can cover ACT_n, RAS_n / A16, CAS_n / A15, WE_n / A14, the address bus including the memory bank address and memory bank group bits, and C0-C2 on 3DS devices.

[0039] refer to Figure 2In existing technologies, parity checking is directly pipelined onto the signal to be checked. That is, the parity checking pipeline latches and pipelines all upcoming commands and addresses to complete the parity check for the current command. For example, in DDR4, the command address signal C / A has 23 possible commands that require parity checking. Simultaneously, the parity check of the command address signal C / A needs to meet an 8nCK parity check latency to support all speed bins, including RFU (reserved for future use). Therefore, up to approximately 180 memory elements (including latches or flip-flops) are required, and these memory elements are pipelined to maintain the parity check latency specification.

[0040] Figure 3 This is a schematic diagram illustrating the implementation flow of a signal verification method provided in an embodiment of this disclosure, as shown below. Figure 3 As shown, the method includes steps S101 to S103.

[0041] S101. Encode the signal to be verified to obtain the encoding command.

[0042] In this embodiment of the disclosure, before performing pipelined parity checking, the signals to be checked can be encoded to obtain an encoding command. The number of data bits in the encoding command is less than the sum of the number of data bits in the signals to be checked. If each signal to be checked consists of only a single data bit, then the sum of the number of data bits in the signals to be checked is equal to the number of signals to be checked. For example, m single-data-bit signals to be checked can be encoded to obtain an n-bit encoding command, where n is less than m.

[0043] S102. Perform pipelined parity checking on the encoded commands to meet the parity check delay.

[0044] It should be noted that parity latency (PL) is a configuration parameter in DDR memory that represents the delay time when performing parity checks.

[0045] In some embodiments of this disclosure, the signal to be verified includes a command address signal (Command / Address, C / A). The parity check delay corresponding to the command address signal C / A is stored in the mode register MR5.

[0046] In other words, the parity check delay corresponding to the command address signal is controlled by a specific bit in the mode register MR5. Specifically, DDR controls whether parity check is enabled and its delay time by configuring the parity check delay in the mode register MR5. If bits A[2:0] of the mode register MR5 are set to 000, then parity check is not performed on the command or address, which can also be understood as a delay time of 0, i.e., no delay. If bits A[2:0] are set to a value other than 000, then parity check will be performed on the command address signal C / A, and the corresponding delay time will be set according to the value of A[2:0].

[0047] It should be noted that the specific configuration and effect of DDR parity delay may vary depending on the DDR version and manufacturer. Therefore, in practical applications, it is advisable to refer to the specific DDR datasheet or technical specification for accurate information; no restrictions are imposed here.

[0048] In this embodiment, the depth of the parity check pipeline depends on the parity check delay PL. That is, the number of storage elements in the parity check pipeline needs to match the parity check delay PL. Simultaneously, the number of storage elements in the parity check pipeline also depends on the number of data bits in the encoded command. For example, if the number of data bits in the encoded command is 5 and the parity check delay PL is 8nCK, then the parity check pipeline needs to include 5 * 8nCK = 40 storage elements (including latches or triggers). These storage elements are pipelined to maintain the parity check delay specification.

[0049] S103. Decode the encoded command to obtain the signal to be verified.

[0050] In this embodiment of the disclosure, after parity checking is performed on the encoded command, the encoded command can be decoded to obtain the signal to be checked again. Decoding is the reverse process of encoding.

[0051] It's understandable that by first encoding the parity signal to obtain the encoded command, and then performing pipelined parity checking on the encoded command, the number of data bits requiring verification is reduced, thereby effectively reducing the number of storage elements in the parity checking pipeline. For example, encoding 23 commands into a 5-bit encoded command reduces the number of storage elements in the parity checking pipeline from over 180 to 40, a reduction of nearly 80%. This reduces the circuit area and facilitates chip size reduction.

[0052] In some embodiments of this disclosure, it is possible to... Figure 4 The steps S201 to S202 shown are used to achieve the following: Figure 3Step S102 is shown. Each step will be explained in detail.

[0053] S201. Register each bit of data in the encoding command separately.

[0054] In this embodiment of the disclosure, the parity check pipeline registers each bit of data in the encoding command separately. Therefore, the number of storage elements in the parity check pipeline depends on the number of bits of data in the encoding command.

[0055] S202. Based on parity check delay, perform pipelined parity check on the encoded command.

[0056] In this embodiment of the disclosure, the parity check pipeline needs to meet the parity check delay requirement. Therefore, the depth of the parity check pipeline depends on the parity check delay. In other words, the number of memory elements in the parity check pipeline also depends on the parity check delay.

[0057] Understandably, after encoding the signal to be checked into an encoding command, each bit of the encoding command is then stored separately to complete the pipelined parity check and satisfy the parity check delay. Since the number of bits in the encoding command is less than the sum of the number of bits in the signal to be checked, the number of storage elements in the parity check pipeline can be reduced. This reduces the circuit area and facilitates chip size reduction.

[0058] In some embodiments of this disclosure, the number of data bits for the encoded command is n; n is greater than or equal to 1. The sum of the number of data bits for the signal to be verified is greater than 2. n-1 and less than or equal to 2 n .

[0059] For example, if the sum of the number of data bits in the signal to be checked is greater than 16 and less than or equal to 32, that is, the sum of the number of data bits in the signal to be checked is between 17 and 32, then the encoded command will have 5 data bits. In other words, for the command address signal C / A, there are 23 possible commands that need to be parity checked, and each of these 23 commands consists of only a single data bit. Therefore, after encoding these 23 commands, a 5-bit encoded command can be obtained.

[0060] Figure 5 This is a schematic diagram of an optional structure of the signal verification circuit provided in an embodiment of this disclosure. For example... Figure 5 As shown, the signal verification circuit includes: a command encoder 30, a parity check pipeline 40, and a command decoder 50.

[0061] The command encoder 30 is configured to encode the signal to be checked to obtain an encoded command. The parity check pipeline 40, coupled to the command encoder 30, is configured to perform pipelined parity checks on the encoded command, satisfying the parity check delay. The command decoder 50, coupled to the parity check pipeline 40, is configured to decode the encoded command to obtain the signal to be checked.

[0062] In this embodiment of the disclosure, the number of data bits in the encoded command is less than the sum of the number of data bits in the signals to be verified; if each signal to be verified consists of only a single data bit, then the sum of the number of data bits in the signals to be verified is equal to the number of signals to be verified. For example, m single data bits of signals to be verified can be encoded into an n-bit encoded command, where n is less than m.

[0063] Understandably, the command encoder 30 first encodes the signal to be checked to obtain the encoded command, and then the parity check pipeline 40 performs pipelined parity checks on the encoded command. This reduces the number of data bits that need to be checked, thereby effectively reducing the number of storage elements (including latches or flip-flops) in the parity check pipeline 40. This, in turn, reduces the circuit area and contributes to the reduction of chip area.

[0064] In some embodiments of this disclosure, the parity pipeline 40 is further configured to register each bit of data in the encoding command separately; and to perform pipelined parity checking on the encoding command based on the parity check delay.

[0065] In this embodiment of the disclosure, the number of storage elements in the parity check pipeline is determined based on the number of data bits in the encoded command and the parity check delay. The depth of the parity check pipeline depends on the parity check delay.

[0066] Understandably, after the command encoder 30 encodes the signal to be checked into an encoding command, the parity check pipeline 40 then registers each bit of data in the encoding command separately to complete the pipelined parity check and meet the parity check delay requirements. Since the number of data bits in the encoding command is less than the sum of the number of data bits in the signal to be checked, the number of storage elements in the parity check pipeline 40 can be reduced. This reduces the circuit area and facilitates chip area reduction.

[0067] In some embodiments of this disclosure, the signal to be verified includes a command address signal C / A. The parity check delay corresponding to the command address signal C / A is stored in the mode register MR5. That is, the parity check delay corresponding to the command address signal is controlled by a specific position in the mode register MR5.

[0068] In some embodiments of this disclosure, the number of data bits for the encoded command is n; n is greater than or equal to 1. The sum of the number of data bits for the signal to be verified is greater than 2. n-1 and less than or equal to 2 n For example, if the sum of the number of data bits of the signal to be verified is greater than 16 and less than or equal to 32, that is, the sum of the number of data bits of the signal to be verified is between 17 and 32, then the number of data bits of the encoded command is 5.

[0069] In this embodiment of the disclosure, reference is made to Figure 6 For the command address signal C / A, the signal to be verified includes 23 possible commands, and each of these 23 commands only includes a single data bit. Therefore, after encoding these 23 commands, a 5-bit encoded command can be obtained.

[0070] In this embodiment of the disclosure, the depth of the parity check pipeline depends on the parity check delay PL; that is, the number of storage elements in the parity check pipeline needs to match the parity check delay PL. Simultaneously, the number of storage elements in the parity check pipeline also depends on the number of data bits in the encoded command. Therefore, continuing to refer to... Figure 6 The 23 commands of the command address signal C / A are encoded to obtain a 5-bit encoded command. At the same time, the parity check delay PL is 8nCK. Therefore, the parity check pipeline needs to set 5*8nCK=40 storage elements (including latches or flip-flops).

[0071] It is understood that, compared with the prior art, in this embodiment of the disclosure, the number of storage elements in the parity check pipeline of the command address signal C / A can be significantly reduced from more than 180 to 40, that is, the number of storage elements can be reduced by nearly 80%.

[0072] This disclosure also provides a memory, such as... Figure 7 As shown, the memory 70 includes a signal verification circuit 60, wherein the signal verification circuit 60 includes the technical features described in the foregoing embodiments; the signal verification circuit 60 may be disposed in the peripheral circuit of the memory 70.

[0073] In some embodiments of this disclosure, reference is made to Figure 7 The memory 70 includes at least dynamic random access memory (DRAM). The DRAM may be double data rate synchronous dynamic random access memory (DDR).

[0074] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0075] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0076] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A signal verification method, characterized in that, The signal verification method includes: The signal to be verified is encoded to obtain the encoding command; The encoded command is subjected to pipelined parity checking to satisfy the parity check delay. The encoded command is decoded to obtain the signal to be verified.

2. The signal verification method according to claim 1, characterized in that, Performing the pipelined parity check on the encoded command includes: Each bit of data in the encoding command is stored separately; Based on the parity check delay, the encoded command is subjected to pipelined parity check.

3. The signal verification method according to claim 1, characterized in that, The signal to be verified includes: a command address signal; The parity check delay corresponding to the command address signal is stored in the mode register MR5.

4. The signal verification method according to claim 1, characterized in that, The number of data bits in the encoded command is n; n is greater than or equal to 1. The sum of the number of data bits in the signal to be verified is greater than 2. n-1 and less than or equal to 2 n .

5. A signal verification circuit, characterized in that, The signal verification circuit includes: The command encoder is configured to encode the signal to be verified to obtain the encoded command; A parity check pipeline, coupled to the command encoder, is configured to perform pipelined parity checks on the encoded command, satisfying the parity check delay. The command decoder, coupled to the parity check pipeline, is configured to decode the encoded command to obtain the signal to be checked.

6. The signal verification circuit according to claim 5, characterized in that, The parity check pipeline is further configured to store each bit of data in the encoding command separately; and to perform pipelined parity check on the encoding command based on the parity check delay.

7. The signal verification circuit according to claim 5, characterized in that, The number of storage elements in the parity pipeline is determined based on the number of data bits in the encoding command and the parity delay.

8. The signal verification circuit according to claim 5, characterized in that, The signal to be verified includes: a command address signal; The parity check delay corresponding to the command address signal is stored in the mode register MR5.

9. The signal verification circuit according to claim 5, characterized in that, The number of data bits in the encoded command is n; n is greater than or equal to 1. The sum of the number of data bits in the signal to be verified is greater than 2. n-1 and less than or equal to 2 n .

10. A memory, characterized in that, The memory includes the signal verification circuit as described in any one of claims 5 to 9.

11. The memory according to claim 10, characterized in that, The memory includes at least dynamic random access memory (DRAM).

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