Double-CPU arbitration reset system and control method thereof

Abstract

The invention relates to the technical field of CPU arbitration reset, in particular to a double-CPU arbitration reset system and a control method thereof, by arranging a first controlled power supply and a second controlled power supply which are mutually independent and respectively supply power to a first CPU and a second CPU, independent control of power supply of the two CPUs is ensured, and mutual interference during reset operation is avoided; the second CPU controls the first controlled power supply through the first power supply control circuit, and the first CPU controls the second controlled power supply through the second power supply control circuit, so that the normal CPU accurately controls the faulted CPU power supply; the two-way heartbeat communication link between the first CPU and the second CPU can reliably and mutually monitor the running state in real time, so that a direct basis is provided for fault judgment; according to the whole architecture, through cooperation of all the modules, effective arbitration and reset triggering are achieved when the double-CPU system breaks down, and the reliability and independence of system fault recovery are improved.

Description

Technical Field

[0001] This invention relates to the field of CPU arbitration and reset technology, and in particular to a dual-CPU arbitration and reset system and its control method. Background Technology

[0002] In electronic systems with high reliability requirements, dual-CPU (or dual-core) architectures are widely used to ensure stable system operation through redundant design and mutual monitoring. When one CPU "crashes" due to program errors, hardware malfunctions, or other reasons, the normally functioning CPU must promptly reset the faulty CPU to quickly restore the overall system functionality.

[0003] Traditional reset methods primarily rely on watchdog circuits or directly controlling the reset pin of a faulty CPU. However, these methods have significant drawbacks: the watchdog circuit itself may fail due to hardware malfunction, failing to reliably send a reset signal; and the "soft reset" method, which directly controls the reset pin, struggles to completely clear abnormal latched states in the CPU's internal registers and some peripherals, potentially leaving the system in an abnormal operating state after reset, thus failing to meet the stringent fault recovery requirements of high-reliability systems. Therefore, a dual-CPU arbitration reset scheme with more thorough reset and more reliable control is urgently needed. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a dual-CPU arbitration and reset system that realizes effective arbitration and reset triggering in the event of a dual-CPU system failure, thereby improving the reliability and independence of system fault recovery.

[0005] To solve the above-mentioned technical problems, the first technical solution adopted by the present invention is as follows:

[0006] A dual-CPU arbitration reset system includes a first controlled power supply, a second controlled power supply, a first CPU, a second CPU, a first power supply control circuit, and a second power supply control circuit. The input terminals of both the first and second controlled power supplies are connected to the external main power supply. The output terminal of the first controlled power supply is connected to the power supply terminal of the first CPU, and the power enable terminal of the first controlled power supply is connected to the general-purpose input / output terminal of the second CPU through the second power control circuit. The output terminal of the second controlled power supply is connected to the power supply terminal of the second CPU, and the power enable terminal of the second controlled power supply is connected to the general-purpose input / output terminal of the first CPU through the first power control circuit. A two-way heartbeat communication link is provided between the first CPU and the second CPU for mutual monitoring of their operating status.

[0007] The second technical solution adopted in this invention is: A control method for the above-mentioned dual-CPU arbitration reset system includes the following steps: S1. Control the general-purpose input / output terminals of the first CPU to be initialized to a high-impedance state, and control the general-purpose input / output terminals of the second CPU to be initialized to a high-impedance state; S2. The first CPU and the second CPU monitor each other's operating status through a two-way heartbeat communication link; If the first CPU determines that the second CPU has malfunctioned, the first CPU performs a first reset arbitration operation on the second controlled power supply through the first power control circuit. If the second CPU determines that the first CPU has malfunctioned, the second CPU performs a second reset arbitration operation on the first controlled power supply through the second power control circuit.

[0008] The beneficial effects of this invention are as follows: This system ensures independent control of the power supply to the two CPUs by setting up a first controlled power supply and a second controlled power supply that supply power to the first CPU and the second CPU respectively, thus avoiding mutual interference during reset operations. The first power supply control circuit and the second power supply control circuit form a cross-control architecture, allowing the second CPU to control the first controlled power supply through the first power supply control circuit, and the first CPU to control the second controlled power supply through the second power supply control circuit, achieving precise control of the power supply of the faulty CPU by the normal CPU. The bidirectional heartbeat communication link between the first CPU and the second CPU can monitor each other's operating status in real time and reliably, providing direct evidence for fault diagnosis. Through the coordinated cooperation of various modules, the overall architecture achieves effective arbitration and reset triggering in the event of a dual-CPU system failure, improving the reliability and independence of system fault recovery. Attached Figure Description

[0009] Figure 1 This is a connection block diagram of the dual-CPU arbitration reset system of the present invention; Figure 2 This is a schematic diagram of the dual-CPU arbitration reset system of the present invention; Figure 3 This is a flowchart of the control method of the dual-CPU arbitration reset system of the present invention; Label Explanation: 1. First controlled power supply; 2. Second controlled power supply; 3. First CPU; 4. Second CPU; 5. First power supply control circuit; 6. Second power supply control circuit. Detailed Implementation

[0010] To explain in detail the technical content, objectives, and effects of the present invention, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0011] Please refer to Figure 1 The first technical solution adopted in this invention is: A dual-CPU arbitration reset system includes a first controlled power supply 1, a second controlled power supply 2, a first CPU 3, a second CPU 4, a first power control circuit 5, and a second power control circuit 6. The input terminals of the first controlled power supply 1 and the second controlled power supply 2 are both connected to the external main power supply. The output terminal of the first controlled power supply 1 is connected to the power supply terminal of the first CPU 3, and the power enable terminal of the first controlled power supply 1 is connected to the general-purpose input / output terminal of the second CPU 4 through the second power control circuit 6. The output terminal of the second controlled power supply 2 is connected to the power supply terminal of the second CPU 4, and the power enable terminal of the second controlled power supply 2 is connected to the general-purpose input / output terminal of the first CPU 3 through the first power control circuit 5. The first CPU3 and the second CPU4 are provided with a bidirectional heartbeat communication link for mutual monitoring of their operating status.

[0012] As can be seen from the above description, the beneficial effects of the present invention are as follows: This system ensures independent control of the power supply to the two CPUs by setting up a first controlled power supply module 1 and a second controlled power supply module 2, which are independent of each other and supply power to the first CPU3 and the second CPU4 respectively, thus avoiding mutual interference during reset operations. The first power control circuit 5 and the second power control circuit 6 form a cross-control architecture, allowing the second CPU4 to control the first controlled power supply module 1 through the first power control circuit 5, and the first CPU3 to control the second controlled power supply module 2 through the second power control circuit 6, realizing precise control of the power supply of the faulty CPU by the normal CPU. The bidirectional heartbeat communication link between the first CPU3 and the second CPU4 can monitor each other's operating status in real time and reliably, providing direct evidence for fault diagnosis. Through the coordinated cooperation of each module, the overall architecture realizes effective arbitration and reset triggering in the event of a dual-CPU system failure, improving the reliability and independence of system fault recovery.

[0013] For further details, please refer to Figure 2 The first power control circuit 5 includes a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to the general-purpose input / output terminal of the first CPU 3, and the other end of the resistor R1 is connected to one end of the capacitor C1 and the power enable terminal of the second controlled power supply 2. The other end of the capacitor C1 is grounded.

[0014] As can be seen from the above description, resistor R1 and capacitor C1 constitute an RC delay circuit, which realizes the buffering and delay of the control signal, avoiding power supply malfunction caused by sudden changes in control level; the energy storage characteristics of capacitor C1 can maintain the stability of the enable terminal voltage of the second controlled power supply 2, ensuring that the controlled power supply remains in the off state within the preset time, and ensuring that the faulty CPU is completely de-energized.

[0015] For further details, please refer to Figure 2 The first power control circuit 5 further includes a resistor R2, one end of which is connected to the power enable terminal of the second controlled power supply 2, one end of the capacitor C1 and the other end of the resistor R1, and the other end of the resistor R2 is grounded.

[0016] As described above, resistor R2 and capacitor C1 form an RC discharge circuit. When the general-purpose input / output terminal of the first CPU3 returns to a high-impedance state, it can accelerate the voltage drop at the enable terminal of the second controlled power supply 2, ensuring a rapid power restart. By adjusting the resistance value of resistor R2, the discharge rate of the power supply enable terminal can be flexibly adjusted to adapt to the turn-on threshold requirements of different power chips. R2 acts as a voltage divider, which can prevent the enable terminal voltage of the second controlled power supply 2 from being too high and damaging the device, thus improving the safety of the circuit operation.

[0017] For further details, please refer to Figure 2 The first power control circuit 5 further includes a diode D1. The anode of the diode D1 is connected to the general-purpose input / output terminal of the first CPU 3 through a resistor R1. The cathode of the diode D1 is connected to one end of the capacitor C1 and the power enable terminal of the second controlled power supply 2.

[0018] As can be seen from the above description, diode D1 has unidirectional conductivity, which can effectively prevent current from flowing back into the general-purpose input / output terminal of the first CPU3 when the second controlled power supply 2 is turned off, thus avoiding damage to the port of the first CPU3; diode D1 can isolate the first power control circuit 5 from the general-purpose input / output terminal of the first CPU3, reduce the interference of voltage fluctuations in the circuit on the normal operation of the first CPU3, and improve system stability; it can also protect the first CPU3 from surge voltage impacts on the power supply side, extending the CPU's service life.

[0019] For further details, please refer to Figure 2 The second power control circuit 6 includes a resistor R3 and a capacitor C2. One end of the resistor R3 is connected to the general-purpose input / output terminal of the second CPU 4, and the other end of the resistor R3 is connected to one end of the capacitor C2 and the power enable terminal of the first controlled power supply 1. The other end of the capacitor C2 is grounded.

[0020] As can be seen from the above description, resistor R3 and capacitor C2 constitute an RC delay circuit, which realizes the buffering and delay of the control signal, avoiding power supply malfunction caused by sudden changes in control level; the energy storage characteristics of capacitor C2 can maintain the stability of the enable terminal voltage of the second controlled power supply 2, ensuring that the controlled power supply remains in the off state within the preset time, and ensuring that the faulty CPU is completely de-energized.

[0021] For further details, please refer to Figure 2 The second power control circuit 6 further includes a resistor R4, one end of which is connected to the power enable terminal of the first controlled power supply 1, one end of the capacitor C2 and the other end of the resistor R3, and the other end of the resistor R4 is grounded.

[0022] As described above, resistor R4 and capacitor C2 form an RC discharge circuit. When the general-purpose input / output terminal of the second CPU4 returns to a high-impedance state, it can accelerate the voltage drop at the enable terminal of the first controlled power supply 1, ensuring a fast power restart. By adjusting the resistance value of resistor R4, the discharge rate of the power enable terminal can be flexibly adjusted to adapt to the turn-on threshold requirements of different power chips. R4 acts as a voltage divider, which can prevent the enable terminal voltage of the first controlled power supply 1 from being too high and damaging the device, thus improving the safety of the circuit operation.

[0023] For further details, please refer to Figure 2 The second power control circuit 6 also includes a diode D2. The anode of the diode D2 is connected to the general-purpose input / output terminal of the second CPU 4 through a resistor R3. The cathode of the diode D2 is connected to one end of the capacitor C2 and the power enable terminal of the first controlled power supply 1, respectively.

[0024] As described above, diode D2 has unidirectional conductivity, which can effectively prevent current from flowing back into the general-purpose input / output terminal of the second CPU4 when the first controlled power supply 1 is turned off, thus avoiding damage to the port of the second CPU4; diode D2 can isolate the second power supply control circuit 6 from the general-purpose input / output terminal of the second CPU4, reduce the interference of voltage fluctuations in the circuit on the normal operation of the second CPU4, and improve system stability; it can also protect the second CPU4 from surge voltage impacts on the power supply side, extending the CPU's service life.

[0025] The second technical solution adopted in this invention is: Please refer to Figure 3 A control method based on the above-mentioned dual-CPU arbitration reset system includes the following steps: S1. Control the general-purpose input / output terminals of the first CPU3 to be initialized to a high-impedance state, and control the general-purpose input / output terminals of the second CPU4 to be initialized to a high-impedance state; S2. The first CPU3 and the second CPU4 monitor each other's operating status through a two-way heartbeat communication link; If the first CPU3 determines that the second CPU4 has malfunctioned, the first CPU3 performs a first reset arbitration operation on the second controlled power supply 2 through the first power control circuit 5. If the second CPU4 determines that the first CPU3 has failed, the second CPU4 performs a second reset arbitration operation on the first controlled power supply 1 through the second power control circuit 6.

[0026] As can be seen from the above description, the beneficial effects of the present invention are as follows: In the status monitoring step, the first CPU3 and the second CPU4 periodically confirm each other's operating status through a heartbeat communication link, ensuring the real-time and continuous monitoring of their respective operating statuses. This provides an accurate and reliable basis for subsequent fault determination, avoiding missed or false faults. The fault determination step uses the failure to receive a valid status confirmation within a preset heartbeat timeout period as the fault determination criterion, making the fault identification logic clear and quantifiable, ensuring that subsequent operations are only triggered when the other party actually exhibits an anomaly. In the power arbitration step, the general-purpose input / output terminals of the control CPU are switched from a high-impedance state to an output shutdown effective level and maintained for a predetermined shutdown delay. This operation directly acts on the corresponding controlled power module, forcing the faulty CPU to shut down. The system achieves a complete hardware-level reset, effectively solving the problem that traditional soft resets cannot clear deeply abnormal latched states. Simultaneously, the pre-set shutdown delay ensures the faulty CPU is completely powered off, guaranteeing the reset effect. In the state recovery step, the control unit restores the general-purpose input / output terminals of the CPU to a high-impedance state, restarting the controlled power module. This allows the faulty CPU to complete the reset, power on, and quickly return to the system. The entire process forms a closed-loop control, ensuring both the thoroughness and reliability of the reset and automating fault recovery without manual intervention. Furthermore, the logical connections between each step are tight, making operation simple and controllable. It is compatible with dual-CPU cross-control system architectures, significantly improving the fault recovery capability and overall operational stability of dual-CPU systems.

[0027] Furthermore, in step S2, the first CPU3 performs a first reset arbitration operation on the second controlled power supply 2 through the first power control circuit 5, specifically including: The general-purpose input / output terminal of the first CPU3 is controlled to switch from high impedance to output mode, and a first control level is output. The first control level is transmitted to the power enable terminal of the second controlled power supply 2 through the first power control circuit 5, and the voltage of the power enable terminal of the second controlled power supply 2 is increased to above the shutdown threshold of the second controlled power supply 2. After maintaining the first control level at the general-purpose input / output terminal of the first CPU3 for a preset duration, the general-purpose input / output terminal of the first CPU3 is restored to a high-impedance state, and the voltage at the power enable terminal of the second controlled power supply 2 is reduced to below the turn-on threshold of the second controlled power supply 2.

[0028] As can be seen from the above description, the switching logic of the control level is clearly defined to ensure that the second controlled power supply 2 is reliably shut down, so that the faulty CPU is completely de-energized; the preset duration setting ensures that the residual charge in the internal circuit of the faulty CPU is fully released, ensuring a thorough reset; the design of restoring the high impedance state allows the system to return to the initial monitoring state, and the status monitoring of the reset CPU can continue, forming a closed-loop control.

[0029] Furthermore, in step S2, the second CPU4 performs a second reset arbitration operation on the first controlled power supply 1 through the second power control circuit 6, specifically including: The general-purpose input / output terminal of the second CPU4 is controlled to switch from high impedance to output mode, and a second control level is output. The second control level is transmitted to the power enable terminal of the first controlled power supply 1 through the second power control circuit 6, and the voltage of the power enable terminal of the first controlled power supply 1 is increased to above the shutdown threshold of the first controlled power supply 1. After maintaining the second control level at the general-purpose input / output terminal of the second CPU4 for a preset duration, the general-purpose input / output terminal of the second CPU4 is restored to a high-impedance state, and the voltage at the power enable terminal of the first controlled power supply 1 is reduced to below the turn-on threshold of the first controlled power supply 1.

[0030] As can be seen from the above description, the above steps can ensure that the first controlled power supply 1 is reliably shut down, and achieve a complete power-off reset of the first CPU 3; the preset duration setting is adapted to the circuit characteristics of the first CPU 3 to ensure the reset effect; after restoring the high impedance state, the working status of the first CPU 3 can continue to be monitored to ensure the continuous and stable operation of the system.

[0031] Please refer to Figure 1 and Figure 2 As shown, Embodiment 1 of the present invention is as follows: Please refer to Figure 1 A dual-CPU arbitration reset system includes a first controlled power supply 1, a second controlled power supply 2, a first CPU 3, a second CPU 4, a first power control circuit 5, and a second power control circuit 6. The input terminals of the first controlled power supply 1 and the second controlled power supply 2 are both connected to the external main power supply. The output terminal of the first controlled power supply 1 is connected to the power supply terminal of the first CPU 3, and the power enable terminal of the first controlled power supply 1 is connected to the general-purpose input / output terminal of the second CPU 4 through the second power control circuit 6. The output terminal of the second controlled power supply 2 is connected to the power supply terminal of the second CPU 4, and the power enable terminal of the second controlled power supply 2 is connected to the general-purpose input / output terminal of the first CPU 3 through the first power control circuit 5. The first CPU3 and the second CPU4 are provided with a bidirectional heartbeat communication link for mutual monitoring of their operating status.

[0032] Please refer to Figure 2 The first power control circuit 5 includes a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to the general-purpose input / output terminal of the first CPU 3, and the other end of the resistor R1 is connected to one end of the capacitor C1 and the power enable terminal of the second controlled power supply 2. The other end of the capacitor C1 is grounded.

[0033] The first power control circuit 5 also includes a resistor R2. One end of the resistor R2 is connected to the power enable terminal of the second controlled power supply 2, one end of the capacitor C1 and the other end of the resistor R1, respectively. The other end of the resistor R2 is grounded.

[0034] The first power control circuit 5 also includes a diode D1. The anode of the diode D1 is connected to the general-purpose input / output terminal of the first CPU 3 through a resistor R1, and the cathode of the diode D1 is connected to one end of the capacitor C1 and the power enable terminal of the second controlled power supply 2.

[0035] The second power control circuit 6 includes a resistor R3 and a capacitor C2. One end of the resistor R3 is connected to the general-purpose input / output terminal of the second CPU 4, and the other end of the resistor R3 is connected to one end of the capacitor C2 and the power enable terminal of the first controlled power supply 1. The other end of the capacitor C2 is grounded.

[0036] The second power control circuit 6 further includes a resistor R4, one end of which is connected to the power enable terminal of the first controlled power supply 1, one end of the capacitor C2, and the other end of the resistor R3, and the other end of the resistor R4 is grounded.

[0037] The second power control circuit 6 also includes a diode D2. The anode of the diode D2 is connected to the general-purpose input / output terminal of the second CPU 4 through a resistor R3. The cathode of the diode D2 is connected to one end of the capacitor C2 and the power enable terminal of the first controlled power supply 1, respectively.

[0038] The dual-CPU arbitration reset system in this solution can achieve precise and complete reset of a faulty CPU. The overall working principle is as follows: (I) System Initialization Phase: After the system is powered on, the first CPU3 initializes its general-purpose input / output terminals used to control the second controlled power supply 2 to a high-impedance state, and the second CPU4 also initializes its general-purpose input / output terminals used to control the first controlled power supply 1 to a high-impedance state. At this time, the enable terminal voltages of the first controlled power supply 1 and the second controlled power supply 2 are determined by the circuit voltage divider or their own characteristics, and are both below the turn-on threshold. The two controlled power supplies output voltage normally, supplying power to the first CPU3 and the second CPU4, and the system enters normal operating state.

[0039] (II) Normal Operation and Condition Monitoring Phase: The first CPU3 and the second CPU4 periodically send heartbeat signals to each other through a bidirectional heartbeat communication link. Each CPU monitors and receives heartbeat signals from the other, and sets the heartbeat monitoring period (usually 0.3 seconds to 1 second) through a software timer. If a valid heartbeat signal is successfully received within this period, it is determined that the other CPU is working normally, and it continues to maintain the high impedance state of its own general-purpose input / output terminals (i.e., I / O ports), and the system continues to operate normally.

[0040] (III) Fault Determination and Reset Arbitration Stage: When the first CPU3 fails to receive a valid heartbeat signal from the second CPU4 within a preset heartbeat monitoring period, it determines that the second CPU4 has malfunctioned and immediately executes the first reset arbitration operation: The first CPU3 switches its general-purpose input / output terminal from high impedance to output mode and outputs the first control level (high level). The high level is transmitted to the enable terminal of the second controlled power supply 2 through the resistor R1 and diode D1 in the first power control circuit 5, causing the voltage of the enable terminal of the second controlled power supply 2 to rise rapidly to above the shutdown threshold of the second controlled power supply 2, the second controlled power supply 2 stops outputting voltage, and the second CPU 4 is powered off. The first CPU3 maintains a high-level output for a preset duration (usually 0.1 to 2 seconds) to ensure that the second CPU4 is completely powered off and clears the internal abnormal latch state; After the preset time expires, the first CPU3 restores its general-purpose input / output terminals to a high-impedance state. At this time, the voltage at the enable terminal of the second controlled power supply 2 gradually decreases through the discharge circuit formed by resistor R2 and capacitor C1. When the voltage drops below the turn-on threshold of the second controlled power supply 2, the second controlled power supply 2 outputs voltage again to power on the second CPU4. The second CPU4 completes a hard reset and resumes normal operation.

[0041] Similarly, when the second CPU4 determines that the first CPU3 has failed, it performs a second reset arbitration operation: the general-purpose input / output terminal of the second CPU4 switches from a high-impedance state to output a second control level (high level), and the first controlled power supply 1 is turned off through the second power supply control circuit 6. After maintaining the high-impedance state for a preset time, the first controlled power supply 1 is restored and powered on again, thus realizing a hard reset of the first CPU3.

[0042] (iv) Recovery phase after repositioning: After the faulty CPU is hard reset and powered on again, it automatically initializes and joins the system, restarts the heartbeat communication mechanism, and resumes normal status monitoring and collaborative work with the other CPU, and the system returns to a stable operating state.

[0043] The entire circuit uses an RC delay circuit to buffer and control voltage discharge, a diode to isolate reverse current, and bidirectional heartbeat communication to accurately determine faults. The hardware and software collaboration ensures the thoroughness and reliability of the reset operation, effectively solving the shortcomings of traditional reset methods and significantly improving the fault recovery capability and overall reliability of the dual-CPU system.

[0044] Please refer to Figure 3 Embodiment two of the present invention is as follows: A control method for the above-mentioned dual-CPU arbitration reset system includes the following steps: S1. Control the general-purpose input / output terminals of the first CPU3 to be initialized to a high-impedance state, and control the general-purpose input / output terminals of the second CPU4 to be initialized to a high-impedance state; S2. The first CPU3 and the second CPU4 monitor each other's operating status through a two-way heartbeat communication link; If the first CPU3 determines that the second CPU4 has malfunctioned, the first CPU3 performs a first reset arbitration operation on the second controlled power supply 2 through the first power control circuit 5. If the second CPU4 determines that the first CPU3 has failed, the second CPU4 performs a second reset arbitration operation on the first controlled power supply 1 through the second power control circuit 6.

[0045] In step S2, the first CPU3 performs a first reset arbitration operation on the second controlled power supply 2 through the first power control circuit 5, specifically including: The general-purpose input / output terminal of the first CPU3 is controlled to switch from high impedance to output mode, and a first control level is output. The first control level is transmitted to the power enable terminal of the second controlled power supply 2 through the first power control circuit 5, and the voltage of the power enable terminal of the second controlled power supply 2 is increased to above the shutdown threshold of the second controlled power supply 2. After maintaining the first control level at the general-purpose input / output terminal of the first CPU3 for a preset duration, the general-purpose input / output terminal of the first CPU3 is restored to a high-impedance state, and the voltage at the power enable terminal of the second controlled power supply 2 is reduced to below the turn-on threshold of the second controlled power supply 2.

[0046] In step S2, the second CPU4 performs a second reset arbitration operation on the first controlled power supply 1 through the second power control circuit 6, specifically including: The general-purpose input / output terminal of the second CPU4 is controlled to switch from high impedance to output mode, and a second control level is output. The second control level is transmitted to the power enable terminal of the first controlled power supply 1 through the second power control circuit 6, and the voltage of the power enable terminal of the first controlled power supply 1 is increased to above the shutdown threshold of the first controlled power supply 1. After maintaining the second control level at the general-purpose input / output terminal of the second CPU4 for a preset duration, the general-purpose input / output terminal of the second CPU4 is restored to a high-impedance state, and the voltage at the power enable terminal of the first controlled power supply 1 is reduced to below the turn-on threshold of the first controlled power supply 1.

[0047] In summary, the dual-CPU arbitration reset system and its control method provided by this invention ensure independent control of the power supply to the two CPUs by setting up a first controlled power supply and a second controlled power supply that are independent and supply power to the first CPU and the second CPU respectively, thus avoiding mutual interference during the reset operation. The first power supply control circuit and the second power supply control circuit form a cross-control architecture, allowing the second CPU to control the first controlled power supply through the first power supply control circuit, and the first CPU to control the second controlled power supply through the second power supply control circuit, achieving precise control of the power supply of the faulty CPU by the normal CPU. The bidirectional heartbeat communication link between the first CPU and the second CPU can monitor each other's operating status in real time and reliably, providing a direct basis for fault diagnosis. Through the coordinated cooperation of various modules, the overall architecture achieves effective arbitration and reset triggering in the event of a dual-CPU system failure, improving the reliability and independence of system fault recovery. In the status monitoring step, the first CPU and the second CPU periodically confirm each other's operating status through a heartbeat communication link, ensuring the real-time and continuous monitoring of both parties' working status. This provides an accurate and reliable basis for subsequent fault determination, avoiding missed or false faults. The fault determination step uses the failure to receive a valid status confirmation within a preset heartbeat timeout period as the fault determination criterion, making the fault identification logic clear and quantifiable, ensuring that subsequent operations are only triggered when the other party actually experiences an anomaly. In the power arbitration step, the general-purpose input / output terminals of the control CPU are switched from a high-impedance state to an output shutdown effective level and maintained for a predetermined shutdown delay. This operation directly acts on the corresponding controlled power module, forcing the faulty CPU to lose power. Achieving a complete hardware-level reset effectively solves the problem that traditional soft resets cannot clear deeply abnormal latched states. Simultaneously, the pre-set shutdown delay ensures the faulty CPU is completely powered off, guaranteeing the reset effect. In the state recovery step, the control CPU's general-purpose input / output terminals are restored to a high-impedance state, causing the controlled power module to restart, enabling the faulty CPU to complete the reset, power on, and quickly return to the system. The entire process forms a closed-loop control, ensuring both the thoroughness and reliability of the reset and automating fault recovery without manual intervention. Furthermore, the logical connections between each step are tight, the operation is simple and controllable, and it is compatible with dual-CPU cross-control system architectures, significantly improving the fault recovery capability and overall operational stability of dual-CPU systems.

[0048] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A dual-CPU arbitration reset system, characterized in that, It includes a first controlled power supply, a second controlled power supply, a first CPU, a second CPU, a first power control circuit, and a second power control circuit; The input terminals of both the first and second controlled power supplies are connected to the external main power supply. The output terminal of the first controlled power supply is connected to the power supply terminal of the first CPU, and the power enable terminal of the first controlled power supply is connected to the general-purpose input / output terminal of the second CPU through the second power control circuit. The output terminal of the second controlled power supply is connected to the power supply terminal of the second CPU, and the power enable terminal of the second controlled power supply is connected to the general-purpose input / output terminal of the first CPU through the first power control circuit. A two-way heartbeat communication link is provided between the first CPU and the second CPU for mutual monitoring of their operating status.

2. The dual-CPU arbitration reset system according to claim 1, characterized in that, The first power control circuit includes a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to the general-purpose input / output terminal of the first CPU, and the other end of the resistor R1 is connected to one end of the capacitor C1 and the power enable terminal of the second controlled power supply. The other end of the capacitor C1 is grounded.

3. The dual-CPU arbitration reset system according to claim 2, characterized in that, The first power control circuit also includes a resistor R2, one end of which is connected to the power enable terminal of the second controlled power supply, one end of the capacitor C1 and the other end of the resistor R1, and the other end of the resistor R2 is grounded.

4. The dual-CPU arbitration reset system according to claim 2, characterized in that, The first power control circuit also includes a diode D1. The anode of the diode D1 is connected to the general-purpose input / output terminal of the first CPU through a resistor R1, and the cathode of the diode D1 is connected to one end of a capacitor C1 and the power enable terminal of the second controlled power supply.

5. The dual-CPU arbitration reset system according to claim 1, characterized in that, The second power control circuit includes a resistor R3 and a capacitor C2. One end of the resistor R3 is connected to the general-purpose input / output terminal of the second CPU, and the other end of the resistor R3 is connected to one end of the capacitor C2 and the power enable terminal of the first controlled power supply. The other end of the capacitor C2 is grounded.

6. The dual-CPU arbitration reset system according to claim 5, characterized in that, The second power control circuit also includes a resistor R4, one end of which is connected to the power enable terminal of the first controlled power supply, one end of the capacitor C2, and the other end of the resistor R3, and the other end of the resistor R4 is grounded.

7. The dual-CPU arbitration reset system according to claim 5, characterized in that, The second power control circuit also includes a diode D2. The anode of the diode D2 is connected to the general-purpose input / output terminal of the second CPU through a resistor R3. The cathode of the diode D2 is connected to one end of the capacitor C2 and the power enable terminal of the first controlled power supply, respectively.

8. A control method for a dual-CPU arbitration reset system based on claim 1, characterized in that, Includes the following steps: S1. Control the general-purpose input / output terminals of the first CPU to be initialized to a high-impedance state, and control the general-purpose input / output terminals of the second CPU to be initialized to a high-impedance state; S2. The first CPU and the second CPU monitor each other's operating status through a two-way heartbeat communication link; If the first CPU determines that the second CPU has malfunctioned, the first CPU performs a first reset arbitration operation on the second controlled power supply through the first power control circuit. If the second CPU determines that the first CPU has malfunctioned, the second CPU performs a second reset arbitration operation on the first controlled power supply through the second power control circuit.

9. The control method for the dual-CPU arbitration reset system according to claim 8, characterized in that, In step S2, the first CPU performs a first reset arbitration operation on the second controlled power supply through the first power control circuit, specifically including: The general-purpose input / output terminal of the first CPU is controlled to switch from a high-impedance state to an output mode, and a first control level is output. The first control level is transmitted to the power enable terminal of the second controlled power supply through the first power control circuit, and the voltage of the power enable terminal of the second controlled power supply is increased to above the shutdown threshold of the second controlled power supply. After maintaining the first control level at the general-purpose input / output terminal of the first CPU for a preset duration, the general-purpose input / output terminal of the first CPU is restored to a high-impedance state, and the voltage at the power enable terminal of the second controlled power supply is reduced to below the turn-on threshold of the second controlled power supply.

10. The control method for the dual-CPU arbitration reset system according to claim 8, characterized in that, In step S2, the second CPU performs a second reset arbitration operation on the first controlled power supply through the second power control circuit, specifically including: The general-purpose input / output terminal of the second CPU is controlled to switch from high impedance to output mode, and a second control level is output. The second control level is transmitted to the power enable terminal of the first controlled power supply through the second power control circuit, and the voltage of the power enable terminal of the first controlled power supply is increased to above the shutdown threshold of the first controlled power supply. After maintaining the second control level at the general-purpose input / output terminal of the second CPU for a preset duration, the general-purpose input / output terminal of the second CPU is restored to a high-impedance state, and the voltage at the power enable terminal of the first controlled power supply is reduced to below the turn-on threshold of the first controlled power supply.

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