Method and device for testing multilevel memory and performance of DSP (Digital Signal Processor) embedded system
By setting up protected and safe test areas in the DSP embedded system, and employing dynamic memory mapping management and data backup, the problems of system failures and communication interruptions caused during testing in existing technologies are solved, achieving seamless testing and ensuring online rates.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING XINLI MACHINERY
- Filing Date
- 2026-01-16
- Publication Date
- 2026-05-12
AI Technical Summary
Existing memory testing methods for DSP embedded systems are highly destructive, easily causing system crashes and adversely affecting normal system operation, especially when testing the RAM of external communication chips, which can lead to communication interruptions.
During the initialization phase of the DSP embedded system, protected areas and safe test areas are set according to the memory layout information. Dynamic memory mapping management is adopted to avoid protected areas necessary for program operation. Memory test algorithms are executed only in the safe test area. Data backup is performed on the external communication chip RAM before testing, and the data is restored after testing.
Non-destructive testing was achieved, ensuring the system remained online during testing, avoiding system failures and communication interruptions, and improving the safety and reliability of the test.
Smart Images
Figure CN122019291A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of testing embedded systems, specifically to a method and apparatus for testing the multi-level memory and performance of a DSP embedded system. Background Technology
[0002] DSP systems are widely used in many high-reliability fields, and their importance is self-evident. Therefore, testing these systems is particularly crucial. However, current testing techniques suffer from two very prominent and serious problems.
[0003] Firstly, there are significant shortcomings in terms of testing security. Traditional memory testing methods, such as the well-known March algorithm, are inherently destructive. This is because if the actual memory layout of the embedded system is not fully considered during testing—including content such as programs and stack traces that often reside in memory—and testing is conducted blindly, it could potentially lead to serious consequences such as system crashes. This is analogous to operating a sophisticated machine without understanding the specific location and function of each component; it will inevitably disrupt the normal operation of the entire system.
[0004] Secondly, testing can negatively impact the normal operation of the system. When testing the RAM of external communication chips such as network ports and CAN controllers, this process erases configuration and cached data. Once this data is erased, communication interruption is inevitable. In many online application scenarios, such communication interruption is completely unacceptable. For example, in a real-time data transmission network environment, if data transmission is suddenly interrupted due to testing, it will cause significant trouble and losses to the entire system's business operations. Summary of the Invention
[0005] The purpose of this application is to overcome the shortcomings and deficiencies in the prior art and to provide a method and apparatus for testing the multi-level memory and performance of a DSP embedded system.
[0006] The first aspect of this application provides a method for testing the multi-level memory and performance of a DSP embedded system, the method comprising:
[0007] During the initialization phase of the DSP embedded system, the address regions of the protected area and the security test area are set according to the preset memory layout information.
[0008] The test instruction set issued by the host computer is parsed to obtain the internal RAM test instructions and the external communication chip RAM test instructions.
[0009] In response to the internal RAM test command, dynamic memory mapping management is adopted to identify and avoid protected areas necessary for program execution, and memory test algorithms are executed only in the safe test area to obtain the first test result;
[0010] In response to the external communication chip RAM test command, the data of the test block of the external communication chip is backed up to a temporary buffer, and then the test block is tested to obtain a second test result;
[0011] The first test result and the second test result are sent back to the host computer.
[0012] In one implementation, the protected area includes the code segment, global data area, heap, and stack.
[0013] As one implementation, the step of executing the memory testing algorithm only in the security test area includes:
[0014] Within the security test area, the March-C algorithm is executed to perform a complete test on the storage unit.
[0015] As one implementation, after the step of parsing the test instruction set issued by the host computer to obtain the internal RAM test instructions and the external communication chip RAM test instructions, the method further includes:
[0016] In response to the internal RAM test command, the Walking 1 / 0 algorithm is used to perform an integrity test on the memory's address lines;
[0017] The Checkerboard algorithm is used to perform integrity testing on the memory's data lines.
[0018] As one implementation, the step of backing up the data of the test block of the external communication chip to a temporary buffer in response to the external communication chip RAM test command, and then testing the test block to obtain a second test result includes:
[0019] After the raw data of the test block of the external communication chip is transferred to a temporary buffer at high speed via DMA, the test block is tested using the March-C algorithm.
[0020] After the test of the block under test is completed, the original data is transferred to the block under test via DMA at high speed.
[0021] Compared to related technologies, the multi-level memory and performance testing method for DSP embedded systems in this application, during the initialization phase of the DSP embedded system, sets the address regions of the protected area and the address regions of the safe test area according to the preset memory layout information; then, it parses the test instruction set issued by the host computer to obtain the internal RAM test instructions and the external communication chip RAM test instructions; then, in response to the internal RAM test instructions, it adopts dynamic memory mapping management to identify and avoid the protected area necessary for program execution, and only executes the memory test algorithm in the safe test area to obtain the first test result; in response to the external communication chip RAM test instructions, it connects the external communication chip RAM to the protected area. After backing up the data of the test block of the communication chip to a temporary buffer, the test block is tested to obtain a second test result. Finally, the first test result and the second test result are sent back to the host computer. The destructive memory testing algorithm (such as March-C) is only performed in the idle memory that is clearly marked as the "safe test area", which fundamentally eliminates the interference of the test process on the system operation and solves the industry problem of "the test itself causing system failure". Moreover, when testing the RAM of the external communication chip, the process of testing after data backup and restoring after testing achieves "seamless testing" and ensures the online rate of the system during the test.
[0022] A second aspect of this application provides a testing apparatus for multi-level memory and performance of a DSP embedded system, comprising:
[0023] The address region setting module is used to set the address regions of the protected area and the address regions of the security test area according to the preset memory layout information during the initialization phase of the DSP embedded system.
[0024] The test instruction acquisition module is used to parse the test instruction set issued by the host computer to obtain the internal RAM test instructions and the external communication chip RAM test instructions.
[0025] The internal RAM testing module is used to respond to the internal RAM test instructions, adopts dynamic memory mapping management, identifies and avoids protected areas necessary for program operation, and executes memory test algorithms only in the safe test area to obtain the first test result;
[0026] An external communication chip testing module is used to respond to the RAM test command of the external communication chip, back up the data of the test block of the external communication chip to a temporary buffer, test the test block, and obtain a second test result.
[0027] The test result upload module is used to send the first test result and the second test result back to the host computer.
[0028] In one implementation, the protected area includes the code segment, global data area, heap, and stack.
[0029] In one implementation, the internal RAM test module performs a complete test of the storage unit using the March-C algorithm within the secure test area.
[0030] In one implementation, the internal RAM test module is also used to perform integrity testing on the memory's address lines using the Walking I / O algorithm, and to perform integrity testing on the memory's data lines using the Checkerboard algorithm.
[0031] In one implementation, the external communication chip test module is used to transfer the original data of the test block of the external communication chip to a temporary buffer at high speed via DMA, then test the test block using the March-C algorithm, and after the test of the test block is completed, transfer the original data to the test block at high speed via DMA.
[0032] Compared to related technologies, the multi-level memory and performance testing device for DSP embedded systems in this application sets the address regions of protected areas and secure test areas according to preset memory layout information during the initialization phase of the DSP embedded system; then, it parses the test instruction set issued by the host computer to obtain internal RAM test instructions and external communication chip RAM test instructions; then, in response to the internal RAM test instructions, it adopts dynamic memory mapping management to identify and avoid protected areas necessary for program execution, and executes memory test algorithms only in the secure test areas to obtain the first test result; in response to the external communication chip RAM test instructions, it connects the external communication chip RAM to the protected area. After backing up the data of the test block of the communication chip to a temporary buffer, the test block is tested to obtain a second test result. Finally, the first test result and the second test result are sent back to the host computer, so that malicious memory testing algorithms (such as March-C) are only performed in the idle memory that is clearly marked as the "safe test area". This fundamentally eliminates the interference of the test process on the system operation and solves the industry problem of "the test itself causing system failure". Moreover, when testing the RAM of the external communication chip, the process of testing after data backup and restoring after testing achieves "seamless testing" and ensures the online rate of the system during the test.
[0033] To provide a clearer understanding of this application, the specific embodiments of this application will be described below in conjunction with the accompanying drawings. Attached Figure Description
[0034] Figure 1 This is a schematic diagram illustrating the steps of a method for testing the multi-level memory and performance of a DSP embedded system according to an embodiment of this application.
[0035] Figure 2This is a system architecture diagram corresponding to a method for testing the multi-level memory and performance of a DSP embedded system according to an embodiment of this application;
[0036] Figure 3 This is a schematic diagram of memory layout information for a method for testing multi-level memory and performance of a DSP embedded system according to an embodiment of this application.
[0037] Figure 4 This is a flowchart illustrating a method for testing the multi-level memory and performance of a DSP embedded system according to an embodiment of this application.
[0038] Figure 5 This is a schematic flowchart illustrating the external communication chip RAM testing process of a DSP embedded system multi-level memory and performance testing method according to an embodiment of this application.
[0039] Figure 6 This is a schematic diagram of the module connections for a test apparatus for multi-level memory and performance of a DSP embedded system according to an embodiment of the application.
[0040] 101. Host computer; 102. External communication chip; 103. DSP chip; 104. DSP internal RAM; 105. External flash chip; 300. Testing device for multi-level memory and performance of DSP embedded system; 301. Address area setting module; 302. Test instruction acquisition module; 303. Internal RAM testing module; 304. External communication chip testing module; 305. Test result uploading module. Detailed Implementation
[0041] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0042] It should be understood that the described embodiments are merely some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of the embodiments of this application.
[0043] In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. In the description of this application, it should be understood that the terms "first," "second," "third," etc., are used only to distinguish similar objects and are not necessarily used to describe a specific order or sequence, nor should they be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. The singular forms "a," "the," and "the" used in this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. The words "if" or "when" as used herein can be interpreted as "when," "when," or "response determined."
[0044] Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.
[0045] Please see Figure 1 This is a schematic diagram illustrating the steps of a method for testing multi-level memory and performance of a DSP embedded system according to the first embodiment of this application. The method includes:
[0046] S1: During the initialization phase of the DSP embedded system, the address regions of the protected area and the security test area are set according to the preset memory layout information.
[0047] S2: Parse the test instruction set issued by the host computer to obtain the internal RAM test instructions and the external communication chip RAM test instructions;
[0048] S3: In response to the internal RAM test instruction, dynamic memory mapping management is adopted to identify and avoid the protected areas necessary for program operation, and the memory test algorithm is executed only in the safe test area to obtain the first test result;
[0049] S4: In response to the external communication chip RAM test command, back up the data of the test block of the external communication chip to a temporary buffer, and then test the test block to obtain a second test result;
[0050] S5: Send the first test result and the second test result back to the host computer.
[0051] In one feasible embodiment, the protected area includes the code segment, global data area, heap, and stack.
[0052] In one feasible embodiment, the step of executing the memory testing algorithm only in the security test area includes:
[0053] Within the security test area, the March-C algorithm is executed to perform a complete test on the storage unit.
[0054] In one feasible embodiment, after the step of parsing the test instruction set issued by the host computer to obtain the internal RAM test instructions and the external communication chip RAM test instructions, the method further includes:
[0055] In response to the internal RAM test command, the Walking 1 / 0 algorithm is used to perform an integrity test on the memory's address lines;
[0056] The Checkerboard algorithm is used to perform integrity testing on the memory's data lines.
[0057] In one feasible embodiment, the step of backing up the data of the test block of the external communication chip to a temporary buffer in response to the external communication chip RAM test command, and then testing the test block to obtain a second test result includes:
[0058] After the raw data of the test block of the external communication chip is transferred to a temporary buffer at high speed via DMA, the test block is tested using the March-C algorithm.
[0059] After the test of the block under test is completed, the original data is transferred to the block under test via DMA at high speed.
[0060] Please see Figure 2 The system hardware corresponding to the multi-level memory and performance testing method of the DSP embedded system in this application includes a host computer 101, an external communication chip 102, a DSP chip 103, an internal RAM of the DSP 104, and an external flash chip 105.
[0061] Please see Figure 3After the DSP embedded system powers on, the bootloader loads the application program from the external FLASH into a specified address in the on-chip RAM for execution. The test program, as part of the application program, precisely obtains memory layout information during the initialization phase by querying the linker map file generated by the compiler or predefined macros. The protected address regions, including the code segment (.text), global data area (.data, .bss), heap, and stack, are as follows: the code segment (.text) starts at address 0x00000000 and has a length of 0x00008000; the global data area (.data, .bss) starts at 0x00080000; the heap grows upwards from 0x00090000; and the stack grows downwards from 0x000A0000. Subsequently, the test scheduling core marks the remaining contiguous memory region (e.g., 0x000B0000-0x000FFFFF) as the "safe test area" for this test.
[0062] Please see Figure 4 The process of receiving instructions is as follows: The host computer sends a test instruction in JSON format via UART: {"TestItems": ["IT_RAM", "EXT_COMM_RAM"], "Params": {...}}. The communication interrupt service routine on the DSP side receives and parses the instruction, waking up the test scheduling task.
[0063] The testing includes internal RAM testing and external communication chip RAM testing. Taking internal RAM testing as an example, the process includes the following steps:
[0064] The test scheduling task confirms that internal RAM testing (IT_RAM) will be performed.
[0065] Based on the obtained partition information, the memory testing engine only performs the March-C algorithm on the "safe test area" (0x000B0000-0x000FFFFF).
[0066] Both writing and reading data are accelerated using DMA, enabling rapid test completion. Test results (pass / fail, and the address of the failed test) are recorded.
[0067] Please see Figure 5 Taking the testing of external communication chip RAM as an example, the process includes the following steps:
[0068] The test scheduling task confirms that an external communication chip RAM test (EXT_COMM_RAM) will be performed.
[0069] Data backup: Through the SPI interface, all data from address 0x0000 to 0x1FFF in the internal RAM of the communication chip (such as an Ethernet controller) is read and temporarily stored in a large cache array in the internal RAM of the DSP.
[0070] Perform test: Perform March-C test on the RAM area 0x0000-0x1FFF of the external communication chip.
[0071] Data recovery: After the test is completed, the data in the cache array is immediately written back to the original RAM address of the communication chip via the SPI interface.
[0072] Record the test results.
[0073] After all required tests have been completed, the test scheduling core aggregates and packages the results from each module, then transmits them back to the host computer via UART. The host computer then displays the test results and test time. The aggregated results include the internal RAM test results and the external communication chip RAM test results. For example, the host computer software parses the data and displays: "Internal RAM test: Passed; External communication chip RAM test: Passed; Total test time: 125ms".
[0074] Compared to related technologies, the multi-level memory and performance testing method for DSP embedded systems in this application, during the initialization phase of the DSP embedded system, sets the address regions of the protected area and the address regions of the safe test area according to the preset memory layout information; then, it parses the test instruction set issued by the host computer to obtain the internal RAM test instructions and the external communication chip RAM test instructions; then, in response to the internal RAM test instructions, it adopts dynamic memory mapping management to identify and avoid the protected area necessary for program execution, and only executes the memory test algorithm in the safe test area to obtain the first test result; in response to the external communication chip RAM test instructions, it connects the external communication chip RAM to the protected area. After backing up the data of the test block of the communication chip to a temporary buffer, the test block is tested to obtain a second test result. Finally, the first test result and the second test result are sent back to the host computer, so that malicious memory testing algorithms (such as March-C) are only performed in the idle memory that is clearly marked as the "safe test area". This fundamentally eliminates the interference of the test process on the system operation and solves the industry problem of "the test itself causing system failure". Moreover, when testing the RAM of the external communication chip, the process of testing after data backup and restoring after testing achieves "seamless testing" and ensures the online rate of the system during the test.
[0075] In summary, this application includes the following two major innovative mechanisms:
[0076] 1. Intelligent Memory Partitioning and Security Isolation Mechanism: Through dynamic memory mapping, the system intelligently divides the memory into "safe testing zones" and "protected zones," ensuring that destructive tests are only performed within the safe zones. Specifically, this involves dynamically identifying the memory mapping layout and precisely avoiding critically important areas such as .text (code segment), .data, .bss, .stack, and .heap. Destructive memory testing algorithms (such as March-C) are only performed within the clearly marked "safe testing zones" of idle memory, fundamentally eliminating interference with system operation during testing and solving the industry problem of "tests themselves causing system failures."
[0077] 2. Seamless Testing Mechanism for External (Communication Chips): Through a "backup-test-restore" process, the field data of the communication chip is preserved before and after testing, achieving "zero impact" on communication functionality during the testing process. This is crucial for ensuring uninterrupted communication during testing. Specifically, before testing, the current running data (configuration, status, cache) in the communication chip's RAM is completely backed up to the DSP's internal secure area; then, the test algorithm is executed; after testing, the data is immediately written back as is. This process is transparent to the communication protocol stack, achieving "seamless testing" and ensuring the system's online rate during testing.
[0078] Therefore, the intelligent partitioning of this application ensures that the test will never damage the critical data of the system, the test process is safe and reliable, and it covers a multi-level complete test from the kernel to all memory subsystems and peripherals without blind spots. The multi-mode test algorithm can also discover more potential and hidden faults, with the advantages of high security, high coverage and high reliability. Moreover, the online function is not affected during the test: the unique backup / recovery mechanism enables the system to maintain external communication even during the test.
[0079] Please see Figure 6 The second embodiment of this application provides a testing device 300 for multi-level memory and performance of a DSP embedded system, comprising:
[0080] Address region setting module 301 is used to set the address region of the protected area and the address region of the security test area according to the preset memory layout information during the initialization phase of the DSP embedded system.
[0081] The protected area includes the code segment, global data area, heap, and stack.
[0082] The test instruction acquisition module 302 is used to parse the test instruction set issued by the host computer to obtain the internal RAM test instructions and the external communication chip RAM test instructions.
[0083] The internal RAM test module 303 is used to respond to the internal RAM test command, adopt dynamic memory mapping management, identify and avoid the protected area necessary for program operation, and execute the memory test algorithm only in the safe test area to obtain the first test result;
[0084] The internal RAM test module 303 performs a complete test of the storage unit using the March-C algorithm within the secure test area.
[0085] The internal RAM test module 303 is also used to perform integrity tests on the address lines of the memory using the Walking I / O algorithm, and to perform integrity tests on the data lines of the memory using the Checkerboard algorithm.
[0086] The external communication chip test module 304 is used to respond to the external communication chip RAM test command, back up the data of the test block of the external communication chip to a temporary buffer, and then test the test block to obtain a second test result.
[0087] The external communication chip test module 304 is used to perform high-speed data transfer of the original data of the test block of the external communication chip to a temporary buffer via DMA, and then use the March-C algorithm to test the test block. After the test of the test block is completed, the original data is transferred to the test block via DMA at high speed.
[0088] The test result upload module 305 is used to send the first test result and the second test result back to the host computer.
[0089] It should be noted that the DSP embedded system multi-level memory and performance testing device 300 provided in the second embodiment of this application, when executing the DSP embedded system multi-level memory and performance testing method, only uses the above-mentioned division of functional modules as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the DSP embedded system multi-level memory and performance testing device 300 provided in the second embodiment of this application and the DSP embedded system multi-level memory and performance testing method of the first embodiment of this application belong to the same concept, and its implementation process is detailed in the method embodiment, which will not be repeated here.
[0090] The device embodiments described above are merely illustrative. The components described as separate parts may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without any inventive effort.
[0091] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0092] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function selected in one or more boxes.
[0093] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function selected in one or more boxes.
[0094] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.
[0095] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.
[0096] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.
[0097] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0098] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.
Claims
1. A method for testing the multi-level memory and performance of a DSP embedded system, characterized in that, include: During the initialization phase of the DSP embedded system, the address regions of the protected area and the security test area are set according to the preset memory layout information. The test instruction set issued by the host computer is parsed to obtain the internal RAM test instructions and the external communication chip RAM test instructions. In response to the internal RAM test command, dynamic memory mapping management is adopted to identify and avoid protected areas necessary for program execution, and memory test algorithms are executed only in the safe test area to obtain the first test result; In response to the external communication chip RAM test command, the data of the test block of the external communication chip is backed up to a temporary buffer, and then the test block is tested to obtain a second test result; The first test result and the second test result are sent back to the host computer.
2. The method for testing the multi-level memory and performance of a DSP embedded system according to claim 1, characterized in that, The protected area includes the code segment, global data area, heap, and stack.
3. The method for testing the multi-level memory and performance of a DSP embedded system according to claim 1, characterized in that, The step of executing the memory testing algorithm only in the security test area includes: Within the security test area, the March-C algorithm is executed to perform a complete test on the storage unit.
4. The method for testing the multi-level memory and performance of a DSP embedded system according to claim 1, characterized in that, After the step of parsing the test instruction set issued by the host computer to obtain the internal RAM test instructions and the external communication chip RAM test instructions, the method further includes: In response to the internal RAM test command, the Walking 1 / 0 algorithm is used to perform an integrity test on the memory's address lines; The Checkerboard algorithm is used to perform integrity testing on the memory's data lines.
5. The method for testing the multi-level memory and performance of a DSP embedded system according to claim 1, characterized in that, The steps of responding to the external communication chip RAM test command, backing up the data of the test block of the external communication chip to a temporary buffer, and then testing the test block to obtain a second test result include: After the raw data of the test block of the external communication chip is transferred to a temporary buffer at high speed via DMA, the test block is tested using the March-C algorithm. After the test of the block under test is completed, the original data is transferred to the block under test via DMA at high speed.
6. A testing device for multi-level memory and performance of a DSP embedded system, characterized in that, include: The address region setting module is used to set the address regions of the protected area and the address regions of the security test area according to the preset memory layout information during the initialization phase of the DSP embedded system. The test instruction acquisition module is used to parse the test instruction set issued by the host computer to obtain the internal RAM test instructions and the external communication chip RAM test instructions. The internal RAM testing module is used to respond to the internal RAM test instructions, adopts dynamic memory mapping management, identifies and avoids protected areas necessary for program operation, and executes memory test algorithms only in the safe test area to obtain the first test result; An external communication chip testing module is used to respond to the RAM test command of the external communication chip, back up the data of the test block of the external communication chip to a temporary buffer, test the test block, and obtain a second test result. The test result upload module is used to send the first test result and the second test result back to the host computer.
7. The testing apparatus for multi-level memory and performance of a DSP embedded system according to claim 6, characterized in that, The protected area includes the code segment, global data area, heap, and stack.
8. The testing apparatus for multi-level memory and performance of a DSP embedded system according to claim 6, characterized in that, The internal RAM testing module performs a complete test of the storage unit using the March-C algorithm within the secure testing area.
9. The testing apparatus for multi-level memory and performance of a DSP embedded system according to claim 6, characterized in that, The internal RAM test module is also used to perform integrity tests on the memory's address lines using the Walking I / O algorithm, and to perform integrity tests on the memory's data lines using the Checkerboard algorithm.
10. The testing apparatus for multi-level memory and performance of a DSP embedded system according to claim 6, characterized in that, The external communication chip test module is used to transfer the original data of the test block of the external communication chip to a temporary buffer at high speed via DMA, and then test the test block using the March-C algorithm. After the test block is completed, the original data is transferred to the test block at high speed via DMA.