AD acquisition system based on PCIE bus and data acquisition control method

Abstract

The invention provides an AD acquisition system based on a PCIE bus and a data acquisition control method, and the system comprises a multi-channel AD acquisition module which is used for carrying out the synchronous acquisition and digital conversion of multi-channel analog signals, and obtaining the digitalized acquisition data; the high-speed data transmission module is used for carrying out caching and format conversion on the digitized collected data in a DMA (Direct Memory Access) mode; the PCIE bus control module is used for establishing a high-bandwidth data path between the FPGA and the CPU through a PCIE bus and managing DMA transmission and interaction of a control instruction; the acquisition configuration module is used for receiving configuration parameters from the CPU end and dynamically configuring the multi-channel AD acquisition module and the high-speed data transmission module; wherein the multi-channel AD acquisition module, the high-speed data transmission module and the acquisition configuration module are integrated at an FPGA (Field Programmable Gate Array) end, and perform data and instruction interaction with a CPU (Central Processing Unit) end through a PCIE (Peripheral Component Interface Express) bus control module. According to the scheme, performance breakthrough of a multi-channel high-speed AD acquisition system is realized, and a high-reliability solution is provided for the fields of scientific experiments and the like.

Description

Technical Field

[0001] This application relates to the field of high-speed data acquisition and transmission technology, specifically to an AD acquisition system and data acquisition control method based on a PCIE bus. Background Technology

[0002] In the field of high-speed data acquisition, traditional acquisition systems based on USB or Ethernet have the following technical bottlenecks: (1) Bandwidth limitation: USB 3.0 has a theoretical bandwidth of only 5Gbps, which is difficult to meet the synchronous sampling requirements of multiple channels (such as 64 channels) (typical requirement ≥16GB / s); (2) High latency: Protocol stack processing latency (>50μs) leads to insufficient real-time performance, which cannot meet microsecond-level response scenarios (such as particle accelerator trigger control); (3) High resource utilization: Software drivers frequently interrupt the CPU, resulting in a system load rate >40%, which affects the execution of other tasks; (4) Poor scalability: The firmware of traditional acquisition cards is fixed and cannot dynamically adjust the sampling parameters.

[0003] Existing traditional data acquisition systems suffer from low driver efficiency and slow interrupt response, which significantly restricts their acquisition performance. The PCIe bus provides high-speed bidirectional bandwidth and supports high-speed data copying and transfer based on DMA (Direct Memory Access). Combined with FPGA hardware acceleration capabilities, a high-throughput, low-latency data acquisition system can be built. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, this application aims to provide an AD acquisition system and data acquisition control method based on the PCIe bus; Firstly, this application proposes an AD acquisition system based on a PCIe bus, comprising: The multi-channel AD acquisition module is used to synchronously acquire and digitize multiple analog signals to obtain digitized data. A high-speed data transmission module is used to cache and convert the digitized acquired data using DMA. The PCIE bus control module is used to establish a high-bandwidth data path between the FPGA and the CPU through the PCIE bus, and to manage the interaction of DMA transfer and control commands. The acquisition configuration module is used to receive configuration parameters from the CPU and dynamically configure the multi-channel AD acquisition module and the high-speed data transmission module. The multi-channel AD acquisition module, the high-speed data transmission module, and the acquisition configuration module are integrated on the FPGA side, and interact with the CPU side through the PCIE bus control module for data and instruction exchange.

[0005] According to the technical solution provided in the embodiments of this application, the multi-channel AD acquisition module includes: The analog front-end circuit supports multiple differential inputs and integrates a programmable gain amplifier and overvoltage protection circuit. A high-precision ADC array, composed of multiple ADC chips, is used for high-speed parallel sampling of multi-channel input signals; The FPGA control logic is used to generate a low-jitter sampling clock and convert the digital signals acquired by the ADC chip into AXIS bus timing data.

[0006] According to the technical solution provided in the embodiments of this application, the high-speed data transmission module includes: A receive buffer FIFO is used to temporarily store the digitized acquisition data output by the multi-channel AD acquisition module; An interface conversion unit is used to encapsulate the data in the receive buffer FIFO into a data stream conforming to the AXIS bus timing. The DMA processing unit is used to directly transfer the packaged data stream to the CPU's DDR memory in burst mode via the PCIe bus, achieving zero-copy transfer.

[0007] According to the technical solution provided in the embodiments of this application, the PCIE bus control module includes: The PCIE IP core provides AXI4-STREAM and AXI4-LITE user interfaces and is mapped to the BAR0 and BAR1 address spaces; The PIO read / write control unit receives configuration commands from the CPU via the AXI4-LITE bus and the BAR0 space. The DMA read / write control unit, through the AXI4-STREAM bus and BAR1 space, completes high-speed data flow transmission from the FPGA to the CPU.

[0008] According to the technical solution provided in the embodiments of this application, the PCIE bus adopts an x4 lane configuration and the maximum link rate is not less than 5GT / s; the BAR0 space is used to transmit control commands and has a space size of 4KB; the BAR1 space is used to transmit acquired data and has a space size of 2MB.

[0009] According to the technical solution provided in the embodiments of this application, the acquisition configuration module receives configuration parameters through the PIO mode of the PCIE bus. The parameters include: ADC enable signal, sampling length, number of sampling repetitions, and DMA transfer length.

[0010] Secondly, this application proposes a data acquisition control method based on the PCIe bus-based AD acquisition system as described above, comprising the following steps: The CPU sends acquisition parameters to the acquisition configuration module on the FPGA via the PIO mode of the PCIe bus. The multi-channel AD acquisition module on the FPGA performs synchronous acquisition and digitization of multiple analog signals according to the acquisition parameters to obtain digitized acquisition data; The high-speed data transmission module buffers the digitized acquired data and converts it into an AXIS bus data stream; The FPGA side initiates DMA transfer through the PCIe bus control module, directly writing the data stream into the DDR memory on the CPU side; The CPU reads data directly from the DDR memory for processing.

[0011] According to the technical solution provided in the embodiments of this application, the step of distributing the collection parameters includes: The CPU configures the ADC's start / stop, sampling length, repetition count, and DMA transfer length by writing to a specified register in the PCIE BAR0 space.

[0012] According to the technical solution provided in the embodiments of this application, the step of initiating DMA transfer includes: The CPU sets the DMA transfer length and sends an enable signal. The DMA controller on the FPGA then transmits the AXIS data stream to the DDR on the CPU in burst mode through the PCIE BAR1 space.

[0013] According to the technical solution provided in the embodiments of this application, the method performs clock domain isolation and data buffering of ADC acquisition data and AXIS bus timing through asynchronous FIFO in the data path of FPGA.

[0014] Compared with existing technologies, the advantages of this application are as follows: Addressing the problems of limited bandwidth, high latency, and poor flexibility in traditional AD acquisition systems, this invention proposes a software design for an AD acquisition system based on the PCIe bus. This scheme achieves high-bandwidth, low-latency communication between the FPGA and CPU via the PCIe bus, utilizes the parallel computing resources of the FPGA to achieve multi-channel DMA parallel transmission and synchronous data sampling, and combines the dynamic parameter configuration and multi-task scheduling features of the CPU to support parallel acquisition of multiple channels and dynamic adjustment of sampling methods. This invention designs a high-speed AD acquisition system by enabling interaction between the FPGA and CPU via the PCIe bus. It leverages the respective advantages of both the FPGA and CPU, combining them to ensure latency during data acquisition and processing. The FPGA ensures interaction with the CPU via the PCIe bus, allowing them to work independently and in parallel, avoiding redundancy in the process. This breakthrough in performance of multi-channel high-speed AD acquisition systems, achieved through the high bandwidth characteristics of PCIe and optimized software architecture combined with the hardware acceleration capabilities of the FPGA, provides a highly reliable, low-latency solution for scientific experiments, industrial inspection, and other fields. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of an AD acquisition system based on the PCIE bus provided in an embodiment of this application. Detailed Implementation

[0016] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0017] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0018] Example 1 As mentioned in the background section, in view of the problems in the prior art, this application proposes an AD acquisition system based on the PCIe bus, such as... Figure 1 As shown, it includes: The multi-channel AD acquisition module is used to synchronously acquire and digitize multiple analog signals to obtain digitized data. A high-speed data transmission module is used to cache and convert the digitized acquired data using DMA. The PCIE bus control module is used to establish a high-bandwidth data path between the FPGA and the CPU through the PCIE bus, and to manage the interaction of DMA transfer and control commands. The acquisition configuration module is used to receive configuration parameters from the CPU and dynamically configure the multi-channel AD acquisition module and the high-speed data transmission module. The multi-channel AD acquisition module, the high-speed data transmission module, and the acquisition configuration module are integrated on the FPGA side, and interact with the CPU side through the PCIE bus control module for data and instruction exchange.

[0019] Specifically, the multi-channel AD acquisition module refers to the analog signal conditioning and digitization circuits physically located outside the FPGA chip, as well as the logic circuits implemented inside the FPGA for controlling the external ADC chip and receiving its data. It is a functional module, not a single physical entity. The high-speed data transmission module, acquisition configuration module, and PCIe bus control module are digital logic functional units fully implemented using the FPGA's programmable logic resources (such as LUTs, registers, and BRAM) in hardware description languages ​​(such as Verilog / VHDL). Together with the FPGA control logic in the multi-channel AD acquisition module, they are integrated on the FPGA side, forming the system's firmware or hardware acceleration engine. The CPU side refers to the computer host system connected to the FPGA via a PCIe slot, including the CPU, motherboard, memory (DDR), and the operating system, device drivers, and upper-level application software running on it.

[0020] Specifically, the system workflow and interaction principle are as follows: The system works in a pipeline mode of "configuration -> acquisition -> transmission -> processing". Its technical principle is to solidify the computationally intensive and real-time-critical tasks on the FPGA hardware, while the complex control, configuration and data analysis tasks are handled by the flexible and general-purpose CPU, and the efficient coupling between the two is achieved through the PCIe bus.

[0021] Initialization and Configuration Phase: After the system powers on, the CPU-side driver identifies the PCIe device and configures its address space (BAR). Subsequently, the CPU calls the driver function to package the parameters required by the acquisition configuration module (such as enable channels, sampling rate, gain, etc.) into a specific instruction format. These instructions are written to specific configuration registers mapped in the BAR space on the FPGA side via the PCIe bus control module through the PCIe bus's PIO (Programming Input / Output) mode. The acquisition configuration module monitors these registers in real time, and once a valid configuration update is detected, it immediately distributes the parameters to the multi-channel AD acquisition module (such as configuring the ADC chip's registers) and the high-speed data transmission module (such as setting the DMA engine's transfer length), completing the system's dynamic initialization. This step enables flexible software control over hardware behavior.

[0022] Data Acquisition and Transmission Phase: After configuration, the CPU issues a "Start Acquisition" command. The multi-channel AD acquisition module begins synchronously acquiring multiple analog signals and converting them into digital signals. The resulting "digitized acquisition data" is immediately sent to the high-speed data transmission module. This module first caches the data in a FIFO (First-In, First-Out) implemented using BRAM or distributed RAM within the FPGA to eliminate the impact of instantaneous bandwidth fluctuations on the PCIe bus. Then, using DMA (Direct Memory Access), the data is retrieved from the FIFO, assembled into the AXI4-Stream data packet required by the PCIe IP core, and transmitted via the PCIe bus control module. The DMA mechanism allows data to be written directly from the FPGA to a preset buffer in the CPU's DDR memory via the PCIe bus without CPU involvement in copying. This process is "zero-copy," significantly reducing CPU utilization and transmission latency.

[0023] Data processing stage: Once the CPU-side application learns from the driver that new acquired data has arrived in the DDR memory, it can directly read the data from the memory for subsequent analysis, display, storage, and other processing. Simultaneously, the acquisition and transmission on the FPGA side continue in parallel, achieving a pipelined, continuous, high-speed data flow.

[0024] This architecture achieves high-throughput, low-latency, and low-CPU-occupancy data acquisition. Parallel processing via FPGA hardware ensures the accuracy of multi-channel synchronous sampling; PCIe DMA transmission overcomes the bandwidth bottleneck of traditional buses (such as USB), achieving continuous data uploads at GB / s levels; and dynamic configuration through hardware and software collaboration combines the high speed of hardware with the flexibility of software. Its core principle lies in heterogeneous computing and hardware acceleration. Utilizing the parallelism and reconfigurability of FPGA, data acquisition, preprocessing, and transmission protocols are encapsulated into hardware circuits, resulting in extremely high processing efficiency. The PCIe bus provides chip-level high-speed interconnect bandwidth, enabling the FPGA to efficiently exchange massive amounts of data with the CPU, acting like a coprocessor in a computer. This architecture, separating the control plane (CPU configuration via PIO) from the data plane (FPGA data transfer via DMA), is a typical design paradigm for modern high-speed data acquisition systems.

[0025] In a preferred embodiment, the multi-channel AD acquisition module includes: The analog front-end circuit supports multiple differential inputs and integrates a programmable gain amplifier and overvoltage protection circuit. A high-precision ADC array, composed of multiple ADC chips, is used for high-speed parallel sampling of multi-channel input signals; The FPGA control logic is used to generate a low-jitter sampling clock and convert the digital signals acquired by the ADC chip into AXIS bus timing data.

[0026] Specifically, the analog front-end circuit is the gateway for signals entering the system. Its "support for multiple differential inputs" means the circuit design employs a differential receiving architecture (such as using differential operational amplifiers), which effectively suppresses common-mode noise and improves signal transmission quality in harsh industrial environments. The "programmable gain amplifier" can be implemented using chips such as the PGA280, with its gain factor (e.g., 1 to 500 times) set via an FPGA-controlled serial interface (e.g., SPI), thus adapting to input signals of varying amplitudes from millivolts to volts and expanding the system's dynamic range. The "overvoltage protection circuit" typically consists of clamping diodes, transient voltage suppressors, and current-limiting resistors, ensuring that even if the input voltage unexpectedly exceeds the limit (e.g., reaching ±30V), the subsequent precision ADC chip will not be damaged. High-precision ADC array: An array means the system uses multiple ADC chips working in parallel to achieve true synchronous multi-channel acquisition. In specific implementations, the AD9213 chip can be selected, with each chip potentially containing multiple channels (e.g., dual-channel). By assigning independent ADC chips to different channel groups and providing them with a common sampling clock, strict alignment of sampling times for all channels can be achieved. The high-speed sampling capability of the ADC (e.g., 250MS / s for the AD9213) is the cornerstone of the system's high bandwidth, while its high precision (e.g., signal-to-noise ratio SNR ≥ 65dB) ensures that the distortion and noise introduced during the digitization process are sufficiently low. FPGA control logic: This is the bridge connecting the external analog world and the internal digital system. First, it contains the clock management unit. An external crystal oscillator provides a stable reference clock (e.g., 100MHz), which is input to the MMCM (Mixed-Mode Clock Manager) IP core inside the FPGA. The MMCM can generate a clock signal with very precise frequency and phase, and low jitter. This clock is directly output to the external ADC chip as its sampling clock, ensuring sampling timing accuracy from the source. Second, it contains the data path. After the digital signal output by the ADC chip (usually parallel data from the LVDS interface) is received by the FPGA pins, the FPGA logic performs serial-to-parallel conversion, bit alignment, and other processing, and then encapsulates it according to the AXI4-Stream (AXIS) bus timing. This means that the FPGA logic generates corresponding TDATA (data) and TVALID (data valid) signals for each data sample, and responds to the TREADY (ready to receive) signal from the subsequent IP core, forming a streaming data interface. The TLAST signal can be used to indicate the end of a data packet.

[0027] In a preferred embodiment, the high-speed data transmission module includes: A receive buffer FIFO is used to temporarily store the digitized acquisition data output by the multi-channel AD acquisition module; An interface conversion unit is used to encapsulate the data in the receive buffer FIFO into a data stream conforming to the AXIS bus timing. The DMA processing unit is used to directly transfer the packaged data stream to the CPU's DDR memory in burst mode via the PCIe bus, achieving zero-copy transfer.

[0028] Specifically, the receive buffer FIFO: This is a first-in, first-out queue instantiated in the FPGA's Block RAM. Its primary function is to temporarily store data to achieve clock domain isolation. The clock domain for ADC data acquisition (e.g., a 125MHz clock generated by the MMCM) and the user interface clock domain of the PCIe IP core (e.g., 250MHz) are typically asynchronous. The FIFO, as an asynchronous queue, allows data to be safely and reliably transferred between different clock domains. Secondly, it acts as a data buffer. When a momentary congestion occurs at the back end of the PCIe bus, the ADC data from the front end can be temporarily stored in the FIFO to prevent data loss; when the bus is idle, enough data can accumulate in the FIFO to initiate an efficient burst transfer, thereby improving bus utilization. Interface conversion unit: This unit is the "translator" of the data format. Although the data from the front end may already be in AXIS format, this unit is responsible for its final processing and packaging to strictly match the interface requirements of the PCIe DMA IP core. Specifically, it ensures the correct data bit width (e.g., 64 bits), generates the correct TKEEP signal to indicate the validity of data bytes, and produces a TLAST signal at the end of a DMA transfer packet. This unit is essentially a finite state machine that monitors the non-empty state of the FIFO and the TREADY signal of the subsequent DMA engine, coordinating data reading and delivery.

[0029] DMA Processing Unit: In practice, this unit works in conjunction with Xilinx's "DMA / Bridge Subsystem for PCI Express" IP core. The CPU-side driver allocates a contiguous buffer in host memory (DDR) and informs the FPGA-side DMA engine of the buffer's physical starting address and length via the configuration bus (AXI4-Lite). When the amount of data in the FIFO reaches a preset trigger threshold, the DMA engine initiates a transfer. It reads data from the FIFO and sends it to the PCIe IP core via the AXI4-Stream interface. The PCIe IP core then writes the data directly to the DDR address specified by the CPU via Memory Write TLP (Transaction Layer Packet). Throughout this process, data travels directly from the FPGA's FIFO to host memory. "Zero copy" means that the CPU does not need to execute any memory copy instructions to move this data, thus freeing the CPU from heavy I / O load.

[0030] In a preferred embodiment, the PCIe bus control module includes: The PCIE IP core provides AXI4-STREAM and AXI4-LITE user interfaces and is mapped to the BAR0 and BAR1 address spaces; The PIO read / write control unit receives configuration commands from the CPU via the AXI4-LITE bus and the BAR0 space. The DMA read / write control unit, through the AXI4-STREAM bus and BAR1 space, completes high-speed data flow transmission from the FPGA to the CPU.

[0031] Specifically, the PCIe IP core: This is a rigorously verified hard or soft core provided by FPGA vendors (such as Xilinx), implementing a complex PCIe protocol stack. In our design, we instantiate the "DMA / Bridge Subsystem for PCIExpress (4.1)" IP core. It provides two standard AXI interfaces to the upper-layer user logic: 1) AXI4-Lite: This is a simple, low-bandwidth memory-mapped interface used for transmitting control information. 2) AXI4-Stream: This is a high-bandwidth streaming interface used for transmitting high-speed data streams. Simultaneously, this IP core declares two BAR (Base Address Register) spaces in the PCIe configuration space: BAR0 (e.g., 4KB) and BAR1 (e.g., 2MB). These BAR spaces are mapped to the CPU's system memory address space. CPU read / write operations to specific memory addresses are translated into accesses to the corresponding BAR addresses on the FPGA side via the PCIe bus. The PIO read / write control unit: This is a lightweight logic unit implemented through the AXI4-Lite slave interface. It is responsible for handling all control signaling. When the CPU needs to configure the FPGA, it performs a write operation to a specific offset address (corresponding to a function register) in the BAR0 space via the device driver. This write request reaches the FPGA via the PCIe bus. The PCIe IP core converts it into an AXI4-Lite write transaction. The PIO read / write control unit decodes the address of the transaction and writes the data into the corresponding internal register. These registers are directly connected to the control ports of the acquisition configuration module and the multi-channel AD acquisition module. Similarly, the CPU can also query the FPGA status by reading the BAR0 space. This mechanism implements "memory-mapped" control of the FPGA by the CPU. DMA Read / Write Control Unit: This unit is usually tightly integrated with the DMA processing unit in the high-speed data transfer module, or even the same entity. It is responsible for managing the high-speed data channel. When data needs to be transferred, this unit sends data to the PCIe IP core via the AXI4-Stream host interface. The PCIe IP core packages this stream data into PCIe memory write request packets and writes the data into the DDR memory on the CPU side through the address window specified in the BAR1 space. The reason for using a separate BAR1 space for data is to completely separate the control flow and data flow in the address space, avoid mutual interference, and ensure that the data path can obtain continuous and stable high bandwidth.

[0032] In a preferred embodiment, the PCIe bus adopts an x4 lane configuration with a maximum link rate of not less than 5GT / s; the BAR0 space is used to transmit control commands and has a size of 4KB; the BAR1 space is used to transmit acquired data and has a size of 2MB.

[0033] Specifically, PCIe x4 Lane configuration and 5GT / s link rate: Physical implementation: In hardware design, the "x4 Lane configuration" requires four pairs of differential signal pairs (called Lanes) to be arranged on the PCB board between the FPGA chip and the PCIe slot for transmitting data, and four pairs of differential signal pairs for receiving data. A reference clock and necessary sideband signals are also required. In the FPGA project, the link width needs to be explicitly set to "x4" in the PCIe IP core configuration interface. The FPGA's PCIe hard core module will use these physical channels to train the link with the PCIe switch or root complex on the motherboard, ultimately establishing a stable connection.

[0034] Rate Implementation: "Maximum link rate not less than 5GT / s" corresponds to the PCIe 2.0 standard. In the IP core configuration, the generated configuration needs to be set to support Gen2. After successful link training, the system will run at the raw signal rate of 5.0 GT / s. Considering the overhead of 8b / 10b encoding, the effective unidirectional bandwidth of the x4 link is approximately 5 GT / s × 4 Lanes × (8 / 10) ÷ 8 bits / Byte = 2 GB / s. This bandwidth provides a solid physical foundation for high-speed multi-channel sampling (such as 64 channels), ensuring that the massive amounts of data collected can be uploaded to the host in a timely manner and will not be lost due to bus bottlenecks.

[0035] Function and Size Division of BAR Space: BAR0 (4KB) is used for control instructions: Setting the BAR0 space to 4KB is a well-considered decision. First, this size is sufficient to map all the control and status registers on the FPGA side. Typically, each functional module (such as ADC control, DMA configuration, clock management, etc.) only needs to be allocated tens to hundreds of bytes of address space. 4KB of space provides ample address resources for the current and future functional expansion of the system. At the software driver level, after the operating system (such as Windows or Linux) recognizes the PCIe device, it maps the 4KB BAR0 space to the kernel's virtual address space. The driver can complete the configuration and status query of the FPGA by performing simple memory read and write operations (i.e., PIO) on these addresses. This size setting follows the minimum granularity of memory page management in computer systems (usually 4KB), achieving efficient memory resource utilization. BAR1 (2MB) is used for transmitting acquired data: Setting BAR1 to 2MB and limiting its use to data pass-through is the core of achieving high-performance DMA transfer. This larger space defines an address window. The CPU-side driver allocates one or more contiguous physical memory buffers of 2MB or more in the system's DDR memory and informs the FPGA-side DMA controller of the physical base addresses of these buffers through the BAR0 configuration interface. When DMA transfer begins, the FPGA-side DMA engine does not directly write data into this 2MB BAR1 space, but instead utilizes the address window represented by the BAR1 space. Specifically, the target address generated by the DMA engine falls within the address range defined by BAR1, and the PCIe IP core uses this address when issuing a Memory Write TLP packet. When the host receives the TLP packet, the PCIe root core converts the address in the TLP (the address within the BAR1 window) into the actual physical address of the DDR memory buffer according to the system's pre-configured address remapping rules, thus completing the data write. Setting such a large space of 2MB allows the driver to configure a large target buffer for DMA at once, and the FPGA can continuously write data into this window, reducing the number of times the CPU needs to frequently intervene and reconfigure the DMA target address, making it particularly suitable for long-term continuous acquisition tasks.

[0036] In a preferred embodiment, the acquisition configuration module receives configuration parameters via the PIO mode of the PCIe bus. The parameters include: ADC enable signal, sampling length, number of sampling repetitions, and DMA transfer length.

[0037] Specifically, the parameter receiving mechanism is PIO mode. Receiving configuration parameters via the PCIe bus in PIO mode means that, in practice, the CPU-side application or driver writes the configuration parameters into specific registers in the BAR0 region, which has been mapped to the kernel address space, by calling APIs provided by the operating system. This process is entirely controlled by CPU programming. Data travels through CPU registers, the memory bus, the PCIe root complex, and finally reaches the FPGA via the PCIe bus; hence, it is called programmable I / O. Detailed explanation of core configuration parameters: ADC Enable Signal: This parameter is a bitmask used to dynamically enable or disable specific acquisition channels. On the FPGA side, this parameter is latched in a configuration register. Each bit of the register corresponds to a physical ADC chip or a channel. For example, setting bit 0 to 1 enables all channels connected to the 0th chip in the ADC array; setting it to 0 disables them. This achieves "on-demand acquisition," saving power when channels are not fully used and preventing data from irrelevant channels from consuming valuable PCIe bandwidth.

[0038] Sampling Length: This parameter defines the size of a "sampling frame," typically expressed in "sampling points." For example, it can be configured to 1024 points. Upon receiving the start acquisition command, the FPGA control logic controls the ADC to acquire data and count the points. When the number of acquired points reaches the value set by the "sampling length," the FPGA can generate an internal interrupt or flag signal to trigger a DMA transfer or notify the CPU that a frame of data is ready. This is crucial for algorithms that require processing continuous data streams divided into fixed-length blocks (such as FFT analysis).

[0039] Sampling Repetition Count: This parameter controls the number of times a single acquisition task is executed in a loop. For example, it can be configured to 1000 times. When used in conjunction with "Sampling Length," the system will automatically repeat the process of "acquiring one frame of data -> triggering DMA transfer" 1000 times. This is extremely useful for scientific research applications that require a large number of repetitive experiments for averaging noise reduction or statistical analysis, achieving "automated batch acquisition" without the need for the CPU to repeatedly issue start commands.

[0040] DMA Transfer Length: This parameter indicates the amount of data the DMA controller should move in each transfer operation, typically in bytes. It may be related to the "sample length," for example, DMA transfer length = sample length × number of channels × number of bytes per sample point. The DMA controller on the FPGA side reads this value from the configuration register before initiating a transfer. Properly setting this parameter is crucial for the efficiency and correctness of DMA transfers: it determines the size of the data block described by a single DMA descriptor. It must match the buffer size allocated in DDR by the CPU-side driver to prevent out-of-bounds transfers. Optimizing this parameter can match the maximum payload size of the PCIe bus, reducing transfer transaction overhead and thus improving overall transfer efficiency.

[0041] Example 2 This application proposes a data acquisition control method based on the PCIe bus-based AD acquisition system as described above, comprising the following steps: The CPU sends acquisition parameters to the acquisition configuration module on the FPGA via the PIO mode of the PCIe bus. The multi-channel AD acquisition module on the FPGA performs synchronous acquisition and digitization of multiple analog signals according to the acquisition parameters to obtain digitized acquisition data; The high-speed data transmission module buffers the digitized acquired data and converts it into an AXIS bus data stream; The FPGA side initiates DMA transfer through the PCIe bus control module, directly writing the data stream into the DDR memory on the CPU side; The CPU reads data directly from the DDR memory for processing.

[0042] Specifically, the acquisition parameters are distributed as follows: On the CPU side, the upper-layer application determines the requirements of this acquisition task (such as which channels need to work, the sampling rate, and the amount of data to be acquired), and generates a set of specific parameter values ​​(i.e., the parameters mentioned above). Then, the application initiates a configuration request by calling the interface functions provided by the device driver (such as ioctl or WriteRegister). The driver translates these parameter values ​​into write operations to specific memory addresses (i.e., virtual addresses mapped to the PCIe BAR0 space). These write operations are transmitted through the operating system kernel and the hardware abstraction layer, and finally delivered to the acquisition configuration module on the FPGA side via the PCIe bus memory write TLP transaction. This module latches these parameters into the corresponding configuration registers, completing the preparation of the hardware environment.

[0043] Specifically, synchronous acquisition and digitization: After parameter configuration, the CPU typically initiates acquisition by writing to a specific "start" or "trigger" register. The control logic state machine in the multi-channel AD acquisition module on the FPGA then transitions from an idle state to an active state. It uses a low-jitter clock generated by the MMCM to simultaneously drive all enabled ADC chips. Multiple analog signals are synchronously sampled and converted into digital signals. This step is executed entirely in parallel by hardware, with timing accuracy and synchronization guaranteed by the hardware circuitry itself, independent of CPU software timing, thus achieving "hard real-time" acquisition.

[0044] Specifically, data buffering and format conversion: The digital signal output by the ADC is sent to the high-speed data transmission module. This module first writes the data into the receive buffer FIFO. This buffering process resolves potential momentary mismatches between the production rate (ADC sampling rate) and the consumption rate (PCIe transfer rate). Then, the interface conversion unit reads the data from the FIFO and encapsulates it into a standard AXI4-Stream data stream. This process ensures full compatibility of the data with the interface protocol of the backend PCIe DMA IP core, preparing it for high-speed streaming.

[0045] Specifically, to initiate DMA transfer and data writing to DDR, the DMA control logic in the PCIe bus control module automatically starts when the amount of data in the FIFO reaches a preset threshold (or other start conditions are met, such as receiving a complete data frame), or the CPU sends a start command via PIO. The DMA controller obtains the target DDR address and transfer length from the configuration register, and then pushes the data to the PCIe IP core through the AXI4-Stream interface. The PCIe IP core packages the streaming data into a memory write TLP packet, and writes it directly to the predetermined area of ​​the CPU-side DDR memory through the PCIe x4 link. The entire process is "zero-copy," and the CPU does not need to participate in data transfer.

[0046] Specifically, for CPU data reading and processing: After the DMA transfer is complete, the FPGA can notify the CPU via an interrupt signal (such as MSI-X) or by polling the CPU status register. Once the CPU driver is aware that the data is ready, the upper-level application can directly access the memory buffer in DDR to read the collected data for subsequent analysis, display, storage, or further calculations. Because the data is already in kernel space or accessible in user space through mapping, the read operation latency is extremely low.

[0047] In a preferred embodiment, the step of sending out the collection parameters includes: The CPU configures the ADC's start / stop, sampling length, repetition count, and DMA transfer length by writing to a specified register in the PCIE BAR0 space.

[0048] Specifically, during the system design phase, a clear register mapping table needs to be defined in the FPGA logic for the BAR0 address space. This is a blueprint that maps software-readable and writable abstract parameters to hardware physical register addresses. For example: Offset address 0x00: ADC control register. Among them, bits [7:0] are the channel enable bit mask, and bit 31 is the global start / stop bit.

[0049] Offset address 0x04: Sample length register. A 32-bit register used to set the frame length in units of sample points.

[0050] Offset address 0x08: Sampling repetition count register. A 32-bit register used to set the number of automatic repetition samplings.

[0051] Offset address 0x0C: DMA transfer length register. A 32-bit register used to set the number of bytes in a single DMA transfer.

[0052] In a preferred embodiment, the step of initiating DMA transfer includes: The CPU sets the DMA transfer length and sends an enable signal. The DMA controller on the FPGA then transmits the AXIS data stream to the DDR on the CPU in burst mode through the PCIE BAR1 space.

[0053] Specifically, the CPU sets parameters and issues an enable signal: Setting the DMA transfer length: This operation is a crucial preparatory step before DMA transfer. The CPU driver writes a specific value to the DMA transfer length register mapped in the BAR0 space on the FPGA side via PIO mode. This value defines the total amount of data expected to be transferred in a single DMA transfer transaction, in bytes. The calculation formula is typically: DMA transfer length = sampling frame length (number of sampling points) × number of active channels × number of bytes per sampling point. For example, for 1024 points, 4 channels, and 16 bits (2 bytes) per sampling point, the transfer length is 8192 bytes. This parameter is critical; it ensures that the FPGA-side DMA engine and the CPU-side memory buffer have a shared and accurate expectation of the amount of data to be transferred, preventing incomplete or out-of-bounds data transfer.

[0054] Specifically, issuing a DMA enable signal: This is usually not a standalone signal, but rather achieved by writing to a specific bit in a DMA control register. For example, after configuring all parameters (including the DMA target DDR address, transfer length, etc.), the driver writes a 1 to the "start bit" (e.g., bit 0) of the DMA control register. This write operation itself is the "enable signal." In more complex systems, a "DMA descriptor" mechanism might be used. The CPU prepares a linked list of descriptors in DDR, each descriptor containing the target address, transfer length, and control flags, and then informs the DMA engine of the address of the first descriptor by writing to a register; this write operation also acts as an enable signal.

[0055] Specifically, the FPGA-side DMA controller's response and data transfer: DMA controller response: The FPGA-side DMA processing unit (typically part of a Xilinx CDMA or XDMA IP core) continuously monitors its control registers. When it detects that the "start bit" is set, or receives a descriptor pointer, it enters the working sequence from the idle state. It first retrieves the key parameters for this transfer (destination address, transfer length) from the configuration register or descriptor. Then, it checks the amount of data in the receive buffer FIFO of the high-speed data transfer module. A common strategy is to initiate an efficient transfer only when the amount of data in the FIFO accumulates to an integer multiple of the maximum payload size of the PCIe bus, or to initiate it immediately after receiving a complete frame of data (controlled by the sample length).

[0056] Specifically, burst transfer via the BAR1 space: This is the core action of data transfer. Through the PCIe BAR1 space: The BAR1 space defines a large address window. The target address generated by the DMA controller falls within this window. When the DMA controller pushes data to the PCIe IP core via the AXI4-Stream interface, it carries this target address information. The PCIe IP core then generates a Memory Write TLP packet pointing to the BAR1 space range based on this address. Burst transfer: This is the efficient operating mode of the PCIe bus. The DMA controller does not transfer byte by byte, but rather combines multiple double words (DWORDs) of data into a single TLP packet. A TLP packet can carry up to 4KB of valid data. This method of packaging large amounts of data into a single transaction greatly reduces the proportion of transaction header overhead in the total transfer time, thereby significantly improving the actual utilization of the bus—the advantage of burst transfer.

[0057] DDR data transferred to the CPU: After receiving these TLP packets pointing to BAR1, the PCIe root complex on the host side does not send them to a physical 2MB hardware memory. Instead, it dynamically remaps the bus address (address within the BAR1 window) in the TLP to the physical address of the actual buffer in DDR according to the address translation table (IOMMU) pre-configured by the driver, thus writing the data directly to the correct memory location. After this step, the data travels directly from the FPGA's FIFO to the CPU-accessible system memory, achieving "zero copy".

[0058] In a preferred embodiment, the method uses an asynchronous FIFO to perform clock domain isolation and data buffering of the ADC acquisition data and the AXIS bus timing in the data path on the FPGA side.

[0059] Specifically, the construction of an asynchronous FIFO: In FPGA design, an asynchronous FIFO is typically instantiated by calling an IP core provided by the FPGA vendor (such as Xilinx's FIFO Generator). Key settings when configuring this IP core include: Interface clock: Explicitly specifies that the write clock and read clock are two asynchronous clock sources.

[0060] Bit width and depth: Set the data bit width (e.g., 16 bits) and the storage depth of the FIFO (e.g., 1024 cells). The depth needs to be calculated to ensure that it can smoothly handle the largest short-term differences in clock rates at both ends.

[0061] Handshake signals: status flags such as enable write, write full, read enable, and read empty.

[0062] The working principle is described as follows: An asynchronous FIFO typically uses dual-port Block RAM as its storage medium. Write operations are performed in the write clock domain: when wr_en is valid and the FIFO is not full, data is written to the FIFO on the rising edge of the write clock. Read operations are performed in the read clock domain: when rd_en is valid and the FIFO is not empty, data is read on the rising edge of the read clock. The core technology lies in its pointer synchronization mechanism. The write pointer and read pointer increment in their respective clock domains. To safely transmit pointer information between different clock domains to determine the empty / full status, Gray code is typically used to encode the pointers before synchronization. Gray code is characterized by only one bit change between adjacent values, which minimizes the risk of metastability during cross-clock domain transmission, thus reliably generating the empty / full flag.

[0063] Specific role in the data path: Clock domain isolation: In this system, the clock for ADC data acquisition (write clock) is typically generated by the FPGA's MMCM based on an external crystal oscillator, with a frequency matching the ADC sampling rate (e.g., 125MHz). The clock for the AXIS bus interface (read clock), however, is typically from the same source as the PCIe IP core's user-side clock (e.g., 250MHz). These two clocks have different frequencies and uncertain phase relationships, representing typical asynchronous clock domains. Directly connecting these two parts would lead to metastability and data errors. The asynchronous FIFO, located between these two clock domains, acts as a safe "isolation chamber," ensuring that write and read operations follow their respective clocks, perfectly resolving the clock domain crossover problem.

[0064] Data Buffer: In addition to isolating the clock domain, the asynchronous FIFO is also an important data buffer. It can absorb rate fluctuations between data production (ADC acquisition) and data consumption (PCIe transmission). For example, when a brief congestion occurs at the back end of the PCIe bus, causing a temporary halt in reading, the ADC data at the writing end can still be continuously written to the FIFO without loss. As long as the FIFO depth is designed reasonably and is not filled during the congestion period, the system can safely weather the congestion period and continue transmission after the bus recovers, thus ensuring data continuity and integrity.

[0065] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. The above descriptions are only preferred embodiments of this application. It should be noted that due to the limitations of written expression, while there are objectively infinite specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, changes, or combinations, or the direct application of the inventive concept and technical solution to other situations without modification, should all be considered within the scope of protection of this application.

Claims

1. An AD acquisition system based on a PCIe bus, characterized in that, include: The multi-channel AD acquisition module is used to synchronously acquire and digitize multiple analog signals to obtain digitized data. A high-speed data transmission module is used to cache and convert the digitized acquired data using DMA. The PCIE bus control module is used to establish a high-bandwidth data path between the FPGA and the CPU through the PCIE bus, and to manage the interaction of DMA transfer and control commands. The acquisition configuration module is used to receive configuration parameters from the CPU and dynamically configure the multi-channel AD acquisition module and the high-speed data transmission module. The multi-channel AD acquisition module, the high-speed data transmission module, and the acquisition configuration module are integrated on the FPGA side, and interact with the CPU side through the PCIE bus control module for data and instruction exchange.

2. The AD acquisition system based on the PCIe bus according to claim 1, characterized in that: The multi-channel AD acquisition module includes: The analog front-end circuit supports multiple differential inputs and integrates a programmable gain amplifier and overvoltage protection circuit. A high-precision ADC array, composed of multiple ADC chips, is used for high-speed parallel sampling of multi-channel input signals; The FPGA control logic is used to generate a low-jitter sampling clock and convert the digital signals acquired by the ADC chip into AXIS bus timing data.

3. The AD acquisition system based on the PCIe bus according to claim 1, characterized in that: The high-speed data transmission module includes: A receive buffer FIFO is used to temporarily store the digitized acquisition data output by the multi-channel AD acquisition module; An interface conversion unit is used to encapsulate the data in the receive buffer FIFO into a data stream conforming to the AXIS bus timing. The DMA processing unit is used to directly transfer the packaged data stream to the CPU's DDR memory in burst mode via the PCIe bus, achieving zero-copy transfer.

4. The AD acquisition system based on the PCIe bus according to claim 1, characterized in that: The PCIe bus control module includes: The PCIE IP core provides AXI4-STREAM and AXI4-LITE user interfaces and is mapped to the BAR0 and BAR1 address spaces; The PIO read / write control unit receives configuration commands from the CPU via the AXI4-LITE bus and the BAR0 space. The DMA read / write control unit, through the AXI4-STREAM bus and BAR1 space, completes high-speed data flow transmission from the FPGA to the CPU.

5. The AD acquisition system based on the PCIe bus according to claim 4, characterized in that: The PCIe bus adopts an x4 lane configuration with a maximum link rate of no less than 5GT / s; the BAR0 space is used to transmit control commands and has a size of 4KB; the BAR1 space is used to transmit acquired data and has a size of 2MB.

6. The AD acquisition system based on the PCIe bus according to claim 1, characterized in that: The acquisition configuration module receives configuration parameters through the PIO mode of the PCIe bus. These parameters include: ADC enable signal, sampling length, number of sampling repetitions, and DMA transfer length.

7. A data acquisition control method for an AD acquisition system based on a PCIe bus as described in any one of claims 1-6, characterized in that, Includes the following steps: The CPU sends acquisition parameters to the acquisition configuration module on the FPGA via the PIO mode of the PCIe bus. The multi-channel AD acquisition module on the FPGA performs synchronous acquisition and digitization of multiple analog signals according to the acquisition parameters to obtain digitized acquisition data; The high-speed data transmission module buffers the digitized acquired data and converts it into an AXIS bus data stream; The FPGA side initiates DMA transfer through the PCIe bus control module, directly writing the data stream into the DDR memory on the CPU side; The CPU reads data directly from the DDR memory for processing.

8. The data acquisition and control method according to claim 7, characterized in that: The steps for distributing the collection parameters include: The CPU configures the ADC's start / stop, sampling length, repetition count, and DMA transfer length by writing to a specified register in the PCIE BAR0 space.

9. The data acquisition and control method according to claim 7, characterized in that: The steps for initiating DMA transfer include: The CPU sets the DMA transfer length and sends an enable signal. The DMA controller on the FPGA then transmits the AXIS data stream to the DDR on the CPU in burst mode through the PCIE BAR1 space.

10. The data acquisition and control method according to claim 7, characterized in that: The method describes using an asynchronous FIFO in the FPGA data path to perform clock domain isolation and data buffering between the ADC acquisition data and the AXIS bus timing.

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