Fast low leakage SRAM cell

Abstract

Fast low leakage SRAM cells, e.g., for digital display systems, are disclosed herein. In one embodiment, a bit memory circuit includes a latch coupled between a supply voltage and ground, and first to fourth transistors. The latch may include a pair of cross-coupled inverters having a first inverter and a second inverter. The first transistor may selectively couple the first inverter to the supply voltage based at least in part on a first control signal. The second transistor may selectively couple an input of the first inverter to ground based at least in part on a second control signal different from the first control signal. The third transistor may selectively couple the second inverter to the supply voltage based at least in part on the second control signal. The fourth transistor may selectively couple an input of the second inverter to ground based at least in part on the first control signal.

Description

Technical Field

[0001] This disclosure generally relates to bit storage devices and associated devices, systems, and methods. For example, several embodiments described in detail below relate to fast, low-leakage static random access memory (SRAM) cells, such as for digital displays and / or display pixel circuitry systems. Background Technology

[0002] SRAM cells are essential components in digital displays, providing a fast and reliable way to store pixel data. Each SRAM cell typically contains a transistor configured to hold a single data bit and directly control the state of the corresponding pixel. In digital displays such as LCDs and OLEDs, SRAM cells are used to maintain the on or off state of individual pixels, ensuring the display of correct image or video frames. Unlike Dynamic RAM (DRAM), SRAM does not require constant refreshing, making it ideal for applications where fast access to and stability of the stored data are critical, especially in high-performance graphics or real-time image processing.

[0003] SRAM cells are valued for their low latency data retrieval and high speed, enabling displays to reproduce images smoothly and without delay. These characteristics make SRAM cells the preferred choice for devices requiring fast response times, such as smartphones, tablets, and high-resolution monitors. The stable storage capacity of SRAM cells helps ensure consistent pixel performance, thereby improving the overall quality of digital displays. Summary of the Invention

[0004] In this example, a bit storage circuit is described. The bit storage circuit includes: a latch coupled between a power supply voltage and ground, wherein the latch includes a pair of cross-coupled inverters having a first inverter and a second inverter; a first transistor coupled between the first inverter and the power supply voltage; a second transistor coupled between the input of the first inverter and ground; a third transistor coupled between the second inverter and the power supply voltage; and a fourth transistor coupled between the input of the second inverter and ground. The first transistor is configured to selectively couple the first inverter to the power supply voltage, at least partially based on a first control signal; the second transistor is configured to selectively couple the input of the first inverter to ground, at least partially based on a second control signal different from the first control signal; the third transistor is configured to selectively couple the second inverter to the power supply voltage, at least partially based on the second control signal; and the fourth transistor is configured to selectively couple the input of the second inverter to ground, at least partially based on the first control signal.

[0005] In this example, a bit storage circuit is described. The bit storage circuit includes: a first inverter; a second inverter having (i) an input coupled to the output of the first inverter and (ii) an output coupled to the input of the first inverter; a first transistor configured to selectively couple the first inverter to a power supply voltage; a second transistor configured to selectively couple the first inverter to ground; a third transistor configured to selectively couple the first inverter to the second transistor; a fourth transistor configured to selectively couple the second inverter to the power supply voltage; a fifth transistor configured to selectively couple the second inverter to ground; and a sixth transistor configured to selectively couple the second inverter to the fifth transistor.

[0006] In this example, a method is described. The method includes writing to a latch of a bit storage circuit. Writing to the latch includes: selectively coupling the input of a first inverter of the latch and the output of a second inverter of the latch to ground, such that the input of the first inverter and the output of the second inverter are pulled down toward a first voltage; and at least when the input of the first inverter is selectively coupled to ground, disabling or weakening the pull-up branch of the second inverter, wherein the pull-up branch of the second inverter extends between a power supply voltage and the second inverter. Attached Figure Description

[0007] The following description, with reference to the figures, outlines non-limiting and non-exhaustive embodiments of the present technology, wherein similar or analogous reference numerals are used throughout to refer to similar or analogous components unless otherwise specified.

[0008] Figure 1 This is a partial schematic diagram of a digital display system configured according to various embodiments of the present technology.

[0009] Figure 2 yes Figure 1 A partial schematic diagram of the display pixel array of a digital display system.

[0010] Figure 3 This is a partial schematic diagram of a bit storage circuit configured according to various embodiments of the present technology.

[0011] Figure 4 This is a partial schematic diagram of another storage circuit configured according to various embodiments of the present technology.

[0012] Figure 5 These are exemplary timing diagrams of bit storage circuits according to various embodiments of the present technology.

[0013] Figure 6This is a diagram illustrating various embodiments of the present technology in the unselected rows. Figure 4 A graph showing the voltage levels at the inverter output of the bit storage circuit.

[0014] Figure 7 This is a partial schematic diagram of another bit of storage circuit configured according to various embodiments of the present technology.

[0015] Those skilled in the art will understand that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be enlarged relative to other elements to aid in understanding various aspects of the art. Furthermore, common but well-known elements or methods that are useful or necessary in commercially viable embodiments are generally not depicted in the figures or described in detail below to avoid unnecessarily obscuring the description of various aspects of the art. Detailed Implementation

[0016] This disclosure generally relates to bit storage devices and associated apparatuses, systems, and methods. For example, several embodiments described herein relate to fast, low-leakage SRAM cells for display pixels and / or digital display systems. As specific examples, several embodiments of the technology relate to SRAM cells that can reduce or minimize current leakage through transistors without compromising speed. Such cells may include latches and multiple transistors forming both pull-down and pull-up paths. In the following description, specific details are set forth to provide a thorough understanding of various aspects of the technology. However, those skilled in the art will recognize that the systems, apparatuses, and techniques described herein can be practiced without the one or more of the specific details set forth herein, or using other methods, components, materials, etc.

[0017] Throughout this specification, references to "example" or "embodiment" indicate that a particular feature, structure, or characteristic described in connection with the example or embodiment is included in at least one example or embodiment of the present technology. Therefore, the phrases "for example," "as an example," or "an embodiment" as used herein do not necessarily all refer to the same example or embodiment and are not necessarily limited to the specific example or embodiment discussed. Furthermore, the features, structures, or characteristics of the present technology described herein can be combined in any suitable manner to provide further examples or embodiments of the present technology.

[0018] For ease of description, spatial relative terms (e.g., “below,” “under,” “above,” “below,” “over,” “upper,” “top,” “top,” “left,” “right,” “center,” “middle,” etc.) are used herein to describe the relationship of an element or feature relative to one or more other elements or features illustrated in the figures. It will be understood that, in addition to the orientations described in the figures, spatial relative terms are intended to encompass different orientations of the device or system during use or operation. For example, if the device or system illustrated in the figures is rotated, turned, or flipped about a horizontal axis, then an element or feature described as “below,” “under,” or “below” one or more other elements or features may be oriented “above” one or more other elements or features. Therefore, the exemplary terms “below” and “below” are non-limiting and can encompass both above and below orientations. Alternatively or additionally, the device or system may be oriented in other ways illustrated in the figures (e.g., rotated 90 degrees about a vertical axis, or otherwise), and the spatial relative descriptors used herein shall be interpreted accordingly. Additionally, it will be understood that when an element is referred to as being “between” two other elements, the element may be the only element between the two other elements, or there may be one or more intervening elements.

[0019] It will be understood that while the terms first, second, third, etc., may be used in this disclosure and claims to describe various elements, these elements should not be limited by these terms and should not be used to determine the process sequence or formation order of related elements. Unless otherwise indicated, these terms are used only to distinguish one element from another. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the disclosed embodiments.

[0020] Several technical terms are used throughout this specification. These terms will be given their general meaning in the field of their respective domains, unless otherwise specifically defined herein or the context in which they are used will clearly imply otherwise. It should be noted that in this document, component names and symbols are used interchangeably (e.g., Si and silicon); however, they have the same meaning.

[0021] A. Overview

[0022] As discussed above, many digital display systems employ bit memory circuitry (e.g., SRAM cells) to maintain the on or off state of individual pixels, ensuring the display of correct image or video frames. While these digital display systems offer excellent image and video display capabilities, a limitation of such systems is that common bit memory circuitry, especially SRAM cells in modern high-resolution displays, is susceptible to leakage current. Leakage occurs when unwanted current flows through transistors, even when the cell is not being actively accessed. This can lead to poor power efficiency, as leakage increases power consumption, which is particularly problematic in battery-powered devices such as smartphones and tablets. With the increasing demand for higher display resolutions and densities, minimizing leakage in bit memory circuitry / SRAM cells has become crucial for improving energy efficiency and extending battery life. To date, attempts to provide digital display systems with low leakage have resulted in compromise solutions that do not meet speed, size, and / or other design / performance requirements.

[0023] It should be understood that bit storage circuits configured according to various embodiments of the present technology solve at least some of the problems discussed above. For example, the bit storage circuits disclosed herein (e.g., SRAM cells) may include transistors that can selectively disconnect (or weaken, but not completely disconnect) the pull-up path between the power supply voltage and the latch, for example, while writing to the latch. Disconnecting or weakening the pull-up path while writing to the latch can prevent or at least reduce the effect of old data stored in the latch competing with new data written to the latch. In some embodiments, the bit storage circuit further includes diodes or transistors that can conduct current between the power supply voltage and the latch to compensate for (or replace) current leaking from the latch.

[0024] Therefore, as will be shown and described in the various examples below, bit storage circuits configured according to various embodiments of the present technology may include a latch coupled between a power supply voltage and ground, and first to fourth transistors. The latch may include a pair of cross-coupled inverters having a first inverter and a second inverter. The first transistor may selectively couple the first inverter to the power supply voltage, at least partially based on a first control signal. The second transistor may selectively couple the input of the first inverter to ground, at least partially based on a second control signal different from the first control signal. The third transistor may selectively couple the second inverter to the power supply voltage, at least partially based on the second control signal. The fourth transistor may selectively couple the input of the second inverter to ground, at least partially based on the first control signal. In some embodiments, the bit storage circuit further includes one or more diodes and / or transistors coupled in parallel with the first transistor or the third transistor between the power supply voltage and the first inverter or the second inverter.

[0025] This technology is expected to offer several advantages. For example, the bit storage circuitry of this technology is expected to prevent old data written to the latch from competing with (or at least reduce) new data written to the latch. As another example, during a write operation of the bit storage circuitry of this technology, the transistor coupled between the power supply voltage and the inverter of the bit storage circuitry can be selectively disabled to break (or at least weaken) the pull-up path between the power supply voltage and the inverter. Breaking or weakening the pull-up path during a write operation is expected to reduce the power consumption of the bit storage circuitry and / or increase the speed at which data is written to the bit storage circuitry. In addition, the bit storage circuitry of this technology is expected to compensate (or replace) leakage current from unselected latches during write operations to prevent write interference. For example, the bit storage circuitry of this technology may include a diode or a biased transistor that conducts current between the power supply voltage and the corresponding latch to compensate for current leakage from the latch.

[0026] B. Selected embodiments of bit storage circuits and associated devices, systems, and methods

[0027] Figure 1 This is a partial schematic diagram of a digital display system 100 (“System 100”) configured according to various embodiments of the present technology. System 100 includes a controller 101, a timing generator 102, a first frame buffer 104, a second frame buffer 106, a data buffer 108, a bit line adjuster 110, a row decoder 112, a column decoder 114, and a display pixel array 116. It should be understood that in other embodiments, System 100 may omit one or more of the illustrated components and / or include additional components.

[0028] Controller 101 may be coupled to receive timing signals from timing generator 102 and may be configured to use those timing signals to (a) coordinate the transfer of video data to frame buffers 104 and 106, and (b) drive the pixels of display pixel array 116 to display an image corresponding to the video data. For example, controller 101 may "set" (e.g., turn on) and "clear" (e.g., turn off or reset) each pixel of the display (e.g., such that each pixel is turned on for a portion of a predetermined frame time). The amount of time a particular pixel is turned on may be based on the value of a corresponding multi-bit intensity value stored in frame buffers 104 or 106.

[0029] The first frame buffer 104 and the second frame buffer 106 can each be configured to receive entire video data frames and are used alternately by the controller 101. For example, while a video data frame from the first frame buffer 104 is being used (e.g., by the controller 101) to determine the signal asserted on the display pixel array 116, a subsequent video data frame can be loaded into the second frame buffer 106. Then, while a video data frame from the second frame buffer 106 is being used (e.g., by the controller 101) to determine the signal asserted on the display pixel array 116, another subsequent video data frame can be loaded into the first frame buffer 104, and so on.

[0030] In the illustrated embodiment, the display pixel array 116 is an m×n array of individual pixels, where m is the number of columns and n is the number of rows. The display pixel array 116 can display video (e.g., a fast-moving sequence of images) by activating individual pixels within a predetermined portion of a frame period corresponding to a specific desired intensity. Individual pixels can be turned on and off by latching data bits asserted on bit line 118 by bit line modulator 110. Pixels can be configured to latch data bits asserted on bit line 118 by a row enable signal from row decoder 112 and a column enable signal from column decoder 114.

[0031] Data buffer 108 can be configured to receive data bit rows, which, in the illustrated embodiment, turn individual pixels of display pixel array 116 on and off. Bit line adjuster 110 can be configured to (a) receive data bits in a low-power electrical state from data buffer 108 via data line 119, and (b) assert stronger signals onto bit line 118 and to display pixel array 116 depending on the value of the original data bits. References below Figures 2 to 7 The internal circuitry and operation of the display pixel array 116 are described in further detail.

[0032] In response to address and control signals from controller 101, row decoder 112 and column decoder 114 enable pixels in display pixel array 116 to latch data bits asserted on bit line 118 by data buffer 108 and bit line adjuster 110. To enable a specific pixel, both column decoder 114 and row decoder 112 must enable that specific pixel.

[0033] A line decoder 112 may be coupled between the controller 101 and the display pixel array 116, and may be configured to selectively assert line enable signals on word lines 120 of various pixel rows connected to the display pixel array 116. The line enable signal (also referred to herein as a “word line select signal WL” or “write enable signal WL”) enables each pixel of the selected row to load data bits asserted by the data buffer 108 on the corresponding bit line 118. More specifically, the line decoder 112 may receive a series of line addresses from the controller 101, and may sequentially assert line enable signals on the corresponding word line 120 for each received line address.

[0034] Column decoder 114 may be coupled between controller 101 and display pixel array 116 and may be configured to selectively assert column enable signals (also referred to herein as “set control signal S” and “clear control signal C”) on various pixel column lines 122 of display pixel array 116 in response to control signals from controller 101. In some embodiments, row decoder 112 may assert row enable signals on one word line 120 at a time, and column decoder 114 may assert control signals on some, all, or none of the pixel column lines 122 simultaneously. Although row enable signals are asserted by row decoder 112 on its word line 120, not asserting column enable signals on a particular pixel column line 122 may allow associated pixels of the enabled row to retain their previous data.

[0035] Figure 2 yes Figure 1 A partial schematic diagram of the display pixel array 116 of system 100 is shown. As illustrated, the display pixel array 116 includes a plurality of pixel units 230 (also referred to herein as “pixels 230” or “pixel circuits 230”) arranged in columns and rows, a common transparent electrode 229 overlaying the entire array 116 of pixels 230, a memory device 224, a processing unit 226, and a voltage controller 228. The memory device 224, the processing unit 226, and / or the voltage controller 228 may be mounted on or off-chip relative to the array 116 of pixels 230. It should be understood that in other embodiments, the display pixel array 116 may omit one or more of the illustrated components and / or include additional components.

[0036] In the illustrated embodiment, each of the pixels 230 is coupled to (i) a first power supply voltage V0 in the voltage controller 228, (ii) a second power supply voltage V1 in the voltage controller 228, (iii) a corresponding first bit line B+118a, (iv) a corresponding second bit line B–118b, and (v) a corresponding word line 120. As shown, pixels 230 in the same column can be coupled to the same first bit line in the first bit line B+118a and the same second bit line in the second bit lines B–118b, and pixels 230 in the same row can be coupled to the same word line in the word lines 120. In some embodiments, the pixels 230 are formed in an integrated monolithic silicon backplane, overlaid with a plurality of pixel mirrors. A layer of liquid crystal material can be interposed between the pixel mirrors and a common transparent electrode 229. The common transparent electrode 229 may be composed of indium tin oxide and / or other suitable materials and may be coupled to a common power supply voltage VC in the voltage controller 228.

[0037] As discussed in further detail herein, each of the pixels 230 may include bit storage circuitry (e.g., including SRAM cells or another type of memory element) that stores a single bit of information representing the on (e.g., active) or off (e.g., inactive) state of the pixel 230. The stored bit directly affects the brightness, color, and / or transparency of the pixel 230. By maintaining the pixel state even when not actively accessed, the bit storage circuitry ensures stable and continuous image reproduction.

[0038] The memory device 224 may include computer-readable media (e.g., RAM, ROM, etc.) having code or instructions (e.g., data and commands) embodied therein for causing the processing unit 226 to implement the various methods and driving schemes described herein. The processing unit 226 is capable of (i) receiving instructions from the memory device 224 (e.g., via a memory bus), (ii) providing internal voltage control signals to the voltage controller 228 (e.g., via a voltage control bus), and (iii) providing data control signals to the pixel 230 (e.g., via a data control bus).

[0039] In operation, data bit rows can be asserted on the first bit line B+118a and the second bit line B–118b, and an assertion on the word line 120 of a specific row can cause the asserted bits to be written into the pixels 230 in that row. In this way, data bits can be sequentially written to each pixel 230 of the entire display. In response to control signals received from the processing unit 226, the voltage controller 228 can provide a predetermined or variable voltage to the pixel 230 via a first power supply voltage V0 and a second power supply voltage V1. The voltage controller 228 can also assert a predetermined voltage on the common electrode 229 via a common power supply voltage VC. The processing unit 226 can provide control signals to the voltage controller 228 and / or directly to the pixel 230. For example, the processing unit 226 can provide set, clear, and / or other control signals to the transistors included in the bit storage circuitry of the pixel 230.

[0040] Figure 3 This is a partial schematic diagram of a bit storage circuit 330 configured according to various embodiments of the present technology. It should be understood that the bit storage circuit 330 may be included in... Figure 2 Examples of bit storage circuitry included in each of the pixels 230 and / or in other pixels configured according to various embodiments of the present technology. In some embodiments, bit storage circuitry 330 may include SRAM cells. For example, bit storage circuitry 330 may include a latch 340 coupled between a first power supply voltage V1 (hereinafter referred to as "VDD" for example and clarity) and a second power supply voltage V0 (hereinafter referred to as "ground" for example and clarity). Bit storage circuitry 330 may further include a first pull-down branch 331 coupled between latch 340 and ground, a second pull-down branch 333 coupled between latch 340 and ground, a first pull-up branch 351 coupled between VDD and latch 340, and a second pull-up branch 353 coupled between VDD and latch 340.

[0041] In the illustrated embodiment, latch 340 includes a pair of cross-coupled inverters. The pair of cross-coupled inverters includes a first inverter 341 and a second inverter 343. The first inverter 341 includes transistors 342 and 346, input j, and output h. The second inverter 343 includes transistors 344 and 348, input i, and output k.

[0042] Referring to the first inverter 341, transistor 342 has a source coupled to ground, a drain coupled to output h and to the drain of transistor 346, and a gate coupled to input j and to the gate of transistor 346. Additionally, transistor 346 includes a source coupled to VDD. In some embodiments, transistor 342 is an NMOS transistor, and transistor 346 is a PMOS transistor.

[0043] Referring now to the second inverter 343, transistor 344 has a source coupled to ground, a drain coupled to output k and coupled to the drain of transistor 348, and a gate coupled to input i and coupled to the gate of transistor 348. Additionally, transistor 348 includes a source coupled to VDD. In some embodiments, transistor 344 is an NMOS transistor, and transistor 348 is a PMOS transistor. Furthermore, the input i of the second inverter 343 may be coupled to the output h of the first inverter 341 at the first latch node 345a (“first node 345a”), and the output k of the second inverter 343 may be coupled to the input j of the first inverter 341 at the second latch node 345b (“second node 345b”).

[0044] The first pull-down branch 331 of the bit storage circuit 330 may include transistors 332 and 336. In the illustrated embodiment, transistor 332 includes a source coupled to ground, a drain coupled to the source of transistor 336, and a terminal coupled to receive a setting control signal S (e.g., from...). Figure 1 and 2 The gate of transistor 332 (one of the first lines B+118a) is such that transistor 332 can selectively couple transistor 336 to ground at least partially based on the state of control signal S. Additionally, transistor 336 includes a drain coupled to the input j of the first inverter 341, the gates of transistors 342 and 346 of the first inverter 341, and the output k of the second inverter 343. Transistor 336 further includes a gate coupled to receive a row enable signal WL, such that transistor 336 can selectively couple the input j of the first inverter 341 to transistor 332 and / or ground (via transistor 332) at least partially based on the state of the row enable signal WL. In some embodiments, transistors 332 and 336 may be NMOS transistors.

[0045] The second pull-down branch 333 of the bit storage circuit 330 is similar to the first pull-down branch 331. For example, the second pull-down branch 333 may include transistors 334 and 338. In the illustrated embodiment, transistor 334 includes a source coupled to ground, a drain coupled to the source of transistor 338, and a source coupled to receive a clear control signal C (e.g., from...). Figure 1 and 2The gate of one of the second bit lines B–118b is provided, such that transistor 334 can selectively couple transistor 338 to ground at least partially based on the state of control signal C. Additionally, transistor 338 includes the gate of transistors 344 and 348 of the second inverter 343 coupled to the input i of the second inverter 343, and the drain of the output h of the first inverter 341. Transistor 338 further includes a gate coupled to receive a row enable signal WL, such that transistor 338 can selectively couple the input i of the second inverter 343 to transistor 334 and / or ground (via transistor 334) at least partially based on the state of the row enable signal WL (e.g., received at the gate terminal of transistor 338). In some embodiments, transistors 334 and 338 may be NMOS transistors.

[0046] In operation, control signals S and C, as well as the row enable signal WL, can be controlled to write data bits to bit storage circuit 330. For example, to set the data bit "1" to the first node 345a, the write enable signal WL and the control signal S can be asserted to activate transistors 336, 338, and 332, respectively. It should be understood that at any given time, only one of the control signals S or C can be asserted. Therefore, when the control signal S is asserted, the control signal C can be deasserted, causing transistor 334 to be deactivated. As a result of the activation of transistors 332 and 336, the input j of the first inverter 341 can be coupled to ground via the first pull-down branch 331. Accordingly, a low voltage level at ground can deactivate transistor 342 (e.g., an NMOS transistor) and activate transistor 346 (e.g., a PMOS transistor). By activating transistor 346, the output h of the first inverter 341 can be coupled to VDD, thereby pulling the first node 345a and the input i of the second inverter 343 towards a high voltage level of VDD using the first pull-up branch 351. As input i is pulled high, transistor 344 (e.g., an NMOS transistor) of the second inverter 343 can be activated and transistor 348 (e.g., a PMOS transistor) of the second inverter 343 can be deactivated. By activating transistor 344, the output k of the second inverter 343 can be coupled to ground, thereby pulling the second node 345b and the input j of the first inverter 341 towards a low voltage level of ground. In this way, the latch 340 of the bit storage circuit 330 can be written such that the voltage at the first node 345a is in a first state (e.g., a high voltage state, or "1") and the voltage at the second node 345b is in a second state (e.g., a low voltage state, or "0").

[0047] The bit storage circuit 330 can operate in a similar manner to set the data bit "0" onto the first node 345a (e.g., to reset or clear the latch 340). More specifically, the write enable signal WL and the control signal C can be asserted to activate transistors 336, 338, and 334, respectively. As discussed above, in some embodiments, only one of the control signals S or C can be asserted at any given time. Therefore, when the control signal C is asserted, the control signal S can be deasserted, causing transistor 332 to be deactivated. As a result of the activation of transistors 334 and 338, the input i of the second inverter 343 can be coupled to ground via the second pull-down branch 333. Accordingly, a low voltage level at ground can deactivate transistor 344 (e.g., an NMOS transistor) and activate transistor 348 (e.g., a PMOS transistor). By activating transistor 348, the output k of the second inverter 343 can be coupled to VDD, thereby pulling the second node 345b and the input j of the first inverter 341 towards a high voltage level of VDD using the second pull-up branch 353. As input j is pulled high, transistor 342 (e.g., an NMOS transistor) of the first inverter 341 can be activated and transistor 346 (e.g., a PMOS transistor) of the first inverter 341 can be deactivated. By activating transistor 342, the output h of the first inverter 341 can be coupled to ground, thereby pulling the first node 345a and the input i of the second inverter 343 towards a low voltage level of ground. In this way, the latch 340 of the bit storage circuit 330 can be written (e.g., reset or cleared) such that the voltage at the first node 345a is in a second state (e.g., a low voltage state, or "0") and the voltage at the second node 345b is in a first state (e.g., a high voltage state, or "1").

[0048] Figure 4 This is a partial schematic diagram of another storage circuit 430 configured according to various embodiments of the present technology. It should be understood that the bit storage circuit 430 may be included in... Figure 2 Examples of bit storage circuitry in each of the pixels 230 and / or other bit storage circuitry configured according to various embodiments of the present technology. In some embodiments, bit storage circuitry 430 may include SRAM cells. For example, bit storage circuitry 430 may include a latch 440 coupled between VDD and ground, a first pull-down branch 431 and a second pull-down branch 433 coupled between latch 440 and ground, and a first pull-up branch 451 and a second pull-up branch 453 coupled between VDD and latch 440.

[0049] As shown, latch 440, first pull-down branch 431 and second pull-down branch 433 may be structurally and / or functionally similar to those described above. Figure 3The latch 340, first pull-down branch 331, and second pull-down branch 333 of the bit storage circuit 330 are identical (or at least substantially similar). For example, latch 440 includes a pair of cross-coupled inverters. The pair of inverters includes a first inverter 441 with transistors 442 and 446 having their drains coupled to each other, and a second inverter 443 with transistors 444 and 448 having their drains coupled to each other. The sources of transistors 442 and 444 may be coupled to ground. The first pull-down branch 431 includes transistors 432 and 436, and the second pull-down branch 433 includes transistors 434 and 438.

[0050] In some embodiments, the transistors 442, 446, 444, 448, the first pull-down branch 431, and / or the second pull-down branch 433 of the latch 440 may include low-leakage transistors (e.g., low-leakage high threshold voltage transistors (LLHVT) or ultra-high threshold voltage transistors (UHVT)). However, low-leakage transistors are generally associated with longer lengths and slower operating times compared to other types of transistors. Therefore, in some embodiments, the transistors 442, 446, 444, and / or 448, the first pull-down branch 431, and / or the second pull-down branch 433 of the latch 440 do not include low-leakage transistors, such that these transistors meet the size, speed, and / or other constraints of the bit storage circuit 430.

[0051] and Figure 3 The bit storage circuit 330 is different. Figure 4The first pull-up branch 451 of the bit storage circuit 430 includes (i) a transistor 452 that selectively couples a first inverter 441 (more specifically, the source of transistor 446) to VDD, at least in part based on the state of a control signal C applied to the gate of transistor 452, and (ii) a diode 456. In the illustrated embodiment, diode 456 is a transistor having a gate coupled to its drain. Transistor 452 and diode 456 may be coupled in parallel between VDD and the first inverter 441 (more specifically, coupled to the source of transistor 446). Similarly, the second pull-up branch 453 of the bit storage circuit 430 includes (i) a transistor 454 that selectively couples a second inverter 443 (more specifically, transistor 448) to VDD, at least in part based on a control signal S applied to the gate of transistor 454, and (ii) a diode 458. In the illustrated embodiment, diode 458 is a transistor having a gate coupled to its drain. Transistor 454 and diode 458 may be coupled in parallel between VDD and the second inverter 443 (more specifically, coupled to the source of transistor 448). As shown, transistor 452 can be activated when transistor 434 is deactivated (e.g., at least in part based on the state of control signal C), and transistor 454 can be activated when transistor 432 is deactivated (e.g., at least in part based on the state of control signal S).

[0052] In some embodiments, transistors 452, 454, diode 456, and / or diode 458 comprise PMOS transistors. In some embodiments, diode 456 and / or diode 458 comprise high-leakage transistors or low-threshold transistors (e.g., LLHVT, UHVT). In these and other embodiments, diodes 456 and / or 458 may be configured to conduct a subthreshold current that is greater than the turn-off current of other transistors in the bit storage circuit 430 (e.g., transistor 442 and / or transistor 444). For example, diode 456 and / or diode 458 may comprise a transistor with a threshold voltage lower than the threshold voltage of one or more other transistors in the bit storage circuit 430 (e.g., transistor 452 and / or transistor 454). As another example, diode 456 and / or diode 458 may comprise a transistor having a shorter length than one or more other transistors in the bit storage circuit 430 (e.g., transistor 452 and / or transistor 454).

[0053] The bit storage circuit 430 can be connected with Figure 3 The bit storage circuit 330 operates in a largely similar manner, with a few exceptions related to the first pull-up branch 451 and the second pull-up branch 453. For the sake of illustration, let's return to the reference for now. Figure 3When the data bit "1" is set on the first node 345a, the write enable signal and control signal S can be asserted, and the control signal C can be deasserted to pull the first node 345a up toward VDD and pull the second node 345b down toward ground. However, before the write operation, the voltage level on the first node 345a may have been grounded, thus activating transistor 348 via input i of the second inverter 343. Since the transistors of latch 340 are activated by the voltage levels of the first node 345a and the second node 345b, there may be a delay in correctly writing the asserted data bit. For example, when the control signal S goes high, although the voltage level on the second node 345b may eventually stabilize to ground, the initially or previously activated transistor 348 may temporarily provide a pull-up path for the second node 345b, causing the voltage level at the second node 345b to be pulled in the opposite direction (at least temporarily): pulled up by transistor 348 and pulled down by transistors 332 and 336. Similarly, when the clear signal C is asserted, the voltage level at the first node 345a can be pulled in the opposite direction (at least temporarily): pulled up by transistor 346 and pulled down by transistors 334 and 338. Therefore, Figure 3 The bit storage circuit 330 is susceptible to competition between old data stored in latch 340 and new data written to latch 340, which can lead to increased power consumption and / or slower access / write times.

[0054] Return to reference Figure 4The transistors 452 and 454 of the bit storage circuit 430 are intended to address this issue. More specifically, when latch 440 is written to set the data bit "1" to the first node 445a, the write enable signal WL and control signal S can be asserted, and control signal C can be deasserted. Therefore, the input j of the first inverter 441 can be pulled down towards ground via the first pull-down branch 431. Additionally, asserting the control signal S disables transistor 454 (e.g., a PMOS transistor) in the second pull-up branch 453. Therefore, the second pull-up branch 453 can be cut off (or at least weakened) so that transistor 448 of the second inverter 443 is not coupled to VDD via transistor 454 and / or coupled to VDD via (e.g., only) diode 458. (In some embodiments, the pull-up path provided by diodes 456, 458 may be minimal or negligible. In other embodiments, diodes 456, 458 are omitted.) Therefore, although the voltage level on the first node 445a immediately preceding the write (set) operation may be low enough to activate transistor 448 (e.g., a PMOS transistor), transistor 454 of the second pull-up branch 453 can be deactivated when the control signal S is asserted. This means that input j can be pulled down toward ground more quickly and / or more easily (via transistors 436, 432) because the pull-up toward VDD at output k is cut off or weakened. In other words, cutting off / weakening the second pull-up branch 453 during a write (set) operation reduces, minimizes, and / or eliminates the competition between old data stored in latch 440 and new data written to latch 440.

[0055] A similar process occurs when latch 440 is written to clear / reset the voltage on first node 445a to data bit "0". More specifically, the write enable signal WL and control signal C are asserted and control signal S is deasserted. Therefore, input i of second inverter 443 can be pulled down towards ground via second pull-down branch 433. Additionally, asserting control signal C disables transistor 452 (e.g., a PMOS transistor) in first pull-up branch 451. Therefore, first pull-up branch 451 can be cut off (or at least weakened) so that transistor 446 of first inverter 441 is not coupled to VDD via transistor 452 and / or coupled to VDD via (e.g., only) diode 456. (In some embodiments, the pull-up path provided by diodes 456, 458 may be minimal or negligible. In other embodiments, diodes 456, 458 are omitted.) Therefore, although the voltage level at the second node 445b immediately preceding the write (reset / clear) operation may be low enough to activate transistor 446 (e.g., a PMOS transistor), transistor 452 of the first pull-up branch 451 can be deactivated when the control signal C is asserted. This means that the input i of the second inverter 443 can be pulled down toward ground more quickly and / or more easily (via transistors 438, 434) because the pull-up toward VDD at the output h of the first inverter 441 is cut off or weakened. In other words, cutting off / weakening the first pull-up branch 451 during a write (clear / reset) operation reduces, minimizes, and / or eliminates the competition between old data stored in latch 440 and new data written (reset / clear) to latch 440.

[0056] Figure 5 These are exemplary timing diagrams for controlling bit storage circuits according to various embodiments of the present technology. Figure 5 The timing diagram can be Figure 3 Bit storage circuit 330, Figure 4 Bit storage circuit 430, Figure 7 Exemplary timing diagrams of the bit storage circuit and / or other bit storage circuits configured according to various embodiments of the present technology. For example, the illustrated timing diagram graphically represents the write enable signal WL of row n, the write enable signal WL of the adjacent row (row n+1), the control signal S on column m, and the control signal C on column m during write operations and clear / reset operations of row n. As discussed in further detail herein, Figure 5 The timing diagram can illustrate the method of writing to and / or clearing a latch (e.g., latch 440) for a bit storage circuit (e.g., bit storage circuit 430).

[0057] In the illustrated embodiment, a method for writing to the latch is shown between time t1 and time t4. As illustrated, during the entire duration between time t1 and time t4, the control signal C for column m and the write enable signal WL for row n+1 remain deasserted. Furthermore, at time t1, the control signal S can be asserted for column m. As previously mentioned, the control signal S can be shared across the entire column m. Thus, the control signal S can be asserted in multiple bit storage circuits arranged in the same column m but located in different rows. Asserting the control signal S may involve activating one or more transistors in one or more pull-down branches of the bit storage circuit.

[0058] Writing to the latch may further include, at time t1, cutting off or weakening the pull-up branch of the bit storage circuit (e.g., Figure 4 The second pull-up branch 453). In some embodiments, cutting off or weakening the pull-up branch of the bit storage circuit includes applying an asserted control signal S to the gate of a transistor (e.g., transistor 454) in the pull-up branch of the bit storage circuit (e.g., causing the transistor to be deactivated).

[0059] At time t2, an assertion can be made for the write enable signal WL for row n. (See reference) Figure 4 For illustrative purposes, asserting the write enable signal WL when the control signal S is also asserted can selectively couple the input of the first inverter of the latch (e.g., the input j of the first inverter 441) and the output of the second inverter (e.g., the output k of the second inverter 443) to a first voltage (e.g., ground), such that the input of the first inverter and the output of the second inverter are pulled down toward the first voltage.

[0060] In some embodiments, writing to the latch further includes, at time t2 or later, selectively coupling the output of the first inverter of the latch (e.g., output h) and the input of the second inverter (e.g., input i) to a second voltage (e.g., VDD), such that the output of the first inverter and the input of the second inverter are pulled up toward the second voltage, which is greater than the first voltage.

[0061] At time t3, the write enable signal WL can be deasserted for row n. Deasserting the write enable signal WL may involve selectively decoupling the input of the first inverter and the output of the second inverter from the first voltage.

[0062] At time t4, the control signal S can be de-asserted for column m. De-asserting the control signal S reactivates the transistors in the pull-up branches of the bit storage circuit. Alternatively, de-asserting the control signal S deactivates one or more transistors in one or more pull-down branches of the bit storage circuit.

[0063] Although Figure 5 The write enable signal WL is shown as being asserted (a) after the control signal S is asserted and (b) before the control signal S is deasserted, but this technique is not limited to this. For example, in other embodiments of this technique, the write enable signal WL may be asserted before or simultaneously with the control signal S. As another example, in other embodiments of this technique, the write enable signal WL may be deasserted after or simultaneously with the control signal S.

[0064] In the illustrated embodiment, a latch reset or clear is shown between time t5 and time t8. As illustrated, during the entire duration between time t5 and time t8, the control signal S for column m and the write enable signal WL for row n+1 remain deasserted. Furthermore, at time t5, the control signal C can be asserted for column m. As previously mentioned, the control signal C can be shared across the entire column m. Thus, the control signal C can be asserted in multiple bit storage circuits arranged in the same column m but located in different rows. Asserting the control signal C may involve activating one or more transistors in one or more pull-down branches of the bit storage circuit.

[0065] Clearing the latch may further include, at time t5, cutting off or weakening the pull-up branch of the bit storage circuit (e.g., the first pull-up branch 451). In some embodiments, cutting off or weakening the pull-up branch of the bit storage circuit includes applying an asserted control signal C to the gate of a transistor (e.g., transistor 452) in the pull-up branch of the bit storage circuit (e.g., causing the transistor to be deactivated).

[0066] At time t6, an assertion can be made for the write enable signal WL for row n. (See reference) Figure 4 For illustrative purposes, asserting the write enable signal WL when the control signal C is also asserted can selectively couple the input of the second inverter and the output of the first inverter to a first voltage (e.g., ground), such that the input of the second inverter and the output of the first inverter are pulled down toward the first voltage.

[0067] In some embodiments, clearing the latch further includes, at time t6 or later, selectively coupling the input of the first inverter and the output of the second inverter to a second voltage (e.g., VDD), such that the input of the first inverter and the output of the second inverter are pulled up toward a second voltage greater than the first voltage.

[0068] At time t7, the write enable signal WL can be deasserted for row n. Deasserting the write enable signal WL may involve selectively decoupling the input of the second inverter and the output of the first inverter from the first voltage.

[0069] At time t8, the control signal C can be de-asserted for column m. De-asserting the control signal C reactivates the transistors in the pull-up branches of the bit storage circuit. Alternatively, de-asserting the control signal C deactivates one or more transistors in one or more pull-down branches of the bit storage circuit.

[0070] As discussed above, the write enable signal WL for row n+1 can remain deasserted during the write operation and / or clear / reset operation of row n, effectively deselecting row n+1 for write and clear / reset operations. However, as previously mentioned, control signals S and C can still be applied to the bit storage circuitry located in the unselected row n+1 within column m. Therefore, one or more pull-up branches in the bit storage circuitry of unselected row n+1 and column m can be cut off or weakened during write and clear / set operations on the bit storage circuitry of row n and column m. Therefore, asserting the control signals S and / or C on the bit storage circuitry of row n+1 and column m without asserting the write enable signal WL for row n+1 can lead to write interference problems on this bit storage circuitry, especially when current leaks from the transistors of the latches in this bit storage circuitry. Diodes (e.g., diodes 456, 458) in the pull-up branches of this bit storage circuitry are expected to mitigate (e.g., reduce, minimize, and / or eliminate) the write interference problem.

[0071] More specifically, Figure 6 This is a diagram illustrating the unselected rows (e.g., lines) of various embodiments according to the present technology. Figure 5 The second inverter 443 in row n+1) Figure 4 A graph showing the voltage level at output k. (Return to reference for now.) Figure 4During write operations to bit storage circuits in the row adjacent to and in the same column as bit storage circuit 430, the second pull-up branch 453 can be cut off / weakened via an assertion of the control signal S of the column. During this time, current can leak through transistor 444 of latch 440. In the absence of diode 458 in the second pull-up branch 453, when current leaks from latch 440 through transistor 444, the current on latch 440 will not be replenished via transistor 448 because (although activated), the second pull-up branch 453 will be decoupled from VDD when transistor 454 is deactivated. Therefore, leakage current can compromise the integrity of data stored in bit storage circuit 430. For example, if the voltage on second node 445b is initially high (e.g., "1") at the start of a write operation, then the leakage current from transistor 444 can lower the voltage on second node 445b toward the voltage of transistor 446 that activates first inverter 441 and deactivates transistor 442. This is caused by Figure 6 Curve 610 illustrates this. As the voltage on the second node 445b drops below the threshold voltage of transistors 446 and 442 of the first inverter 441, the voltage value on the first node 445a can be flipped from low (e.g., "0") to high, while the voltage value on the second node 445b can be flipped from high to low, thereby destroying the data stored on the latch 440.

[0072] However, the presence of diode 458 in the second pull-up branch 453 is expected to reduce, minimize, and / or eliminate this problem. More specifically, during the period when transistor 454 is deactivated, diode 458 is expected to conduct a certain amount of subthreshold current. Therefore, the current conducted through diode 458 is expected to supplement the current of latch 440 via transistor 448 to compensate for the current leaking from transistor 444, thereby stopping the voltage drop on the second node 445b. This is due to Figure 6 Curve 620 is shown. Therefore, diode 458 in the second pull-up branch 453 of bit memory circuit 430 is expected to reduce, minimize, and / or eliminate the risk of write interference on bit memory circuit 430 while writing to other bit memory circuits in the same column. Diode 556 in the first pull-up branch 451 of bit memory circuit 430 is expected to provide similar benefits during reset / clear operations of other bit memory circuits in the same column.

[0073] For completeness, return to Figure 6In the diagrammatic discussion, in the embodiment where the bit storage circuit 430 omits diodes 456 and 458, the first curve 610 represents the voltage level at either (i) the output h of the first inverter 441 (for reset / clear operations of other bit storage circuits in the same column) or (ii) the output k of the second inverter 443 (for write operations of other bit storage circuits in the same column). Conversely, in the embodiment including the bit storage circuit 430 with diodes 456 and 458, the second curve 620 represents the voltage level at either (i) the output h of the first inverter 441 (for reset / clear operations of other bit storage circuits in the same column) or (ii) the output k of the second inverter 443 (for write operations of other bit storage circuits in the same column). Figure 6 As shown, each of curves 610 and 620 indicates that the corresponding latch node initially stores approximately 720mV (at or before time x), which in some embodiments may correspond to a data bit "1". At time x, control signal S or control signal C is asserted (thereby cutting off or weakening the pull-up branch of bit storage circuit 430), while write enable signal WL is deasserted. Subsequently, leakage current from latch 440 causes the voltage level on the corresponding latch node to drop. As shown, the voltage drop and rate of voltage drop of the second curve 620 (in embodiments including diodes 456, 458) are significantly smaller than those of the first curve 610 (in embodiments omitting diodes 456, 458). In some embodiments, the voltage drop shown by the first curve 610 may be sufficient to toggle the state of latch 440, thereby causing data corruption. For curve 620, the amount of leakage from latch 440 is balanced by the amount of current supplemented into latch 440 via diodes 456 and / or 458 at a voltage level that does not toggle the state of latch 440 (e.g., approximately 550 mV in the illustrated embodiment). Alternatively, the amount of current supplemented into latch 440 via diodes 456 and / or 458 extends the amount of time it takes for the voltage to drop to a level that toggles the state of latch 440. This extension ensures that write or clear / reset operations of other bit memory circuits in the same column end before the voltage drops to a level that toggles the state of latch 440.

[0074] Figure 7 This is a partial schematic diagram of another storage circuit 730 configured according to various embodiments of the present technology. It should be understood that the bit storage circuit 730 may be included in... Figure 2Examples of bit storage circuitry in each of the pixels 230 and / or other bit storage circuitry configured according to various embodiments of the present technology. In some embodiments, bit storage circuitry 730 may include SRAM cells. For example, bit storage circuitry 730 may include a latch 740 coupled between VDD and ground, a first pull-down branch 731 and a second pull-down branch 733 coupled between latch 740 and ground, and a first pull-up branch 751 and a second pull-up branch 753 coupled between VDD and latch 740.

[0075] As shown, latch 740, first pull-down branch 731, and second pull-down branch 733 can be respectively structurally and / or functionally related to Figure 4 The latch 440, first pull-down branch 431, and second pull-down branch 433 of the bit storage circuit 430 are the same or substantially similar. For example, latch 740 includes a pair of cross-coupled inverters. The pair of inverters includes a first inverter 741 having transistors 742 and 746 and a second inverter 743 having transistors 744 and 748. First pull-down branch 731 includes transistors 732 and 736, and second pull-down branch 733 includes transistors 734 and 738.

[0076] In some embodiments, the transistors of latch 740, the first pull-down branch 731, and / or the second pull-down branch 733 may include low-leakage transistors (e.g., low-leakage high threshold voltage transistors (LLHVT) or ultra-high threshold voltage transistors (UHVT)). However, low-leakage transistors are typically associated with longer lengths and slower operating times compared to other types of transistors (e.g., conventional transistors). Therefore, in some embodiments, transistors 742, 746, 744, 748 of latch 740, the first pull-down branch 731, and / or the second pull-down branch 733 do not include low-leakage transistors, such that these transistors meet the size, speed, and / or other constraints of the bit storage circuit 730.

[0077] as Figure 4 The bit storage circuit 430 has a first pull-up branch 751 comprising a transistor 752 (e.g., a PMOS transistor) that selectively couples a first inverter 741 to VDD at least partially based on the state of a control signal C applied to the gate of transistor 752, and a second pull-up branch 753 comprising a transistor 754 that selectively couples a second inverter 743 to VDD at least partially based on the state of a control signal S applied to the gate of transistor 754. However, with Figure 4Unlike the bit storage circuit 430, the first pull-up branch 751 includes a transistor 756 instead of a diode, having a gate coupled to receive a bias voltage PBias, and the second pull-up branch 753 includes a transistor 758, having a gate coupled to receive a bias voltage (e.g., bias voltage PBias or another bias voltage level). Transistor 756 couples a first inverter 743 (more specifically, the source of transistor 746) to VDD, and transistor 758 couples a second inverter 743 (more specifically, the source of transistor 748) to VDD.

[0078] In operation, the bias voltage PBias applied to the gates of transistors 756 and 758 allows a certain amount of current to be conducted through them. The bias voltage PBias can be set at a level such that the amount of current conducted through transistors 756 and 758 is approximately 20 nA, which is greater than the amount of current leaking from the corresponding one of the first inverter 741 and the second inverter 743. Therefore, similar to... Figure 4 The diodes 456 and 458, and the transistors 756 and 758 are expected to provide a solution to the leakage current / write interference problem described above.

[0079] Therefore, refer back to the above reference. Figure 5 The method described in the timing diagram may further include conducting current between VDD and one of the first and second inverters via (a) a diode (e.g., one of diodes 456 and 458) or (b) a transistor having a gate coupled to receive a bias voltage (e.g., one of transistors 756 and 758) when (i) a write enable signal WL applied to the gate of the corresponding transistor (e.g., transistors 436 and 438) is deasserted and (ii) a control signal S or a control signal C is asserted. In some embodiments, the conduction current includes an amount of current conducted between VDD and the second inverter that is equal to or greater than the amount of current leaking from the latch.

[0080] D. in conclusion

[0081] The above detailed description of embodiments of this technology is not intended to be exhaustive or to limit the technology to the precise forms disclosed above. While specific embodiments and examples of this technology have been described above for illustrative purposes, those skilled in the art will recognize that various equivalent modifications can be made within the scope of this technology. For example, although the steps are presented in a given order above, alternative embodiments may perform the steps in a different order. Furthermore, the various embodiments described herein may be combined to provide further embodiments.

[0082] Based on the foregoing, it will be understood that specific embodiments of the present technology have been described herein for illustrative purposes, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of embodiments of the present technology. To the extent that any material incorporated herein by reference conflicts with this disclosure, this disclosure shall prevail. Where the context permits, singular or plural terms may also contain plural or singular terms, respectively. Furthermore, unless the word “or” is expressly limited to referring only to a single item excluding other items when referring to a list of two or more items, its use in this list shall be construed as including (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Moreover, as used herein, the phrase “and / or” in “A and / or B” means only A, only B, and both A and B. Furthermore, throughout the text, the terms “comprising,” “including,” “having,” and “with” are used to mean that at least the described feature is included, without excluding any larger number of the same feature and / or other features of additional types. The phrases “about” or “substantially” will be interpreted as values ​​included within ±10% of the provided values. Additionally, as used herein, the phrases “based on,” “depending on,” “as a result of,” and “in response to” should not be interpreted as references to a closed set of conditions. For example, an exemplary step described as “based on condition A” may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase “based on” should be interpreted in the same manner as the phrases “based at least in part on” or “based at least partially on.” Moreover, the terms “connection” and “coupling” are used interchangeably herein and refer to both direct and indirect connection or coupling. For example, where the context permits, "connected" or "coupled" to element B can mean (i) A is directly "connected" or directly "coupled" to B and / or (ii) A is indirectly "connected" or indirectly "coupled" to B.

[0083] Based on the foregoing, it will also be understood that various modifications can be made without departing from this disclosure or the present technology. For example, those skilled in the art will understand that various components of the present technology can be further divided into sub-components, or various components and functions of the present technology can be combined and integrated. Additionally, in other embodiments, specific aspects of the present technology described in the context of a particular embodiment can be combined or eliminated. Furthermore, while advantages associated with specific embodiments of the present technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments necessarily need to exhibit such advantages to fall within the scope of the present technology. Therefore, this disclosure and related technologies may encompass other embodiments not explicitly shown or described herein.

Claims

1. A bit storage circuit, comprising: A latch coupled between a power supply voltage and ground, the latch including a pair of cross-coupled inverters having a first inverter and a second inverter; A first transistor is coupled between the first inverter and the power supply voltage, and the first transistor is configured to selectively couple the first inverter to the power supply voltage, at least in part, based on a first control signal. A second transistor is coupled between the input of the first inverter and ground, and the second transistor is configured to selectively couple the input of the first inverter to ground, at least in part, based on a second control signal different from the first control signal; A third transistor is coupled between the second inverter and the power supply voltage, the third transistor being configured to selectively couple the second inverter to the power supply voltage, at least in part, based on the second control signal; and A fourth transistor, coupled between the input of the second inverter and ground, is configured to selectively couple the input of the second inverter to ground, at least in part, based on the first control signal.

2. The bit storage circuit of claim 1, further comprising a diode, wherein the diode and the first transistor are coupled in parallel between the first inverter and the power supply voltage.

3. The bit storage circuit of claim 2, wherein the diode comprises a PMOS transistor having (i) a source terminal, (ii) a drain terminal, and (iii) a gate coupled to the drain terminal.

4. The bit storage circuit of claim 2, wherein the diode comprises a low-threshold or high-leakage transistor.

5. The bit storage circuit of claim 2, wherein the diode comprises a transistor with a length less than that of the first transistor.

6. The bit storage circuit of claim 2, wherein the diode comprises a transistor having a threshold voltage lower than the threshold voltage of the first transistor.

7. The bit storage circuit of claim 2, wherein the diode is a first diode, wherein the bit storage circuit further includes a second diode, and wherein the second diode and the third transistor are coupled in parallel between the second inverter and the power supply voltage.

8. The bit storage circuit of claim 1, further comprising a fifth transistor, wherein the fifth transistor and the first transistor are coupled in parallel between the first inverter and the power supply voltage.

9. The bit storage circuit of claim 8, wherein the fifth transistor includes a gate coupled to receive a bias voltage.

10. The bit storage circuit of claim 9, wherein the fifth transistor is configured to conduct a current greater than the leakage current from the first inverter between the power supply voltage and the first inverter immediately after receiving the bias voltage at the gate.

11. The bit storage circuit of claim 10, wherein the current is approximately 20 nA.

12. The bit storage circuit of claim 8, further comprising a sixth transistor, wherein the sixth transistor and the third transistor are coupled in parallel between the second inverter and the power supply voltage, and wherein the sixth transistor includes a gate coupled to receive a bias voltage.

13. The bit storage circuit according to claim 1, wherein: The first inverter includes a fifth transistor and a sixth transistor; The fifth transistor includes a source coupled to the first transistor and (a) a diode or (b) a transistor having a gate coupled to receive a bias voltage, a gate coupled to the input of the first inverter, and a drain coupled to the output of the first inverter. The diode or the transistor is coupled in parallel with the first transistor between the power supply voltage and the first inverter; and The sixth transistor includes the drain of the fifth transistor and the drain of the output of the first inverter, a source coupled to ground, and a gate coupled to the input of the first inverter.

14. The bit storage circuit according to claim 13, wherein: The second inverter includes a seventh transistor and an eighth transistor; The seventh transistor includes a source coupled to the third transistor and coupled to (a) another diode or (b) another transistor having a gate coupled to receive the bias voltage, a gate coupled to the input of the second inverter, and a drain coupled to the output of the second inverter; The other diode or the other transistor is coupled in parallel with the third transistor between the power supply voltage and the second inverter; and The eighth transistor includes the drain of the seventh transistor and the drain of the output of the second inverter, a source coupled to ground, and a gate coupled to the input of the second inverter.

15. The bit storage circuit of claim 1, further comprising a fifth transistor coupled between the second transistor and the input of the first inverter, the fifth transistor being configured to selectively couple the second transistor to the input of the first inverter based at least in part on a third control signal different from the first control signal and the second control signal.

16. The bit storage circuit of claim 15, further comprising a sixth transistor coupled between the fourth transistor and the input of the second inverter, the sixth transistor being configured to selectively couple the fourth transistor to the input of the second inverter at least in part based on the third control signal.

17. The bit storage circuit according to claim 15, wherein the first control signal is a set control signal, the second control signal is a clear control signal, and the third control signal is a word line selection control signal.

18. The bit storage circuit of claim 1, wherein the bit storage circuit comprises a static random access memory unit.

19. A bit storage circuit, comprising: First inverter; A second inverter has (i) an input coupled to the output of the first inverter and (ii) an output coupled to the input of the first inverter; A first transistor is configured to selectively couple the first inverter to a power supply voltage; A second transistor is configured to selectively couple the first inverter to ground; A third transistor is configured to selectively couple the first inverter to the second transistor; A fourth transistor, configured to selectively couple the second inverter to the power supply voltage; A fifth transistor, configured to selectively couple the second inverter to ground; and A sixth transistor, configured to selectively couple the second inverter to the fifth transistor.

20. The bit storage circuit of claim 19, further comprising a diode, wherein the diode and the first transistor are coupled in parallel between the power supply voltage and the first inverter.

21. The bit storage circuit of claim 20, wherein the diode is a first diode, wherein the bit storage circuit further includes a second diode, and wherein the second diode and the fourth transistor are coupled in parallel between the power supply voltage and the second inverter.

22. The bit storage circuit of claim 19, further comprising a seventh transistor, wherein the seventh transistor and the first transistor are coupled in parallel between the power supply voltage and the first inverter, and wherein the gate of the seventh transistor is coupled to receive a bias voltage.

23. The bit storage circuit of claim 22, wherein the bias voltage is a first bias voltage, wherein the bit storage circuit further includes an eighth transistor, wherein the eighth transistor and the fourth transistor are coupled in parallel between the power supply voltage and the second inverter, and wherein the gate of the eighth transistor is coupled to receive a second bias voltage.

24. The bit storage circuit of claim 19, wherein the first transistor and the fifth transistor are configured such that the first transistor and the fifth transistor are activated and deactivated together.

25. The bit storage circuit of claim 24, wherein the second transistor and the fourth transistor are configured such that the second transistor and the fourth transistor are activated and deactivated together.

26. The bit storage circuit of claim 19, wherein the gate of the first transistor and / or the gate of the fifth transistor are coupled to receive a first control signal, and wherein the gate of the second transistor and / or the gate of the fourth transistor are coupled to receive a second control signal different from the first control signal.

27. A method comprising: Writing to the latch of the bit storage circuit, wherein writing to the latch includes— Selectively couple the input of the first inverter of the latch and the output of the second inverter of the latch to ground, such that the input of the first inverter and the output of the second inverter are pulled down toward a first voltage. At least when the input of the first inverter is selectively coupled to ground, the pull-up branch of the second inverter is cut off or weakened, wherein the pull-up branch of the second inverter extends between the power supply voltage and the second inverter.

28. The method of claim 27, wherein writing to the latch further comprises, at least when the input of the first inverter and the output of the second inverter are selectively coupled to ground, selectively coupling the output of the first inverter and the input of the second inverter to the power supply voltage, such that the output of the first inverter and the input of the second inverter are pulled up toward a second voltage greater than the first voltage.

29. The method of claim 27, wherein selectively coupling the input of the first inverter and the output of the second inverter to ground comprises (i) asserting a first control signal applied to the gate of the first transistor of the bit storage circuit, and (ii) asserting a write enable signal applied to the gate of the second transistor of the bit storage circuit, wherein the first transistor and the second transistor are coupled in series between the input of the first inverter and ground.

30. The method of claim 29, wherein cutting off or weakening the pull-up branch of the second inverter comprises asserting the first control signal applied to the gate of a third transistor of the bit storage circuit, wherein the third transistor is coupled in series between the power supply voltage and the second inverter.

31. The method of claim 29, further comprising conducting current between the power supply voltage and the second inverter via a diode or a transistor having a gate coupled to receive a bias voltage when (i) the write enable signal applied to the gate of the second transistor is not enabled and (ii) the second inverter is not selectively coupled to the power supply voltage by the pull-up branch of the second inverter.

32. The method of claim 31, wherein conducting the current includes a current quantity greater than the leakage current escaping from the second inverter that is conducted between the power supply voltage and the second inverter.

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