Calibration method, integrated circuit and memory device including same

Abstract

The invention provides a calibration method, an integrated circuit and a memory device. The calibration method includes outputting a second data clock obtained by compensating a first data clock based on a calibration signal and a first voltage; outputting a first pulse based on the first data clock and the second data clock; updating the control signal based on a reference voltage and the first pulse, the reference voltage being generated based on the control signal; outputting a third data clock obtained by compensating the first data clock based on the calibration signal and a second voltage smaller than the first voltage; outputting a second pulse based on the first data clock and the third data clock; and updating the calibration signal according to a reference voltage and a second pulse generated based on the updated control signal.

Description

Cross-references to related applications

[0001] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0158979, filed on November 11, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to calibration methods, integrated circuits, and memory devices including integrated circuits. Background Technology

[0003] The storage device receives and processes signals such as commands, addresses, and data from outside the memory. During the process of receiving and storing data from the outside, and outputting data to the outside, the storage device samples the data according to a data clock. At this time, a delay may occur in the data clock path (i.e., the path through which the data clock is transmitted within the storage device).

[0004] The power supply voltage required for operation can be supplied to the storage device from an external source. However, due to factors such as noise, the amplitude of the received power supply voltage may not remain constant. The magnitude of the delay in the data clock may vary depending on fluctuations in the power supply voltage received by the data clock path. Therefore, a compensation circuit exists on the data clock path to compensate for the differences in the magnitude of the delay in the data clock caused by power supply voltage fluctuations. However, due to factors such as the different sensitivities of each storage device to the power supply voltage, the degree of compensation may vary for each storage device. Summary of the Invention

[0005] One aspect of the present invention provides a calibration method.

[0006] The present invention also provides an integrated circuit capable of performing the calibration method.

[0007] The present invention also provides a storage device for applying an integrated circuit capable of performing the calibration method.

[0008] According to some embodiments of this disclosure, a calibration method is provided, comprising: outputting a second data clock obtained by compensating a first data clock based on a calibration signal and a first voltage; outputting a first pulse based on the first data clock and the second data clock; updating a control signal based on a reference voltage and the first pulse, the reference voltage being generated based on the control signal; outputting a third data clock obtained by compensating the first data clock based on the calibration signal and a second voltage smaller than the first voltage; outputting a second pulse based on the first data clock and the third data clock; and updating the calibration signal according to the reference voltage and the second pulse generated based on the updated control signal.

[0009] According to some embodiments of this disclosure, an integrated circuit is provided, comprising: a data clock path circuit configured to receive a first voltage, a first data clock, and a calibration signal, and configured to use the first voltage to compensate for a delay in the first data clock based on the calibration signal to output a second data clock; a comparison circuit configured to output a first pulse based on the first data clock and the second data clock; a reference voltage generation circuit configured to receive a control signal and configured to output a reference voltage based on the control signal; and a duty cycle monitor configured to compare the amplitude of the reference voltage with the duty cycle of the first pulse, and configured to output a first comparison signal corresponding to the comparison result of the amplitude of the reference voltage and the duty cycle of the first pulse.

[0010] According to some embodiments of this disclosure, a storage device is provided, comprising: a memory cell array configured to store data; a data clock path circuit configured to output a second data clock based on a first data clock and a first voltage, and configured to output a third data clock based on the first data clock and a second voltage smaller than the first voltage; a calibration circuit configured to determine a calibration signal based on the first data clock, the second data clock, and the third data clock; and a control logic circuit configured to provide the calibration signal to the data clock path circuit, wherein the data clock path circuit is configured to output a fourth data clock based on the first data clock and the calibration signal, and the control logic circuit is configured to write data to the memory cell array using the fourth data clock.

[0011] However, the aspects of the invention are not limited to those set forth herein. The above and other aspects of the invention will become more apparent to those skilled in the art from the following detailed description of the invention.

[0012] Detailed descriptions of other embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0013] Figure 1This is a diagram of a storage system according to some embodiments.

[0014] Figure 2 yes Figure 1 A block diagram of the storage device.

[0015] Figure 3 This is a block diagram of a data clock according to some embodiments.

[0016] Figure 4 This is a diagram of signals associated with a data clock according to some embodiments.

[0017] Figure 5 This is a block diagram of a circuit according to some embodiments, which implements a method for compensating for delays in the data clock.

[0018] Figure 6 This is a diagram illustrating the operation of a method for compensating for data clock delays according to some embodiments.

[0019] Figure 7 This is a block diagram of a calibration circuit according to some embodiments.

[0020] Figure 8 This is a flowchart of a calibration method according to some embodiments.

[0021] Figure 9 This is a block diagram of a circuit implementing a calibration method according to some embodiments.

[0022] Figure 10 This is a graph of signals according to a calibration method based on some embodiments.

[0023] Figure 11 This is a diagram of a circuit implementing a calibration method according to some embodiments.

[0024] Figure 12 This is a graph of signals according to a calibration method based on some embodiments.

[0025] Figure 13 This is a flowchart of a calibration method according to some embodiments.

[0026] Figure 14 This is a flowchart of a calibration method according to some embodiments.

[0027] Figure 15 It is a block diagram of an electronic device including a storage device with a calibration circuit applied according to some embodiments. Detailed Implementation

[0028] In the following description, embodiments of the technical concept according to the present invention are illustrated with reference to the accompanying drawings. Throughout this document, terms indicating sequence (e.g., first, second, etc.) are used to distinguish elements having the same / similar functions, and the ordinal numbers may be interchanged depending on the order in which the terms are mentioned. For clarity of this disclosure, parts irrelevant to the description will be omitted, and throughout the specification, the same elements or equivalents are referred to by the same reference numerals.

[0029] Figure 1 This is a diagram of the storage system.

[0030] refer to Figure 1 The storage system 1 may include a storage device 20 and a storage controller 10.

[0031] The storage controller 10 can control the overall operation of the storage device 20. For example, the storage controller 10 can control data exchange between the external device and the storage device 20. For example, the storage controller 10 can control the storage device 20 according to external requests, and can write or read data through the storage device 20.

[0032] The storage controller 10 and the storage device 20 can communicate with each other via a storage interface. Furthermore, the storage controller 10 and the host can communicate with each other via a host interface. That is, the storage controller 10 can coordinate signals between the storage device 20 and the host. The storage controller 10 can control the operation of the storage device 20 by applying commands (CMD) to control the storage device 20. Here, the storage device 20 may include dynamic storage cells. For example, the storage device 20 may include dynamic random access memory (DRAM), double data rate 4 (DDR4) synchronous DRAM (DDR4 SDRAM), DDR5 SDRAM, low power DDR4 (LPDDR4) SDRAM, LPDDR5 SDRAM, etc. However, embodiments according to the technical concept of the present invention are not limited thereto, and the storage device 20 may include a non-volatile storage device. However, in these embodiments, the storage device 20 will be described as a volatile storage device.

[0033] The storage controller 10 can send system clock CLK, data clock WCK, command CMD, address ADDR, power PWR, etc. to the storage device 20. The storage controller 10 can provide data DATA to the storage device 20 and can receive data DATA from the storage device 20. The storage device 20 may include a storage cell array 280 for storing data DATA, control logic circuitry 201, data input / output (I / O) buffers 295, etc.

[0034] Figure 2 yes Figure 1 A block diagram of the storage device.

[0035] refer to Figure 2 The storage device 20 may include control logic circuitry 201, address register 220, memory bank control logic circuitry 230, row address multiplexer (RA MUX) 240, refresh counter 242, refresh address generator 244, column address latch 250, row decoder 260, column decoder 270, memory cell array 280, sense amplifier unit 285, input / output (I / O) gate circuitry 290, and data input / output buffer 295.

[0036] The storage cell array 280 may include multiple storage cell arrays 280a to 280h. Although the storage cell array 280 is... Figure 2 The embodiment is shown as including eight memory arrays 280a to 280h, but the embodiment is not limited thereto.

[0037] Each of the multiple memory bank arrays 280a to 280h may include multiple word lines WL, multiple bit lines BL, and multiple memory cells MC formed at the intersection between the word lines WL and the bit lines BL.

[0038] The row decoder 260 may include multiple memory bank row decoders 260a to 260h, each electrically connected to multiple memory bank arrays 280a to 280h. The column decoder 270 may include multiple column decoders 270a to 270h, each electrically connected to multiple memory bank arrays 280a to 280h. The sense amplifier unit 285 may include multiple sense amplifiers 285a to 285h, each electrically connected to multiple memory bank arrays 280a to 280h.

[0039] Address register 220 can be accessed from the memory controller ( Figure 1 10) Receive address ADDR, where address ADDR includes the bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR. Address register 220 can provide the received bank address BANK_ADDR to the bank control logic circuit 230, the received row address ROW_ADDR to the row address multiplexer 240, and the received column address COL_ADDR to the column address latch 250.

[0040] The memory bank control logic circuit 230 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. In response to the memory bank control signal, the memory bank row decoders corresponding to the memory bank address BANK_ADDR among the multiple memory bank row decoders 260a to 260h can be activated, and the column decoders corresponding to the memory bank address BANK_ADDR among the multiple column decoders 270a to 270h can also be activated.

[0041] The refresh counter 242 can sequentially output the count row address CRA according to the control of the control logic circuit 201. For example, the control logic circuit 201 can generate a refresh count signal in response to a normal refresh command. The refresh counter 242 can perform a counting operation in response to the refresh count signal and output the count row address CRA. That is, the refresh counter 242 can output the refresh address used to perform a normal refresh operation.

[0042] The refresh address generator 244 can be provided with a bank address BANK_ADDR and a row address ROW_ADDR. The refresh address generator 244 can count the values ​​of the activated bank address BANK_ADDR and row address ROW_ADDR based on the bank address BANK_ADDR and row address ROW_ADDR. The refresh address generator 244 can generate a row address corresponding to a word line that has been activated a certain number of times based on the count value, or a row address corresponding to an adjacent word line, as a hammer address. That is, the refresh address generator 244 can output a refresh address for performing a target row refresh operation.

[0043] The refresh address generator 244 can output the count row address CRA or the hammer address as the refresh row address RRA.

[0044] The refresh counter 242 and the refresh address generator 244 can be implemented as separate configurations as shown in the figure, or they can be implemented as a single configuration. Alternatively, the refresh counter 242 and the refresh address generator 244 can be included in the control logic circuit 201.

[0045] The row address multiplexer 240 can receive the row address ROW_ADDR from the address register 220 and the refresh row address RRA from the refresh address generator 244. The row address multiplexer 240 can selectively output either the row address ROW_ADDR or the refresh row address RRA as the row address RA. The row address RA output from the row address multiplexer 240 can be applied to each of the multiple memory bank row decoders 260a to 260h.

[0046] Among the multiple bank row decoders 260a to 260h, the bank row decoder activated by the bank control logic circuit 230 can decode the row address RA output from the row address multiplexer 240 to activate the word line corresponding to that row address. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to that row address.

[0047] Column address latch 250 can receive column address COL_ADDR from address register 220 and temporarily store the received column address COL_ADDR. Column address latch 250 can incrementally increment the received column address COL_ADDR in burst mode. Column address latch 250 can apply the temporarily stored or incrementally incremented column address COL_ADDR to each of the multiple column decoders 270a to 270h.

[0048] Among the multiple column decoders 270a to 270h, the memory bank column decoder activated by the memory bank control logic circuit 230 can activate the sense amplifier corresponding to the memory bank address BANK_ADDR and the column address COL_ADDR through the corresponding input / output gate circuit 290.

[0049] The input / output gating circuit 290 may include input data masking logic, a read data latch for storing data output from multiple memory arrays 280a to 280h, a write driver for writing data to the multiple memory arrays 280a to 280h, and circuitry for gating the input / output data.

[0050] Data DQ to be read from one of the multiple memory arrays 280a to 280h can be detected by the sense amplifiers 285a to 285h corresponding to that memory array and stored in a read data latch. The data DQ stored in the read data latch can be synchronized with the data clock WCK through the data input / output buffer 295 and provided to the memory controller 10.

[0051] Data DQ to be written to one of the multiple memory bank arrays 280a to 280h can be synchronized with the data clock WCK through the data input / output buffer 295 and provided to the input / output gating circuit 290, and the input / output gating circuit 290 can write the data to one of the memory bank arrays through the write driver.

[0052] The control logic circuit 201 can control the operation of the storage device 20. For example, the control logic circuit 201 can generate control signals that cause the storage device 20 to perform a write operation or a read operation. The control logic circuit 201 may include a command decoder 202, which decodes the command CMD received from the storage controller 10.

[0053] According to some embodiments, the control logic circuit 201 may also include a data clock path (WCK path) 204 (also referred to as a data clock path circuit). Although the data clock path 204 is... Figure 2The data clock path 204 is shown as being included in the control logic circuitry 201, but according to an embodiment of the invention, it can be configured separately from the control logic circuitry 201. The control logic circuitry 201 receives the system clock CLK and the data clock WCK from the memory controller 10. The system clock CLK can be a clock used for processing commands CMD and addresses ADDR. The data clock WCK can be a clock used for processing data DATA. A delay may occur in the data clock WCK as it travels through the data clock path 204 of the memory device 20. Therefore, the data clock path 204 can reduce the impact of this delay by including a compensation circuit that can compensate for the delayed data clock WCK.

[0054] The memory cell MC can be, for example, a DRAM memory cell. The memory cell MC can be connected to each of a word line WL and a bit line BL. The memory cell MC can store charge through a cell capacitor. Due to leakage current caused by the structure of the memory cell MC, the memory cell MC may erase the data stored in the cell capacitor. Therefore, the storage device 20 can perform a refresh operation to recharge the data in the memory cell MC to prevent the data stored in the memory cell MC from being altered by leakage current.

[0055] Figure 3 This is a block diagram of the data clock. Figure 4 It is a diagram of signals associated with the data clock. In Figure 4 In the diagram, the x-axis of both graphs represents time, and the y-axis represents the logic value of the signal. For example, a state with a relatively large signal amplitude can be called logic high, and a state with a relatively small signal amplitude can be called logic low.

[0056] refer to Figure 3 and Figure 4 The storage device can receive an input data clock WCK_IN from an external source (e.g., a storage controller). The received data clock WCK_IN can be transmitted along data clock path 204. Data clock path 204 may include various circuitry and wiring, and delays may occur in the data clock WCK_IN as it is transmitted along this path.

[0057] The storage device can be supplied with the power supply voltages required for various operations of the storage device from an external source (e.g., a memory controller). For example, LPDDR5 SDRAM can be supplied with power supply voltages specified in the JEDEC specification for PDDR5 SDRAM, such as VDD1, VDD2H, VDD2L, and VDDQ. Data clock path 204 can output a data clock WCK_OUT, and the data clock WCK_OUT output by data clock path 204 can be a clock that exhibits a delay (with a delayed phase) in the data clock WCK_IN input to data clock path 204. The data clock WCK_OUT output by data clock path 204 may reduce the performance margin for data read and write operations.

[0058] Data clock path 204 can be provided with, for example, a first power supply voltage VDD2H, and the data clock WCK_OUT can be output using this first power supply voltage VDD2H. Incidentally, the first power supply voltage VDD2H received by data clock path 204 may be unstable due to reasons such as noise. Therefore, it may not be possible to consistently supply a power supply voltage with a specified operating voltage amplitude (e.g., 1.05V in the case of VDD2H according to the JEDEC specification), and the memory device may receive a power supply voltage that is smaller or larger (i.e., low or high) than the specified operating voltage at a particular moment. The higher the first power supply voltage VDD2H received by data clock path 204, the faster the circuit operation. Therefore, the delay of the data clock WCK_OUT output by data clock path 204 can be reduced. Conversely, the lower the first power supply voltage VDD2H received by data clock path 204, the slower the circuit operation. Therefore, the delay of the data clock WCK_OUT output by data clock path 204 can be increased. The difference in data clock delay caused by fluctuations in power supply voltage (e.g., the first power supply voltage VDD2H) is specified as tWK2DQI_volt in the JEDEC specification.

[0059] Figure 5 This is a block diagram of a circuit that implements a method for compensating for data clock delays. Figure 6 This is a diagram illustrating the operation of a method used to compensate for data clock delays. Figure 6 The x-axis of the graph represents the magnitude of the delay in the data clock by comparing the input data clock WCK_IN with the output data clock WCK_OUT, and the y-axis represents the number of storage devices. For ease of illustration, the magnitude of the delay in the data clock WCK will be expressed as tWCK2DQI_volt as specified in the JEDEC specification. However, the embodiment is not limited to this. In this example, tWCK2DQI_volt has units of [ps / 50mV], meaning that for every 50mV change in the supply voltage, there is a 1ps delay.

[0060] refer to Figure 5 and Figure 6 The data clock path 204 may include a buffer 205 and a compensation circuit 206. The buffer 205 may be, for example, various circuits included in the data clock path 204. The compensation circuit 206 may compensate for data clock delays occurring in the data clock path 204 based on the received calibration signal CAL_CODE. The compensation circuit 206 may be designed in various ways. For example, the compensation circuit 206 may adjust the delay occurring in the data clock WCK by adjusting the phase to reduce or increase the delay of the data clock WCK. For example, based on a specified operating voltage, the compensation circuit 206 may eliminate more delays in the data clock WCK when the amplitude of the received power supply voltage (e.g., the first power supply voltage VDD2H) is small, and eliminate less delays in the data clock WCK as the amplitude of the received power supply voltage (e.g., the first power supply voltage VDD2H) increases. In some embodiments, a delay can be added when the amplitude of the power supply voltage (e.g., the first power supply voltage VDD2H) received based on a specified operating voltage is large, and the delay can be eliminated when the amplitude of the power supply voltage (e.g., the first power supply voltage VDD2H) received based on a specified operating voltage is small. The design method of the compensation circuit 206 is not limited to the examples described above. That is, the compensation circuit 206 can reduce the delay difference (tWKK2DQI_volt) caused by fluctuations in the received power supply voltage. The calibration signal CAL_CODE can determine the amount of compensation for the data clock based on the amplitude of the power supply voltage received by the compensation circuit 206. In other words, the larger the amplitude of the calibration signal CAL_CODE, the more tWKK2DQI_volt can be reduced.

[0061] When the compensation circuit 206 compensates for the data clock WCK, ideally, tWKK2DQI_volt will be zero. In other words, the delay in the data clock will not be affected by the amplitude of the first supply voltage VDD2H. However, due to process variations (e.g., process inflection points) or various other reasons during the mass production of memory devices, the voltage sensitivity of each memory device may be different for each device. Therefore, tWCK2DQI_volt may vary for each memory device. Figure 6In the graph, tWCK2DQI_volt = 0 on the x-axis, meaning that the memory devices on the left have excessive compensation from the compensation circuit 206, while the memory devices on the right have insufficient compensation from the compensation circuit 206. Data read / write performance margin decreases not only when the compensation from the compensation circuit 206 is insufficient, but also when the compensation is excessive. Therefore, to eliminate variations in the tWCK2DQI_volt value for each memory device, an appropriate calibration signal CAL_CODE needs to be determined for each device.

[0062] Figure 7 This is a block diagram of a calibration circuit according to some embodiments.

[0063] refer to Figure 7 The calibration circuit 210 may include a data clock path 204, a comparator circuit 211, a reference voltage generation circuit 212, and a duty cycle monitor (DCM) 213. The data clock path 204 may receive an input data clock WCK_IN from an external source. For example, the data clock path 204 may receive the input data clock WCK_IN from a duty cycle fine-tuning oscillator in a memory controller or memory device. The data clock path 204 may receive a first power supply voltage VDD2H. The buffer 205 may be, for example, various circuits included in the data clock path 204. The amount of delay appearing in the data clock may vary depending on the amount of power supply voltage received by the data clock path 204. The compensation circuit 206 may be external (e.g., Figure 1 The control logic circuit 201 receives the calibration signal CAL_CODE. The calibration signal CAL_CODE determines the degree to which the compensation circuit 206 compensates for the data clock. The compensation circuit 206 can compensate for the data clock delay occurring in the data clock path 204 based on the received calibration signal CAL_CODE. The data clock path 204 can output an output data clock WCK_OUT whose delay has been compensated by the compensation circuit 206.

[0064] Comparator circuit 211 receives an input data clock WCK_IN and an output data clock WCK_OUT, and outputs a first pulse based on the input data clock WCK_IN and the output data clock WCK_OUT. The first pulse may, for example, be a pulse that is logic high during a delay period of the input data clock WCK_IN and logic low otherwise. Comparator circuit 211 can be implemented using, for example, an AND gate. When comparator circuit 211 is implemented using an AND gate, it receives the input data clock WCK_IN and a signal obtained by inverting the output data clock WCK_OUT, and can generate the first pulse by performing an AND operation on the input data clock WCK_IN and the received signal. However, this is merely an example, and comparator circuit 211 can be implemented in various ways and configurations.

[0065] The reference voltage generation circuit 212 may include a first resistor R1 and a second resistor R2. The reference voltage generation circuit 212 may receive a second power supply voltage VDD and a control signal R_CODE. The second power supply voltage VDD may be, for example, (but not limited to) one of the power supply voltages specified in the JEDEC specification of LPDDR5 SDRAM (such as VDD1, VDD2H, VDD2L, and VDDQ).

[0066] The first resistor R1 of the reference voltage generation circuit 212 can act as a variable resistor whose resistance is controlled by the control signal R_CODE. The reference voltage generation circuit 212 can, for example, adjust the resistance ratio of the first resistor R1 and the second resistor R2 by adjusting the value of the first resistor R1 according to the control signal R_CODE. The reference voltage generation circuit 212 can use the second power supply voltage VDD to generate a reference voltage based on the resistance ratio of the first resistor R1 and the second resistor R2.

[0067] The duty cycle monitor 213 receives a reference voltage from the reference voltage generation circuit 212 and a first pulse from the comparator circuit 211. The duty cycle monitor 213 compares the duty cycle of the received first pulse with the amplitude of the reference voltage and outputs a comparison signal DCM_OUT indicating the comparison result. The duty cycle is the proportion of time the signal is on within one cycle of the signal. If we assume the amplitude of the reference voltage received from the reference voltage generation circuit 212 is 0.4V and the duty cycle of the first pulse received from the comparator circuit 211 is 0.3V, then the duty cycle monitor 213 can output a logic high signal. Conversely, if we assume the amplitude of the reference voltage received from the reference voltage generation circuit 212 is 0.3V and the duty cycle of the first pulse received from the comparator circuit 211 is 0.4V, then the duty cycle monitor 213 can output a logic low signal.

[0068] Figure 8 This is a flowchart of a calibration method according to some embodiments. Figure 9 This is a block diagram of a circuit for implementing a calibration method according to some embodiments. Figure 10 This is a graph of signals according to a calibration method based on some embodiments. Figure 11 This is a diagram of a circuit for implementing a calibration method according to some embodiments. Figure 12 This is a graph of signals according to a calibration method based on some embodiments.

[0069] refer to Figures 1 to 12 The calibration method (S100) includes outputting a second data clock obtained by compensating for the first data clock (S110). For example, data clock path 204 receives the first data clock WCK1 and a first voltage V1, and compensation circuit 206 can output a second data clock WCK2, which is obtained by compensating for the delay caused by the data clock path 204 using the first voltage V1. Here, the first voltage V1 is, for example, the maximum operating voltage VDD2H specified in the JEDEC specification, and can be (but is not limited to) about 1.2V. Before this operation (S110), control logic circuit 201 can initialize the calibration signal CAL_CODE and the control signal R_CODE.

[0070] The calibration method (S100) includes outputting a first pulse based on a first data clock and a second data clock (S120). For example, the comparator circuit 211 may receive a first data clock WCK1 and a second data clock WCK2, and output a first pulse PULSE1 based on the first data clock WCK1 and the second data clock WCK2. The first pulse PULSE1 output by the comparator circuit 211 may be a pulse output by performing a bitwise AND operation on the signals obtained by inverting the first data clock WCK1 and the second data clock WCK2. The first pulse PULSE1 may be a pulse that is in a logic high state during the time period when the first data clock WCK1 is delayed (e.g., time period t1 and time period t2) and in a logic low state under other circumstances. The first pulse PULSE1 may be a pulse that is in a logic high state when the first data clock WCK1 is in a logic high state and the second data clock WCK2 is in a logic low state and in a logic low state under other circumstances.

[0071] The calibration method (S100) includes updating the control signal based on a reference voltage and a first pulse (S130). For example, the duty cycle monitor 213 can receive a reference voltage VREF according to the control signal R_CODE from the reference voltage generation circuit 212, and receive a first pulse PULSE1 from the comparison circuit 211. The duty cycle monitor 213 can compare the amplitude of the received reference voltage VREF with the duty cycle DC_PULSE1 of the first pulse PULSE1, and output a first comparison signal CS1 corresponding to the comparison result. The control logic circuit 201 can receive the first comparison signal CS1 and update the control signal R_CODE based on the first comparison signal CS1. At this time, the control logic circuit 201 can update the control signal R_CODE such that the amplitude of the reference voltage VREF_UP generated based on the updated control signal R_CODE_UP is equal to or greater than the duty cycle DC_PULSE1 of the first pulse PULSE1. The method for updating the control signal R_CODE will be described below.

[0072] The calibration method (S100) includes outputting a third data clock obtained by compensating for the first data clock (S140). For example, data clock path 204 receives the first data clock WCK1 and the second voltage V2, and compensation circuit 206 can output a third data clock WCK3 obtained by compensating for the delay caused by the data clock path 204 using the second voltage V2. The second voltage V2 may be lower than the first voltage V1. The second voltage V2 is the minimum operating voltage of VDD2H specified in the JEDEC specification, and may be, for example, (but not limited to) about 0.9V. Because the second voltage V2 is lower than the first voltage V1, a larger delay occurs when the first data clock WCK1, which is the input clock, is transmitted through data clock path 204.

[0073] The calibration method (S100) includes outputting a second pulse based on a first data clock and a third data clock (S150). For example, the comparator circuit 211 may receive a first data clock WCK1 and a third data clock WCK3, and output a second pulse PULSE2 based on the first data clock WCK1 and the third data clock WCK3. The second pulse PULSE2 may be a pulse output by performing a bitwise AND operation on the signals obtained by inverting the first data clock WCK1 and the third data clock WCK3. The second pulse PULSE2 may be a pulse that is logic high during the time period when the first data clock WCK1 is delayed (e.g., t3 and t4) and logic low under other conditions. The first pulse PULSE1 may be a pulse that is logic high when the first data clock WCK1 is logic high and the third data clock WCK3 is logic low and logic low under other conditions. Since the second voltage V2 is lower than the first voltage V1, the duty cycle DC_PULSE2 of the second pulse PULSE2 may be greater than the duty cycle DC_PULSE1 of the first pulse PULSE1.

[0074] The calibration method (S100) includes updating the calibration signal based on a reference voltage and a second pulse (S160). For example, the duty cycle monitor 213 can receive a reference voltage VREF_UP from the reference voltage generation circuit 212 according to the updated control signal R_CODE_UP, and receive a second pulse PULSE2 from the comparison circuit 211. The duty cycle monitor 213 can compare the amplitude of the received reference voltage VREF_UP with the duty cycle DC_PULSE2 of the second pulse PULSE2, and output a second comparison signal CS2 corresponding to the comparison result. The control logic circuit 201 can receive the second comparison signal CS2 and update the calibration signal CAL_CODE based on the second comparison signal CS2. At this time, the control logic circuit 201 can update the calibration signal CAL_CODE such that the amplitude of the reference voltage VREF_UP generated based on the updated control signal R_CODE_UP is equal to or greater than the duty cycle DC_PULSE2 of the second pulse PULSE2. The method for updating the calibration signal CAL_CODE will be described below.

[0075] Figure 13 This is a flowchart of a calibration method according to some embodiments. Specific examples will be provided below. Figure 13 Description Figure 8 The update method. Figure 13 The update method described herein is merely an example, and the embodiments are not limited thereto. Figure 13 Lieutenant General does not provide Figure 8 Duplicate content in the text.

[0076] refer to Figures 1 to 13 The calibration method (S200) includes providing a first voltage to the compensation circuit (S210). For example, the data clock path 204 receives a first data clock WCK1 and a first voltage V1, and the compensation circuit 206 can output a second data clock WCK2, which is obtained by compensating for the delay caused by the data clock path 204 using the first voltage V1.

[0077] The calibration method (S200) includes outputting a first pulse based on a first data clock and a second data clock (S220). For example, the comparator circuit 211 can receive the first data clock WCK1 and the second data clock WCK2, and output the first pulse PULSE1 based on the first data clock WCK1 and the second data clock WCK2.

[0078] The calibration method (S200) includes determining whether the amplitude of the reference voltage is equal to or greater than the duty cycle of the first pulse (S230). For example, the duty cycle monitor 213 receives the reference voltage VREF according to the control signal R_CODE from the reference voltage generation circuit 212, and receives the first pulse PULSE1 from the comparison circuit 211. The duty cycle monitor 213 can compare the amplitude of the received reference voltage VREF with the duty cycle DC_PULSE1 of the first pulse PULSE1, and output a first comparison signal CS1 corresponding to the comparison result. Initially, the control signal R_CODE can be in an initialized state. Using the initialized control signal R_CODE, the reference voltage generation circuit 212 can output, for example, 0V as the reference voltage VREF. Since the duty cycle DC_PULSE1 of the first pulse PULSE1 is greater than the amplitude of the current reference voltage VREF, the first comparison signal CS1 output by the duty cycle monitor 213 can remain in a logic low state.

[0079] The control logic circuit 201 receives a first comparison signal CS1, and when the first comparison signal CS1 is in a logic low state, i.e., when the amplitude of the reference voltage output by the reference voltage generation circuit 212 is less than the duty cycle DC_PULSE1 of the first pulse PULSE1 (S230 - No), the calibration method (S200) includes updating the control signal R_CODE by adding a first offset to the control signal R_CODE (S235). The control signal R_CODE can be, for example, an n-bit (n is a natural number) digital code, and the first offset can be, for example, but not limited to, 1. If the resistance ratio of the reference voltage generation circuit 212 is set to a value obtained, for example, by dividing the size of the second resistor R2 by the size of the first resistor R1, then the larger the code value of the control signal R_CODE, the larger the resistance ratio of the reference voltage generation circuit 212, and the larger the amplitude of the reference voltage VREF output by the reference voltage generation circuit 212 can be. The first comparison signal CS1, output by the duty cycle monitor 213, remains logic low and can then change to logic high at a specific time as the amplitude of the reference voltage VREF output by the reference voltage generation circuit 212 increases. The control logic circuit 201 can repeatedly add a first offset to the control signal R_CODE until the first comparison signal CS1 changes to logic high, that is, until the amplitude of the reference voltage output by the reference voltage generation circuit 212 is greater than or equal to the duty cycle DC_PULSE1 of the first pulse PULSE1.

[0080] If the amplitude of the reference voltage output by the reference voltage generation circuit 212 is equal to or greater than the duty cycle of the first pulse PULSE1 (S230 - Yes), then the calibration method (S200) includes terminating the update of the control signal R_CODE. The updated control signal R_CODE_UP can be stored, for example, in a register of the control logic circuit 201.

[0081] The calibration method (S200) includes providing a second voltage to the compensation circuit (S250). For example, the data clock path 204 receives a first data clock WCK1 and a second voltage V2, and the compensation circuit 206 can output a third data clock WCK3, which is obtained by compensating for the delay caused by the data clock path 204 using the second voltage V2.

[0082] The calibration method (S200) includes outputting a second pulse based on a first data clock and a third data clock (S260). For example, the comparator circuit 211 can receive the first data clock WCK1 and the third data clock WCK3, and output the second pulse PULSE2 based on the first data clock WCK1 and the third data clock WCK3.

[0083] The calibration method (S200) includes determining whether the amplitude of the reference voltage is equal to or greater than the duty cycle of the second pulse (S270). For example, the duty cycle monitor 213 can receive the reference voltage VREF_UP according to the updated control signal R_CODE_UP from the reference voltage generation circuit 212, and receive the second pulse PULSE2 from the comparison circuit 211. The duty cycle monitor 213 can compare the amplitude of the received reference voltage VREF_UP with the duty cycle DC_PULSE2 of the second pulse PULSE2, and output a second comparison signal CS2 corresponding to the comparison result. The amplitude of the reference voltage VREF_UP according to the updated control signal R_CODE_UP can be equal to or greater than the duty cycle DC_PULSE1 of the first pulse PULSE1, but can be less than (i.e., lower than) the duty cycle DC_PULSE2 of the second pulse PULSE2. Since the duty cycle DC_PULSE2 of the second pulse PULSE2 is greater than the amplitude of the reference voltage VREF_UP, the second comparison signal CS2 output by the duty cycle monitor 213 can remain in a logic low state.

[0084] The control logic circuit 201 receives the second comparison signal CS2, and when the second comparison signal CS2 is in a logic low state, i.e., when the amplitude of the reference voltage VREF_UP output by the reference voltage generation circuit 212 is less than the duty cycle of the second pulse PULSE2 (S270 - No), the calibration method (S200) includes updating the calibration signal CAL_CODE by adding a second offset to the calibration signal CAL_CODE (S275). The calibration signal CAL_CODE can be, for example, an m-bit (m is a natural number) digital code or a voltage with a specific amplitude. When the calibration signal CAL_CODE is a digital code, the second offset can be, for example, 1, and when the calibration signal CAL_CODE is a voltage with a specific amplitude, the second offset can be, for example, 0.1V, but is not limited thereto. As the amplitude of the calibration signal CAL_CODE increases, the difference in the amount of compensation based on the amplitude of the power supply voltage received by the compensation circuit 206 can also increase. As the amplitude of the calibration signal CAL_CODE increases, the data clock delay decreases, and the duty cycle DC_PULSE2 of the second pulse PULSE2 can decrease. The second comparison signal CS2, output by the duty cycle monitor 213, remains logic low, and then can change to logic high at a specific time as the duty cycle DC_PULSE2 of the second pulse PULSE2 decreases. The control logic circuit 201 can repeatedly add a second offset to the calibration signal CAL_CODE until the second comparison signal CS2 changes to logic high, that is, until the amplitude of the reference voltage VREF_UP output by the reference voltage generation circuit 212 becomes equal to or greater than the duty cycle of the second pulse PULSE2.

[0085] When the amplitude of the reference voltage output by the reference voltage generation circuit 212 is equal to or greater than the duty cycle of the second pulse PULSE2 (S270 - Yes), the calibration method (S200) includes terminating the update of the calibration signal CAL_CODE (S280). The updated calibration signal CAL_CODE can be stored, for example, in a register of the control logic circuit 201.

[0086] According to some embodiments, the duty cycle value DC_PULSE1 of the first pulse PULSE1 and the duty cycle value DC_PULSE2 of the second pulse PULSE2 can be the same, or can have a small difference sufficient to be identified as the same. When the duty cycle value DC_PULSE1 of the first pulse PULSE1 and the duty cycle value DC_PULSE2 of the second pulse PULSE2 are the same or have a small difference sufficient to be identified as the same, the delay difference of the data clock due to voltage fluctuations (e.g., tWCK2DQI_volt as specified in the JEDEC specification) can be ideally eliminated (e.g., tWCK2DQI_volt=0).

[0087] According to some embodiments, the amplitude of an appropriate calibration signal to be input to a storage device can be obtained by the method described above, wherein the method is performed on the storage device. Since the amplitude of the appropriate calibration signal can be obtained according to the voltage sensitivity of each storage device by the method described above, the variation in delay differences (e.g., tWCK2DQI_volt) of each storage device due to voltage fluctuations can be reduced.

[0088] Figure 14 This is a flowchart of a calibration method according to some embodiments. Figure 14 Lieutenant General Description Figure 8 A specific example of the update method. Figure 14 The update method described herein is merely an example, and the embodiments are not limited thereto. Figure 14 Lieutenant General does not provide Figure 8 and Figure 13 The content is repeated.

[0089] refer to Figures 1 to 14 The calibration method (S300) includes supplying a second voltage to the compensation circuit (S310). For example, when the update of the control signal R_CODE is terminated, the data clock path 204 receives a first data clock WCK1 and a second voltage V2, and the compensation circuit 206 can output a third data clock WCK3 obtained by using the second voltage V2 to compensate for the delay caused by the data clock path 204.

[0090] The calibration method (S300) includes outputting a second pulse based on a first data clock and a third data clock (S320). For example, the comparator circuit 211 can receive the first data clock WCK1 and the third data clock WCK3, and output the second pulse PULSE2 based on the first data clock WCK1 and the third data clock WCK3.

[0091] The calibration method (S300) includes determining whether the calibration signal is at a preset maximum value (S330). If the current calibration signal CAL_CODE reaches the preset maximum value, a second offset is no longer added to the calibration signal CAL_CODE. If the calibration signal CAL_CODE reaches the preset maximum value (S330 - Yes), the calibration method (S300) includes terminating the update of the calibration signal (S360). If the calibration signal CAL_CODE does not reach the preset maximum value (S330 - No), operation S340 can be performed.

[0092] The calibration method (S300) includes determining whether the amplitude of the reference voltage is equal to or greater than the duty cycle of the second pulse (S340). For example, the duty cycle monitor 213 can receive the reference voltage VREF_UP from the reference voltage generation circuit 212 according to the updated control signal R_CODE_UP, and receive the second pulse PULSE2 from the comparison circuit 211. The duty cycle monitor 213 can compare the amplitude of the received reference voltage VREF_UP with the duty cycle DC_PULSE2 of the second pulse PULSE2, and output a second comparison signal CS2 corresponding to the comparison result.

[0093] The control logic circuit 201 receives the second comparison signal CS2, and if the second comparison signal CS2 is in a logic low state, i.e., when the amplitude of the reference voltage output by the reference voltage generation circuit 212 is less than (i.e., lower than) the duty cycle of the second pulse PULSE2 (S340 - No), the calibration method (S300) includes updating the calibration signal CAL_CODE by adding a second offset to the calibration signal CAL_CODE (S350). The control logic circuit 201 may repeatedly add the second offset to the calibration signal CAL_CODE until the second comparison signal CS2 changes to a logic high state, i.e., until the amplitude of the reference voltage VREF_UP output by the reference voltage generation circuit 212 becomes greater than or equal to the duty cycle DC_PULSE2 of the second pulse PULSE2. At this time, after adding the second offset to the calibration signal CAL_CODE, it is determined whether the calibration signal CAL_CODE has reached a preset maximum value, and if the calibration signal CAL_CODE has reached the preset maximum value, the updating of the calibration signal CAL_CODE can be terminated.

[0094] If the amplitude of the reference voltage VREF_UP output by the reference voltage generation circuit 212 is equal to or greater than the duty cycle DC_PULSE2 of the second pulse PULSE2 (S340 - Yes), then the calibration method (S300) includes terminating the update of the calibration signal CAL_CODE (S360). The updated calibration signal CAL_CODE can be stored, for example, in a register of the control logic circuit 201.

[0095] Figure 15 It is a block diagram of an electronic device including a storage device with a calibration circuit applied according to some embodiments.

[0096] refer to Figure 15 Electronic device 601 within network environment 600 can communicate with electronic device 602, for example, via a first network 698 such as a short-range wireless network, or with electronic device 604 or server 608, for example, via a second network 699 such as a long-range wireless network. In some embodiments, although such electronic device 601 may be, for example, a laptop computer, a portable mobile terminal, etc., the embodiments are not limited thereto.

[0097] Electronic device 601 can communicate with electronic device 604 through server 608. Electronic device 601 may include processor 620, memory 630, input device 650, sound output device 655, display device 660, audio module 670, sensor module 676, interface 677, haptic module 679, camera module 680, power management module 688, battery 689, communication module 690, subscriber identification module (SIM) 696, antenna module 697, etc.

[0098] In some embodiments, at least one component, such as display device 660 or camera module 680, may be omitted from electronic device 601, or one or more other components may be added to electronic device.

[0099] Some components can be implemented as a single integrated circuit (IC). For example, sensor module 676 (e.g., fingerprint sensor, iris sensor, or illuminance sensor) can be embedded in an image display device such as a display.

[0100] The processor 620 can execute software (e.g., program 640) for controlling other components of at least one electronic device 601 (e.g., hardware or software components connected to the processor 620), thereby performing various data processing and calculations.

[0101] As at least part of data processing or computation, processor 620 can load commands or data received from other components such as sensor module 676 or communication module 690 into volatile memory 632, process the commands or data stored in volatile memory 632, and store the resulting data in non-volatile memory 634.

[0102] Processor 620 may include, for example, a main processor 621 such as a central processing unit (CPU) or an application processor (AP), and an auxiliary processor 623, which operates independently of or in conjunction with the main processor 621.

[0103] Such auxiliary processors 623 may include, for example, graphics processing units (GPUs), image signal processors (ISPs), sensor central processors, communication processors (CPs), etc.

[0104] The auxiliary processor 623 can be configured to consume less power than the main processor 621 or to perform specific functions. The auxiliary processor 623 can be implemented separately from the main processor 621 or as part of the main processor 621.

[0105] The auxiliary processor 623 may, for example, represent the main processor 621 when the main processor 621 is inactive or, together with the main processor 621 when the main processor 621 is active, control at least some functions or states associated with at least one of the components of the electronic device 601.

[0106] Memory 630 can store various types of data used in at least one component of electronic device 601. These various types of data may include, for example, input and output data of software such as program 640, and associated commands. Memory 630 may include volatile memory 632 and non-volatile memory 634.

[0107] The program 640 can be stored as software in the memory 630 and may include, for example, an operating system (OS) 642, middleware 644, or application 646.

[0108] Input device 650 can receive commands or data from outside electronic device 601 for use in other components of electronic device 601. Input device 650 may include, for example, a microphone, mouse, or keyboard.

[0109] The sound output device 655 can output sound signals to the outside of the electronic device 601. The sound output device 655 may include, for example, a speaker. Multimedia data can be output through the speaker.

[0110] Display device 660 can provide information to the outside of electronic device 601 in a visually perceptible manner. Display device may include, for example, a monitor, a holographic device, or a projector, and control circuitry for controlling a corresponding one of the monitor, holographic device, or projector.

[0111] Display device 660 may include touch circuitry or sensor circuitry configured to detect touch (e.g., a pressure sensor configured to measure the intensity of the force generated by the touch).

[0112] The audio module 670 can convert sound into electrical signals and vice versa. In some embodiments, the audio module 670 can acquire sound through the input device 650, or output sound through the sound output device 655 or through headphones connected directly or wirelessly to the external electronic device 602.

[0113] Sensor module 676 detects the operational state of electronic device 601 (e.g., power or temperature) or the external environmental state of electronic device 601 (e.g., user state), and can generate electrical signals or data values ​​corresponding to the detected state. Sensor module 676 may include, for example, a gesture sensor, gyroscope sensor, atmospheric pressure sensor, magnetic sensor, accelerometer, grip sensor, proximity sensor, color sensor, infrared (IR) sensor, biometric sensor, temperature sensor, humidity sensor, or illuminance sensor.

[0114] Interface 677 may support one or more specified protocols to be used by electronic device 601, which is directly or wirelessly connected to external electronic device 602. In some embodiments, interface 677 may include, for example, a high-resolution multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital card (SD) interface, or an audio interface.

[0115] Connection terminal 678 may include a connector through which electronic device 601 can be physically connected to external electronic device 602. In some embodiments, connection terminal 678 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0116] The haptic module 679 can convert electrical signals into mechanical stimuli, such as vibrations or movements that can be perceived by a user through touch or kinesthesia. In some embodiments, the haptic module 679 may include, for example, a motor, a piezoelectric element, or an electrostimulator.

[0117] Camera module 680 can capture still or moving images. In some embodiments, camera module 680 may include one or more lenses, an image sensor, an image signal processor, a flash, etc.

[0118] Battery 689 can supply power to at least one component of electronic device 601. According to some embodiments, battery 689 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0119] The power management module 688 can manage the power supplied to the electronic device 601. The power management module 688 can be implemented, for example, as at least part of a power management integrated circuit (PMIC).

[0120] The communication module 690 can support the establishment of a direct communication channel or a wireless communication channel between the electronic device 601 and an external electronic device (e.g., electronic device 602, electronic device 604, or server 608), and can perform communication through the established communication channel.

[0121] The communication module 690 may include one or more communication processors, which may operate independently of the processor 620 and support direct or wireless communication.

[0122] The communication module 690 may include a wireless communication module 692 (e.g., a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) or a wired communication module 694 (e.g., a local area network (LAN) communication module or a power line communication module (PLC)).

[0123] Among these communication modules, the corresponding communication module can communicate via the first network 698 (e.g., Bluetooth). TM It can communicate with external electronic devices via WiFi (Wireless Fidelity) Direct or IrDA (Infrared Data Association standard) or a second network 699 (e.g., cellular communication network, Internet or long-range communication network).

[0124] Various types of communication modules can be implemented as a single component or as multiple components that are separate from each other. The wireless communication module 692 can use user information (such as the International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module 696 to verify and authenticate the electronic device 601 within the communication network (e.g., the first network 698 or the second network 699).

[0125] Antenna module 697 can transmit or receive signals or power to or from the outside of electronic device 601. In some embodiments, antenna module 697 may include one or more antennas, so communication module 690 can select at least one antenna suitable for a communication scheme used in a communication network (such as a first network 698 or a second network 699). Signals or power can then be transmitted or received between communication module and external electronic device through at least one selected antenna.

[0126] At least some of the aforementioned components can be connected to each other to perform signal communication between them via an inter-peripheral communication scheme (e.g., General Purpose Input and Output (GPIO), Serial Peripheral Interface (SPI), or Mobile Industry Processor Interface (MIPI)).

[0127] Commands or data can be sent or received between electronic device 601 and external electronic device 606 via server 608 connected to the second network 699. Electronic devices 602 and 606 can each be devices of the same or different type as electronic device 601. All or some of the operations to be performed in electronic device 601 can be performed in one or more external electronic devices 602, 606, or 608.

[0128] For example, if electronic device 601 needs to perform functions or services automatically or in response to requests from users or other devices, electronic device 601 performing these functions or services may request one or more external electronic devices to perform at least some of these functions or services on its behalf or additionally. Upon receiving the request, one or more external electronic devices may perform the requested function or service, or at least some of the additional functions or services associated with the request, and send the results of the performance to electronic device 601. With or without further processing of these results, electronic device 601 provides these results as at least part of its response to the request. For example, cloud computing, distributed computing, or client-server computing technologies may be used for this purpose.

[0129] According to some embodiments, memory 630 may include Figure 1 The memory device 20. The memory 630 may include a data clock path and calibration circuitry. The memory 630 can perform... Figures 1 to 14 The calibration method described herein. The memory 630 may be supplied with a power supply voltage, for example, from a power management module 688, a battery 689, etc. The memory 630 may be supplied with a data clock, for example, from a processor 620. The data clock path of the memory 630 may, for example, receive a first data clock and a first voltage, and output a second data clock. Furthermore, the data clock path of the memory 630 may receive the first data clock and a second voltage smaller than the first voltage (i.e., a second voltage smaller than the first voltage), and output a third data clock. The calibration circuitry of the memory 630 may, for example, determine a calibration signal to be input to the data clock path of the memory 630 based on the first, second, and third data clocks. The data clock path of the memory 630 may receive the determined calibration signal and output a data clock signal from which delay differences caused by fluctuations in the power supply voltage have been eliminated.

[0130] As used herein, the singular forms “a” and “described” are intended to also include the plural forms unless the context explicitly indicates otherwise. It will also be understood that the terms “comprising,” “having,” and / or “including” as used herein mean the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The term “and / or” includes any and all combinations of one or more of the listed items. The term “connection” may be used herein to refer to a physical and / or electrical connection, and may refer to a direct or indirect physical and / or electrical connection.

[0131] Although some embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to these embodiments and can be implemented in various different forms. Those skilled in the art to which this disclosure pertains will understand that the present disclosure can be implemented in other specific forms without altering the technical concept or essential characteristics of the disclosure. Therefore, it should be understood that the embodiments described above are illustrative in all respects rather than limiting.

Claims

1. A calibration method, comprising: The output is a second data clock obtained by compensating the first data clock based on a calibration signal and a first voltage; The first pulse is output based on the first data clock and the second data clock; The control signal is updated based on a reference voltage and the first pulse, wherein the reference voltage is generated based on the control signal; The output is a third data clock obtained by compensating the first data clock based on the calibration signal and a second voltage that is smaller than the first voltage; A second pulse is output based on the first data clock and the third data clock; and The calibration signal is updated based on the reference voltage generated based on the updated control signal and the second pulse.

2. The calibration method according to claim 1, in, Outputting the first pulse based on the first data clock and the second data clock includes: The first pulse is output by performing a bitwise AND operation between the inverted second data clock and the first data clock.

3. The calibration method according to claim 1, in, Outputting the first pulse based on the first data clock and the second data clock includes: The first pulse, which is at a logic high voltage, is output during a first time period when the first data clock is at a logic high voltage and the second data clock is at a logic low voltage.

4. The calibration method according to claim 1, in, Updating the control signal based on the reference voltage and the first pulse includes: The control signal is updated such that the amplitude of the reference voltage generated based on the updated control signal is equal to or greater than the duty cycle of the first pulse.

5. The calibration method according to claim 1, in, Updating the control signal based on the reference voltage and the first pulse includes: The control signal is updated by repeatedly adding a first offset to it until the amplitude of the reference voltage generated based on the control signal is equal to or greater than the duty cycle of the first pulse.

6. The calibration method according to claim 1, in, Updating the calibration signal based on the reference voltage and the second pulse includes: The calibration signal is updated such that the amplitude of the reference voltage generated based on the updated control signal is equal to or greater than the duty cycle of the second pulse.

7. The calibration method according to claim 1, in, Updating the calibration signal based on the reference voltage and the second pulse includes: The calibration signal is updated by repeatedly adding a second offset to the calibration signal until the amplitude of the reference voltage is greater than or equal to the duty cycle of the second pulse.

8. The calibration method according to claim 1, in, Updating the calibration signal based on a reference voltage generated based on the updated control signal and the second pulse includes: The calibration signal is updated by repeatedly adding a second offset to it until the updated calibration signal has a preset maximum value.

9. The calibration method according to claim 1, in, The reference voltage is generated by adjusting the resistance ratio of the first resistor and the second resistor in the reference voltage generation circuit according to the control signal.

10. The calibration method according to claim 1, further comprising: Initialize the calibration signal and the control signal.

11. An integrated circuit, comprising: A data clock path circuit is configured to receive a first voltage, a first data clock, and a calibration signal, and is configured to use the first voltage to compensate for the delay of the first data clock according to the calibration signal to output a second data clock; The comparator circuit is configured to output a first pulse based on the first data clock and the second data clock; A reference voltage generation circuit is configured to receive a control signal and to output a reference voltage according to the control signal; as well as A duty cycle monitor is configured to compare the amplitude of the reference voltage with the duty cycle of the first pulse, and is configured to output a first comparison signal corresponding to the comparison result of the amplitude of the reference voltage and the duty cycle of the first pulse.

12. The integrated circuit according to claim 11, in, The comparator circuit is configured to perform an AND operation on the inverted second data clock and the first data clock to output the first pulse.

13. The integrated circuit according to claim 11, in, The comparator circuit is configured to output the first pulse, which is at a logic high voltage, during a first time interval when the first data clock is at a logic high voltage and the second data clock is at a logic low voltage.

14. The integrated circuit according to claim 11, in, The reference voltage generation circuit includes a first resistor and a second resistor, and is configured to adjust the resistance ratio of the first resistor and the second resistor according to the control signal to output the reference voltage.

15. The integrated circuit according to claim 14, in, The reference voltage generation circuit adjusts the value of the first resistor according to the control signal to adjust the resistance ratio of the first resistor and the second resistor.

16. The integrated circuit according to claim 11, further comprising: The control logic circuit is configured to update the control signal based on the first comparison signal.

17. The integrated circuit according to claim 16, in, The control logic circuit is configured to update the control signal such that the amplitude of the reference voltage generated based on the updated control signal is equal to or greater than the duty cycle of the first pulse.

18. The integrated circuit according to claim 16, in, The control logic circuit is configured to update the control signal by repeatedly adding a first offset to the control signal until the logic value of the first comparison signal changes.

19. The integrated circuit according to claim 16, in, The control logic circuit is configured to update the control signal by repeatedly adding a first offset to the control signal until the amplitude of the reference voltage generated based on the updated control signal is greater than or equal to the duty cycle of the first pulse.

20. A storage device comprising: A storage cell array, configured to store data; The data clock path circuit is configured to output a second data clock based on a first data clock and a first voltage, and is configured to output a third data clock based on the first data clock and a second voltage that is smaller than the first voltage; The calibration circuit is configured to determine a calibration signal based on the first data clock, the second data clock, and the third data clock. as well as Control logic circuitry is configured to provide the calibration signal to the data clock path circuitry. The data clock path circuit is configured to output a fourth data clock based on the first data clock and the calibration signal. The control logic circuit is configured to write data into the memory cell array using the fourth data clock.

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