Pressure converter

Abstract

The invention relates to a voltage converter. The voltage converter comprises a cross coupling circuit, a differential pair circuit, a NOT gate and a pull element, the NOT gate receives an input signal and generates an inverted input signal. The cross-coupled circuit is connected to a first node and a second node, and receives a first supply voltage, and a voltage of the second node serves as an output signal. The differential pair circuit is connected to the first node and the second node, and receives a ground voltage, an input signal and a reverse input signal. The pull element is connected to the second node, and the pull element receives the enable signal. When the enable signal does not act, the output signal is maintained at a specific logic level. When the enable signal acts, the output signal changes along with the change of the input signal.

Description

Technical Field

[0001] This invention relates to a circuit, and more particularly to a level shifter. Background Technology

[0002] Generally, IC chips have different power domains, and circuits in different power domains receive different supply voltages. For example, V DD1 The supply voltage of the power domain is V DD1 V DD2 The supply voltage of the power domain is V DD2 Supply voltage V DD1 Different from the supply voltage V DD2 For example, the supply voltage V DD1 The supply voltage is 1.2V, V. DD2 It is 5V.

[0003] Furthermore, current CMOS semiconductor processes offer different fabrication methods for different voltage operating ranges of devices. For example, medium voltage device (MV) devices can be fabricated using MV processes to produce transistors with higher voltage stress, suitable for medium voltage operation. Conversely, low voltage device (LV) devices can be fabricated using LV processes to produce transistors with faster processing speeds but lower voltage stress, suitable for low voltage operation. For instance, during medium voltage operation, the voltage stress that the gate and source of a transistor can withstand ranges from approximately 3.0V to 10V; during low voltage operation, the voltage stress that the gate and source of a transistor can withstand ranges from approximately 0.8V to 2.0V.

[0004] Please refer to Figure 1A The diagram illustrates the circuit operation between different power domains in an IC chip. In the IC chip 100's V... DD1 Within the power domain, the signal for the operation of the first circuit 102 has a logic high level equal to the supply voltage V. DD1 The logic low level is ground voltage GND. In IC chip 100, the V... DD2 Within the power domain, the signal for the operation of the second circuit 106 is at a logic high level corresponding to the supply voltage V. DD2 The logic low level is the ground voltage GND.

[0005] Furthermore, signals between different power domains require logic level conversion using a level shifter 104 to enable normal communication between circuits in different power domains. Essentially, the main circuit (i.e., the second circuit 106) in the IC chip is designed for V... DD2 In the power domain, only a small portion of the circuitry (i.e., the first circuit 102) is designed for V. DD1 In the power domain.

[0006] For example, the first circuit 102 utilizes control signal C TRL1 It communicates with the second circuit 106. At this time, the transformer 104 receives the control signal C from the first circuit 102. TRL1 IN serves as the input signal to transformer 104, and OUT, the output signal generated by transformer 104, serves as another control signal C. TRLA And transmit it to the second circuit 106. That is, the transformer 104 can convert V DD1 High logic level in the power domain (i.e., V) DD1 The control signal C TRL1 Convert to V DD2 High logic level in the power domain (i.e., V) DD2 The control signal C TRLA Additionally, transformer 104 can also convert V... DD1 The control signal C is a logic low level (i.e., GND) in the power domain. TRL1 Convert to V DD2 The control signal C is a logic low level (i.e., GND) in the power domain. TRLA Thus, the two circuits 102 and 106 can communicate normally.

[0007] Of course, if the first circuit 102 uses more control signals to communicate with the second circuit 106, then more transformers are needed. For example, if the first circuit 102 uses ten control signals to communicate with the second circuit 106, then ten transformers are needed to perform logic level conversion for the ten control signals.

[0008] Please refer to Figure 1B The diagram illustrates a known transformer. Transformer 110 can convert a signal range between the supply voltage V and the input voltage V. DD1 The input signal IN to ground voltage GND and the inverted input signal ZIN are converted into signals with a range of supply voltage V. DD2 The output signal OUT is between the supply voltage V and the ground voltage GND. DD1 For example, the supply voltage V can be 1.2V. DD2For example, it could be 5V, with the ground voltage GND being 0V. That is, the supply voltage V... DD2 Greater than the supply voltage V DD1 And the supply voltage V DD1 It is greater than the ground voltage GND.

[0009] like Figure 1B As shown, the transformer 110 includes a NOT gate 116, a cross-coupled circuit 112, and a differential pair circuit 114. The NOT gate 116 is designed to operate at V... DD1 In the power domain, cross-coupled circuit 112 and differential pair circuit 114 are designed in V DD2 Power supply domain. Furthermore, the cross-coupled circuit 112 includes a P-type transistor M. P1 With a P-type transistor M P2 The differential pair circuit 114 includes an N-type transistor M. N1 With an N-type transistor M N2 Among them, the P-type transistor M P1 M P2 With N-type transistor M N1 M N2 All of them are metal-oxide-semiconductor field-effect transistors (MOSFET transistors).

[0010] The two power terminals of NOT gate 116 are respectively connected to the supply voltage V. DD1 The input of NOT gate 116 receives the input signal IN, and the output of NOT gate 116 generates an inverted input signal ZIN. The input signal IN and the inverted input signal ZIN are complementary.

[0011] Cross-coupled circuit 112 is connected between node a and node b, and cross-coupled circuit 112 receives supply voltage V. DD2 Among them, the P-type transistor M P1 The source receives the supply voltage V DD2 P-type transistor M P1 The drain of the P-type transistor M is connected to node a. P1 The gate of the P-type transistor M is connected to node b. P2 The source receives the supply voltage V DD2 P-type transistor M P2 The drain of the P-type transistor M is connected to node b. P2 The gate of the signal is connected to node a, and the voltage at node b is the output signal OUT.

[0012] Differential pair circuit 114 is connected between node a and node b, and receives ground voltage GND, input signal IN, and inverted input signal ZIN. Among them, N-type transistor M... N1 The drain of the N-type transistor M is connected to node a. N1 The source receives the ground voltage GND, and the N-type transistor M... N1 The gate of the N-type transistor receives the input signal IN. N2 The drain of the N-type transistor M is connected to node b. N2 The source receives the ground voltage GND, and the N-type transistor M... N2 The gate receives the inverted input signal ZIN.

[0013] When the input signal IN of transformer 110 is at a logic high level, the supply voltage V DD1 And when the inverted input signal ZIN is the logic low ground voltage GND, the N-type transistor M... N1 With P-type transistor M P2 Turn on, N-type transistor M N2 With P-type transistor M P1 Turn off. Therefore, the voltage at node b is the supply voltage V. DD2 Therefore, the supply voltage V is logic high for the output signal OUT. DD2 In other words, transformer 110 converts the logic high-level supply voltage V... DD1 The supply voltage V is converted to another logic high level. DD2 .

[0014] Furthermore, when the input signal IN of transformer 110 is a logic low ground voltage GND and the inverted input signal ZIN is a logic high supply voltage V... DD1 N-type transistor M N1 With P-type transistor M P2 Off, N-type transistor M N2 With P-type transistor M P1 Enabled. Therefore, the voltage at node b is the ground voltage GND, so the output signal OUT is the logic low level ground voltage GND. In other words, transformer 110 converts the logic low level ground voltage GND to the same logic low level ground voltage GND.

[0015] As can be seen from the above explanation, Figure 1B In the transformer 110, four transistors M P1 M P2 M N1 M N2 The maximum voltage stress it withstands is approximately equal to the supply voltage V.DD2 In other words, the four transistors M inside the transformer 110 are known. P1 M P2 M N1 M N2 It must be a medium-voltage device (MV device). Furthermore, due to the N-type transistors manufactured using the medium-voltage device (MV device) process, M... N1 M N2 Its threshold voltage is related to the supply voltage V. DD1 Very close. In other words, the N-type transistor M in the differential pair circuit 114 N1 or N-type transistor M N2 The gate receives the supply voltage V DD1 At that time, N-type transistor M N1 or N-type transistor M N2 The inability to fully turn on results in the N-type transistor M... N1 or N-type transistor M N2 The insufficient driving capability prevents the operating speed of the transformer 110 from being increased. Summary of the Invention

[0016] The present invention proposes a transformer that converts an input signal with a signal range between a first supply voltage and a ground voltage into an output signal with a signal range between a second supply voltage and the ground voltage, wherein the second supply voltage is greater than the first supply voltage. The transformer includes: a first P-type transistor, the source of which receives the second supply voltage, the drain of which is coupled to a first node, and the gate of which is coupled to a second node, the voltage of which is the output signal; a second P-type transistor, the source of which receives the second supply voltage, the drain of which is coupled to the second node, and the gate of which is coupled to the first node; a first N-type transistor, the source of which receives the ground voltage, the drain of which is coupled to a third node, and the gate of which receives the input signal; and a second N-type transistor, the source of which receives the ground voltage, the drain of which is coupled to a fourth node, and the gate of which receives an inverted input signal, and the input signal is... The inverted input signal is complementary; a third N-type transistor, one source of which is coupled to the third node, one drain of which is coupled to the first node, and one gate of which receives the input signal; a fourth N-type transistor, one source of which is coupled to the fourth node, one drain of which is coupled to the second node, and one gate of which receives the inverted input signal; and a pull element connected to the second node; wherein the pull element receives an enable signal; wherein when at least one of the first supply voltage and the second supply voltage is not supplied and the enable signal is not activated, the pull element is turned on and the output signal is maintained at a specific logic level; and when both the first supply voltage and the second supply voltage are provided and the enable signal is activated, the pull element is turned off and the output signal changes with the input signal.

[0017] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description

[0018] Figure 1A This is a schematic diagram of the circuit operation between different power domains in an IC chip.

[0019] Figure 1B Given a transformer;

[0020] Figure 2 This is the transformer according to the first embodiment of the present invention;

[0021] Figure 3A The second embodiment is a transformer;

[0022] Figure 3B and Figure 3C These are two examples of the pulling element in the second embodiment;

[0023] Figure 4 This is a transformer according to the third embodiment of the present invention;

[0024] Figure 5A and Figure 5B For P-type transistor M PA The third embodiment, a transformer, serves as a pulling element;

[0025] Figure 6A This is the transformer according to the fourth embodiment of the present invention;

[0026] Figure 6B This is the transformer according to the fifth embodiment of the present invention;

[0027] Figure 6C This is the transformer according to the sixth embodiment of the present invention;

[0028] Figure 7A and Figure 7B For N-type transistor M NA The third embodiment, a transformer, serves as a pulling element;

[0029] Figure 8A This is the transformer according to the seventh embodiment of the present invention;

[0030] Figure 8B This is the transformer according to the eighth embodiment of the present invention;

[0031] Figure 8C This is the transformer according to the ninth embodiment of the present invention;

[0032] Figure 8D This is the transformer according to the tenth embodiment of the present invention;

[0033] Figure 8E An example of a transformer according to the eleventh embodiment of the present invention; and

[0034] Figure 8F This is an example of a transformer according to the twelfth embodiment of the present invention.

[0035] [Symbol Explanation]

[0036] 100: IC chip

[0037] 102: First Circuit

[0038] 104, 110, 220, 240, 400, 440, 450, 460, 500, 510, 520, 530, 540, 550: Transformer

[0039] 106: Second Circuit

[0040] 100: IC chip

[0041] 112, 212, 512, 522, 532, 542: Cross-coupled circuits

[0042] 114, 234, 434, 444, 454, 464: Differential pair circuits

[0043] 116, 216: NOT gate

[0044] 242: Pulling element

[0045] 514, 526, 544: Switching elements Detailed Implementation

[0046] This invention proposes several embodiments of the transformer, and the transformer of this invention is also applicable to... Figure 1A The IC chip 100 shown is an example of this. Furthermore, the transformer of this invention consists of a medium-voltage component and a low-voltage component.

[0047] Please refer to Figure 2 The diagram illustrates a transformer according to a first embodiment of the present invention. The transformer 220 includes a medium-voltage component and a low-voltage component. The transformer 220 includes a NOT gate 216, a cross-coupled circuit 212, and a differential pair circuit 234. The NOT gate 216 is designed to operate at V... DD1 In the power domain, cross-coupled circuit 212 and differential pair circuit 234 are designed in V DD2 Power domain.

[0048] The two power supply terminals of NOT gate 216 are respectively connected to the supply voltage V. DD1 The input of NOT gate 216 receives the input signal IN, and the output of NOT gate 216 generates an inverted input signal ZIN. The input signal IN and the inverted input signal ZIN are complementary.

[0049] The cross-coupled circuit 212 includes a P-type transistor M P1 With a P-type transistor M P2 Cross-coupled circuit 212 is connected between node a and node b, and cross-coupled circuit 212 receives the supply voltage V. DD2 Among them, the P-type transistor M P1 The source receives the supply voltage V DD2 P-type transistor MP1 The drain of the P-type transistor M is coupled to node a. P1 The gate of the P-type transistor M is coupled to node b. P2 The source receives the supply voltage V DD2 P-type transistor M P2 The drain of the P-type transistor M is coupled to node b. P2 The gate of the signal is coupled to node a, and the voltage at node b is the output signal OUT.

[0050] Differential pair circuit 234 is connected between node a and node b. Differential pair circuit 234 receives ground voltage GND, input signal IN, and inverted input signal ZIN. Differential pair circuit 234 includes an N-type transistor M. N1 An N-type transistor M N2 An N-type transistor M N3 With an N-type transistor M N4 N-type transistor M N3 The drain of the N-type transistor M is coupled to node a. N3 The source of the N-type transistor M is coupled to node c. N3 The gate of the N-type transistor receives the input signal IN. N4 The drain of the N-type transistor M is coupled to node b. N4 The source of the N-type transistor M is coupled to node d. N4 The gate of the N-type transistor receives the inverted input signal ZIN. N1 The drain-coupled node c, N-type transistor M N1 The source receives the ground voltage GND, and the N-type transistor M... N1 The gate of the N-type transistor receives the input signal IN. N2 The drain is coupled to node d, N-type transistor M N2 The source receives the ground voltage GND, and the N-type transistor M... N2 The gate receives the inverted input signal ZIN.

[0051] According to an embodiment of the present invention, the N-type transistor M N1 M N2 For low-voltage devices (LV devices), P-type transistor M P1 M P2 With N-type transistor M N3 M N4 This is a medium-voltage device (MV device). Furthermore, the P-type transistor M... P1 M P2 With N-type transistor M N1 M N2 All are metal-oxide-semiconductor field-effect transistors. N-type transistor M N3 MN4 This is a native transistor, also known as a depletion-mode transistor. A native transistor is a transistor that is already conducting, with a very low threshold voltage Vt, approximately between -0.3 volts and +0.3 volts.

[0052] When the input signal IN of transformer 220 is at a logic high level, the supply voltage V DD1 And when the inverted input signal ZIN is the logic low ground voltage GND, the N-type transistor M... N1 M N3 With P-type transistor M P2 Turn on, N-type transistor M N2 M N4 With P-type transistor M P1 Shut down. Therefore, the voltage at node b is the supply voltage V. DD2 Therefore, the supply voltage V is logic high for the output signal OUT. DD2 In other words, transformer 220 converts the logic high-level supply voltage V... DD1 The supply voltage V is converted to another logic high level. DD2 .

[0053] Furthermore, when the input signal IN of transformer 220 is a logic low ground voltage GND and the inverted input signal ZIN is a logic high supply voltage V... DD1 N-type transistor M N1 M N3 With P-type transistor M P2 Off, N-type transistor M N2 M N4 With P-type transistor M P1 Enabled. Therefore, the voltage at node b is the ground voltage GND, so the output signal OUT is the logic low level ground voltage GND. In other words, transformer 220 converts the logic low level ground voltage GND to the same logic low level ground voltage GND.

[0054] exist Figure 2 In the differential pair circuit 234 of transformer 220, N-type transistor M N4 It is a medium-voltage component and an N-type transistor M N2 It is a low-voltage component. The supply voltage V is high when the output signal OUT is at logic high. DD2 At that time, two N-type transistors M N4 M N2 Commonly withstands supply voltage V DD2 Voltage stress. Due to the N-type transistor M N4It can share some of the voltage stress, so the N-type transistor M N2 This can be achieved using low-voltage components. Similarly, the N-type transistor M... N1 This can also be achieved using low-voltage components.

[0055] In addition, due to the N-type transistor M N1 M N2 As a low-voltage component, its critical voltage Vt is very low, approximately equal to the supply voltage V. DD1 Half of it. When the N-type transistor M... N1 or N-type transistor M N2 The gate receives the supply voltage V DD1 At that time, N-type transistor M N1 or N-type transistor M N2 It can be fully opened, allowing the transformer 220 to operate normally and increasing the operating speed of the transformer 220.

[0056] In addition, Figure 1A In IC chip 100, the supply voltage V DD1 V DD2 The order in which the supply voltage is supplied may affect the operation of the transformer 220 and cause malfunctions in the second circuit 106. For example, in the IC chip 100, if the user first supplies the supply voltage V... DD2 At this time, due to the supply voltage V DD1 Since this information is not yet available, the logic level of the input signal IN cannot be determined, and therefore the logic level of the output signal OUT cannot be determined either, causing the second circuit 106 to malfunction.

[0057] To address the above problems, the present invention proposes... Figure 3A The second embodiment of the transformer 240. Compared to the transformer 220 of the first embodiment, the transformer 240 of the second embodiment further includes a pulling device 242. The connection relationship of the pulling device 242 in the transformer 240 will only be described below. The connection relationship of other components is similar to that of the first embodiment and will not be described again here.

[0058] Pull element 242 is connected to node b and receives a uniform energy signal EN. Pull element 242 is designed in the power domain V. DD2 Furthermore, the enable signal EN can be a power enable signal. When the enable signal EN is activated, it represents the operation of two supply voltages V. DD1 V DD2 All components have been provided, and IC chip 100 and transformer 240 are functioning correctly. When the enable signal EN is not activated, it indicates that the two supply voltages V... DD1 V DD2If at least one supply voltage is not provided, IC chip 100 and transformer 240 cannot function properly. For example, the enable signal EN is a logic high level V. DD2 When the enable signal is at a low level (GND), it indicates that the enable signal EN is activated. When the enable signal EN is at a low level (GND), it indicates that the enable signal EN is not activated.

[0059] When the enable signal EN is not activated, the pull element 242 is connected to node b and pulls the voltage of node b to a specific logic level, so that the output signal OUT is maintained at that specific logic level. When the enable signal EN is activated, the pull element 242 is disconnected from node b and stops pulling the voltage of node b to that specific logic level, so that the output signal OUT changes with the input signal IN.

[0060] The following are two examples of the pull element 242. Please refer to them. Figure 3B and Figure 3C The illustrations show two examples of the pull element in the second embodiment.

[0061] like Figure 3B As shown, the pull element 242 includes an N-type transistor M. NA AND-NOT gate 246. The two power supply terminals of NOT gate 246 receive the supplied voltage V respectively. DD2 The input of NOT gate 246 receives the enable signal EN, and the output of NOT gate 246 generates an inverted enable signal ZEN, which is complementary to the inverted enable signal ZEN. N-type transistor M NA The drain of the N-type transistor M is connected to node b. NA The source receives the ground voltage GND, and the N-type transistor M... NA The gate of the N-type transistor receives the inverted enable signal ZEN. Furthermore, the N-type transistor M... NA It is a metal-oxide-semiconductor field-effect transistor, and the N-type transistor M NA It is a medium-voltage component.

[0062] When the enable signal EN is not activated, the enable signal EN is at logic low level GND, and the inverted enable signal ZEN is at logic high level V. DD2 At this time, the N-type transistor M... NA When enabled, the voltage at node b is pulled down to ground (GND), indicating that the output signal OUT is at a logic low level. Conversely, when the enable signal EN is activated, the enable signal EN is at a logic high level (V). DD2 The inverting enable signal ZEN is at logic low level GND. At this time, the N-type transistor M... NA When the input signal IN changes, the output signal OUT changes accordingly.

[0063] like Figure 3C As shown, the pull element 242 includes a P-type transistor M PA P-type transistor M PA The drain of the P-type transistor M is connected to node b. NA The source receives the supply voltage V DD2 P-type transistor M PA The gate of the P-type transistor receives the enable signal EN. Furthermore, the P-type transistor M... PA It is a metal-oxide-semiconductor field-effect transistor, and the P-type transistor M PA It is a medium-voltage component.

[0064] When the enable signal EN is not activated, the enable signal EN is at logic low level GND. At this time, the P-type transistor M... PA When enabled, the voltage at node b is pulled up to the supply voltage V. DD2 This indicates that the output signal OUT is at a logic high level. Conversely, when the enable signal EN is activated, the enable signal EN is at a logic high level. DD2 At this time, the P-type transistor M... PA When the input signal IN changes, the output signal OUT changes accordingly.

[0065] Of course, those skilled in the art can also modify the logic level of the enable signal EN. For example, when the enable signal EN is at logic low GND, it means that the enable signal EN is activated. When the enable signal EN is at logic high V... DD2 When this occurs, it indicates that the enable signal EN is not activated. At this time, the transistor connections in the pull element 242 can also be modified to achieve the purpose of this invention.

[0066] Furthermore, when the enable signal EN is activated, during the operation of the transformer 240 in the second embodiment, node c or node d may become floating. For example, when the input signal IN is at a logic high level V... DD1 And when the inverting input signal ZIN is logic low GND, the N-type transistor M N4 M N2 When the circuit is closed, node d is floating, and its voltage cannot be determined. Similarly, when the input signal IN is logic low (GND) and the inverting input signal ZIN is logic high (V), the voltage at node d cannot be determined. DD1 At that time, N-type transistor M N3 M N1 When the circuit is closed, node c is floating, and the voltage at node c cannot be determined. To address this issue, the present invention further proposes a transformer according to a third embodiment.

[0067] Please refer to Figure 4The diagram illustrates a transformer according to a third embodiment of the present invention. The difference between the transformer 240 of the second embodiment and the transformer 400 lies in the differential pair circuit 434. The following only describes the connection relationship of the differential pair circuit 434 in the transformer 400; other details will not be elaborated upon.

[0068] Differential pair circuit 434 is connected between node a and node b, and differential pair circuit 434 receives ground voltage GND and supply voltage V. DD1 The input signal IN and the inverted input signal ZIN are used. The differential pair circuit 434 includes an N-type transistor M. N1 An N-type transistor M N2 An N-type transistor M N3 An N-type transistor M N4 A P-type transistor M PB With a P-type transistor M PC .

[0069] N-type transistor M N1 M N2 M N3 With M N4 Designed for power domain V DD2 Additionally, N-type transistor M N1 M N2 P-type transistor M PB M PC It is a low-voltage device (LV device). N-type transistor M N3 M N4 This is a medium-voltage device (MV device). Additionally, the N-type transistor M... N1 M N2 P-type transistor M PB M PC This is a metal-oxide-semiconductor field-effect transistor. N-type transistor M N3 M N4 It is a native transistor, also known as a depletion transistor.

[0070] In the differential pair circuit 434, the N-type transistor M N3 The drain of the N-type transistor M is coupled to node a. N3 The source of the N-type transistor M is coupled to node c. N3 The gate of the N-type transistor receives the input signal IN. N4 The drain of the N-type transistor M is coupled to node b. N4 The source of the N-type transistor M is coupled to node d. N4 The gate of the N-type transistor receives the inverted input signal ZIN. N1 The drain-coupled node c, N-type transistor M N1 The source receives the ground voltage GND, and the N-type transistor M...N1 The gate of the N-type transistor receives the input signal IN. N2 The drain is coupled to node d, N-type transistor M N2 The source receives the ground voltage GND, and the N-type transistor M... N2 The gate of the P-type transistor receives the inverted input signal ZIN. PB The source receives the supply voltage V DD1 P-type transistor M PB The drain of the P-type transistor M is coupled to node c. PB The gate of the P-type transistor receives the input signal IN. PC The source receives the supply voltage V DD1 P-type transistor M PC The drain of the P-type transistor M is coupled to node d. PC The gate receives the inverted input signal ZIN.

[0071] After the enable signal EN is activated, the transformer 400 in the third embodiment can operate normally. When the input signal IN is at a logic high level V... DD1 And when the inverting input signal ZIN is logic low GND, the N-type transistor M N1 M N3 Turn on and P-type transistor M PB With the circuit closed, both node c and node a are grounded at GND. Furthermore, the N-type transistor M... N2 M N4 Turn off and P-type transistor M PC Enabled, node d is the supply voltage V DD1 And node b is the supply voltage V DD2 That is, the output signal OUT is a logic high level V. DD2 .

[0072] Conversely, when the input signal IN is logic low (GND) and the inverted input signal ZIN is logic high (V)... DD1 At that time, N-type transistor M N1 M N3 Turn off and P-type transistor M PB Enabled, node c is the supply voltage V DD1 And node a is the supply voltage V DD2 Furthermore, the N-type transistor M... N2 M N4 Turn on and P-type transistor M PC With the circuit closed, both nodes d and b are grounded (GND). That is, the output signal OUT is logic low (GND).

[0073] As explained above, when the enable signal EN is activated and the transformer 400 of the third embodiment is operating normally, nodes c and d will not be floating. However, although the transformer 400 of the third embodiment can operate normally, the supply voltage V... DD1 V DD2 Different supply sequences may cause leakage current in the transformer 400. The following uses two different pull elements 242 as examples to illustrate this.

[0074] The following will be respectively based on Figure 3C The transformer 240 shown has a pull element 242 and Figure 3B The transformer with pull element 242 shown is an example to further explain the cause of leakage current. Furthermore, the present invention provides several improved transformer embodiments to eliminate leakage current.

[0075] Please refer to Figure 5A and Figure 5B The diagram shows a P-type transistor M. PA The third embodiment, a transformer, serves as a pull-in element. Similar to... Figure 3C Pull element 242 includes P-type transistor M PA P-type transistor M PA The source receives the supply voltage V DD2 P-type transistor M PA The drain of the P-type transistor M is connected to node b. PA The gate receives the enable signal EN.

[0076] like Figure 5A At time point t A The transformer 400 first receives the supplied voltage V. DD1 At time point t B The transformer 400 then receives the supply voltage V. DD2 At time point t C The enable signal EN is activated.

[0077] When the supply voltage V DD1 Provided time point t A Earlier than the supply voltage V DD2 Provided time point t B At that time, the transformer 400 will generate at least one leakage current path. For example, at time t... A With time point t B Between, leakage current I LK From the supply voltage V DD1 via P-type transistor M PC Node d, N-type transistor MN4 Node b, P-type transistor M PA Flow to supply voltage V DD2 .

[0078] like Figure 5B At time point t D The transformer 400 first receives the supplied voltage V. DD2 At time point t E The transformer 400 then receives the supply voltage V. DD1 At time point t F The enable signal EN is activated.

[0079] When the supply voltage V DD2 Provided time point t D Earlier than the supply voltage V DD1 Provided time point t E At that time, the transformer 400 will generate at least one leakage current path. For example, at time t... D With time point t E Between, leakage current I LK From the supply voltage V DD2 via P-type transistor M PA Node b, N-type transistor M N4 Node d, P-type transistor M PC Flow to supply voltage V DD1 .

[0080] The present invention further modifies the differential pair circuit 434 in the transformer 400 of the third embodiment to eliminate Figure 5A and Figure 5B The leakage current path is shown below. The following are examples of leakage current paths. Figure 6A , Figure 6B and Figure 6C We will now introduce three improved transducer implementation examples.

[0081] Please refer to Figure 6A The diagram illustrates a transformer according to a fourth embodiment of the present invention. Compared to the differential pair circuit 434 of the transformer 400 in the third embodiment, Figure 6A The differential pair circuit 444 of the transformer 440 in the fourth embodiment also includes an N-type transistor M. NB M NC N-type transistor M NB M NC It is a metal-oxide-semiconductor field-effect transistor, and the N-type transistor M NB M NC This is a medium-voltage component. The following only introduces the N-type transistor M. NB M NC The connection relationships are as follows, and the rest will not be elaborated further.

[0082] In the differential pair circuit 444, the N-type transistor M N3 The drain is connected to the N-type transistor M NB Coupled to node a, N-type transistor M N4 The drain is connected to the N-type transistor M NC Coupled to node b. Wherein, N-type transistor M... NB The drain of the N-type transistor M is connected to node a. NB The source is connected to the N-type transistor M. N3 The drain of the N-type transistor M NB The gate of the N-type transistor receives the enable signal EN. NC The drain of the N-type transistor M is connected to node b. NC The source is connected to the N-type transistor M. N4 The drain of the N-type transistor M NC The gate receives the enable signal EN.

[0083] Even before the enable signal EN is activated, the supply voltage V DD1 V DD2 The supply order is different for N-type transistors M NB M NC All are closed. Therefore, no leakage current path can be formed in the transformer 440, which effectively prevents leakage current from occurring in the transformer 440.

[0084] Please refer to Figure 6B The diagram illustrates a transformer according to the fifth embodiment of the present invention. Compared to the differential pair circuit 434 of the transformer 400 in the third embodiment, Figure 6B The differential pair circuit 454 of the transformer 450 in the fifth embodiment also includes an N-type transistor M. ND M NE N-type transistor M ND M NE It is a metal-oxide-semiconductor field-effect transistor, and the N-type transistor M ND M NE This is a medium-voltage component. The following only introduces the N-type transistor M. ND M NE The connection relationships are as follows, and the rest will not be elaborated further.

[0085] In the differential pair circuit 454, the N-type transistor M N3 The source is via an N-type transistor M ND Coupled to node c, N-type transistor M N4 The source is via N-type transistor M NE Coupled to node d. Wherein, N-type transistor M... ND The drain is connected to the N-type transistor M. N3 The source of the N-type transistor M NDThe source of the N-type transistor M is connected to node c. ND The gate of the N-type transistor receives the enable signal EN. NE The drain is connected to the N-type transistor M. N4 The source of the N-type transistor M NE The source of the N-type transistor M is connected to node d. NE The gate receives the enable signal EN.

[0086] Even before the enable signal EN is activated, when the supply voltage V DD1 V DD2 The supply order is different for N-type transistors M ND M NE All are closed. Therefore, no leakage current path can be formed in the transformer 450, which effectively prevents leakage current from occurring in the transformer 450.

[0087] Please refer to Figure 6C The diagram illustrates a transformer according to the sixth embodiment of the present invention. Compared to the differential pair circuit 434 of the transformer 400 in the third embodiment, Figure 6C The differential pair circuit 464 of the transformer 460 in the sixth embodiment also includes an N-type transistor M. NF M NG N-type transistor M NF M NG It is a metal-oxide-semiconductor field-effect transistor, and the N-type transistor M NF M NG This is a medium-voltage component. The following only introduces the N-type transistor M. NF M NG The connection relationships are as follows, and the rest will not be elaborated further.

[0088] In the differential pair circuit 464, the P-type transistor M PB The drain is connected to the N-type transistor M NF P-type transistor M is coupled to node c. PC The drain is connected to the N-type transistor M NG Coupled to node d. Wherein, N-type transistor M... NF The drain is connected to the P-type transistor M. PB The drain of the N-type transistor M NF The source of the N-type transistor M is connected to node c. NF The gate of the N-type transistor receives the enable signal EN. NG The drain is connected to the P-type transistor M. PC The drain of the N-type transistor M NG The source of the N-type transistor M is connected to node d. NG The gate receives the enable signal EN.

[0089] Even before the enable signal EN is activated, the supply voltage V DD1 V DD2 The supply order is different for N-type transistors M NF M NG All are closed. Therefore, no leakage current path can be formed in the transformer 460, which effectively prevents leakage current from occurring in the transformer 460.

[0090] Please refer to Figure 7A and Figure 7B The diagram is drawn using an N-type transistor M. NA The third embodiment, a transformer, serves as a pull-in element. Similar to... Figure 3B The pull element 242 includes an N-type transistor M. NA N-type transistor M NA The source receives the ground voltage GND, and the N-type transistor M... NA The drain of the N-type transistor M is connected to node b. NA The gate receives the inverted enable signal ZEN, and the enable signal EN is complementary to the inverted enable signal ZEN.

[0091] like Figure 7A At time point t A The transformer 400 first receives the supplied voltage V. DD1 At time point t B The transformer 400 then receives the supply voltage V. DD2 At time point t C The enable signal EN is activated.

[0092] When the supply voltage V DD1 Provided time point t A Earlier than the supply voltage V DD2 Provided time point t B At that time, the transformer 400 will generate at least one leakage current path. For example, at time t... A With time point t B Between, leakage current I LK From the supply voltage V DD1 via P-type transistor M PC Node d, N-type transistor M N4 Node b, N-type transistor M NA It flows to the ground voltage GND.

[0093] like Figure 7B At time point t D The transformer 400 first receives the supplied voltage V. DD2 At time point t E The transformer 400 then receives the supply voltage V. DD1 At time point t FThe enable signal EN is activated.

[0094] When the supply voltage V DD2 Provided time point t D Earlier than the supply voltage V DD1 Provided time point t E At that time, the transformer 400 will generate at least one leakage current path. For example, at time t... D With time point t E Between, leakage current I LK1 From the supply voltage V DD2 via P-type transistor M P2 Node b, N-type transistor M NA It flows to the ground voltage GND. Furthermore, the leakage current I... LK2 From the supply voltage V DD2 via P-type transistor M P2 Node b, N-type transistor M N4 Node d, P-type transistor M PC Flow to supply voltage V DD1 Additionally, the leakage current I LK3 From the supply voltage V DD2 via P-type transistor M P1 Node a, N-type transistor M N3 Node c, P-type transistor M PB Flow to supply voltage V DD1 .

[0095] The present invention further modifies the cross-coupling circuit 212 or the differential pair circuit 434 in the transformer 400 of the third embodiment to eliminate Figure 7A and Figure 7B The leakage current path is shown below. The following are examples of leakage current paths. Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F Here are six improved transducer implementation examples.

[0096] Please refer to Figure 8A The diagram illustrates a transformer according to the seventh embodiment of the present invention. Compared to the cross-coupled circuit 212 of the transformer 400 in the third embodiment, Figure 8A The cross-coupling circuit 512 of the transformer 500 in the seventh embodiment further includes a switching device 514. The switching device 514 includes a P-type transistor M. PD P-type transistor M PD It is a metal-oxide-semiconductor field-effect transistor, and the P-type transistor M PDThis is a medium-voltage component. The following only describes the connection relationship of the switching device 514; the rest will not be described in detail.

[0097] In the cross-coupled circuit 512, the P-type transistor M P1 The source receives the supply voltage V via the switching element 514. DD2 P-type transistor M P2 The source receives the supply voltage V via the switching element 514. DD2 Among them, the P-type transistor M PD The source receives the supply voltage V DD2 P-type transistor M PD The drain is connected to the P-type transistor M. P1 The source of the P-type transistor M PD The drain is connected to the P-type transistor M. P2 The source of the P-type transistor M PD The gate receives the inverted enable signal ZEN, and the enable signal EN is complementary to the inverted enable signal ZEN.

[0098] Even before the enable signal EN is activated, the supply voltage V DD2 The supply time point is earlier than the supply voltage V. DD1 The supply time point, P-type transistor M PD The transformer is shut off. Therefore, no leakage current path can be formed in the transformer 500, which effectively prevents leakage current from occurring in the transformer 500.

[0099] In the seventh embodiment, the switching element 514 of the transformer 500 contains only one P-type transistor M. PD Of course, the switching element can also be modified to consist of multiple P-type transistors.

[0100] Please refer to Figure 8B The diagram illustrates a transformer according to the eighth embodiment of the present invention. In the cross-coupling circuit 522 of the transformer 510, the switching element 526 includes a P-type transistor M. PE M PF P-type transistor M PE M PF It is a metal-oxide-semiconductor field-effect transistor, and the P-type transistor M PE M PF This is a medium-voltage component. The following only describes the connection relationship of the switching element 526; the rest will not be elaborated upon.

[0101] In the cross-coupled circuit 522, the P-type transistor M P1 The source receives the supply voltage V via the switching element 526. DD2 P-type transistor M P2The source receives the supply voltage V via the switching element 526. DD2 Among them, the P-type transistor M PE The source receives the supply voltage V DD2 P-type transistor M PE The drain is connected to the P-type transistor M. P1 The source of the P-type transistor M PE The gate of the P-type transistor receives the inverted enable signal ZEN. PF The source receives the supply voltage V DD2 P-type transistor M PF The drain is connected to the P-type transistor M. P2 The source of the P-type transistor M PF The gate receives the inverted enable signal ZEN.

[0102] Please refer to Figure 8C The diagram illustrates a transformer according to the ninth embodiment of the present invention. Compared to the cross-coupled circuit 212 of the transformer 400 in the third embodiment, Figure 8C The cross-coupling circuit 532 of the transformer 520 in the ninth embodiment also includes a P-type transistor M. PG M PH P-type transistor M PG M PH It is a metal-oxide-semiconductor field-effect transistor, and the P-type transistor M PG M PH This is a medium-voltage component. The following only introduces the P-type transistor M. PG M PH The connection relationships are as follows, and the rest will not be elaborated further.

[0103] In the cross-coupled circuit 532, the P-type transistor M P1 The drain is connected to the P-type transistor M PG P-type transistor M is coupled to node a. P2 The drain is connected to the P-type transistor M PH Coupled to node b. Among them, the P-type transistor M... PG Source-to-P type transistor M P1 The drain of the P-type transistor M PG The drain of the P-type transistor M is connected to node a. PG The gate of the P-type transistor receives the inverted enable signal ZEN. PH Source-to-P type transistor M P2 The drain of the P-type transistor M PH The drain of the P-type transistor M is connected to node b. PH The gate receives the inverted enable signal ZEN.

[0104] Even before the enable signal EN is activated, the supply voltage VDD2 The supply time point is earlier than the supply voltage V. DD1 The supply time point, P-type transistor M PG M PH The transformer is shut off. Therefore, no leakage current path can be formed in the transformer 520, which effectively prevents leakage current from occurring in the transformer 520.

[0105] certainly, Figure 8A , Figure 8B and Figure 8C The cross-coupled circuits 512, 522, and 532 can be further combined with Figure 6A , Figure 6B and Figure 6C Differential circuits 444, 454, and 464 are used to form other transformers to prevent leakage current. A brief explanation follows.

[0106] Figure 8D This is a transformer according to the tenth embodiment of the present invention. In this embodiment, the transformer 530 includes a cross-coupled circuit 542 and a differential pair circuit 444. The cross-coupled circuit 542 includes a switching element 544 and a P-type transistor M. P1 M P2 In the cross-coupled circuit 542, the connection relationship of the switching elements 544 is similar to... Figure 8A Switching element 514 or Figure 8B The switching element 526. Furthermore, the connection relationship of the differential pair circuit 444 is the same as... Figure 6A The differential pair circuit 444.

[0107] Figure 8E This is a transformer according to the eleventh embodiment of the present invention. In this embodiment, the transformer 540 includes a cross-coupled circuit 542 and a differential pair circuit 454. The connection relationship of the cross-coupled circuit 542 is the same as that of... Figure 8D The cross-coupling circuit 542 is included. Additionally, the connection relationship of the differential pair circuit 454 is the same as... Figure 6B The differential pair circuit 454.

[0108] Figure 8F This is a transformer according to the twelfth embodiment of the present invention. In this embodiment, the transformer 550 includes a cross-coupled circuit 542 and a differential pair circuit 464. The connection relationship of the cross-coupled circuit 542 is the same as that of... Figure 8D The cross-coupling circuit 542 is included. Additionally, the connection relationship of the differential pair circuit 464 is the same as... Figure 6C The differential pair circuit 464.

[0109] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A transformer that converts an input signal with a signal range between a first supply voltage and a ground voltage into an output signal with a signal range between a second supply voltage and the ground voltage, wherein the second supply voltage is greater than the first supply voltage, the transformer comprising: A first P-type transistor, the source of which receives the second supply voltage, the drain of which is coupled to a first node, the gate of which is coupled to a second node, and the voltage of the second node serving as the output signal. The second P-type transistor has its source receiving the second supply voltage, its drain coupled to the second node, and its gate coupled to the first node. A first N-type transistor, the source of which receives the ground voltage, the drain of which is coupled to the third node, and the gate of which receives the input signal; The second N-type transistor has its source receiving the ground voltage, its drain coupled to the fourth node, and its gate receiving an inverted input signal that is complementary to the inverted input signal. The third N-type transistor has its source coupled to the third node, its drain coupled to the first node, and its gate receiving the input signal. The fourth N-type transistor has its source coupled to the fourth node, its drain coupled to the second node, and its gate receiving the inverted input signal. as well as A pull element, which is connected to the second node; The pulling element receives a consistent energy signal; Specifically, when at least one of the first supply voltage and the second supply voltage is not supplied and the enable signal is not activated, the pull element is turned on and the output signal is maintained at a specific logic level; and when both the first supply voltage and the second supply voltage are provided and the enable signal is activated, the pull element is turned off and the output signal changes in accordance with the changes in the input signal.

2. The transformer as described in claim 1, further comprising: The third P-type transistor has its source receiving the first supply voltage, its drain coupled to the third node, and its gate receiving the input signal. as well as The fourth P-type transistor has its source receiving the first supply voltage, its drain coupled to the fourth node, and its gate receiving the inverted input signal.

3. The transformer as claimed in claim 2, wherein the first P-type transistor, the second P-type transistor, the third N-type transistor, and the fourth N-type transistor are medium-voltage components, and the third P-type transistor, the fourth P-type transistor, the first N-type transistor, and the second N-type transistor are low-voltage components.

4. The transformer as claimed in claim 3, wherein the first P-type transistor, the second P-type transistor, the third P-type transistor, the fourth P-type transistor, the first N-type transistor, and the second N-type transistor are metal-oxide-semiconductor field-effect transistors, and the third N-type transistor and the fourth N-type transistor are depletion-type transistors.

5. The transformer of claim 2, wherein when the enable signal is not activated, the enable signal is the ground voltage; and when the enable signal is activated, the enable signal is the second supply voltage.

6. The transformer of claim 5, wherein the pull element comprises: The fifth P-type transistor has its source receiving the second supply voltage, its drain connected to the second node, and its gate receiving the enable signal.

7. The transformer as described in claim 6, further comprising: The fifth N-type transistor, wherein the source of the third N-type transistor is coupled to the third node via the fifth N-type transistor; as well as The sixth N-type transistor, wherein the source of the fourth N-type transistor is coupled to the fourth node via the sixth N-type transistor; The drain of the fifth N-type transistor is connected to the source of the third N-type transistor, the source of the fifth N-type transistor is connected to the third node, the gate of the fifth N-type transistor receives the enable signal, and the fifth N-type transistor is turned on when the enable signal is activated. The drain of the sixth N-type transistor is connected to the source of the fourth N-type transistor, the source of the sixth N-type transistor is connected to the fourth node, the gate of the sixth N-type transistor receives the enable signal, and the sixth N-type transistor is turned on when the enable signal is activated.

8. The transformer as claimed in claim 6, further comprising: The fifth N-type transistor, wherein the drain of the third N-type transistor is coupled to the first node via the fifth N-type transistor; as well as The sixth N-type transistor, wherein the drain of the fourth N-type transistor is coupled to the second node via the sixth N-type transistor; The drain of the fifth N-type transistor is connected to the first node, the source of the fifth N-type transistor is connected to the drain of the third N-type transistor, the gate of the fifth N-type transistor receives the enable signal, and the fifth N-type transistor is turned on when the enable signal is activated. The drain of the sixth N-type transistor is connected to the second node, the source of the sixth N-type transistor is connected to the drain of the fourth N-type transistor, the gate of the sixth N-type transistor receives the enable signal, and the sixth N-type transistor turns on when the enable signal is activated.

9. The transformer as claimed in claim 6, further comprising: The fifth N-type transistor, the drain of the third P-type transistor is coupled to the third node via the fifth N-type transistor; as well as The sixth N-type transistor, the drain of the fourth P-type transistor is coupled to the fourth node via the sixth N-type transistor; The drain of the fifth N-type transistor is connected to the drain of the third P-type transistor, the source of the fifth N-type transistor is connected to the third node, the gate of the fifth N-type transistor receives the enable signal, and the fifth N-type transistor is turned on when the enable signal is activated. The drain of the sixth N-type transistor is connected to the drain of the fourth P-type transistor, the source of the sixth N-type transistor is connected to the fourth node, the gate of the sixth N-type transistor receives the enable signal, and the sixth N-type transistor is turned on when the enable signal is activated.

10. The transformer of claim 5, wherein the pull element comprises: The fifth N-type transistor has its source receiving the ground voltage, its drain connected to the second node, and its gate receiving an inverted enable signal that is complementary to the inverted enable signal.

11. The transformer of claim 10, further comprising a switching element, wherein the source of the first P-type transistor receives the second supply voltage via the switching element, and the source of the second P-type transistor receives the second supply voltage via the switching element, and the switching element is turned on when the enable signal is activated.

12. The transformer of claim 11, wherein the switching element comprises: Fifth P-type transistor; The source of the fifth P-type transistor receives the second supply voltage; The drain of the fifth P-type transistor is connected to the source of the first P-type transistor; the drain of the fifth P-type transistor is connected to the source of the second P-type transistor; the gate of the fifth P-type transistor receives the inverted enable signal, and the fifth P-type transistor is turned on when the enable signal is activated.

13. The transformer of claim 11, wherein the switching element comprises: The fifth P-type transistor and the sixth P-type transistor; The source of the fifth P-type transistor receives the second supply voltage, the drain of the fifth P-type transistor is connected to the source of the first P-type transistor, the gate of the fifth P-type transistor receives the inverted enable signal, and the fifth P-type transistor is turned on when the enable signal is activated. In addition, the source of the sixth P-type transistor receives the second supply voltage, the drain of the sixth P-type transistor is connected to the source of the second P-type transistor, the gate of the sixth P-type transistor receives the inverted enable signal, and the sixth P-type transistor turns on when the enable signal is activated.

14. The transformer of claim 11, further comprising: The sixth N-type transistor, wherein the source of the third N-type transistor is coupled to the third node via the sixth N-type transistor; as well as The seventh N-type transistor, wherein the source of the fourth N-type transistor is coupled to the fourth node via the seventh N-type transistor; The drain of the sixth N-type transistor is connected to the source of the third N-type transistor, the source of the sixth N-type transistor is connected to the third node, the gate of the sixth N-type transistor receives the enable signal, and the sixth N-type transistor is turned on when the enable signal is activated. The drain of the seventh N-type transistor is connected to the source of the fourth N-type transistor, the source of the seventh N-type transistor is connected to the fourth node, the gate of the seventh N-type transistor receives the enable signal, and the seventh N-type transistor is turned on when the enable signal is activated.

15. The transformer of claim 11, further comprising: The sixth N-type transistor, wherein the drain of the third N-type transistor is coupled to the first node via the sixth N-type transistor; as well as The seventh N-type transistor, wherein the drain of the fourth N-type transistor is coupled to the second node via the seventh N-type transistor; The drain of the sixth N-type transistor is connected to the first node, the source of the sixth N-type transistor is connected to the drain of the third N-type transistor, the gate of the sixth N-type transistor receives the enable signal, and the sixth N-type transistor is turned on when the enable signal is activated. The drain of the seventh N-type transistor is connected to the second node, the source of the seventh N-type transistor is connected to the drain of the fourth N-type transistor, the gate of the seventh N-type transistor receives the enable signal, and the seventh N-type transistor is turned on when the enable signal is activated.

16. The transformer of claim 11, further comprising: The drain of the third P transistor is coupled to the third node via the sixth N-type transistor; as well as The seventh N-type transistor, the drain of the fourth P-type transistor is coupled to the fourth node via the seventh N-type transistor; The drain of the sixth N-type transistor is connected to the drain of the third P-type transistor, the source of the sixth N-type transistor is connected to the third node, the gate of the sixth N-type transistor receives the enable signal, and the sixth N-type transistor is turned on when the enable signal is activated. The drain of the seventh N-type transistor is connected to the drain of the fourth P-type transistor, the source of the seventh N-type transistor is connected to the fourth node, the gate of the seventh N-type transistor receives the enable signal, and the seventh N-type transistor is turned on when the enable signal is activated.

17. The transformer of claim 10, further comprising: The fifth P-type transistor, wherein the drain of the first P-type transistor is coupled to the first node via the fifth P-type transistor; as well as The sixth P-type transistor, the drain of the second P-type transistor is coupled to the second node via the sixth P-type transistor; The source of the fifth P-type transistor is connected to the drain of the first P-type transistor, the drain of the fifth P-type transistor is connected to the first node, the gate of the fifth P-type transistor receives the inverted enable signal, and the fifth P-type transistor is turned on when the enable signal is activated. The source of the sixth P-type transistor is connected to the drain of the second P-type transistor, the drain of the sixth P-type transistor is connected to the second node, the gate of the sixth P-type transistor receives the inverted enable signal, and the sixth P-type transistor is turned on when the enable signal is activated.

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