Low-heating light-emitting element driving circuit

Abstract

The invention discloses a light-emitting element driving circuit with low heating. The light-emitting element driving circuit comprises a voltage regulator, a multipath voltage selector, a VIN voltage detector, a constant current source (IDRV), a constant current source capable of configuring the magnitude of current, a switch (SW) and a shared resistor RSHUNT. According to the invention, the power consumption and heating of the driving circuit are optimized and reduced, and the application range of the power supply voltage VIN is greatly widened under the condition of the same current.

Description

Technical Field

[0001] This invention relates to a light-emitting element driving circuit, and more particularly to a low-heat-generating light-emitting element driving circuit, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] Chinese Patent Publication No. CN114828334A discloses a light-emitting element driving circuit, device, and electrical equipment. The light-emitting element driving circuit, used to drive a light-emitting element, includes a power supply, a shunt unit, an adjustment unit, a driving power stage, and an impedance adjustment branch. The shunt unit and the adjustment unit are connected in parallel and in series between the power supply and the driving input side of the driving power stage. The driving output side of the driving power stage is connected to the light-emitting element. The impedance adjustment branch includes a sampling input side, a reference input side, and an adjustment output side. The sampling input side is connected to the driving output side, the reference input side is connected to the driving input side, and the adjustment output side is connected to the adjustment control terminal of the adjustment unit. The impedance adjustment branch is configured to adjust the impedance value of the adjustment unit based on a first voltage value from the sampling input side and a second voltage value from the reference input side. The light-emitting element driving circuit provided by this invention can achieve technical effects such as balancing heat generation power, reducing the self-heating of the driving circuit, and improving driving efficiency and driving current capability.

[0003] With the increasing demand for wider power input voltage ranges (VIN) in practical applications, and the growing need for higher current from LEDs, the external resistors for the shunt units mentioned in the aforementioned driver circuits are difficult to design and determine. If the resistance is too high, the shunt effect is weakened during high-current output, leading to excessive heat generation in the driver circuit itself. Conversely, if the resistance is too low, it limits the upper limit of the input power supply voltage and increases the design difficulty and cost of the impedance regulation branch. Therefore, existing technical solutions are insufficient to cover application scenarios with higher power requirements (higher upper limit of power supply voltage, larger output current). Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a low-heat-generating light-emitting element driving circuit that optimizes heat generation and improves input / output power.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A low-heat-generating light-emitting element driving circuit includes a voltage regulator, a voltage selector, a VIN voltage detector, and a constant current source I. DRV Configurable constant current source, switch SW, and shared resistor R SHUNTThe power supply terminals of the voltage regulator, the VIN voltage detector, and the shared resistor R. SHUNT One end is connected to the input power supply VIN, the output of the voltage regulator is connected to the input of the configurable current source, and a shared resistor R. SHUNT The other end is connected to and generates the signal VINS. The N outputs of the configurable constant current source are connected to the N inputs of the voltage selector, generating signals OUT1 to OUTN sequentially. The output of the voltage selector is connected to the input of the voltage regulator. The output of the VIN voltage detector (VIN Monitor) is connected to the control terminal of the switch SW. One end of the switch SW is connected to the shared resistor R. SHUNT The control terminal is connected, and the other terminal of switch SW is connected to constant current source I. DRV One end is connected to the constant current source I. DRV The other end is grounded.

[0006] Furthermore, the voltage regulator includes a voltage buffer, a main operational amplifier (AMP), and a built-in power transistor (MOS). The input terminal of the voltage buffer is connected to the output terminal of the voltage selector and receives the signal OUT_SMP. The output terminal of the voltage buffer is connected to the non-inverting input terminal of the AMP and generates the signal OUT_BUF. The output terminal of the AMP is connected to the gate of the MOS and generates the signal NGATE. The drain of the MOS is connected to the input power supply VIN, and the source of the MOS is connected to the input terminal of the voltage selector and superimposed with the signal -V. HR It is then connected to the inverting input of the main operational amplifier (AMP).

[0007] Furthermore, the voltage buffer includes a buffer BUF, the non-inverting input of the buffer BUF is connected to the signal OUT_SMP, and the output of the buffer BUF is connected to the inverting input of the buffer BUF to generate the signal OUT_BUF.

[0008] Further, the main operational amplifier AMP includes a current source I0, PMOS transistors M1 and M2, NMOS transistors M3-M6, and PMOS transistors M7-M10. One end of the current source I0 is connected to the reference voltage VREG, and the other end of the current source I0 is connected to the source of PMOS transistors M1 and M2. The gate of PMOS transistor M1 serves as the non-inverting input terminal of the main operational amplifier AMP, and the gate of PMOS transistor M2 serves as the inverting input terminal of the main operational amplifier AMP. The drain of PMOS transistor M1 is connected to the drain of NMOS transistor M3 and the source of NMOS transistor M5, and the drain of PMOS transistor M2 is connected to the drain of NMOS transistor M4 and the source of NMOS transistor M6. The sources of NMOS transistors M3 and M4 are grounded. The sources of NMOS transistors M3 and M4 are connected to the bias voltage. The sources of NMOS transistors M5 and M6 are connected to the bias voltage. The drain of NMOS transistor M5 is connected to the drain of PMOS transistor M7, the gate of PMOS transistor M9, and the gate of PMOS transistor M10. The drain of NMOS transistor M6 is connected to the drain of PMOS transistor M8 and serves as the output of the main operational amplifier AMP to generate the signal NGATE. The gate of PMOS transistor M7 is connected to the gate of PMOS transistor M8. The source of PMOS transistor M9 and the source of PMOS transistor M10 are connected to the input power supply VIN.

[0009] Furthermore, the voltage selector includes diodes D1 to D2. N Diodes D1 to D2 N The anodes are sequentially input with signals OUT1 to OUTN, and diodes D1 to D2 are connected. N The cathodes are interconnected and output signal OUT_SMP.

[0010] Furthermore, the configurable constant current source includes a current source IEF, NMOS transistors NM1 and NM2, PMOS transistors PM0 and PM1-PMN. One end of the current source IEF is connected to the drain of NMOS transistor NM1, the gate of NMOS transistor NM1, and the gate of NMOS transistor NM2. The sources of NMOS transistors NM1 and NM2 are grounded. The drain of NMOS transistor NM2 is connected to the drain of PMOS transistor PM0, the drain of PMOS transistor PM0, and the gates of PMOS transistors PM1-PMN. The source of PMOS transistor PM0 and the sources of PMOS transistors PM1-PMN are connected to the signal VINS. The drains of PMOS transistors PM1-PMN sequentially output current I. OUT1 ~I OUTN .

[0011] Furthermore, the NMOS transistors NM1 and NM2 form an NMOS current mirror, with the current flowing through NMOS transistors NM1 and NMOS transistors NM2 in a 1:1 ratio. The PMOS transistors PM0 and PMOS transistors PM1 to PMN form a PMOS current mirror, with the current flowing through PMOS transistors PM0 and PMOS transistors PM1 to PMN in a 1:K ratio, and the currents flowing through PMOS transistors PM1 to PMN are equal.

[0012] Furthermore, the switch SW includes resistors R1 and R2, a comparator CMP, and an NMOS transistor NM3. One end of resistor R1 is connected to the input power supply VIN, and the other end of resistor R1 is connected to one end of resistor R2 and the first input terminal of comparator CMP. The other end of resistor R2 is grounded, and the second input terminal of comparator CMP is connected to signal V. TH The output of comparator CMP is connected to the gate of NMOS transistor NM3, and the drain of NMOS transistor NM3 is connected to the shared resistor R. SHUNT The control terminal is connected, and the source of NMOS transistor NM3 is connected to the constant current source I. DRV One end is connected.

[0013] Furthermore, the shared resistor R SHUNT Including resistor R S1 Resistance R S2 Resistance R PULL Diode D0 and PMOS transistor P SW resistance R S1 One end, resistor R PULL One end, the cathode of diode D0 and PMOS transistor P SW The source is connected to the input power supply VIN, and the resistor R S1 The other end is connected to resistor R S2 One end and PMOS transistor P SW The drain connection, resistor R S2 The other end is connected to the signal VINS, and the resistor R PULL The other end is connected to the anode of diode D0 and PMOS transistor P. SW The gate is connected and acts as a shared resistor R. SHUNT The control terminal.

[0014] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a low-heat-generating light-emitting element driving circuit, which benefits from the flexible adjustment of the thermally shared resistor along with the VIN voltage, and the end voltage of the thermally shared operating region is raised from VIN2 to VIN3; similarly, in the thermally increasing region, when the driving circuit reaches the upper limit of the withstand power consumption, the upper limit of the VIN voltage is also raised from VIN3 to VIN4; by further increasing the power shared on the thermally shared resistor (see the VIN>VTH interval), the power consumption and heat generation of the driving circuit itself are optimized and reduced; under the same current conditions, the present invention significantly broadens the application range of the power supply voltage VIN, and better meets the application requirements of larger input / output power. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a low-heat-generating light-emitting element driving circuit according to the present invention.

[0016] Figure 2 This is a schematic diagram of the driving section of a low-heat-generating light-emitting element driving circuit according to the present invention.

[0017] Figure 3 This is a schematic diagram of the configurable current source of the present invention.

[0018] Figure 4 This is a schematic diagram of the voltage selector of the present invention.

[0019] Figure 5 This is a schematic diagram of the voltage buffer of the present invention.

[0020] Figure 6 This is a schematic diagram of the main operational amplifier (AMP) of the present invention.

[0021] Figure 7 The present invention relates to the switch SW and the shared resistor R. SHUNT A schematic diagram.

[0022] Figure 8 The shared resistor R in an embodiment of the present invention SHUNT Voltage-power consumption curve.

[0023] Figure 9 The shared resistor R of different resistance values ​​in embodiments of the present invention SHUNT Voltage-power consumption curve.

[0024] Figure 10 The shared resistor R after the resistance value is switched in an embodiment of the present invention SHUNT Voltage-power consumption curve. Detailed Implementation

[0025] To elaborate on the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0026] like Figure 1 As shown, a low-heat-generating light-emitting element driving circuit of the present invention includes a voltage regulator, a voltage selector, a VIN voltage detector, and a constant current source I. DRV Configurable constant current source, switch SW, and shared resistor R SHUNT The power supply terminals of the voltage regulator, the VIN voltage detector, and the shared resistor R. SHUNT One end is connected to the input power supply VIN, the output of the voltage regulator is connected to the input of the configurable current source CurrentSource, and a shared resistor R. SHUNT The other end is connected to and generates the signal VINS. The N outputs of the configurable constant current source are connected to the N inputs of the voltage selector, generating signals OUT1 to OUTN sequentially. The output of the voltage selector is connected to the input of the voltage regulator. The output of the VIN voltage detector (VIN Monitor) is connected to the control terminal of the switch SW. One end of the switch SW is connected to the shared resistor R. SHUNT The control terminal is connected, and the other terminal of switch SW is connected to constant current source I. DRV One end is connected to the constant current source I. DRV The other end is grounded.

[0027] Where VINS = MAX(OUT1~OUTN) + V HR .

[0028] like Figure 2As shown, the voltage regulator includes a voltage buffer, a main operational amplifier (AMP), and a built-in power transistor (MOS). The input of the voltage buffer is connected to the output of the voltage selector and receives the signal OUT_SMP. The output of the voltage buffer is connected to the non-inverting input of the AMP and generates the signal OUT_BUF. The output of the AMP is connected to the gate of the MOS and generates the signal NGATE. The drain of the MOS is connected to the input power supply VIN, and the source of the MOS is connected to the input of the voltage selector and superimposed with the signal -V. HR It is then connected to the inverting input of the main operational amplifier (AMP).

[0029] like Figure 5 As shown, the voltage buffer includes a buffer BUF. The non-inverting input of the buffer BUF is connected to the signal OUT_SMP, and the output of the buffer BUF is connected to the inverting input of the buffer BUF to generate the signal OUT_BUF. Shorting the output and inverting input of the buffer BUF can form a unity-gain operational amplifier, where OUT_BUF = OUT_SMP. After buffering, the output signal driving capability is further increased, and electrical isolation between the output and input signals can be achieved.

[0030] like Figure 6As shown, the main operational amplifier (AMP) includes a current source I0, PMOS transistors M1 and M2, NMOS transistors M3-M6, and PMOS transistors M7-M10. One end of the current source I0 is connected to the reference voltage VREG, and the other end of the current source I0 is connected to the source of PMOS transistors M1 and M2. The gate of PMOS transistor M1 serves as the non-inverting input of the main operational amplifier AMP, and the gate of PMOS transistor M2 serves as the inverting input of the main operational amplifier AMP. The drain of PMOS transistor M1 is connected to the drain of NMOS transistor M3 and the source of NMOS transistor M5, and the drain of PMOS transistor M2 is connected to the drain of NMOS transistor M4 and the source of NMOS transistor M6. The sources of NMOS transistors M3 and M4 are grounded. The sources of NMOS transistors M3 and M4 are connected to a bias voltage. The sources of NMOS transistors M5 and M6 are connected to a bias voltage. The drain of NMOS transistor M5 is connected to the drain of PMOS transistors M7, M9, and M10. The drain of NMOS transistor M6 is connected to the drain of PMOS transistor M8 and serves as the output of the main operational amplifier (AMP) to generate the signal NGATE. The gate of PMOS transistor M7 is connected to the gate of PMOS transistor M8. The source of PMOS transistor M9 and M10 is connected to the input power supply VIN. PMOS transistors M1 and M2 form a differential input pair. NMOS transistors M5, M6, M7, and M8 are common-gate cascode transistors to improve the output gain of the main operational amplifier (AMP). The main operational amplifier (AMP) has an inverting input INP = OUT_BUF and an inverting input INN = VINS - VHR. VHR is called the headroom voltage, or DC offset voltage.

[0031] like Figure 4 As shown, the voltage selector includes diodes D1 to D2. N Diodes D1 to D2 N The anodes are sequentially input with signals OUT1 to OUTN, and diodes D1 to D2 are connected. N The cathodes of diodes D1 to D2 are interconnected and output the signal OUT_SMP. N Using a common cathode connection, the voltages of each output pin OUT1~OUTN of the driving circuit are passed through this array, and the largest OUTx voltage can be selected and output as OUT_SMP (OUT1~N Sampling), which is MAX(OUT1~OUTN).

[0032] like Figure 3As shown, the configurable constant current source includes a current source IEF, NMOS transistors NM1 and NM2, PMOS transistors PM0 and PM1-PMN. One end of the current source IEF is connected to the drain of NMOS transistor NM1, the gate of NMOS transistor NM1, and the gate of NMOS transistor NM2. The sources of NMOS transistors NM1 and NM2 are grounded. The drain of NMOS transistor NM2 is connected to the drain of PMOS transistor PM0, the drain of PMOS transistor PM0, and the gates of PMOS transistors PM1-PMN. The source of PMOS transistor PM0 and the sources of PMOS transistors PM1-PMN are connected to the signal VINS. The drains of PMOS transistors PM1-PMN sequentially output current I. OUT1 ~I OUTN .

[0033] NMOS transistors NM1 and NM2 form an NMOS current mirror, with a current ratio of 1:1 flowing through them. PMOS transistors PM0 and PM1-PMN form a PMOS current mirror, with a current ratio of 1:K flowing through them, meaning the currents flowing through PM1-PMN are equal. The current IREF is copied from the NMOS current mirror to the PMOS transistor PM0, then amplified by a factor of K by the PMOS current mirror and output as a multi-channel constant current source to supply the external load LED of the driver circuit. That is, IOUT1 = ... = IOUTN = K × IREF = K × VREF / RREF; VINS serves as the power supply for the current mirror, with a load current I... TOTAL That is, IOUT1 + … IOUTN + IREF.

[0034] like Figure 7 As shown, switch SW includes resistors R1 and R2, comparator CMP, and NMOS transistor NM3. One end of resistor R1 is connected to the input power supply VIN, and the other end of resistor R1 is connected to one end of resistor R2 and the first input terminal of comparator CMP. The other end of resistor R2 is grounded, and the second input terminal of comparator CMP is connected to signal V. TH The output of comparator CMP is connected to the gate of NMOS transistor NM3, and the drain of NMOS transistor NM3 is connected to the shared resistor R. SHUNT The control terminal is connected, and the source of NMOS transistor NM3 is connected to the constant current source I. DRV One end is connected.

[0035] Shared resistor R SHUNT Including resistor R S1 Resistance R S2 Resistance R PULL Diode D0 and PMOS transistor PSW resistance R S1 One end, resistor R PULL One end, the cathode of diode D0 and PMOS transistor P SW The source is connected to the input power supply VIN, and the resistor R S1 The other end is connected to resistor R S2 One end and PMOS transistor P SW The drain connection, resistor R S2 The other end is connected to the signal VINS, and the resistor R PULL The other end is connected to the anode of diode D0 and PMOS transistor P. SW The gate is connected and acts as a shared resistor R. SHUNT The control terminal.

[0036] The working principle of a low-heat-generating light-emitting element driving circuit of the present invention is as follows: Given a specific output current, as the input power supply voltage VIN increases, the total power consumption increases linearly. This power consumption flows through the shared resistor R. SHUNT The current increases linearly, thus sharing some of the power consumption and transferring some power to the external environment, reducing the heat generated by the drive circuit itself, and achieving the so-called heat sharing function: the drive circuit and the shared resistor R SHUNT They share power consumption and heat generation.

[0037] like Figure 8 As shown, the Y-axis represents power consumption (W), and the X-axis represents the power supply voltage (VIN). The solid black line represents the power consumption of the drive circuit, and the dashed black line represents the power consumption on the external thermally shared resistor RSHUNT. The dashed red line represents the upper limit of the power consumption that the drive circuit itself can withstand, which is affected by factors such as the application scenario, the packaging and materials of the components used, and heat dissipation conditions.

[0038] As the input power supply VIN voltage increases, the circuit can be roughly divided into three operating regions: 1. Low Dropout Area, 2. Thermal Share Area, and 3. Thermal Increasing Area.

[0039] In the low-dropout region, the voltage of the voltage regulator output signal VINS rises synchronously with the input power supply VIN (i.e., VINS≈VIN), and the shared resistor R... SHUNT With equal voltages at both ends, the voltage regulator provides all current to outputs OUT1~OUTN in this region. On the power curve, power consumption increases linearly on the drive circuit (PIC), R... SHUNT The power consumption across the resistor is approximately 0.

[0040] When the VIN voltage rises to V_STT (VDROPOUT + VOUT + VHEADROOM), slightly higher than the VINS target adjustment voltage (VOUT + VHEADROOM), it enters the thermal sharing region: the total current of the output constant current source I... TOTAL Composed of a voltage regulator and a shared resistor R SHUNT Provided jointly. VINS remains approximately constant at the target adjustment voltage. As the VIN voltage increases further, current flows through the shared resistor R. SHUNT The current IRS = (VIN - VINS) / R SHUNT As the current increases linearly, the voltage regulator will linearly decrease its current output IREG through negative feedback to maintain the total output current I. TOTAL The same applies. Therefore, the drive circuit and the shared resistor R remain unchanged. SHUNT The power consumption of all components increases in a parabolic manner.

[0041] When the VIN voltage rises to V_FNS, it enters the thermally increasing region, and the total current I... TOTAL Almost all of it flows through the shared resistor R SHUNT ,like Figure 8 The black dashed line represents the constant power consumption across the resistor, while the power consumption of the drive circuit increases linearly with VIN. When the VIN voltage rises to V_TOL, the power consumption of the drive circuit will exceed the upper limit of tolerable power consumption.

[0042] Given total output current I TOTAL Under certain conditions, a shared resistor R with different resistance values SHUNT Drive circuit and shared resistor R SHUNT The power consumption curve on the screen is as follows Figure 9 As shown, The solid black line represents the drive circuit with a small shared resistor R. SHUNT Power consumption under the following conditions; the blue dashed line represents the power consumption under a large shared resistor R. SHUNT The power consumption under these conditions.

[0043] The drive circuit is paired with a small shared resistor R SHUNT The design exceeds the tolerable power consumption limit above the power supply voltage VIN3. Large shared resistor R SHUNT During the design phase, the voltage ranges from VIN1 to VIN2, as well as above VIN4, exceeded the maximum tolerable power consumption. Therefore, the shared resistor R... SHUNT If the value is too small, the power supply voltage range is limited (e.g., VIN3), while the shared resistor R... SHUNT If the voltage is too high, the power consumption in the medium voltage range of VIN will exceed the standard (such as VIN1~VIN2).

[0044] This invention automatically sets a suitable shared resistor R by detecting the VIN voltage value. SHUNTThe resistance value covers a wider power supply voltage range, meeting the application requirements of higher power output. Simply put, for low to medium VIN voltages, a smaller shared resistor R is used. SHUNT To ensure the power consumption of the drive circuit meets the standard, a larger shared resistor R is used when the VIN voltage is medium to high. SHUNT This further expands the voltage range of the heat sharing area and raises the upper limit of the power supply voltage.

[0045] When VIN is at a low to medium voltage, the internal VIN detection comparator turns on switch SW, outputting I. DRV Current flows through the external resistor R PULL PMOS transistor P SW The gate-source voltage Vgs is equal to I DRV ╳ R PULL PMOS transistor P SW On, bypass resistor R S1 Only with a small resistance value R S2 This reduces the power consumption of the drive circuit. As the VIN voltage rises to VIN2, the heat-sharing region ends, and the region enters the heat-incrementing region. When the VIN voltage rises to the switching threshold VTH in real time, the internal constant current source I... DRV Off, PMOS transistor P SW The gate is made of resistor R PULL Pull-up to VIN, PMOS transistor P SW When shut down, the external thermal shared resistance R increases. S1 +R S2 The drive circuit returns to the thermally shared region until the VIN voltage rises to VIN3, at which point it re-enters the thermally increasing region.

[0046] After switching (adjusting) the resistance value as described above, such as Figure 10 The solid black line represents the power consumption on the drive circuit, and the dashed black line represents the power consumption on the thermally shared resistor.

[0047] Benefiting from the flexible adjustment of the thermally shared resistor along with the VIN voltage, the end voltage of the thermally shared operating region is raised from VIN2 to VIN3; similarly, in the thermally increasing region, when the drive circuit reaches its maximum power consumption limit, the upper limit of the VIN voltage is also raised from VIN3 to VIN4.

[0048] By further increasing the power shared by the thermally shared resistor (see the VIN>VTH range), the power consumption and heat generation of the drive circuit itself are optimized and reduced. Under the same current conditions, the applicable range of the power supply voltage VIN is significantly widened, better meeting the application requirements of higher input / output power.

[0049] This invention provides a low-heat-generating light-emitting element driving circuit. Benefiting from the flexible adjustment of the thermally shared resistor along with the VIN voltage, the voltage at the end of the thermally shared operating region is raised from VIN2 to VIN3. Similarly, in the thermally increasing region, when the driving circuit reaches its maximum withstand power consumption limit, the upper limit of the VIN voltage is also raised from VIN3 to VIN4. By further increasing the power shared on the thermally shared resistor (see the VIN>VTH range), the power consumption and heat generation of the driving circuit itself are optimized and reduced. Under the same current conditions, this invention significantly expands the applicable range of the power supply voltage VIN, better meeting the application requirements of higher input / output power.

[0050] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A low-heat-generating light-emitting element driving circuit, characterized in that: Includes a voltage regulator, a voltage selector, a VIN voltage detector, and a constant current source I. DRV Configurable constant current source, switch SW, and shared resistor R SHUNT The power supply terminals of the voltage regulator, the VIN voltage detector, and the shared resistor R. SHUNT One end is connected to the input power supply VIN, the output of the voltage regulator is connected to the input of the configurable current source CurrentSource, and a shared resistor R. SHUNT The other end is connected to and generates the signal VINS. The N outputs of the configurable constant current source are connected to the N inputs of the voltage selector, generating signals OUT1 to OUTN sequentially. The output of the voltage selector is connected to the input of the voltage regulator. The output of the VIN voltage detector (VIN Monitor) is connected to the control terminal of the switch SW. One end of the switch SW is connected to the shared resistor R. SHUNT The control terminal is connected, and the other terminal of switch SW is connected to constant current source I. DRV One end is connected to the constant current source I. DRV The other end is grounded.

2. The low-heat-generating light-emitting element driving circuit according to claim 1, characterized in that: The voltage regulator includes a voltage buffer, a main operational amplifier (AMP), and a built-in power transistor (MOS). The input of the voltage buffer is connected to the output of a voltage selector and receives the signal OUT_SMP. The output of the voltage buffer is connected to the non-inverting input of the AMP and generates the signal OUT_BUF. The output of the AMP is connected to the gate of the MOS and generates the signal NGATE. The drain of the MOS is connected to the input power supply VIN, and the source of the MOS is connected to the input of the voltage selector and superimposed with the signal -V. HR It is then connected to the inverting input of the main operational amplifier (AMP).

3. The low-heat-generating light-emitting element driving circuit according to claim 2, characterized in that: The voltage buffer includes a buffer BUF. The non-inverting input of the buffer BUF is connected to the signal OUT_SMP, and the output of the buffer BUF is connected to the inverting input of the buffer BUF to generate the signal OUT_BUF.

4. The low-heat-generating light-emitting element driving circuit according to claim 2, characterized in that: The main operational amplifier (AMP) includes a current source I0, PMOS transistors M1 and M2, NMOS transistors M3-M6, and PMOS transistors M7-M10. One end of the current source I0 is connected to the reference voltage VREG, and the other end of the current source I0 is connected to the source of PMOS transistors M1 and M2. The gate of PMOS transistor M1 serves as the non-inverting input of the main operational amplifier AMP, and the gate of PMOS transistor M2 serves as the inverting input of the main operational amplifier AMP. The drain of PMOS transistor M1 is connected to the drain of NMOS transistor M3 and the source of NMOS transistor M5, and the drain of PMOS transistor M2 is connected to the drain of NMOS transistor M4 and the source of NMOS transistor M6. The sources of NMOS transistors M3 and M4 are grounded. The sources of NMOS transistors M3 and M4 are connected to the bias voltage. The sources of NMOS transistors M5 and M6 are connected to the bias voltage. The drain of NMOS transistor M5 is connected to the drain of PMOS transistor M7, the gate of PMOS transistor M9, and the gate of PMOS transistor M10. The drain of NMOS transistor M6 is connected to the drain of PMOS transistor M8 and serves as the output terminal of the main operational amplifier AMP to generate the signal NGATE. The gate of PMOS transistor M7 is connected to the gate of PMOS transistor M8. The source of PMOS transistor M9 and the source of PMOS transistor M10 are connected to the input power supply VIN.

5. The low-heat-generating light-emitting element driving circuit according to claim 1, characterized in that: The voltage selector includes diodes D1 to D2. N Diodes D1 to D2 N The anodes are sequentially input with signals OUT1 to OUTN, and diodes D1 to D2 are connected. N The cathodes are interconnected and output signal OUT_SMP.

6. The low-heat-generating light-emitting element driving circuit according to claim 1, characterized in that: The configurable constant current source includes a current source IEF, NMOS transistors NM1 and NM2, PMOS transistors PM0 and PM1-PMN. One end of the current source IEF is connected to the drain of NMOS transistor NM1, the gate of NMOS transistor NM1, and the gate of NMOS transistor NM2. The sources of NMOS transistors NM1 and NM2 are grounded. The drain of NMOS transistor NM2 is connected to the drain of PMOS transistor PM0, the drain of PMOS transistor PM0, and the gates of PMOS transistors PM1-PMN. The source of PMOS transistor PM0 and the sources of PMOS transistors PM1-PMN are connected to the signal VINS. The drains of PMOS transistors PM1-PMN sequentially output current I. OUT1 ~I OUTN .

7. The low-heat-generating light-emitting element driving circuit according to claim 6, characterized in that: The NMOS transistors NM1 and NM2 form an NMOS current mirror, and the current ratio flowing through NMOS transistors NM1 and NMOS transistors NM2 is 1:

1. The PMOS transistors PM0 and PMOS transistors PM1 to PMN form a PMOS current mirror, and the current ratio flowing through PMOS transistors PM0 and PMOS transistors PM1 to PMN is 1:K. The currents flowing through PMOS transistors PM1 to PMN are equal.

8. The low-heat-generating light-emitting element driving circuit according to claim 1, characterized in that: The switch SW includes resistors R1 and R2, a comparator CMP, and an NMOS transistor NM3. One end of resistor R1 is connected to the input power supply VIN, and the other end of resistor R1 is connected to one end of resistor R2 and the first input terminal of comparator CMP. The other end of resistor R2 is grounded, and the second input terminal of comparator CMP is connected to signal V. TH The output of comparator CMP is connected to the gate of NMOS transistor NM3, and the drain of NMOS transistor NM3 is connected to the shared resistor R. SHUNT The control terminal is connected, and the source of NMOS transistor NM3 is connected to the constant current source I. DRV One end is connected.

9. The low-heat-generating light-emitting element driving circuit according to claim 1, characterized in that: The shared resistor R SHUNT Including resistor R S1 Resistance R S2 Resistance R PULL Diode D0 and PMOS transistor P SW resistance R S1 One end, resistor R PULL One end, the cathode of diode D0 and PMOS transistor P SW The source is connected to the input power supply VIN, and the resistor R S1 The other end is connected to resistor R S2 One end and PMOS transistor P SW The drain connection, resistor R S2 The other end is connected to the signal VINS, and the resistor R PULL The other end is connected to the anode of diode D0 and PMOS transistor P. SW The gate is connected and acts as a shared resistor R. SHUNT The control terminal.

Images