Semiconductor structure, forming method thereof and electronic equipment
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2026-04-10
- Publication Date
- 2026-05-12
AI Technical Summary
Existing technologies for transistor fabrication suffer from limitations in steps such as diffusion and ion implantation, resulting in significant leakage current in transistors and impacting device performance.
By covering the first part of the semiconductor layer with a first dielectric layer and performing doping treatment to form doped and undoped regions, and subsequently forming channel regions and source/drain regions, the first dielectric layer is used as a mask to avoid doping in the undoped region, reduce the accumulation of bulk holes caused by quantum tunneling effect, and reduce the tunneling electric field between the drain and the gate.
It reduces the leakage current of transistors and improves the electrical performance of devices. The off-state leakage current is reduced by 45% to 55%, the subthreshold swing is reduced by 0.1% to 0.2%, the threshold voltage is reduced by 1% to 2%, and the source-drain current is increased by 1.5% to 2.5%.
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Figure CN122028418A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same, and an electronic device. Background Technology
[0002] To meet the high integration requirements of devices, continue Moore's Law, and maintain device performance, chips have shifted from planar transistors to fin field-effect transistors. However, due to limitations in processes such as diffusion and ion implantation, transistors still have significant leakage current, which affects their performance.
[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0004] In view of this, a semiconductor structure and a method for forming the same, as well as an electronic device, are provided. This method can improve the leakage current of the device and enhance its performance.
[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.
[0006] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, the method comprising: Provide substrate; A stacked structure is formed on the substrate, the stacked structure including stacked semiconductor layers and an initial sacrificial layer, the stacked structure having trenches that at least penetrate the stacked structure and expose a portion of the surface of the substrate; The initial sacrificial layer is etched along a first direction to form a sacrificial layer that exposes a first portion of the semiconductor layer, the end of which forms a portion of the sidewall of the trench; the first direction is parallel to the substrate. A first dielectric layer is formed, which covers the end face of the sacrificial layer and extends along the first direction to cover a portion of the outer sidewall of a first portion of the semiconductor layer; Using the first dielectric layer, a first doping process is performed on a first portion of the exposed semiconductor layer to form a doped region.
[0007] In one exemplary embodiment of this disclosure, forming a first dielectric layer includes: An initial first dielectric layer is formed, which simultaneously covers the end face of the sacrificial layer and the outer sidewall and end face of the first portion of the semiconductor layer, and extends to cover the surface of the stacked structure; The initial first dielectric layer is formed by removing portions of the surface of the stacked structure, the end face of the first portion of the semiconductor layer, and the outer sidewall of the first portion of the semiconductor layer.
[0008] In one exemplary embodiment of this disclosure, after forming the initial first dielectric layer, the process includes: A second dielectric layer is formed, which at least fills the voids between the first portions of two adjacent semiconductor layers.
[0009] In one exemplary embodiment of this disclosure, removing a portion of the initial first dielectric layer located on the surface of the stacked structure, the end face of the first portion of the semiconductor layer, and the outer sidewall of the first portion of the semiconductor layer includes: Using the second dielectric layer as a mask, the initial first dielectric layer is etched along the first direction.
[0010] In one exemplary embodiment of this disclosure, the etching rate of the second dielectric layer is less than the etching rate of the first dielectric layer.
[0011] In one exemplary embodiment of this disclosure, after forming the doped region, the process includes: The doped region is subjected to a second doping treatment so that the portion of the doped region near the trench forms a first source / drain region, and the remaining doped region forms a channel region; the dopant ions in the second doping treatment are of a different type than the dopant ions in the first doping treatment.
[0012] In one exemplary embodiment of this disclosure, after forming the doped region, the portion of the semiconductor layer covered by the first dielectric layer is an undoped region, and the method further includes: The undoped region is subjected to the second doping process so that at least a portion of the undoped region forms a second source / drain region.
[0013] According to another aspect of this disclosure, a semiconductor structure is provided, the semiconductor structure comprising: Substrate; A stacked structure includes a semiconductor layer and a sacrificial layer sequentially stacked on the substrate, wherein the sacrificial layer exposes a first portion of the semiconductor layer; A trench that penetrates at least through the stacked structure and exposes a portion of the substrate surface, wherein the end face of a first portion of the semiconductor layer forms a portion of the sidewall of the trench; The first portion of the semiconductor layer includes at least a first source / drain region, a channel region, and a second source / drain region sequentially distributed along a first direction and away from the trench; the first direction is parallel to the substrate; A first dielectric layer covers the second source / drain region and is adjacent to the sacrificial layer. The orthographic projection of the end face of the first dielectric layer near the trench on the substrate coincides with the orthographic projection of the boundary between the second source / drain region and the channel region on the substrate.
[0014] In one exemplary embodiment of this disclosure, in the first direction, a first source-drain extension region is provided between the first source-drain region and the channel region, and a second source-drain extension region is provided between the second source-drain region and the channel region; The ion doping concentration of the second source / drain extension region is less than that of the first source / drain extension region.
[0015] In one exemplary embodiment of this disclosure, the second source / drain region is an undoped region.
[0016] In one exemplary embodiment of this disclosure, the first source / drain region and the second source / drain region include different doped ions.
[0017] According to another aspect of this disclosure, an electronic device is provided, the electronic device comprising: A processing device; and a memory device electrically connected to the processing device, the memory device comprising the semiconductor structure of any of the above embodiments.
[0018] The semiconductor structure formation method disclosed herein involves covering one end of a first portion of a semiconductor layer with a first dielectric layer. During the doping process of the first portion of the semiconductor layer, only the semiconductor layer without the first dielectric layer covering it is doped. The doped semiconductor layer subsequently forms a channel region and a first source / drain region, while the semiconductor layer located at the other end of the channel region and covered by the first dielectric layer forms an undoped region. This undoped region subsequently forms a second source / drain region. That is, the second source / drain region does not undergo the same doping process as the channel region. When the transistor drain is subsequently formed in the second source / drain region, the accumulation of bulk holes due to the quantum tunneling effect can be reduced, the tunneling electric field between the drain and the gate can be reduced, thereby reducing the leakage current of the transistor and improving the electrical performance of the device.
[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0021] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0022] Figure 2 This is a schematic diagram of the structure of an initial sacrificial layer in an exemplary embodiment of this disclosure.
[0023] Figure 3 This is a schematic diagram of the structure of a trench in an exemplary embodiment of the present disclosure.
[0024] Figure 4 This is a schematic diagram of the structure of a first portion of an undoped semiconductor layer in an exemplary embodiment of the present disclosure.
[0025] Figure 5 This is a schematic diagram of the structure of an insulating material layer in an exemplary embodiment of the present disclosure.
[0026] Figure 6 This is a schematic diagram of the structure of an initial first dielectric layer in an exemplary embodiment of the present disclosure.
[0027] Figure 7 This is a schematic diagram of the structure of a second dielectric layer in an exemplary embodiment of the present disclosure.
[0028] Figure 8 This is a schematic diagram of the structure of a first dielectric layer in an exemplary embodiment of the present disclosure.
[0029] Figure 9 This is a schematic diagram of the structure of a doped region in an exemplary embodiment of the present disclosure.
[0030] Figure 10 This is a schematic diagram of the structure of a channel region and a first source / drain region in an exemplary embodiment of this disclosure.
[0031] Figure 11 This is a schematic diagram of the structure of the first part of a semiconductor layer after a second doping treatment, as shown in an exemplary embodiment of this disclosure.
[0032] Figure 12 This is a schematic diagram of the structure of the first part of a semiconductor layer after a second doping treatment, as shown in an exemplary embodiment of this disclosure.
[0033] Figure 13 This is a schematic diagram of an electronic device according to an exemplary embodiment of the present disclosure.
[0034] The reference numerals in the attached figures are explained as follows: 100, Substrate; 200, Stacked structure; 210, Semiconductor layer; 211, First portion of semiconductor layer; 212, Second portion of semiconductor layer; 221, Initial sacrificial layer; 220, Sacrificial layer; 230, Insulating material layer; 241, Initial first dielectric layer; 240, First dielectric layer; 250, Second dielectric layer; 300, Trench; 401, Doped region; 402, Undoped region; 510, First source / drain region; 511, First source / drain extension region; 520, Channel region; 530, Second source / drain region; 531, Second source / drain extension region; 601, Gate oxide layer; 602, Gate layer; 10, Electronic device; 20, Processing device; 30, Memory device; 40, Semiconductor structure; X, First direction; Y, Second direction. Detailed Implementation
[0035] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.
[0036] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.
[0037] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.
[0038] This disclosure provides a method for forming a semiconductor structure, such as... Figure 1 As shown, the forming method includes steps S10 to S50.
[0039] Step S10: Provide a substrate; Step S20: Form a stacked structure on the substrate. The stacked structure includes stacked semiconductor layers and an initial sacrificial layer. The stacked structure has trenches that penetrate at least through the stacked structure and expose a portion of the substrate surface. Step S30: Etch the initial sacrificial layer along a first direction to form a sacrificial layer, the sacrificial layer exposing a first portion of the semiconductor layer, the end of the first portion of the semiconductor layer forming a partial sidewall of the trench; the first direction is parallel to the substrate; Step S40: Form a first dielectric layer, which covers the end face of the sacrificial layer and extends along a first direction to cover a portion of the outer sidewall of a first part of the semiconductor layer; Step S50: Using the first dielectric layer, a first doping process is performed on a first portion of the exposed semiconductor layer to form a doped region.
[0040] The semiconductor structure formation method disclosed herein involves covering one end of a first portion of a semiconductor layer with a first dielectric layer. During the doping process of the first portion of the semiconductor layer, only the semiconductor layer without the first dielectric layer covering it is doped. The doped semiconductor layer subsequently forms a channel region and a first source / drain region, while the semiconductor layer located at the other end of the channel region and covered by the first dielectric layer forms an undoped region. This undoped region subsequently forms a second source / drain region. That is, the second source / drain region does not undergo the same doping process as the channel region. When the transistor drain is subsequently formed in the second source / drain region, the accumulation of bulk holes due to the quantum tunneling effect can be reduced, the tunneling electric field between the drain and the gate can be reduced, thereby reducing the leakage current of the transistor and improving the electrical performance of the device.
[0041] It should be noted that, in the embodiments provided in this disclosure, such as Figures 2 to 10 As shown, the first direction X is parallel to the surface of the substrate 100, and the first direction X can be understood as the horizontal direction in the embodiments of this disclosure; the second direction Y is perpendicular to the surface of the substrate 100 and intersects with the first direction X, and the second direction Y can be understood as the vertical direction in the embodiments of this disclosure; in some embodiments, in order to clearly illustrate the semiconductor structure formation method provided by the embodiments of this disclosure in conjunction with the accompanying drawings, the first direction X and the second direction Y can constitute a two-dimensional rectangular coordinate system.
[0042] The steps of the method for forming a semiconductor structure according to the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings: In the embodiments provided in this disclosure, in step S10, as follows Figures 2 to 10 As shown, a substrate 100 is provided.
[0043] The substrate 100 can be a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, SOI (Silicon on Insulator), or GOI (Germanium on Insulator). In some embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide (SiC), indium phosphide (InP), or gallium arsenide (GaAs). The embodiments provided in this disclosure use silicon as an example for the substrate 100, but do not limit the specific material of the substrate 100. The substrate 100 provided in this disclosure can serve as a mechanical support carrier, providing effective physical support for the formation of active devices within the stacked structure 200.
[0044] In the embodiments provided in this disclosure, in step S20, as Figure 2 and Figure 3 As shown, a stacked structure 200 is formed on the substrate 100.
[0045] Among them, such as Figure 2 As shown, the stacked structure 200 includes a semiconductor layer 210 and an initial sacrificial layer 221. The stacked structure 200 uses an alternating stacking of the semiconductor layer 210 and the initial sacrificial layer 221, which can transform the formed device structure from a two-dimensional planar structure to a three-dimensional structure, thereby improving the device integration.
[0046] In some embodiments, semiconductor layer 210 can be a single-crystal semiconductor, for example, semiconductor layer 210 can be a silicon layer, providing a structural basis for subsequent transistor formation. The initial sacrificial layer 221 can be made of an insulating material to form electrical isolation between two adjacent semiconductor layers 210, ensuring the reliability of subsequent processes.
[0047] In some specific embodiments, the semiconductor layer 210 and the initial sacrificial layer 221 may adopt a silicon / silicon oxide stack structure.
[0048] Among them, such as Figure 3 As shown, the stacked structure 200 also includes a trench 300, which at least penetrates the stacked structure 200 and exposes a portion of the surface of the substrate 100. By providing the trench 300 in the stacked structure 200, the trench 300 can serve as a solution or gas channel in subsequent transistor fabrication processes. In addition, the trench 300 can also be used to form structures such as bit lines or capacitors to form signal lines or storage nodes of the device, thereby realizing functions such as signal transmission or data reading and writing.
[0049] In some embodiments, the stacked structure 200 can be etched along the second direction Y by an etching process to form a trench 300.
[0050] The etching process can employ one or a combination of methods such as wet etching and dry etching. Wet etching can include chemical solution etching, electrochemical etching, or photo-enhanced wet etching, while dry etching can include plasma etching, atomic layer etching, or vapor phase etching.
[0051] Within the stacked structure 200, the ends of the semiconductor layer 210 and the initial sacrificial layer 221 form the sidewalls of the trench 300. The sidewalls of the trench 300 extend along the second direction Y, meaning that the sidewalls of the trench 300 are perpendicular or approximately perpendicular to the surface of the substrate 100. However, due to the different etching rates of the semiconductor layer 210 and the initial sacrificial layer 221, the sidewalls of the trench 300 may have an uneven structure. But it should be understood that the shape of the sidewalls of the trench 300 does not affect the integrity and stability of the overall device structure.
[0052] In the embodiments provided in this disclosure, in step S30, as Figure 4 As shown, a sacrificial layer 220 is formed.
[0053] Among them, reference Figure 4 The process involves forming a sacrificial layer 220, including etching an initial sacrificial layer 221 along a first direction X to form the sacrificial layer 220, which exposes a first portion 211 of the semiconductor layer. The sacrificial layer 220 is formed by etching the initial sacrificial layer 221 to define the active region of the transistor. Specifically, the first portion 211 of the semiconductor layer serves as the active region of the transistor, providing a structural basis for the subsequent formation of the source / drain region and channel region 520 of the transistor.
[0054] In some embodiments, refer again Figure 4 After forming the sacrificial layer 220, the method may further include: trimming the first portion 211 of the semiconductor layer to improve the interface quality of the first portion 211 of the semiconductor layer and improve the yield.
[0055] In the embodiments provided in this disclosure, in step S40, as Figures 5 to 8 As shown, a first dielectric layer 240 is formed.
[0056] Among them, such as Figure 8 As shown, the first dielectric layer 240 covers the end face of the sacrificial layer 220, and the first dielectric layer 240 extends along the first direction X to cover part of the outer sidewall of the first portion 211 of the semiconductor layer. By covering part of the outer sidewall of the first portion 211 of the semiconductor layer, the first dielectric layer 240 can serve as a mask, and the end face of the first dielectric layer 240 away from the sacrificial layer 220 can serve as the boundary between the second source / drain region 530 and the channel region 520.
[0057] The first dielectric layer 240 can be made of insulating materials such as silicon nitride, and it can be made using one of the following methods: physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering deposition, etc.
[0058] In some embodiments, since the first dielectric layer 240 and the sacrificial layer 220 are adjacent in the first direction X, and the first dielectric layer 240 needs to be used as a mask in subsequent doping processes, in order to distinguish the first dielectric layer 240 and the sacrificial layer 220 during the process, the first dielectric layer 240 and the sacrificial layer 220 need to be made of different insulating materials. For example, the sacrificial layer 220 can be made of silicon oxide, and the first dielectric layer 240 can be made of silicon nitride. By using different materials, the adjacent film layers can be protected from damage during subsequent removal of the first dielectric layer 240 or processing of the sacrificial layer 220, thereby improving the accuracy of the process.
[0059] In some embodiments, forming a first dielectric layer 240 includes: such as Figure 6 As shown, an initial first dielectric layer 241 is formed, which simultaneously covers the end face of the sacrificial layer 220 and the outer wall and end face of the first portion 211 of the semiconductor layer, and extends to cover the surface of the stacked structure 200; as Figure 8 As shown, a portion of the initial first dielectric layer 241 located on the surface of the stacked structure 200, the end face of the first portion 211 of the semiconductor layer, and the outer sidewall of the first portion 211 of the semiconductor layer is removed to form the first dielectric layer 240. Since the initial first dielectric layer 241 can be formed using a large-area deposition process, the process difficulty of directly forming the first dielectric layer 240 can be reduced by etching the initial first dielectric layer 241 to form the first dielectric layer 240.
[0060] In some embodiments, such as Figure 5 As shown, before forming the initial first dielectric layer 241, the method may further include: forming an insulating material layer 230, which simultaneously covers the end face of the sacrificial layer 220 and the outer wall and end face of the first portion 211 of the semiconductor layer, and extends to cover the surface of the stacked structure 200.
[0061] The insulating material layer 230 can be made of silicon oxide and can be formed by methods such as PVD, CVD, or ALD. Since the insulating material layer 230 has better adhesion to the semiconductor layer 210, the adhesion between the first dielectric layer 240 and the semiconductor layer 210 can be improved by forming the insulating material layer 230 between the first dielectric layer 240 and the semiconductor layer 210.
[0062] In some embodiments, after forming the initial first dielectric layer 241, the method further includes: Figure 7As shown, a second dielectric layer 250 is formed, which at least fills the gap between the first portions 211 of two adjacent semiconductor layers; as Figure 8 As shown, using the second dielectric layer 250 as a mask, the initial first dielectric layer 241 is etched along the first direction X to remove part of the initial first dielectric layer 241, and the remaining initial first dielectric layer 241 forms the first dielectric layer 240.
[0063] The second dielectric layer 250 can be made of insulating materials such as silicon oxide, and can be formed using methods such as PVD, CVD, or ALD. Since the portion of the initial first dielectric layer 241 adjacent to the sacrificial layer 220 needs to be retained during the etching process of the initial first dielectric layer 241, when etching the initial first dielectric layer 241 using the second dielectric layer 250 as a mask, the etching rate of the second dielectric layer 250 needs to be different from that of the first dielectric layer 240; that is, the etching rate of the second dielectric layer 250 must be less than that of the first dielectric layer 240 to ensure the formation quality and shape of the first dielectric layer 240.
[0064] In the embodiments provided in this disclosure, in step S50, as Figure 9 As shown, the first portion 211 of the exposed semiconductor layer is subjected to a first doping process using the first dielectric layer 240 to form a doped region 401.
[0065] The first doping process can employ P-type doping atoms to transform the first portion 211 of the exposed semiconductor layer into a P-type semiconductor. The doping atoms in the first doping process can include boron (B), gallium (Ga), indium (In), etc. This embodiment uses boron as an example for the first doping process, but is not limited thereto.
[0066] In some embodiments, the first doping process may employ diborane (B₂H₆) gas to dope the first portion 211 of the exposed semiconductor layer via LPCVD, APCVD, or PECVD. For example, when using PECVD, doping may be performed using B₂H₆ gas at a temperature of 200°C to 400°C and a pressure of 1 Torr to 10 Torr.
[0067] In some embodiments, after the first doping treatment, the process further includes annealing the first portion 211 of the doped semiconductor layer to repair lattice damage caused by ion implantation, activate dopant atoms, and suppress ion diffusion into the undoped region 402. The annealing treatment can be one of rapid thermal annealing (RTA), laser annealing, microwave annealing, etc.
[0068] In some embodiments, the first portion of the semiconductor includes an undoped region 402 and a doped region 401 sequentially distributed along a first direction X and close to the trench 300. The doped region 401 is subsequently used to form the channel region 520 and the first source / drain region 510 of the transistor, and the undoped region 402 is subsequently used to form the second source / drain region 530 of the transistor. The first source / drain region 510 can be coupled to a bit line, and the second source / drain region 530 can be coupled to a capacitor to form a 1T1C (one transistor, one capacitor) memory cell, enabling signal transmission and data reading / writing functions.
[0069] In some embodiments, the method may further include: Figure 10 As shown, a gate structure is formed covering the channel region 520. The gate structure includes at least a gate oxide layer 601 and a gate layer 602 that sequentially cover the channel region 520.
[0070] The gate oxide layer 601 can be made of a high dielectric constant material. For example, it can be made of hafnium-based oxides, zirconium-based oxides, lanthanide oxides, yttrium-based oxides, tantalum-based oxides, titanate systems, etc. Specifically, it can be made of one or more of the following materials: hafnium dioxide (HfO2), hafnium silicate (HfSiO4), zirconium dioxide (ZrO2), zirconium silicate (ZrSiO4), lanthanum oxide (La2O3), praseodymium oxide (Pr2O3), strontium titanate (SrTiO3), gadolinium oxide (Gd2O3), yttrium oxide (Y2O3), scandium oxide (Sc2O3), and tantalum-hafnium oxide (HfTaO). The threshold voltage of the transistor can be controlled through the gate oxide layer 601, thereby improving the switching efficiency of the transistor.
[0071] The gate layer 602 can be made of a metallic material, such as at least one of tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium aluminum carbide (TiAlC), titanium aluminum carbonitride (TiAlCN), titanium silicon carbonitride (TiSiCN), aluminum carbonitride tantalum (TaAlCN), or silicon carbonitride tantalum (TaSiCN). The gate layer 602 controls the conduction state of the transistor, thereby achieving effective transistor control.
[0072] In some embodiments, refer again Figure 10 , combined Figure 11After forming the gate structure covering the channel region 520, the method further includes: using the gate structure as a mask, performing a second doping treatment on the doped region 401, so that a portion of the doped region 401 near the trench 300 forms a first source / drain region 510, and the doped region 401 covered by the gate structure forms the channel region 520. By performing the second doping treatment on the doped region 401, the first source / drain region 510 can be formed, and the first source / drain region 510 can subsequently be coupled to a bit line to achieve signal transmission.
[0073] The dopant ions in the second doping treatment are of a different type than those in the first doping treatment. Since the first doping treatment can use P-type dopant atoms to transform the first portion 211 of the exposed semiconductor layer into a P-type semiconductor, and to form the first source / drain region 510 within the doped region 401, N-type dopant atoms can be used to dope the doped region 401, forming the first source / drain region 510 coupled to the bit line. The dopant atoms in the second doping treatment may include pentavalent atoms such as phosphorus (P), arsenic (As), and antimony (Sb).
[0074] In some embodiments, the second doping treatment may employ ion implantation to dope a portion of the doped region 401. After the second doping treatment, the doped region 401 may be annealed to repair lattice damage caused by ion implantation, activate dopant atoms, and suppress ion diffusion into the undoped region 402. The annealing treatment may employ one of the following: rapid thermal annealing (RTA), laser annealing, or microwave annealing.
[0075] In some embodiments, such as Figure 12 As shown, combined with Figure 10 When performing a second doping treatment on the partially doped region 401, the conditions of the doping treatment, such as ion implantation energy and ion implantation dose, can be controlled to form a first source-drain extension region 511 between the first source-drain region 510 and the channel region 520. The doping concentration of the first source-drain extension region 511 is less than that of the first source-drain region 510, which can reduce the maximum electric field strength of the transistor, suppress the hot carrier effect, and reduce the leakage current of the device.
[0076] In some embodiments, refer again Figure 10 , combined Figure 11 After forming the doped region 401, the portion of the semiconductor layer 210 covered by the first dielectric layer 240 is an undoped region 402. The method further includes performing a second doping treatment on the undoped region 402 to form a second source / drain region 530 at least partially. The second source / drain region 530 is subsequently coupled to a capacitor to form a memory cell, enabling functions such as data reading and writing.
[0077] The second doping treatment of the undoped region 402 and the second doping treatment of the doped region 401 can use the same or similar N-type doping atoms, and the treatment conditions can also be the same or roughly the same.
[0078] In some embodiments, such as Figure 12 As shown, combined with Figure 10 When performing a second doping treatment on the undoped region 402, the doping conditions, such as ion implantation energy and ion implantation dose, can be controlled to form a second source / drain extension region 531 between the second source / drain region 530 and the channel region 520. The doping concentration of the second source / drain extension region 531 is less than that of the second source / drain region 530, which can reduce the maximum electric field strength of the transistor, reduce the drain-induced barrier reduction, alleviate the short-channel effect, reduce the gate-drain leakage current (GIBL), and thus improve the electrical reliability of the device.
[0079] In the above embodiment, since the doping concentration of the undoped region 402 is less than that of the doped region 401, that is, when the intrinsic semiconductor layer 210 is doped, the undoped region 402 is not doped. When the undoped region 402 forms the second source / drain region 530 and the doped region 401 forms the first source / drain region 510, the doping concentration of doped ions in the second source / drain region 530 can be reduced. This method can further reduce the tunneling electric field of the second source / drain region 530, further reduce the gate-induced drain leakage current (GIBL), and improve the electrical reliability of the device.
[0080] Based on the semiconductor structure formation method provided in the above embodiments, experiments show that, compared to transistors fabricated by simultaneously forming the first source / drain region 510, the channel region 520, and the second source / drain region 530 within the P-type semiconductor layer 210, transistors fabricated using the formation method provided in this disclosure exhibit a 45%~55% reduction in off-state leakage current, a 0.1%~0.2% reduction in subthreshold swing, a 1%~2% reduction in threshold voltage, and a 1.5%~2.5% increase in source / drain current. These data demonstrate that the semiconductor structure fabricated using the formation method provided in this disclosure exhibits a significant performance improvement.
[0081] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.
[0082] This disclosure provides a semiconductor structure fabricated using the semiconductor structure formation method provided in any of the above embodiments, such as... Figure 10 As shown, combined with Figure 9 The semiconductor structure includes: a substrate 100, a stacked structure 200, a trench 300, and a first dielectric layer 240.
[0083] The stacked structure 200 includes a semiconductor layer 210 and a sacrificial layer 220 sequentially stacked on a substrate 100, with the sacrificial layer 220 exposing a first portion 211 of the semiconductor layer; a trench 300 at least penetrates the stacked structure 200 and exposes a portion of the surface of the substrate 100, with the end face of the first portion 211 of the semiconductor layer forming a portion of the sidewall of the trench 300; the first portion 211 of the semiconductor layer includes at least a first source / drain region 510, a channel region 520, and a second source / drain region 530 sequentially distributed along a first direction X and away from the trench 300; a first dielectric layer 240 covers the second source / drain region 530 and is adjacent to the sacrificial layer 220, with the orthographic projection of the end face of the first dielectric layer 240 near the trench 300 on the substrate 100 coinciding with the orthographic projection of the boundary between the second source / drain region 530 and the channel region 520 on the substrate 100.
[0084] The second source / drain region 530 in the semiconductor structure provided in this disclosure is covered by the first dielectric layer 240. When doping the semiconductor layer 210, the first dielectric layer 240 can be used as a mask to retain a portion of the semiconductor layer 210 without doping to form an undoped region 402. The second source / drain region 530 can then be formed using this undoped region 402. This can reduce the tunneling electric field of the second source / drain region 530, reduce the gate-induced drain leakage current (GIBL), and improve the electrical reliability of the device.
[0085] In the embodiments provided in this disclosure, such as Figure 10 As shown, the semiconductor structure includes a substrate 100. Taking a silicon substrate as an example, the semiconductor structure provided in this disclosure is also applicable to other semiconductor substrates.
[0086] In the embodiments provided in this disclosure, such as Figure 10 As shown, combined with Figure 9The semiconductor structure includes a stacked structure 200 on a substrate 100. The stacked structure 200 includes a stacked semiconductor layer 210 and a sacrificial layer 220. The semiconductor layer 210 includes at least a first portion and a second portion. The orthographic projection of the second portion 212 of the semiconductor layer on the substrate 100 coincides with or at least partially overlaps with the orthographic projection of the sacrificial layer 220 on the substrate 100. The sacrificial layer 220 exposes the first portion 211 of the semiconductor layer. The first portion 211 of the semiconductor layer is subsequently used to form a transistor structure. The second portion 212 of the semiconductor layer plays a role in supporting and connecting the first portion 211 of the semiconductor layer during the transistor fabrication process to ensure that the first portion 211 of the semiconductor layer does not deform, thereby ensuring the quality of transistor fabrication.
[0087] The sacrificial layer 220 is located between adjacent semiconductor layers 210, which can ensure effective electrical isolation between adjacent semiconductor layers 210. In addition, the sacrificial layer 220 can also provide a certain support for the semiconductor layer 210, so as to avoid irreversible deformation of the semiconductor layer 210 and the problem of device yield reduction.
[0088] like Figure 10 As shown, the stacked structure 200 also includes a trench 300. The trench 300 extends through the stacked structure 200 at least along the second direction Y and exposes a portion of the surface of the substrate 100. The trench 300 can serve as a solution or gas channel in subsequent transistor fabrication processes. In addition, the trench 300 can also be used to form structures such as bit lines or capacitors, thereby realizing functions such as signal transmission or data reading and writing.
[0089] In some embodiments, such as Figure 11 and Figure 12 As shown, the first portion 211 of the semiconductor layer includes at least a first source / drain region 510, a channel region 520, and a second source / drain region 530 sequentially distributed along a first direction X and away from the trench 300. The channel region 520 serves as the current path for the transistor, allowing current to flow between the first source / drain region 510 and the second source / drain region 530 under the control of the gate voltage. The first source / drain region 510 can be coupled to a bit line, and the second source / drain region 530 can be coupled to a capacitor to form a 1T1C memory cell, enabling functions such as data reading and writing under signal control.
[0090] In the embodiments provided in this disclosure, reference is made again. Figure 10 , combined Figure 9The semiconductor structure includes a first dielectric layer 240, which covers the second source / drain region 530 and is adjacent to the sacrificial layer 220. The orthographic projection of the end face of the first dielectric layer 240 near the trench 300 onto the substrate 100 coincides with the orthographic projection of the boundary between the second source / drain region 530 and the channel region 520 onto the substrate 100. That is, the surface where the end face of the first dielectric layer 240 is located is the boundary line between the second source / drain region 530 and the channel region 520. When forming the second source / drain region 530, the first dielectric layer 240 can be used as a mask to reduce the ion doping concentration in the second source / drain region 530, thereby reducing the tunneling electric field of the second source / drain region 530, reducing the gate-to-drain leakage current (GIBL), and improving the electrical reliability of the device. In addition, the first dielectric layer 240 is the film layer required for the formation of the transistor gate structure, and there is no need to form a new film layer on the semiconductor layer 210. Moreover, the presence of the first dielectric layer 240 does not affect the dimensions of the device in the second direction Y.
[0091] In some embodiments, the first source / drain region 510 and the second source / drain region 530 include different doped ions. The second source / drain region 530 is formed by N-type doping in the undoped region 402 within the semiconductor layer 210, while the first source / drain region 510 is formed by N-type doping in the P-type semiconductor layer 210 region within the semiconductor layer 210. Therefore, compared to the first source / drain region 510, the second source / drain region 530 does not have P-type doped ions; that is, the doping concentration in the second source / drain region 530 is lower than that in the first source / drain region 510. By reducing the ion doping concentration in the second source / drain region 530, the leakage current of the transistor can be reduced, and the performance of the transistor can be improved.
[0092] In some embodiments, the second source / drain region 530 can also be an undoped region, that is, the second source / drain region 530 can be directly formed from the undoped region 402 without ion doping, which can further reduce the accumulation of bulk holes caused by the quantum tunneling effect, thereby improving the tunneling electric field, further reducing the leakage current of the transistor, and improving the reliability of the transistor.
[0093] In some embodiments, such as Figure 12 As shown, combined with Figure 9 and Figure 10In the first direction X, a first source / drain extension region 511 is formed between the first source / drain region 510 and the channel region 520, and a second source / drain extension region 531 is formed between the second source / drain region 530 and the channel region 520. That is, when the semiconductor layer 210 is doped to form the first source / drain region 510 and the second source / drain region 530, a lightly doped first source / drain extension region 511 can be formed between the first source / drain region 510 and the channel region 520, and a lightly doped second source / drain extension region 531 can be formed between the second source / drain region 530 and the channel region 520. By setting the first source / drain extension region 511 and the second source / drain extension region 531, the leakage current of the transistor can be further reduced and the performance of the transistor can be improved.
[0094] The ion doping concentration of the second source / drain extension region 531 can be lower than that of the second source / drain region 530, and the ion doping concentration of the first source / drain extension region 511 can be lower than that of the second source / drain region 530. That is, the first source / drain extension region 511 and the second source / drain extension region 531 can be lightly doped regions. For example, the N-type ion doping concentration in the first source / drain extension region 511 and the second source / drain extension region 531 can be [missing information - likely a value]. ~ The first source / drain region 510 and the second source / drain region 530 can be heavily doped regions. For example, the N-type ion doping concentration in the first source / drain extension region 511 and the second source / drain extension region 531 can be [missing information]. ~ By setting a first source-drain extension region 511 between the first source-drain region 510 and the channel region 520, and setting a second source-drain extension region 531 between the second source-drain region 530 and the channel region 520, the maximum electric field strength of the device can be reduced, the hot carrier effect can be suppressed, and the leakage current problem of the device can be improved.
[0095] The ion doping concentration of the second source / drain extension region 531 can be lower than that of the first source / drain extension region 511. Since the second source / drain extension region 531 is formed by N-type doping in the undoped region 402 within the semiconductor layer 210, while the first source / drain region 510 is formed by N-type doping in the P-type semiconductor layer 210 region within the semiconductor layer 210, the second source / drain extension region 531 does not possess P-type doped ions compared to the first source / drain extension region 511. In other words, the doping concentration in the second source / drain extension region 531 is lower than that in the first source / drain extension region 511. By reducing the ion doping concentration of the second source / drain extension region 531, the leakage current of the transistor can be further reduced, thereby improving the transistor's performance.
[0096] This disclosure also provides an electronic device 10 with storage functionality, such as... Figure 13As shown, the electronic device 10 includes a processing device 20 and a storage device 30 electrically connected to the processing device 20. The storage device 30 includes the semiconductor structure 40 in any of the above embodiments. The electronic device 10 can be a terminal device, such as a personal computer, mobile phone, tablet computer, consumer electronics such as smart home appliances, autonomous vehicles, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, or a server, data center, etc. The storage function in the electronic device 10 can be implemented through these storage devices 30.
[0097] In some embodiments, the processing device 20 and the memory device 30 can be two independent chips forming a separate memory. In other embodiments, the memory device 30 and the processing device 20 can also be integrated into the same chip to form an embedded memory. This electronic device 10 can solve the same technical problems and achieve the same expected results as the semiconductor structure 40 in any of the above embodiments.
[0098] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A stacked structure is formed on the substrate, the stacked structure including stacked semiconductor layers and an initial sacrificial layer, the stacked structure having trenches that at least penetrate the stacked structure and expose a portion of the surface of the substrate; The initial sacrificial layer is etched along a first direction to form a sacrificial layer that exposes a first portion of the semiconductor layer, the end of which forms a portion of the sidewall of the trench; the first direction is parallel to the substrate. A first dielectric layer is formed, which covers the end face of the sacrificial layer and extends along the first direction to cover a portion of the outer sidewall of a first portion of the semiconductor layer; Using the first dielectric layer, a first doping process is performed on a first portion of the exposed semiconductor layer to form a doped region.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, Forming a first dielectric layer includes: An initial first dielectric layer is formed, which simultaneously covers the end face of the sacrificial layer and the outer sidewall and end face of the first portion of the semiconductor layer, and extends to cover the surface of the stacked structure; The initial first dielectric layer is formed by removing portions of the surface of the stacked structure, the end face of the first portion of the semiconductor layer, and the outer sidewall of the first portion of the semiconductor layer.
3. The method for forming a semiconductor structure according to claim 2, characterized in that, After the initial first dielectric layer is formed, the process includes: A second dielectric layer is formed, which at least fills the voids between the first portions of two adjacent semiconductor layers.
4. The method for forming a semiconductor structure according to claim 3, characterized in that, Removing portions of the initial first dielectric layer located on the surface of the stacked structure, the end face of the first portion of the semiconductor layer, and the outer sidewall of the first portion of the semiconductor layer, including: Using the second dielectric layer as a mask, the initial first dielectric layer is etched along the first direction.
5. The method for forming a semiconductor structure according to claim 3 or 4, characterized in that, The etching rate of the second dielectric layer is less than that of the first dielectric layer.
6. The method for forming a semiconductor structure according to claim 4, characterized in that, After the doped region is formed, it includes: The doped region is subjected to a second doping treatment so that the portion of the doped region near the trench forms a first source / drain region, and the remaining doped region forms a channel region; the dopant ions in the second doping treatment are of a different type than the dopant ions in the first doping treatment.
7. The method for forming a semiconductor structure according to claim 6, characterized in that, After the doped region is formed, the portion of the semiconductor layer covered by the first dielectric layer is an undoped region, and the method further includes: The undoped region is subjected to the second doping process so that at least a portion of the undoped region forms a second source / drain region.
8. A semiconductor structure, characterized in that, include: Substrate; A stacked structure includes a semiconductor layer and a sacrificial layer sequentially stacked on the substrate, wherein the sacrificial layer exposes a first portion of the semiconductor layer; A trench that penetrates at least through the stacked structure and exposes a portion of the substrate surface, wherein the end face of a first portion of the semiconductor layer forms a portion of the sidewall of the trench; The first portion of the semiconductor layer includes at least a first source / drain region, a channel region, and a second source / drain region sequentially distributed along a first direction and away from the trench; the first direction is parallel to the substrate; A first dielectric layer covers the second source / drain region and is adjacent to the sacrificial layer. The orthographic projection of the end face of the first dielectric layer near the trench on the substrate coincides with the orthographic projection of the boundary between the second source / drain region and the channel region on the substrate.
9. The semiconductor structure according to claim 8, characterized in that, In the first direction, there is a first source-drain extension region between the first source-drain region and the channel region, and there is a second source-drain extension region between the second source-drain region and the channel region; The ion doping concentration of the second source / drain extension region is less than that of the first source / drain extension region.
10. The semiconductor structure according to claim 8 or 9, characterized in that, The second source / drain region is an undoped region.
11. The semiconductor structure according to claim 8 or 9, characterized in that, The first source / drain region and the second source / drain region contain different doped ions.
12. An electronic device, characterized in that, include: A processing device; and a memory device electrically connected to the processing device, the memory device comprising the semiconductor structure of any one of claims 8-11.