Semiconductor structure and forming method thereof
By introducing a dielectric layer to isolate the source and drain doped layers in the CFET device, the current leakage problem is solved and the electrical performance of the device is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2024-11-12
- Publication Date
- 2026-05-12
AI Technical Summary
Current CFET device manufacturing technology has not been able to effectively solve the current leakage problem at the source and drain, which affects its electrical performance.
By forming a first dielectric layer on the first source-drain doped layer and then forming a second source-drain doped layer thereon, electrical isolation between the first source-drain doped layer and the second source-drain doped layer is achieved, thereby reducing leakage current.
The switching current ratio of the semiconductor structure was improved, and its performance was optimized.
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Figure CN122028490A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density, higher integration, and higher performance. When the technology node reaches below 2nm, the manufacturing of FINFET and GAA transistors can no longer reduce the size. At this point, a new device structure, CFET (Complementary field-effect transistor), can further increase transistor density by vertically stacking P-type and N-type transistors, thus becoming one of the strong candidates for the continued advancement of Moore's Law.
[0003] However, the manufacturing technology of CFET devices is still under exploration, and their electrical performance still needs to be improved. Summary of the Invention
[0004] In view of this, embodiments of the present invention provide a semiconductor structure and a method for forming the same, which can improve the performance of the semiconductor structure.
[0005] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of stacked structures on the substrate, the stacked structures including: a first channel structure located on the substrate and a second channel structure located on the first channel structure; filling a first source / drain doped layer on the substrate between the stacked structures, the first source / drain doped layer covering the sidewalls of the first channel structure; forming a first dielectric layer on the first source / drain doped layer; and filling a second source / drain doped layer on the first dielectric layer, the second source / drain doped layer covering the sidewalls of the second channel structure.
[0006] This invention provides a semiconductor structure, including: a substrate; a plurality of stacked structures, the stacked structures including a first channel structure on the substrate and a second channel structure on the first channel structure; a first source / drain doped layer located on the substrate between the stacked structures and covering the side of the first channel structure; a first dielectric layer located on the first source / drain doped layer; and a second source / drain doped layer located on the first dielectric layer and covering the side of the second channel structure.
[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0008] In the technical solution provided by the embodiments of the present invention, a first dielectric layer is formed on the first source-drain doped layer, and a second source-drain doped layer is formed on the first dielectric layer. This enables electrical isolation between the first source-drain doped layer and the second source-drain doped layer through the first dielectric layer, reduces the leakage current between the first source-drain doped layer and the second source-drain doped layer, and improves the switching current ratio of the semiconductor structure, thereby optimizing the performance of the semiconductor structure. Attached Figure Description
[0009] To more clearly illustrate the technical solutions of the embodiments of this specification, the drawings used in the description of the embodiments of this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0010] Figures 1 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0011] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density, higher integration, and higher performance. When the technology node reaches below 2nm, FINFET and GAA transistor manufacturing can no longer further reduce size. CFET (Complementary Field-Effect Transistor), by vertically stacking P-type and N-type transistors, can further increase transistor density, thus becoming one of the strong candidates for continuing Moore's Law. However, the source and drain of CFET are prone to current leakage, affecting CFET performance.
[0012] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of stacked structures on the substrate, the stacked structures including: a first channel structure located on the substrate and a second channel structure located on the first channel structure; filling a first source / drain doped layer on the substrate between the stacked structures, the first source / drain doped layer covering the sidewalls of the first channel structure; forming a first dielectric layer on the first source / drain doped layer; and filling a second source / drain doped layer on the first dielectric layer, the second source / drain doped layer covering the sidewalls of the second channel structure.
[0013] In the semiconductor structure formation method provided by the embodiments of the present invention, a first dielectric layer is formed on a first source-drain doped layer, and a second source-drain doped layer is formed on the first dielectric layer. This enables electrical isolation between the first source-drain doped layer and the second source-drain doped layer through the first dielectric layer, reduces the leakage current between the first source-drain doped layer and the second source-drain doped layer, and improves the switching current ratio of the semiconductor structure, thereby optimizing the performance of the semiconductor structure.
[0014] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0015] Figures 1 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0016] In this embodiment, refer to Figure 1 A substrate 100 is provided. The substrate 100 is used to provide a process platform for the formation of subsequent semiconductor structures.
[0017] The substrate 100 can be made of one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, the substrate 100 is a silicon substrate.
[0018] In this embodiment, refer to Figure 1 A plurality of stacked structures 200 are formed on the substrate 100. Each stacked structure 200 includes a first channel structure 210 and a second channel structure 220, wherein the first channel structure 210 is located on the substrate 100 and the second channel structure 220 is located on the first channel structure 210. This allows the first channel structure 210 and the second channel structure 220 to be stacked vertically, thereby improving the integration density of the semiconductor structure.
[0019] In some examples, refer to Figure 1 The first channel structure 210 may include: alternatingly stacked first channel layers 211 and first sacrificial layers 212, with first sidewalls 213 on both sides of the first sacrificial layer 212 connected to the adjacent first channel layers 211. The first channel layers 211 are used to form a channel, the first sacrificial layers 212 are used to occupy space for structures formed in subsequent processes, and the first sidewalls 213 are used to reduce the capacitance between the gate and source / drain that are subsequently formed.
[0020] The material of the first channel layer 211 can be one or more of silicon (Si), germanium (Ge), silicon germanide (SiGe), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), and indium gallium nitride (GaIn). In this embodiment, the material of the first channel layer 211 is silicon.
[0021] The material of the first sacrificial layer 212 can be one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The first sacrificial layer 212 is made of a different material than the first channel layer 211. Different materials have different removal rates. By selecting an appropriate process, damage to the first channel layer 211 during subsequent removal of the first sacrificial layer 212 can be reduced. In this embodiment, the material of the first sacrificial layer 212 is silicon germanide.
[0022] The material of the first sidewall 213 can be one or more of silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxycarbide (SiCO), silicon oxycarbonide (SiCON), and silicon carbide nitride (SiCN). In this embodiment, the material of the first sidewall 213 is silicon nitride.
[0023] In some examples, refer to Figure 1 The second channel structure 220 may include: alternately stacked second channel layers 221 and second sacrificial layers 222, with second sidewalls 223 on both sides of the second sacrificial layer 222 connected to the adjacent second channel layer 221. The second channel layer 224 is used to form channels, the second sacrificial layer 222 is used to occupy space for structures formed in subsequent processes, and the second sidewalls 223 are used to support the adjacent second channel layer 221 after the second sacrificial layer 222 is subsequently removed.
[0024] The material of the second channel layer 221 can be one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, the material of the second channel layer 221 is silicon.
[0025] The material of the second sacrificial layer 222 can be one or more of silicon germanide, silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The material of the second sacrificial layer 222 differs from that of the second channel layer 221. Different materials have different removal rates. By selecting an appropriate process, damage to the second channel layer 221 during subsequent removal of the second sacrificial layer 222 can be reduced. In this embodiment, the material of the second sacrificial layer 222 is silicon germanide.
[0026] The material of the second sidewall 223 can be one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbide, and silicon carbide. In this embodiment, the material of the second sidewall 223 is silicon nitride.
[0027] In some examples, refer to Figure 1 The stacked structure 200 may further include a second dielectric layer 230 located between the first channel structure 210 and the second channel structure 220. The second dielectric layer 230 can serve as an isolation layer, acting as a barrier layer to prevent boundary shift during the formation of work function layers of different thicknesses between the upper and lower transistors.
[0028] The material of the second dielectric layer 230 can be one or more of silicon nitride, silicon oxide, silicon carbide, silicon oxycarbonide, and silicon carbide nitride. In this embodiment, the material of the second dielectric layer 230 is silicon nitride.
[0029] The thickness of the second dielectric layer 230 can be 3nm to 10nm. In this embodiment, the thickness of the second dielectric layer 230 is 3nm.
[0030] The sides of the first channel structure 210, the second dielectric layer 230, and the second channel structure 220 may be on the same plane or on different planes. In this embodiment, the sides of the first channel structure 210, the second dielectric layer 230, and the second channel structure 220 are on the same plane.
[0031] In some examples, refer to Figure 1 The stacked structure 200 may further include a dummy gate structure 240 located above the second channel structure 220. The dummy gate structure 240 is used to occupy space for a gate structure layer (not shown) formed in subsequent processes of the semiconductor structure, wherein the gate structure layer includes a work function layer for adjusting the threshold voltage of the transistor formed in the semiconductor structure.
[0032] In some examples, refer to Figure 1 The pseudo gate structure 240 may include: a gate oxide layer 241 located on the second channel structure 220, a pseudo gate layer 242 located on the gate oxide layer 241, and third sidewalls 243 located on both sides of the gate oxide layer 241 and the pseudo gate layer 242.
[0033] The gate oxide layer 241 can be made of one or more high-k dielectric materials such as hafnium oxide (HfO2), zirconium oxide (ZrO2), silicon hafnium oxide (HfSiO), silicon oxynitride hafnium (HfSiON), tantalum hafnium oxide (HfTaO), titanium hafnium oxide (HfTiO), zirconium hafnium oxide (HfZrO), or aluminum oxide (Al2O3).
[0034] The material of the pseudo-gate layer 242 can be polycrystalline silicon.
[0035] The material of the third sidewall 243 can be one or more of silicon nitride, silicon oxide, silicon carbide, silicon oxycarbonide, and silicon carbide nitride. The material of the third sidewall 243 is different from that of the dummy gate layer 242. Different materials have different removal rates. By selecting a suitable process, damage to the third sidewall 243 during subsequent removal of the dummy gate layer 242 can be reduced. In this embodiment, the material of the third sidewall 243 is silicon nitride.
[0036] The side surface of the dummy gate structure 240 may be on the same plane or on a different plane from the side surface of the second channel structure 220. In this embodiment, the side surface of the dummy gate structure 240 is on the same plane as the side surface of the second channel structure 220.
[0037] In this embodiment, refer to Figures 2 to 7 A first source / drain doped layer 300 is formed on the substrate 100 adjacent to the first channel structure 210. The first source / drain doped layer 300 covers the sidewalls of the first channel structure 210, thereby enabling the first source / drain doped layer 300 to connect with the channel formed by the first channel structure 210. By providing a low-resistivity path through the first source / drain doped layer 300, the current transport efficiency in the corresponding transistor formed can be improved.
[0038] The material of the first source / drain doped layer 300 can be one or more of germanium, silicon, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, the material of the first source / drain doped layer 300 is silicon germanide.
[0039] The first source / drain doped layer 300 can be either P-type or N-type doped. In this embodiment, the first source / drain doped layer 300 is P-type doped.
[0040] The doping material of the first source / drain doped layer 300 can be one or more of boron (B), aluminum (Al), gallium (Ga), and indium (In). In this embodiment, the first source / drain doped layer 300 is boron doped.
[0041] The top surface of the first source / drain doped layer 300 may be on the same plane as the top surface of the first channel structure 210 or on a different plane. In this embodiment, the top surface of the first source / drain doped layer 300 and the top surface of the first channel structure 210 are on the same plane.
[0042] The process of forming the first source / drain doped layer 300 on the substrate 100 adjacent to the first channel structure 210 can be a flowable chemical vapor deposition (FCVD) process, a plasma enhanced oxide deposition (PEOX) process, or an epitaxial growth process. In this embodiment, an epitaxial growth process is used.
[0043] The epitaxial growth process can uniformly grow the first source / drain doped layer 300 on the substrate 100 between the first channel structures 210, forming a first source / drain doped layer 300 with high film quality. The epitaxial growth process can better control the process parameters, has high process controllability, and is easy to obtain a more accurate film thickness. At the same time, the epitaxial growth process is easy to form a film with fewer impurities, resulting in a high quality first source / drain doped layer 300.
[0044] In this embodiment, refer to Figures 2 to 5 Before filling the first source / drain doped layer 300, a conformal protective layer 400 is formed on the side of the second channel structure 220 and the side of the second dielectric layer 230.
[0045] In this way, during the subsequent process of forming the first source / drain doped layer 300, the second channel structure 220 and the second dielectric layer 230 can be protected by the protective layer 400, reducing the damage to the second channel structure 220 and the second dielectric layer 230 caused by subsequent processes.
[0046] In this embodiment, the step of conformally covering the protective layer 400 on the side of the second channel structure 220 and the side of the second dielectric layer 230 may include: referring to Figures 2 to 5 A placeholder layer 500 is filled on the base 100 between the stacked structures 200, the placeholder layer 500 covering the sidewall of the first channel structure 210; a protective material layer 410 is conformally covered on the side of the second channel structure 220 and the top surface of the placeholder layer 500; the protective material layer 410 at the top surface of the placeholder layer 500 is removed, and the protective material layer 410 on the side of the second channel structure 220 is retained as a protective layer 400.
[0047] Remove the protective material layer 410 at the top surface of the occupier layer 500, and retain the protective material layer 410 at the side surface of the second channel structure 220 and the side surface of the second dielectric layer 230, so as to protect the side surface of the second channel structure 220 and the side surface of the second dielectric layer 230 in the subsequent etching process.
[0048] The protective layer 400 can be made of one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbide, and silicon carbide. In this embodiment, the protective layer 400 is made of silicon nitride.
[0049] The conformal coating protective layer 400 can be formed by one or more of ion deposition or atomic layer deposition. The protective layer 400 formed by ion deposition or atomic layer deposition has good uniformity and can achieve conformal coverage of the protective layer 400 on the sides of the second channel structure 220, the sides of the second dielectric layer 230, and the top surface of the placeholder layer 500. In this embodiment, the protective layer 400 is formed by ion deposition.
[0050] It should be noted that appropriately reducing the thickness of the protective layer 400 facilitates its removal in subsequent processes, reducing the difficulty and time of the process; appropriately increasing the thickness of the protective layer 400 prevents it from being consumed prematurely, thereby improving the protection effect on the second channel structure 220 and the second dielectric layer 230 in subsequent processes. Therefore, the thickness of the protective layer 400 can be 1 nm to 5 nm. In this embodiment, the thickness of the protective layer 400 is 1 nm.
[0051] The process of removing the protective material layer 410 at the top surface of the occupier layer 500 can employ anisotropic etching. In this embodiment, ion etching is used, and the etching selectivity ratio of the ion etching process for the protective material layer 410 at the top surface of the occupier layer 500 and the protective material layer 410 on the sides of the stacked structure 200 (the sides of the second channel structure 220 and the second dielectric layer 230) is greater than or equal to 2:1. The ion etching process can vertically and orientally remove the protective layer at the top surface of the occupier layer 500 while reducing the amount of protective material layer 410 removed from the sides of the second channel structure 220 and the second dielectric layer 230.
[0052] In this embodiment, in conjunction with reference Figure 2 and Figure 3 The step of filling a placeholder layer 500 on the substrate 100 between the first channel structures 210 may include: filling a placeholder material layer 510 on the substrate 100 between the first channel structures 210; removing a portion of the thickness of the placeholder material layer 510, and retaining the placeholder material layer 510 on the side of the first channel structure 210 as a placeholder layer 500.
[0053] This exposes the sides of the second channel structure 220 and the second dielectric layer 230, thereby providing support for the subsequent process of forming a protective layer 400 on the sides of the second channel structure 220 and the second dielectric layer 230; the placeholder layer 500 is used to place the first source / drain doped layer 300 formed in the subsequent process, preventing the subsequent protective material layer 410 from being formed on the sides of the first channel structure 210.
[0054] The material of the placeholder layer 500 can be one or more of silicon nitride, silicon oxide, silicon carbide, silicon oxycarbonide, and silicon carbide nitride. The material of the placeholder layer 500 is different from that of the protective layer 400. Different materials have different removal rates. By selecting an appropriate process, damage to the protective layer 400 can be reduced when the placeholder layer 500 covering the side of the first channel structure 210 is subsequently removed. In this embodiment, the material of the placeholder layer 500 is silicon oxide.
[0055] The process of filling the spacer material layer 510 on the substrate 100 between the first channel structures 210 can be one or more of FCVD, PEOX, and epitaxial growth processes. In this embodiment, FCVD is used.
[0056] The process of removing a portion of the occupier material layer 510 can be one or more isotropic etching processes, such as wet etching or vapor phase etching. In this embodiment, wet etching is used.
[0057] In this embodiment, refer to Figure 6 The step of filling the first source / drain doped layer 300 may include: removing the placeholder layer 500; and filling the first source / drain doped layer 300 at the original position of the placeholder layer 500.
[0058] The process for removing the occupant layer 500 can be one or more isotropic etching processes, such as wet etching or vapor phase etching. In this embodiment, wet etching is used. Wet etching can uniformly etch the occupant layer 500 in all directions, thereby making it easier to reduce the residual occupant layer 500 on the sides of the first channel structure 210 and the bottom surface of the protective layer 400.
[0059] In this embodiment, refer to Figures 8 to 10 A first dielectric layer 600 is formed on the first source / drain doped layer 300.
[0060] The first dielectric layer 600 is located between the first source / drain doped layer 300 and the second source / drain doped layer formed by subsequent processes. It can achieve electrical isolation between the first source / drain doped layer 300 and the second source / drain doped layer, reduce the leakage current between the first source / drain doped layer 300 and the second source / drain doped layer, and improve the switching current ratio of the semiconductor structure.
[0061] The top surface of the first dielectric layer 600 may be on the same plane as the top surface of the second dielectric layer 230 or on different planes. In this embodiment, the top surface of the first dielectric layer 600 and the top surface of the second dielectric layer 230 are on the same plane.
[0062] In this embodiment, in conjunction with reference Figure 8 and Figure 9The step of forming a first dielectric layer 600 on the first source / drain doped layer 300 may include: filling the first source / drain doped layer 300 with a dielectric material layer 611; removing a portion of the dielectric material layer 611, leaving the dielectric material layer 611 on the side of the second dielectric layer 230 as a first intermediate dielectric layer 610; removing the protective layer 400 covering the side of the second channel structure 220, leaving the protective layer 400 on the side of the second dielectric layer 230 as a second intermediate dielectric layer 620; wherein the first intermediate dielectric layer 610 and the second intermediate dielectric layer 620 constitute the first dielectric layer 600.
[0063] By removing a portion of the dielectric material layer 611, the dielectric material layer 611 remaining on the side of the second dielectric layer 230 can expose the side of the protective layer 400 covering the second channel structure 220; by removing the protective layer 400 covering the side of the second channel structure 220, the protective layer 400 remaining on the side of the second dielectric layer 230 can be used as the second intermediate dielectric layer 620, thus exposing the side of the second channel structure 220.
[0064] The process of filling the dielectric material layer 611 on the first source / drain doped layer 300 can be one or more of the following: FCVD process, PEOX process, and epitaxial growth process. In this embodiment, the FCVD process is used.
[0065] The process of removing a portion of the dielectric material layer 611 can be one or more isotropic etching processes, such as wet etching or vapor phase etching. In this embodiment, wet etching is used.
[0066] The process for removing the protective layer 400 covering the side of the second channel structure 220 can be one or more isotropic etching processes, such as wet etching or vapor phase etching. In this embodiment, vapor phase etching is used.
[0067] In this embodiment, refer to Figures 10 to 11 A second source / drain doped layer 700 is filled on the first dielectric layer 600. The second source / drain doped layer 700 covers the sides of the second channel structure 220, thereby enabling the second source / drain doped layer 700 to connect with the channel formed by the second channel structure 220. By providing a low-resistivity path through the second source / drain doped layer 700, the current transport efficiency in the corresponding transistor formed can be improved.
[0068] The material of the second source / drain doped layer 700 can be one or more of silicon phosphide (SiP), silicon, silicon carbide, gallium nitride, gallium arsenide, and indium gallium phosphate. In this embodiment, the material of the second source / drain doped layer 700 is silicon phosphide.
[0069] The second source / drain doped layer 700 can be either P-type or N-type doped. The second source / drain doped layer 700 has a different doping type than the first source / drain doped layer 300, and is used to form different types of transistors. In this embodiment, the second source / drain doped layer 700 is N-type doped.
[0070] The doping material of the second source / drain doped layer 700 can be one or more of phosphorus (P), arsenic (As), and antimony (Sb). In this embodiment, the second source / drain doped layer 700 is phosphorus-doped.
[0071] The top surface of the second source / drain doped layer 700 may be on the same plane as the top surface of the second channel structure 220 or on a different plane. In this embodiment, the top surface of the second source / drain doped layer 700 and the top surface of the second channel structure 220 are on the same plane.
[0072] The process of filling the second source / drain doped layer 700 on the first dielectric layer 600 can be one or more of FCVD, PEOX, or epitaxial growth processes. In this embodiment, an epitaxial growth process is used.
[0073] To address the aforementioned technical problems, the present invention also provides a semiconductor structure, comprising: a substrate; a plurality of stacked structures, the stacked structures including a first channel structure located on the substrate and a second channel structure located on the first channel structure; a first source / drain doped layer located on the substrate between the stacked structures and covering the sidewalls of the first channel structure; a first dielectric layer located on the first source / drain doped layer; and a second source / drain doped layer located on the first dielectric layer and covering the sidewalls of the second channel structure.
[0074] In the semiconductor structure provided by the embodiments of the present invention, the first dielectric layer is located between the first source / drain doped layer and the second source / drain doped layer. This enables electrical isolation between the first source / drain doped layer and the second source / drain doped layer through the first dielectric layer, reduces the leakage current between the first source / drain doped layer and the second source / drain doped layer, and improves the switching current ratio of the semiconductor structure, thereby optimizing the performance of the semiconductor structure.
[0075] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0076] Figure 11 This is a schematic diagram of an embodiment of the semiconductor structure formation method of the present invention.
[0077] In this embodiment, reference Figure 11A semiconductor structure includes: a substrate 100; a plurality of stacked structures 200, the stacked structures 200 including a first channel structure 210 located on the substrate 100 and a second channel structure 220 located on the first channel structure 210; a first source / drain doped layer 300 located on the substrate 100 between the stacked structures 200, covering the side of the first channel structure 210; a first dielectric layer 600 located on the first source / drain doped layer 300; and a second source / drain doped layer 700 located on the first dielectric layer 600, covering the side of the second channel structure 220.
[0078] Substrate 100 is used to provide a process platform for the formation of subsequent semiconductor structures.
[0079] The substrate 100 can be made of one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, the substrate 100 is a silicon substrate.
[0080] In some examples, the first channel structure 210 may include: alternating stacked first channel layers 211 and first sacrificial layers 212, with first sidewalls 213 on both sides of the first sacrificial layer 212 connected to the adjacent first channel layer 211. The first channel layers 211 are used to form channels, the first sacrificial layers 212 are used to occupy space for structures formed in subsequent processes, and the first sidewalls 213 are used to support the adjacent first channel layers 211 after the first sacrificial layers 212 are subsequently removed.
[0081] The material of the first channel layer 211 can be one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, the material of the first channel layer 211 is silicon.
[0082] The material of the first sacrificial layer 212 can be one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The first sacrificial layer 212 is made of a different material than the first channel layer 211. Different materials have different removal rates. By selecting an appropriate process, damage to the first channel layer 211 during subsequent removal of the first sacrificial layer 212 can be reduced. In this embodiment, the material of the first sacrificial layer 212 is silicon germanide.
[0083] The material of the first sidewall 213 can be one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbide, and silicon carbide. In this embodiment, the material of the first sidewall 213 is silicon nitride.
[0084] In some examples, the second channel structure 220 may include: alternately stacked second channel layers 221 and second sacrificial layers 222, with second sidewalls 223 on both sides of the second sacrificial layers 222 connected to the adjacent second channel layers 221. The second channel layers 221 are used to form a channel, the second sacrificial layers 222 are used to occupy space for structures formed by subsequent processes, and the second sidewalls 223 are used to reduce the capacitance between the gate and the source / drain.
[0085] The material of the second channel layer 221 can be one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, the material of the second channel layer 221 is silicon.
[0086] The material of the second sacrificial layer 222 can be one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The material of the second sacrificial layer 222 differs from that of the second channel layer 221. Different materials have different removal rates. By selecting an appropriate process, damage to the second channel layer 221 during subsequent removal of the second sacrificial layer 222 can be reduced. In this embodiment, the material of the second sacrificial layer 222 is silicon germanide.
[0087] The material of the second sidewall 223 can be one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbide, and silicon carbide. In this embodiment, the material of the second sidewall 223 is silicon nitride.
[0088] In some examples, the stacked structure 200 may further include a second dielectric layer 230 located between the first channel structure 210 and the second channel structure 220. The second dielectric layer 230 can act as a barrier layer to prevent boundary shift during the formation of work function layers of different thicknesses for the upper and lower transistors.
[0089] The material of the second dielectric layer 230 can be one or more of silicon nitride, silicon oxide, silicon carbide, silicon oxycarbonide, and silicon carbide nitride. In this embodiment, the material of the second dielectric layer 230 is silicon nitride.
[0090] The thickness of the second dielectric layer 230 can be 3nm to 10nm. In this embodiment, the thickness of the second dielectric layer 230 is 3nm.
[0091] The sides of the first channel structure 210, the second dielectric layer 230, and the second channel structure 220 may be on the same plane or on different planes. In this embodiment, the sides of the first channel structure 210, the second dielectric layer 230, and the second channel structure 220 are on the same plane.
[0092] In some examples, the first dielectric layer 600 may include a first intermediate dielectric layer 610 and a second intermediate dielectric layer 620, wherein the first intermediate dielectric layer 610 is located on the first source / drain doped layer 300; and the second intermediate dielectric layer 620 is located on the first source / drain doped layer 300 and between the first intermediate dielectric layer 610 and the stacked structure 200.
[0093] The material of the first intermediate dielectric layer 610 is one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbide, and silicon carbide. In this embodiment, the material of the first intermediate dielectric layer 610 is silicon oxide.
[0094] The material of the second intermediate dielectric layer 620 is one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbide, and silicon carbide. In this embodiment, the material of the second intermediate dielectric layer 620 is silicon nitride.
[0095] The thickness of the second intermediate dielectric layer 620 can be 1 nm to 5 nm. In this embodiment, the thickness of the second intermediate dielectric layer 620 is 1 nm.
[0096] In some examples, the stacked structure 200 may further include a dummy gate structure 240 located above the second channel structure 220. The dummy gate structure 240 is used to occupy space for a gate structure layer formed in subsequent processes of the semiconductor structure, wherein the gate structure layer includes a work function layer for adjusting the threshold voltage of the transistors formed in the semiconductor structure.
[0097] In some examples, the pseudo gate structure 240 may include: a gate oxide layer 241 on the second channel structure 220, a pseudo gate layer 242 on the gate oxide layer 241, and third sidewalls 243 on both sides of the gate oxide layer 241 and the pseudo gate layer 242.
[0098] The gate oxide layer 241 can be made of one or more high-k dielectric materials such as hafnium oxide (HfO2), zirconium oxide (ZrO2), silicon hafnium oxide (HfSiO), silicon oxynitride hafnium (HfSiON), tantalum hafnium oxide (HfTaO), titanium hafnium oxide (HfTiO), zirconium hafnium oxide (HfZrO), or aluminum oxide (Al2O3).
[0099] The material of the pseudo-gate layer 242 can be polycrystalline silicon.
[0100] The material of the third sidewall 243 can be one or more of silicon nitride, silicon oxide, silicon carbide, silicon oxycarbonide, and silicon carbide nitride. The material of the third sidewall 243 is different from that of the dummy gate layer 242. Different materials have different removal rates. By selecting a suitable process, damage to the third sidewall 243 during subsequent removal of the dummy gate layer 242 can be reduced. In this embodiment, the material of the third sidewall 243 is silicon nitride.
[0101] The side surface of the dummy gate structure 240 may be on the same plane or on a different plane from the side surface of the second channel structure 220. In this embodiment, the side surface of the dummy gate structure 240 is on the same plane as the side surface of the second channel structure 220.
[0102] The material of the first source / drain doped layer 300 can be one or more of germanium, silicon, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, the material of the first source / drain doped layer 300 is silicon germanide.
[0103] The first source / drain doped layer 300 can be either P-type or N-type doped. In this embodiment, the first source / drain doped layer 300 is P-type doped.
[0104] The doping material of the first source / drain doped layer 300 can be one or more of boron, aluminum, gallium, and indium. In this embodiment, the first source / drain doped layer 300 is boron doped.
[0105] The top surface of the first source / drain doped layer 300 may be on the same plane as the top surface of the first channel structure 210 or on a different plane. In this embodiment, the top surface of the first source / drain doped layer 300 and the top surface of the first channel structure 210 are on the same plane.
[0106] The material of the first dielectric layer 600 can be one or more of silicon nitride, silicon oxide, silicon carbide, silicon oxycarbonide, and silicon carbide nitride. The material of the first dielectric layer 600 is different from that of the protective layer 400. Different materials have different removal rates. By selecting an appropriate process, damage to the first dielectric layer 600 during the subsequent removal of the protective layer 400 covering the sides of the second channel structure 220 can be reduced. In this embodiment, the material of the first dielectric layer 600 is silicon oxide.
[0107] The top surface of the first dielectric layer 600 may be on the same plane as the top surface of the second dielectric layer 230 or on different planes. In this embodiment, the top surface of the first dielectric layer 600 and the top surface of the second dielectric layer 230 are on the same plane.
[0108] The material of the second source / drain doped layer 700 can be one or more of silicon phosphide, silicon, silicon carbide, gallium nitride, gallium arsenide, and indium gallium phosphate. In this embodiment, the material of the second source / drain doped layer 700 is silicon phosphide.
[0109] The second source / drain doped layer 700 can be either P-type or N-type doped. The second source / drain doped layer 700 has a different doping type than the first source / drain doped layer 300, and is used to form different types of transistors. In this embodiment, the second source / drain doped layer 700 is N-type doped.
[0110] The doping material of the second source / drain doped layer 700 can be one or more of phosphorus, arsenic, and antimony. In this embodiment, the second source / drain doped layer 700 is phosphorus-doped.
[0111] The top surface of the second source / drain doped layer 700 may be on the same plane as the top surface of the second channel structure 220 or on a different plane. In this embodiment, the top surface of the second source / drain doped layer 700 and the top surface of the second channel structure 220 are on the same plane.
[0112] It is understood that the above description provides multiple embodiment solutions provided by the embodiments of the present invention. The optional methods described in each embodiment solution can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment solutions. These can all be considered as the embodiment solutions disclosed and published by the present invention.
[0113] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: Provide a base; Multiple stacked structures are formed on the substrate, the stacked structures including: a first channel structure located on the substrate and a second channel structure located on the first channel structure; A first source / drain doped layer is filled on the substrate between the stacked structures, and the first source / drain doped layer covers the side of the first channel structure. A first dielectric layer is formed on the first source / drain doped layer; A second source / drain doped layer is filled on the first dielectric layer, and the second source / drain doped layer covers the side surface of the second channel structure.
2. The forming method according to claim 1, characterized in that, Before filling the first source / drain doped layer, the formation method further includes: A shape-preserving protective layer is applied to the side of the second channel structure.
3. The forming method according to claim 2, characterized in that, The steps for applying a conformal coating include: A placeholder layer is filled on the substrate between the stacked junctions, the placeholder layer covering the sidewalls of the first channel structure; A conformal protective material layer is applied to the sides of the second channel structure and the top surface of the occupant layer. Remove the protective material layer on the top surface of the occupant layer, and retain the protective material layer on the side of the second channel structure as a protective layer.
4. The forming method according to claim 3, characterized in that, The steps for filling the first source / drain doped layer include: Remove the placeholder layer; A first source / drain doped layer is filled at the original location of the placeholder layer.
5. The forming method according to claim 4, characterized in that, The process for removing the occupier layer includes: Wet etching process.
6. The forming method according to claim 3, characterized in that, The process of removing the protective material layer at the top surface of the occupier layer includes: Ion etching process.
7. The forming method according to claim 6, characterized in that, The etching process employs an etching selectivity ratio of 2:1 for the protective material layer at the top surface of the occupant layer and the protective material layer on the side surface of the stacked structure.
8. The forming method according to claim 3, characterized in that, The steps for filling the placeholder layer include: A layer of spacer material is filled on the substrate between the stacked structures; A portion of the spacer material layer is removed, and the spacer material layer remaining on the side of the first channel structure is used as a spacer layer.
9. The forming method according to claim 2, characterized in that, The stacked structure further includes a second dielectric layer, which is located between the first channel structure and the second channel structure. The steps for forming the first dielectric layer include: A dielectric material layer is filled on the first source / drain doped layer; A portion of the dielectric material layer is removed, and the dielectric material layer remaining on the side of the second dielectric layer is used as the first intermediate dielectric layer. Remove the protective layer covering the side of the second channel structure, and retain the protective layer on the side of the second dielectric layer as the second intermediate dielectric layer; The first intermediate dielectric layer and the second intermediate dielectric layer are used as the first dielectric layer.
10. The forming method according to claim 2, characterized in that, The thickness of the protective layer is 1 nm to 5 nm.
11. A semiconductor structure, characterized in that, include: Base; Multiple stacked structures, the stacked structures including a first channel structure located on a substrate and a second channel structure located on the first channel structure; A first source / drain doped layer is located on a substrate between the stacked structures and covers the side of the first channel structure; The first dielectric layer is located on the first source / drain doped layer; The second source / drain doped layer is located on the first dielectric layer and covers the side of the second channel structure.
12. The semiconductor structure according to claim 11, wherein the first dielectric layer comprises: The first intermediate dielectric layer is located on the first source / drain doped layer; The second intermediate dielectric layer is located on the first source / drain doped layer and between the first intermediate dielectric layer and the stacked structure.
13. The semiconductor structure according to claim 12, characterized in that, The material of the first intermediate dielectric layer is one or more of silicon nitride, silicon oxide, silicon carbon oxide, silicon carbon oxynitride, and silicon nitrocarbon.
14. The semiconductor structure according to claim 12, characterized in that, The material of the second intermediate dielectric layer is one or more of silicon nitride, silicon oxide, silicon carbon oxide, silicon carbon oxynitride, and silicon nitrocarbon.
15. The semiconductor structure according to claim 11, characterized in that, The stacked structure further includes: The second dielectric layer is located between the first and second channel structures.
16. The semiconductor structure according to claim 15, characterized in that, The material of the second dielectric layer is one or more of silicon nitride, silicon oxide, silicon carbon oxide, silicon carbon oxynitride, and silicon nitride.