Solar cell and preparation method thereof, cell module and photovoltaic system

Abstract

The invention relates to the field of photovoltaic cells, and particularly discloses a solar cell and a preparation method thereof, a cell module and a photovoltaic system. The solar cell comprises a silicon substrate, a first tunneling layer, a first diffusion barrier layer, a first doping layer, a first passivation layer and a first electrode. The silicon substrate is provided with a first surface and a second surface which are oppositely arranged, and the first surface or the second surface is provided with at least one first internal expansion area along a second direction; at least one hole is formed in the first diffusion barrier layer, so that a doping source of the first doping layer is diffused into the silicon substrate through the hole to form the first internal expansion region; the first doping layer comprises first parts and second parts which are alternately distributed in the second direction, the doping concentration of the first parts is larger than that of the second parts, and the first parts and the first internal expansion areas are correspondingly arranged. By implementing the invention, the photoelectric conversion efficiency of the solar cell can be improved.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cells, and more particularly to a solar cell, its preparation method, cell module, and photovoltaic system. Background Technology In the traditional tunneling oxide passivated contact (TOPCon) structure of solar cells, the heat treatment after the tunneling oxide layer is prepared results in the formation of numerous pinholes on the tunneling oxide layer. Subsequently, during the fabrication of the doped polycrystalline silicon layer, the dopant source diffuses into the silicon substrate through these pinholes, forming an inner extension layer. While a certain amount of inner extension layer is beneficial for carrier transport, a large number of inner extension regions can easily lead to increased Auger recombination, reducing the open-circuit voltage and consequently affecting the photoelectric conversion efficiency of the solar cell. Summary of the Invention

[0002] The technical problem to be solved by the present invention is to provide a solar cell and a method for preparing the same, which can effectively improve photoelectric conversion efficiency.

[0003] Another technical problem that the present invention needs to solve is to provide a battery module and a photovoltaic system.

[0004] To address the above problems, the present invention discloses a solar cell comprising: A silicon substrate has a first surface and a second surface disposed opposite to each other, wherein the first surface or the second surface has at least one first inner expansion region along a second direction; the first direction intersects the thickness direction of the silicon substrate; A first tunneling layer is disposed on the first surface; A first diffusion barrier layer is disposed on the first tunneling layer; the first diffusion barrier layer has at least one hole so that the doping source of the first doped layer diffuses into the silicon substrate through the hole to form the first inner expansion region. A first doped layer is disposed above the first tunneling layer; the first doped layer includes a first part and a second part that are alternately distributed along a second direction, the first part and the second part extend along the first direction, the doping concentration of the first part is greater than the doping concentration of the second part, the first part is disposed corresponding to the first inner expansion region; the first direction and the second direction intersect. A first passivation layer is disposed on the first doped layer; and The first electrode is disposed on the first passivation layer and is in contact with the first doped layer.

[0005] As an improvement to the above technical solution, the thickness of the first tunneling layer is 2nm~10nm; and / or The first tunneling layer is a stack formed by one or more of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer. The thickness of the first diffusion barrier layer is 1 nm to 5 nm; and / or The first diffusion barrier layer is a stack formed by one or more of the following: silicon nitride layer, silicon carbide layer, silicon oxynitride layer, silicon oxycarbonate layer, silicon carbide nitride layer, and aluminum oxide layer.

[0006] As an improvement to the above technical solution, the first tunneling layer is a silicon oxide layer with a thickness of 3nm~10nm; and / or The thickness of the first diffusion barrier layer is 1 nm to 3 nm; and / or The first diffusion barrier layer is a silicon nitride layer or a silicon carbide layer.

[0007] As an improvement to the above technical solution, the depth of the first inner expansion region is ≥0.1μm; and / or The doping concentration of the first inner expansion region is ≥1×10 18 cm -3 ; and / or The doping concentration of the first part is ≥1×10 20 cm -3 ; and / or The doping concentration of the second part is ≤5×10 20 cm -3 .

[0008] As an improvement to the above technical solution, the depth of the first inner expansion region is 0.1 μm to 0.5 μm; and / or The doping concentration of the first inner expansion region is 1×10 18 cm -3 ~5×10 19 cm -3 ; and / or The doping concentration of the first part is 3×10 20 cm -3 ~5×10 21 cm -3 ; and / or The doping concentration of the second part is 5×10 19 cm -3 ~5×10 20 cm -3 .

[0009] As an improvement to the above technical solution, the first doped layer includes a plurality of first portions and second portions that are alternately distributed along the second direction; the widths of the plurality of first portions in the second direction may be the same or different, and the widths of the plurality of second portions in the second direction may be the same or different. The first doped layer beneath the first electrode includes the first portion and / or the second portion.

[0010] As an improvement to the above technical solution, the first doped layer includes a plurality of first portions and second portions that are alternately distributed along a first direction; the plurality of second portions have different widths in the second direction, and the plurality of first portions have the same width in the second direction. The first doped layer below the first electrode is the second part, and the width of the first electrode in the second direction is smaller than the width of the second part below it in the second direction.

[0011] As an improvement to the above technical solution, the width of the first part in the second direction is 2μm~100μm, and the width of the second part in the second direction is 30μm~100μm.

[0012] As an improvement to the above technical solution, the pinhole distribution density of the first tunneling layer below the first part is greater than the pinhole distribution density of the first tunneling layer below the second part.

[0013] As an improvement to the above technical solution, the first inner expansion region, the first tunneling layer, the first diffusion barrier layer, the first doped layer, the first passivation layer, and the first electrode are all disposed on the first surface. The solar cell further includes a doped layer, a second passivation layer, an antireflection layer, and a second electrode sequentially disposed on the second surface, wherein the second electrode is in contact with the doped layer.

[0014] As an improvement to the above technical solution, the first tunneling layer, the first diffusion barrier layer, the first doped layer, the first passivation layer, and the first electrode are all disposed on the first surface; the first inner expansion region is disposed on the first surface and the second surface. The solar cell further includes a second tunneling layer, a second diffusion barrier layer, a second doped layer, a second passivation layer, and a second electrode sequentially disposed on the second surface; the second diffusion barrier layer has at least one via so that the doping source of the second doped layer diffuses into the silicon substrate through the via to form the first inner expansion region; the second doped layer includes at least one third part and at least one fourth part in a first direction, the doping concentration of the third part is greater than the doping concentration of the fourth part, and the third part is disposed corresponding to the first inner expansion region; the second electrode is in contact with the second doped layer.

[0015] As an improvement to the above technical solution, the first surface of the silicon substrate includes a first region and a second region alternately arranged along a second direction; The first inner expansion region, the first tunneling layer, the first diffusion barrier layer, the first doped layer, the first passivation layer, and the first electrode are all disposed within the first region; A passivation layer and a second electrode are sequentially stacked in the second region, and the second electrode is in contact with the silicon substrate.

[0016] As an improvement to the above technical solution, the first surface of the silicon substrate includes a first region and a second region alternately arranged along a second direction; The first inner expansion region, the first tunneling layer, the first diffusion barrier layer, the first doped layer, the first passivation layer, and the first electrode are all disposed within the first region; The second region is sequentially stacked with a second tunneling layer, a second diffusion barrier layer, a second doped layer, a second passivation layer, and a second electrode; the second region has at least one second inner expansion region along a first direction; the second diffusion barrier layer has at least one via so that the doping source of the second doped layer diffuses into the silicon substrate through the via to form the second inner expansion region; the second doped layer includes at least one third part and at least one fourth part in the first direction, the doping concentration of the third part is greater than the doping concentration of the fourth part, and the third part is correspondingly disposed with the first inner expansion region; the second electrode is in contact with the second doped layer.

[0017] Accordingly, the present invention also discloses a method for preparing a solar cell, which includes: Provide silicon substrate; A first initial tunneling layer, a first initial diffusion barrier layer, and a first doped layer are sequentially formed on the silicon substrate to obtain a first intermediate. A doped source layer is formed on the first intermediate; A laser is used to advance the dopant source of the doped source layer into the first doped layer, and at least one hole is formed on the first initial diffusion barrier layer. The dopant source of the first doped layer is then advanced into the silicon substrate through the hole to form at least one first inner expansion region. The first doped layer forms a first part and a second part after laser processing. The first initial diffusion barrier layer and the first initial tunneling layer form a first diffusion barrier layer and a first tunneling layer, respectively, after laser processing. The remaining doped source layer is removed to obtain the second intermediate. A first passivation layer is formed on the second intermediate; A first electrode is formed on the first passivation layer, and the first electrode is in contact with the first doped layer.

[0018] As an improvement to the above technical solution, the doped source layer is a phosphorus-silicon glass layer, a borosilicate glass layer, a boron-doped silicon slurry layer, a phosphorus-doped silicon slurry layer, a liquid phosphorus source layer, or a liquid boron source layer.

[0019] Accordingly, the present invention also discloses a battery assembly comprising the aforementioned solar cell.

[0020] Accordingly, the present invention also discloses a photovoltaic system comprising the aforementioned battery assembly.

[0021] Implementing this invention has the following beneficial effects: A solar cell according to an embodiment of the present invention includes a silicon substrate, a first tunneling layer, a first diffusion barrier layer, a first doped layer, a first passivation layer, and a first electrode. The silicon substrate has a first surface and a second surface disposed opposite to each other. At least one first inner expansion region is formed on the first surface or the second surface along a second direction. The first diffusion barrier layer has at least one hole, allowing the dopant source of the first doped layer to diffuse into the silicon substrate through the hole, forming the first inner expansion region. The first doped layer includes a first part and a second part alternately distributed along the second direction, with the doping concentration of the first part being greater than that of the second part. The first part corresponds to the first inner expansion region. Based on this technical solution, a non-uniform first inner expansion region can be formed within the silicon substrate by controlling the distribution position of the holes. In other areas without holes, the first diffusion barrier layer maintains the integrity of the silicon substrate-first tunneling layer interface, improves the surface passivation effect, increases the open-circuit voltage, and thus improves the conversion efficiency of the solar cell. Furthermore, the carrier selectivity can be improved and the carrier transport resistance reduced by the first part, which has a higher doping concentration and corresponds to the first inner expansion region, thereby increasing the fill factor and photoelectric conversion efficiency. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of the solar cell in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure of the first doped layer and the first electrode in Embodiment 1 of the present invention; Figure 3 yes Figure 1 A magnified view of a section at point A in the middle; Figure 4 This is a flowchart of the method for preparing a solar cell in Embodiment 2 of the present invention; Figure 5 This is a schematic diagram of the structure of the solar cell in Embodiment 4 of the present invention; Figure 6 This is a schematic diagram of the structure of the first doped layer and the first electrode in Embodiment 4 of the present invention; Figure 7 This is a schematic diagram of the structure of the second doped layer and the second electrode in Embodiment 4 of the present invention; Figure 8 This is a schematic diagram of the structure of the solar cell in Embodiment 5 of the present invention; Figure 9 This is a schematic diagram of the structure of the first doped layer, the first electrode, and the second electrode in Embodiment 5 of the present invention; Figure 10This is a schematic diagram of the structure of the solar cell in Embodiment Six of the present invention; Figure 11 This is a schematic diagram of the structure of the first doped layer, the second doped layer, the first electrode, and the second electrode in Embodiment Six of the present invention; Figure 12 This is a schematic diagram of the system composition of the battery assembly in Embodiment 7 of the present invention; Figure 13 This is a schematic diagram of the composition of the photovoltaic system in Embodiment 8 of the present invention. Detailed Implementation

[0023] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.

[0024] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.

[0026] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0028] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0029] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0030] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0031] Example 1 Please see Figures 1-3 This embodiment discloses a solar cell, which includes a silicon substrate 100, a first tunneling layer 210, a first diffusion barrier layer 310, a first doped layer 400, a first passivation layer 510, and a first electrode 610.

[0032] Among them, such as Figure 1 As shown, the silicon substrate 100 can be P-type single-crystal silicon or N-type single-crystal silicon, but is not limited to these. When the silicon substrate 100 is N-type single-crystal silicon, the doping element can be one or more of phosphorus (P), bismuth (Bi), antimony (Sb), and arsenic (As), but is not limited to these. When the silicon substrate 100 is P-type single-crystal silicon, the doping element can be one or more of boron (B), aluminum (Al), gallium (Ga), and indium (In), but is not limited to these.

[0033] In terms of thickness, the silicon substrate 100 includes a first surface 110 and a second surface 120 disposed opposite each other, wherein either surface can be the surface receiving light, and the other surface is the backlight surface. However, it should be noted that in some embodiments, the backlight surface can also absorb light incident through the backlight surface, thereby generating photocurrent. Specifically, the first surface 110 and / or the second surface 120 may also be provided with a textured surface to reduce the reflection of incident light and improve light utilization efficiency.

[0034] Specifically, in some embodiments, a plurality of first inner expansion regions 111 are provided on the first surface 110 and / or the second surface 120 of the silicon substrate 100. These first inner expansion regions 111 are formed by the diffusion of external doping elements into the silicon substrate 100. The doping elements can be the same as or different from the doping elements of the silicon substrate 100 itself, thus forming either heavily doped regions or PN junctions. More specifically, the first inner expansion regions 111 are spaced apart along a second direction and extend along a first direction.

[0035] The first tunneling layer 210 is disposed on the first surface 110. The first tunneling layer 210 is a stack formed by one or more of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, in some embodiments, the first tunneling layer 210 is a silicon oxide layer.

[0036] The first diffusion barrier layer 310 is disposed on the first tunneling layer 210, and more specifically, the first diffusion barrier layer 310 is disposed on the side of the first tunneling layer 210 facing away from the first surface 110. The first diffusion barrier layer 310 can prevent external elements from diffusing into the first tunneling layer 210 and the silicon substrate 100. At least one hole 311 penetrating the first diffusion barrier layer 310 can be provided on the first diffusion barrier layer 310, so that the doping source of the first doped layer 400 diffuses into the silicon substrate 100 through the hole 311, forming a first inner expansion region 111. Based on this, by controlling the distribution position of the hole 311, a non-uniform first inner expansion region 111 can be formed in the silicon substrate 100. In other regions without holes 311, the first diffusion barrier layer 310 maintains the integrity of the interface between the silicon substrate 100 and the first tunneling layer 210, improves the surface passivation effect, increases the open-circuit voltage, and thus improves the conversion efficiency of the solar cell.

[0037] The first diffusion barrier layer 310 is a stack of one or more of the following materials: silicon nitride, silicon carbide, silicon oxynitride, silicon carbide, silicon oxycarbonate, and aluminum oxide. These layers are chemically inert and can effectively block the diffusion of dopants. Furthermore, the first diffusion barrier layer 310 can be combined with the first tunneling layer 210 to effectively enhance chemical passivation, reduce carrier recombination, and increase short-circuit current and open-circuit voltage, thereby improving output characteristics and conversion efficiency. Preferably, in some embodiments, the first diffusion barrier layer 310 is a silicon nitride layer or a silicon carbide layer.

[0038] The first doped layer 400 is disposed on the first diffusion barrier layer 310, and more specifically, on the side of the first diffusion barrier layer 310 facing away from the first tunneling layer 210. Specifically, depending on the type of solar cell, the first doped layer 400 may completely or partially cover the first surface 110. For example, when the solar cell is a TOPCon cell, the first doped layer 400 may completely cover the first surface 110; when the solar cell is a TBC cell, the first doped layer 400 may partially cover the first surface 110. Multiple first doped layers 400 are spaced apart along a second direction and extend along a first direction, but are not limited thereto.

[0039] Specifically, the first doped layer 400 can be a doped polycrystalline silicon layer, a doped amorphous silicon layer, or a doped microcrystalline silicon layer, but is not limited to these. More specifically, the first doped layer 400 can be an N-type polycrystalline silicon layer, a P-type polycrystalline silicon layer, a P-type amorphous silicon layer, an N-type amorphous silicon layer, a P-type microcrystalline silicon layer, or an N-type microcrystalline silicon layer, but is not limited to these. Preferably, the first doped layer 400 is an N-type polycrystalline silicon layer or a P-type polycrystalline silicon layer, which has good conductivity and can improve the selective transport capability of charge carriers and improve the photoelectric conversion efficiency. It should be noted that in conventional P-type polycrystalline silicon layers, because the dopant element (B) diffuses more easily, it often forms a deep internal expansion region inside the silicon substrate 100, leading to increased Auger recombination and a decrease in open-circuit voltage. Moreover, B also dops into the tunneling oxide layer (SiO2), forming BO bonds, which leads to a decrease in the crystal quality of the tunneling oxide layer and a weakening of the passivation effect. Furthermore, in the P-type polycrystalline silicon-based tunneling oxide passivation contact structure (TOPCon), the valence band shift between the tunneling oxide layer (SiO2) and the silicon substrate 100 limits the thickness of the tunneling oxide layer itself to prevent hole carriers from being unable to tunnel through. A thinner tunneling oxide layer also results in relatively poor passivation. Therefore, most existing tunneling oxide passivation contact structures are based on an N-type monocrystalline silicon substrate 100 and an N-type polycrystalline silicon layer. This application, however, effectively optimizes the passivation effect through a specific structural design, making its technical solution applicable to both N-type monocrystalline silicon-N-type polycrystalline silicon layer and P-type monocrystalline silicon-P-type polycrystalline silicon layer tunneling oxide passivation contact structures.

[0040] Specifically, in some embodiments, the first doped layer 400 includes a first portion 410 and a second portion 420 alternately distributed along a second direction. The first portion 410 and the second portion 420 extend along a first direction. The doping concentration of the first portion 410 is greater than that of the second portion 420. The first portion 410 is correspondingly disposed with respect to the first inner expansion region 111. Based on this, the selectivity of charge carriers can be improved and the transport resistance of charge carriers can be reduced by the first portion 410 with a larger doping concentration that is corresponding to the first inner expansion region 111. The fill factor can be improved and the photoelectric conversion efficiency can be improved.

[0041] Specifically, the first passivation layer 510 is disposed on the first doped layer 400, specifically on the side of the first doped layer 400 facing away from the first diffusion barrier layer 310. The first passivation layer 510 can effectively reduce the surface recombination rate and improve carrier lifetime. Specifically, the first passivation layer 510 can be a stacked structure formed by one or more of silicon nitride, silicon oxynitride, aluminum oxide, and silicon oxide layers. Preferably, in some embodiments, the first passivation layer 510 includes an aluminum oxide layer and a silicon nitride layer sequentially stacked on the first doped layer 400. This first passivation layer 510 not only has a good passivation effect but also serves as an anti-reflection layer, enhancing light capture efficiency and thus improving photoelectric conversion efficiency.

[0042] Specifically, the first electrode 610 is disposed on the first passivation layer 510 and contacts the first doped layer 400 through a hole disposed on the first passivation layer 510. More specifically, the first electrode 610 is disposed corresponding to the first part 410 to better transport charge carriers.

[0043] Specifically, the thickness of the first tunneling layer 210 is 2nm to 10nm, exemplarily 2.5nm, 3.5nm, 4nm, 5.5nm, 6nm, 7nm, 8nm, or 9.5nm, but not limited thereto. Preferably, it is 3nm to 10nm, more preferably 3nm to 7nm. It should be noted that in traditional tunneling oxide passivation contact structures, since carriers need to tunnel, the thickness of the tunneling layer is often relatively thin, around 1nm to 2.5nm. However, such tunneling layers often have poor crystal quality and weak passivation effect. In this application, a hole 311 is used to form the first internally doped region, through which carrier transport is realized. Therefore, the thickness of the tunneling layer can be increased accordingly, the passivation performance can be optimized, and the photoelectric conversion efficiency can be improved.

[0044] Specifically, the thickness of the first diffusion barrier layer 310 is 1 nm to 5 nm. If its thickness is too small, it will be difficult to effectively block the diffusion of the dopant source into the first tunneling layer 210 and the silicon substrate 100; if its thickness is too large, it will increase the contact resistance and reduce the conversion efficiency. For example, the thickness of the first diffusion barrier layer 310 is 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, or 4.5 nm, but is not limited thereto. Preferably, the thickness of the first diffusion barrier layer 310 is 1 nm to 3 nm.

[0045] Specifically, the diffusion depth of the first inner expansion region 111 is ≥0.1 μm. Based on this, carriers can be effectively collected, surface recombination can be reduced, and the open-circuit voltage can be improved. Preferably, the diffusion depth of the first inner expansion region 111 is 0.1 μm to 0.5 μm, exemplarily 0.15 μm, 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, or 0.45 μm, but is not limited thereto. More preferably, it is 0.2 μm to 0.4 μm.

[0046] Specifically, the doping concentration of the first inner expansion region 111 is ≥1×10⁻⁶. 18 cm -3 Based on this, conductivity can be effectively enhanced and contact resistance reduced, thereby improving carrier extraction efficiency. Preferably, the doping concentration of the first inner expansion region 111 is 1×10⁻⁶. 18 cm -3 ~5×10 19 cm -3 For example, 1.5 × 10 18 cm-3 3×10 18 cm -3 4.5×10 18 cm -3 6×10 18 cm -3 7.5×10 18 cm -3 9×10 18 cm -3 1.5×10 19 cm -3 3×10 19 cm -3 Or 4.5×10 19 cm -3 However, it is not limited to this. More preferably, the doping concentration of the first inner expansion region 111 is 5 × 10⁻⁶. 18 cm -3 ~3×10 19 cm -3 .

[0047] Specifically, the doping concentration of the first part 410 is ≥1×10 20 cm -3 This effectively improves carrier migration efficiency. Preferably, the doping concentration of the first part 410 is 3 × 10⁻⁶. 20 cm -3 ~5×10 21 cm -3 For example, 5×10 20 cm -3 7×10 20 cm -3 9×10 20 cm -3 1×10 21 cm -3 3×10 21 cm -3 Or 4.5×10 21 cm -3 However, it is not limited to this. More preferably, the doping concentration of the first part 410 is 8 × 10⁻⁶. 20 cm -3 ~3×10 21 cm -3 .

[0048] Specifically, the doping concentration of the second part 420 is ≤5×10 20 cm -3 This ensures that the first doped layer 400 has a good passivation effect and improves the open-circuit voltage. Preferably, the doping concentration of the second part 420 is 5 × 10⁻⁶. 19 cm -3 ~5×1020 cm -3 For example, 6.5 × 10 19 cm -3 8×10 19 cm -3 9.5×10 19 cm -3 1.5×10 20 cm -3 3×10 20 cm -3 Or 4.5×10 20 cm -3 However, it is not limited to this. More preferably, the doping concentration of the second part 420 is 5 × 10⁻⁶. 19 cm -3 ~3×10 20 cm -3 .

[0049] Specifically, the widths of the plurality of first portions 410 in the first doped layer 400 in the second direction may be the same or different. Specifically, they may be 2 μm to 100 μm, and exemplary examples are 3 μm, 15 μm, 27 μm, 35 μm, 45 μm, 55 μm or 65 μm, but are not limited thereto.

[0050] Accordingly, the widths of the plurality of second portions 420 in the first doped layer 400 in the second direction may be the same or different, specifically 30 μm to 100 μm, exemplary of 35 μm, 45 μm, 55 μm, 65 μm, 75 μm or 85 μm, but not limited thereto.

[0051] Specifically, based on the above embodiments, the first doped layer 400 below the first electrode 610 is either a first part 410 or a second part 420, or both a first part 410 and a second part 420.

[0052] Preferably, in some embodiments, the width of the plurality of first parts 410 in the second direction is the same (i.e.) Figure 3 In the middle d11=d12), the widths of multiple second parts 420 in the second direction are different (i.e. Figure 3 In the above embodiment (where d21≠d22), the first doped layer 400 located below the first electrode 610 is the second part 420, and the width of the first electrode 610 in the second direction is smaller than the width of the second part 420. Based on this embodiment, the carrier transport path can be effectively controlled, the transport resistance can be reduced, and recombination in the electrode region can be reduced, thereby improving the photoelectric conversion efficiency.

[0053] Preferably, in some embodiments, a plurality of pinholes are formed in the first tunneling layer 210, and the distribution density of pinholes located below the first part 410 is greater than the distribution density of pinholes located below the second part 420. Based on this embodiment, damage to the first doped layer 400 can be further reduced, passivation effect can be improved, and photoelectric conversion efficiency can be improved.

[0054] Example 2 Please see Figure 4 This embodiment provides a method for preparing a solar cell, which includes the following steps: S110: Provides a silicon substrate; S120: A first initial tunneling layer, a first initial diffusion barrier layer and a first initial doping layer are sequentially formed on a silicon substrate to obtain a first intermediate. S130: A doped source layer is formed on the first intermediate; S140: A laser is used to advance the dopant source of the doped source layer to the first initial doped layer, and at least one hole is formed on the first initial barrier diffusion layer. The dopant source of the first doped layer is then advanced into the silicon substrate through the hole to form at least one first inner expansion region. S150: Remove the remaining doped source layer to obtain the second intermediate; S160: A first passivation layer is formed on the second intermediate; S170: A first electrode is formed on the first passivation layer; In step S140, after laser processing, the first doped layer 400 forms a first part 410 and a second part 420, and the first initial diffusion barrier layer and the first initial tunneling layer form a first diffusion barrier layer 310 and a first tunneling layer 210, respectively. In step S170, the first electrode 610 comes into contact with the first doped layer 400.

[0055] Based on the above preparation method, firstly, a hole 311 is formed on the first diffusion barrier layer 310 through laser processing, and then the dopant source of the first doped layer 400 diffuses into the silicon substrate 100 through the hole 311 to form the first inner expansion region 111; while maintaining the integrity of the interface between the first tunneling layer 210 and the silicon substrate 100 in the location where no laser processing is performed, the surface passivation effect is improved, the open-circuit voltage is increased, and the photoelectric conversion efficiency is improved. Secondly, through the process steps of forming the doped source layer and laser processing, a first part 410 with a high doping concentration and a second part 420 with a low doping concentration are formed in the first doped layer 400. The first part 410 improves the selectivity of charge carriers, reduces the transport resistance of charge carriers, improves the fill factor, and improves the photoelectric conversion efficiency. Thirdly, the first tunneling layer 210 and the first diffusion barrier layer 310 together serve as a passivation structure, further enhancing the passivation effect. Fourthly, the process of forming the doped source layer and laser processing is simple and easy to operate.

[0056] Specifically, in step S110, the silicon substrate 100 may be P-type monocrystalline silicon or N-type monocrystalline silicon, but is not limited thereto. In terms of thickness, the silicon substrate 100 includes a first surface 110 and a second surface 120 disposed opposite to each other. A textured surface may also be provided on the first surface 110 and / or the second surface 120 to reduce the reflection of incident light and improve light utilization efficiency.

[0057] Specifically, in step S120, the first initial tunneling layer can be formed by thermal oxidation, LPCVD, or PECVD, but is not limited to these methods. Preferably, in some embodiments, the first initial tunneling layer is formed by thermal oxidation.

[0058] Specifically, the first initial tunneling layer is a stack formed of one or more of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, in some embodiments, the first initial tunneling layer is a silicon oxide layer.

[0059] Specifically, in step S120, the first initial diffusion barrier layer can be formed by PECVD or LPCVD, but is not limited thereto. Preferably, in some embodiments, the first initial diffusion barrier layer is formed by LPCVD.

[0060] Specifically, the first initial diffusion barrier layer is a stack formed of one or more of the following: silicon nitride layer, silicon carbide layer, silicon oxynitride layer, silicon oxycarbide layer, silicon nitride layer, and aluminum oxide layer, but is not limited thereto. Preferably, in some embodiments, the first initial diffusion barrier layer is a silicon nitride layer or a silicon carbide layer.

[0061] Specifically, in some implementations, the first doped layer 400 can be grown by LPCVD or PECVD. More specifically, an intrinsic amorphous silicon layer can be grown first by PECVD, then annealed and crystallized and diffused to obtain the first doped layer 400; or a doped amorphous silicon layer can be grown first by PECVD, then annealed and crystallized to obtain the first doped layer 400; or a polycrystalline silicon layer can be grown first by LPCVD, then diffused to obtain the first doped layer 400; or a doped polycrystalline silicon layer can be grown in situ by PECVD to obtain the first doped layer 400, but these are not limited to these methods.

[0062] Specifically, the first doped layer 400 may be a doped polycrystalline silicon layer, a doped amorphous silicon layer, or a doped microcrystalline silicon layer, but is not limited thereto. More preferably, the first doped layer 400 is a doped polycrystalline silicon layer.

[0063] Specifically, in step S130, the doped source layer is a phosphorus silicate glass layer, a borosilicate glass layer, a boron-doped silicon slurry layer, a phosphorus-doped silicon slurry layer, a liquid phosphorus source layer, or a liquid boron source layer, but is not limited to these. The doped source layer can be formed during diffusion doping or by screen printing, but is not limited to these methods.

[0064] Specifically, in step S140, laser processing is performed according to a preset pattern. During laser processing, the dopant source in the doped source layer is advanced into the first doped layer 400, thereby forming a first part 410 with a high doping concentration in the first doped layer 400, and forming a hole 311 on the first diffusion barrier layer 310. The dopant source in the first doped layer 400 then enters the silicon substrate 100 through the hole 311, forming a first inner expansion region. It should be noted that in this step, the first tunneling layer 210 may or may not be penetrated by the laser. When not penetrated, the pinholes on the first tunneling layer 210 can also transmit the dopant source to the silicon substrate 100.

[0065] Specifically, in step S150, the remaining doped source layer is removed by dry etching or wet etching processes, but is not limited thereto. Preferably, in some embodiments, the remaining doped source layer can be removed by alkaline washing.

[0066] Specifically, in step S160, the first passivation layer 510 can be formed by PECVD, LPCVD, or MOCVD, but is not limited to these methods. Preferably, in some embodiments, the first passivation layer 510 is formed by PECVD.

[0067] The first passivation layer 510 may be a stacked structure formed by one or more of the following: silicon nitride layer, silicon oxynitride layer, aluminum oxide layer, and silicon oxide layer, but is not limited thereto. Preferably, in some embodiments, the first passivation layer 510 includes an aluminum oxide layer and a silicon nitride layer sequentially stacked on the first doped layer 400.

[0068] Specifically, in step S170, a first initial electrode is first formed by screen printing or electroplating, and then sintered to obtain the first electrode 610, but not limited to this.

[0069] Example 3 This embodiment provides a solar cell, the specific structure of which is as follows: Figures 1-3 As shown. The solar cell includes a silicon substrate 100, a first inner expansion region 111, a first tunneling layer 210, a first diffusion barrier layer 310, a first doped layer 400, a first passivation layer 510 and a first electrode 610 sequentially disposed on a first surface 110 of the silicon substrate 100; and a second doped layer 700, an antireflection layer 800 and a second electrode 620 sequentially disposed on a second surface 120.

[0070] The silicon substrate 100 can be P-type or N-type single-crystal silicon, and includes a first surface 110 and a second surface 120 in the thickness direction. The first surface 110 of the silicon substrate 100 is a backlight surface, and it has a first inner expansion region 111, which is formed by the diffusion of an external dopant element into the silicon substrate 100. The dopant element can be the same as or different from the dopant element of the silicon substrate 100 itself. More specifically, the first inner expansion region 111 is spaced apart along a second direction and extends along a first direction.

[0071] The first tunneling layer 210 is disposed on the first surface 110. The first tunneling layer 210 is a stack formed by one or more of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, in some embodiments, the first tunneling layer 210 is a silicon oxide layer.

[0072] The first diffusion barrier layer 310 is disposed on the first tunneling layer 210. More specifically, the first diffusion barrier layer 310 is disposed on the side of the first tunneling layer 210 facing away from the first surface 110. A plurality of holes 311 penetrating the first diffusion barrier layer 310 are provided therein, so that the doping source of the first doped layer 400 diffuses into the silicon substrate 100 through the holes 311, forming the first inner expansion region 111. The first diffusion barrier layer 310 is a stack formed of one or more of the following: silicon nitride layer, silicon carbide layer, silicon oxynitride layer, silicon oxycarbide layer, silicon carbide nitride layer, and aluminum oxide layer. Preferably, in some embodiments, the first diffusion barrier layer 310 is a silicon nitride layer or a silicon carbide layer.

[0073] The first doped layer 400 is disposed on the first diffusion barrier layer 310, and more specifically, on the side of the first diffusion barrier layer 310 facing away from the first tunneling layer 210. Specifically, in this embodiment, the first doped layer 400 completely covers the first surface 110, that is, its projection on the first surface 110 completely covers the first surface 110. It should be noted that GAP regions not covered by the first doped layer 400 may be formed at the periphery of the silicon substrate 100, but the first surface 110 is mostly covered by the first doped layer 400.

[0074] Specifically, the first doped layer 400 may be a doped polycrystalline silicon layer, a doped amorphous silicon layer, or a doped microcrystalline silicon layer, but is not limited thereto. More specifically, the first doped layer 400 may be an N-type polycrystalline silicon layer, a P-type polycrystalline silicon layer, a P-type amorphous silicon layer, an N-type amorphous silicon layer, a P-type microcrystalline silicon layer, or an N-type microcrystalline silicon layer, but is not limited thereto. Preferably, the first doped layer 400 is an N-type polycrystalline silicon layer or a P-type polycrystalline silicon layer.

[0075] Specifically, in some embodiments, the first doped layer 400 includes a first portion 410 and a second portion 420 alternately distributed along a second direction. The first portion 410 and the second portion 420 extend along a first direction. The doping concentration of the first portion 410 is greater than that of the second portion 420. The first portion 410 is correspondingly disposed with respect to the first inner expansion region 111. Based on this, the selectivity of charge carriers can be improved and the transport resistance of charge carriers can be reduced by the first portion 410 with a larger doping concentration that is corresponding to the first inner expansion region 111. The fill factor can be improved and the photoelectric conversion efficiency can be improved.

[0076] Specifically, the first passivation layer 510 is disposed on the first doped layer 400, specifically on the side of the first doped layer 400 facing away from the first diffusion barrier layer 310. The first passivation layer 510 may be a stacked structure formed by one or more of silicon nitride, silicon oxynitride, aluminum oxide, and silicon oxide layers. Preferably, in some embodiments, the first passivation layer 510 includes an aluminum oxide layer and a silicon nitride layer sequentially stacked on the first doped layer 400.

[0077] Specifically, the first electrode 610 is disposed on the first passivation layer 510 and contacts the first doped layer 400 through a hole disposed on the first passivation layer 510.

[0078] Specifically, the second surface 120 is the light-receiving surface of the solar cell, and a second doped layer 700 is provided on the second surface 120. The second doped layer 700 is an emitter formed by inward doping into the silicon substrate 100, and its polarity is opposite to that of the silicon substrate 100. A textured structure may also be provided on the second surface 120 to reduce the reflection of sunlight.

[0079] The antireflection layer 800 is disposed on the second doped layer 700, and may be a stacked structure formed by one or more of the following: silicon oxide layer, silicon nitride layer, silicon oxynitride layer, titanium oxide layer, or zirconium oxide layer, but is not limited thereto. Preferably, it is a silicon nitride layer.

[0080] The second electrode 620 is disposed on the antireflection layer 800 and passes through the antireflection layer 800 to contact the second doped layer 700.

[0081] Preferably, in some embodiments, a second passivation layer 520 may be provided between the second doped layer 700 and the antireflection layer 800, which may be a stacked structure formed by one or more of silicon nitride layers, aluminum oxide layers, and silicon oxide layers. Preferably, it is a silicon oxide layer.

[0082] Specifically, the thickness of the first tunneling layer 210 is 2nm to 10nm. Preferably, it is 3nm to 10nm, and more preferably, it is 3nm to 7nm. Based on this, passivation performance and conversion efficiency can be improved.

[0083] Specifically, the thickness of the first diffusion barrier layer 310 is 1nm to 5nm, preferably 1nm to 3nm.

[0084] Specifically, the diffusion depth of the first inner expansion region 111 is ≥0.1μm, preferably 0.1μm~0.5μm, and more preferably 0.2μm~0.4μm.

[0085] Specifically, the doping concentration of the first part 410 is ≥1×10 20 cm -3 Preferably, it is 3×10 20 cm -3 ~5×10 21 cm -3 More preferably 8×10 20 cm -3 ~3×10 21 cm -3 .

[0086] Specifically, the doping concentration of the second part 420 is ≤5×10 20 cm -3 Preferably, it is 5×10 19 cm -3 ~5×10 20 cm -3 More preferably 5×10 19 cm -3 ~3×10 20 cm -3 .

[0087] Specifically, the widths of the plurality of first portions 410 in the first doped layer 400 in the second direction may be the same or different. Specifically, they may be 2 μm to 100 μm. Correspondingly, the widths of the plurality of second portions 420 in the first doped layer 400 in the second direction may be the same or different, specifically 30 μm to 100 μm.

[0088] Specifically, based on the above embodiments, the first doped layer 400 below the first electrode 610 is either a first part 410 or a second part 420, or both a first part 410 and a second part 420.

[0089] Preferably, in some embodiments, the plurality of first portions 410 have the same width in the second direction, and the plurality of second portions 420 have different widths in the second direction. Based on the above embodiments, the first doped layer 400 located below the first electrode 610 is the second portion 420, and the width of the first electrode 610 in the second direction is smaller than the width of the second portion 420. Based on this embodiment, the carrier transport path can be effectively controlled, the transport resistance can be reduced, recombination in the electrode region can be reduced, and the photoelectric conversion efficiency can be improved.

[0090] Preferably, in some embodiments, a plurality of pinholes are formed in the first tunneling layer 210, and the distribution density of pinholes located below the first part 410 is greater than the distribution density of pinholes located below the second part 420. Based on this embodiment, damage to the first doped layer 400 can be further reduced, passivation effect can be improved, and photoelectric conversion efficiency can be improved.

[0091] The method for preparing the solar cell in this embodiment includes the following steps: S211: Provide a silicon substrate and clean it to form a textured surface on the second surface; S212: A second doped layer is formed on the second surface by a diffusion process, and the second doped layer is removed from the periphery of the silicon substrate 100 and the first surface; S213: Polish and clean the first surface of the diffused silicon substrate; S214: A first initial tunneling layer, a first initial diffusion barrier layer, and a first doped layer are formed on the first surface after polishing and cleaning to obtain a first intermediate; S215: A doped source layer is formed on one side of the first doped layer of the first intermediate; S216: A laser is used to advance the dopant source of the doped source layer to the first doped layer, and at least one hole is formed on the first initial barrier diffusion layer. The dopant source of the first doped layer is then advanced into the silicon substrate through the hole to form at least one first inner expansion region. S217: Remove the remaining doped source layer to obtain the second intermediate; S218: An anti-reflection layer is formed on one side of the second doped source layer of the second intermediate, and a first passivation layer is formed on one side of the first doped layer of the second intermediate. S219: A first electrode is formed on the first passivation layer, a second electrode is formed on the anti-reflection layer, and then sintered.

[0092] Example 4 This embodiment provides a solar cell, the specific structure of which is as follows: Figures 5-7 As shown, the solar cell includes a silicon substrate 100, a first tunneling layer 210, a first diffusion barrier layer 310, a first doped layer 400, a first passivation layer 510 and a first electrode 610 sequentially disposed on a first surface 110 of the silicon substrate 100; and a second tunneling layer 220, a second diffusion barrier layer 320, a second passivation layer 520 and a second electrode 620 sequentially disposed on a second surface 120 of the silicon substrate 100.

[0093] The silicon substrate 100 can be P-type or N-type single-crystal silicon, and includes a first surface 110 and a second surface 120 in the thickness direction. The first surface 110 of the silicon substrate 100 is a backlight surface, and it has a first inner expansion region 111, which is formed by the diffusion of an external dopant element into the silicon substrate 100. The dopant element can be the same as or different from the dopant element of the silicon substrate 100 itself. More specifically, the first inner expansion region 111 is spaced apart along a second direction and extends along a first direction.

[0094] The first tunneling layer 210 is disposed on the first surface 110. The first tunneling layer 210 is a stack formed by one or more of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, in some embodiments, the first tunneling layer 210 is a silicon oxide layer.

[0095] The first diffusion barrier layer 310 is disposed on the first tunneling layer 210. More specifically, the first diffusion barrier layer 310 is disposed on the side of the first tunneling layer 210 facing away from the first surface 110. A plurality of holes 311 penetrating the first diffusion barrier layer 310 are provided therein, so that the doping source of the first doped layer 400 diffuses into the silicon substrate 100 through the holes 311, forming the first inner expansion region 111. The first diffusion barrier layer 310 is a stack formed of one or more of the following: silicon nitride layer, silicon carbide layer, silicon oxynitride layer, silicon oxycarbide layer, silicon carbide nitride layer, and aluminum oxide layer. Preferably, in some embodiments, the first diffusion barrier layer 310 is a silicon nitride layer or a silicon carbide layer.

[0096] The first doped layer 400 is disposed on the first diffusion barrier layer 310, more specifically on the side of the first diffusion barrier layer 310 facing away from the first tunneling layer 210. Specifically, in this embodiment, the first doped layer 400 completely covers the first surface 110, meaning its projection onto the first surface 110 completely covers the first surface 110. It should be noted that GAP regions not covered by the first doped layer 400 can be formed around the periphery of the silicon substrate 100, but the first surface 110 is mostly covered by the first doped layer 400. It should also be noted that in the prior art, to avoid weakening the passivation effect of the P-type polysilicon layer, often only the P-type polysilicon layer in the passivation contact structure region of the tunneling oxide layer is retained, while other P-type polysilicon layers are removed. This not only complicates the process but also easily damages other structural layers. The technical solution of this application optimizes the passivation performance of the tunnel oxide passivation contact structure based on the P-type polycrystalline silicon layer through a specific structure. Therefore, it is not necessary to remove the P-type polycrystalline silicon layer in other areas, which simplifies the production process and optimizes the performance of the solar cell.

[0097] Specifically, the first doped layer 400 may be a doped polycrystalline silicon layer, a doped amorphous silicon layer, or a doped microcrystalline silicon layer, but is not limited thereto. More specifically, the first doped layer 400 may be an N-type polycrystalline silicon layer, a P-type polycrystalline silicon layer, a P-type amorphous silicon layer, an N-type amorphous silicon layer, a P-type microcrystalline silicon layer, or an N-type microcrystalline silicon layer, but is not limited thereto. Preferably, the first doped layer 400 is an N-type polycrystalline silicon layer or a P-type polycrystalline silicon layer.

[0098] Specifically, in some embodiments, the first doped layer 400 includes a first portion 410 and a second portion 420 alternately distributed along a second direction. The first portion 410 and the second portion 420 extend along a first direction. The doping concentration of the first portion 410 is greater than that of the second portion 420. The first portion 410 is correspondingly disposed with respect to the first inner expansion region 111. Based on this, the selectivity of charge carriers can be improved and the transport resistance of charge carriers can be reduced by the first portion 410 with a larger doping concentration that is corresponding to the first inner expansion region 111. The fill factor can be improved and the photoelectric conversion efficiency can be improved.

[0099] Specifically, the first passivation layer 510 is disposed on the first doped layer 400, specifically on the side of the first doped layer 400 facing away from the first diffusion barrier layer 310. The first passivation layer 510 may be a stacked structure formed by one or more of silicon nitride, silicon oxynitride, aluminum oxide, and silicon oxide layers. Preferably, in some embodiments, the first passivation layer 510 includes an aluminum oxide layer and a silicon nitride layer sequentially stacked on the first doped layer 400.

[0100] Preferably, in some embodiments, the first passivation layer 510 may not be provided, and only the TCO layer or other antireflection layer 800 may be provided, but this is not the only option.

[0101] Specifically, the first electrode 610 is disposed on the first passivation layer 510 and contacts the first doped layer 400 through a hole disposed on the first passivation layer 510.

[0102] Specifically, the second surface 120 is the light-receiving surface of the solar cell, and it has a second inner expansion region 121, which is formed by the diffusion of an external dopant element into the silicon substrate 100. The dopant element may be the same as or different from the dopant element of the silicon substrate 100 itself. More specifically, the second inner expansion regions 121 are spaced apart along a second direction and extend along a first direction.

[0103] The second tunneling layer 220 is disposed on the second surface 120. The second tunneling layer 220 may be a stack formed of one or more of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, in some embodiments, the second tunneling layer 220 is a silicon oxide layer.

[0104] The second diffusion barrier layer 320 is disposed on the second tunneling layer 220. More specifically, the second diffusion barrier layer 320 is disposed on the side of the second tunneling layer 220 facing away from the second surface 120. A plurality of through-holes 321 are provided on the second diffusion barrier layer 320 to allow the doping source of the second doped layer 700 to diffuse into the silicon substrate 100 through the through-holes 321, forming the second inner expansion region 121. The second diffusion barrier layer 320 is a stack formed of one or more of the following: silicon nitride layer, silicon carbide layer, silicon oxynitride layer, silicon oxycarbide layer, silicon carbide nitride layer, and aluminum oxide layer. Preferably, in some embodiments, the second diffusion barrier layer 320 is a silicon nitride layer or a silicon carbide layer.

[0105] The second doped layer 700 is disposed on the second diffusion barrier layer 320, and more specifically, on the side of the second diffusion barrier layer 320 facing away from the second tunneling layer 220. Specifically, in this embodiment, the second doped layer 700 completely covers the second surface 120, that is, its projection on the second surface 120 completely covers the second surface 120. It should be noted that gap areas not covered by the second doped layer 700 can be formed at the periphery of the silicon substrate 100, but the second surface 120 is mostly covered by the second doped layer 700.

[0106] Specifically, the second doped layer 700 may be a doped polycrystalline silicon layer, a doped amorphous silicon layer, or a doped microcrystalline silicon layer, but is not limited thereto. More specifically, the second doped layer 700 may be an N-type polycrystalline silicon layer, a P-type polycrystalline silicon layer, a P-type amorphous silicon layer, an N-type amorphous silicon layer, a P-type microcrystalline silicon layer, or an N-type microcrystalline silicon layer, but is not limited thereto. Preferably, the second doped layer 700 is an N-type polycrystalline silicon layer or a P-type polycrystalline silicon layer.

[0107] Specifically, in some embodiments, the second doped layer 700 includes a third portion 710 and a fourth portion 720 alternately distributed along a second direction. The third portion 710 and the fourth portion 720 extend along a first direction. The doping concentration of the third portion 710 is greater than that of the fourth portion 720. The third portion 710 is correspondingly disposed with respect to the second inner expansion region 121. Based on this, the selectivity of charge carriers can be improved and the transport resistance of charge carriers can be reduced by the third portion 710, which has a larger doping concentration and is correspondingly disposed with respect to the second inner expansion region 121. The fill factor can be improved and the photoelectric conversion efficiency can be improved.

[0108] Specifically, the second passivation layer 520 is disposed on the second doped layer 700, specifically on the side of the second doped layer 700 opposite to the second diffusion barrier layer 320. The second passivation layer 520 may be a stacked structure formed by one or more of silicon nitride, silicon oxynitride, aluminum oxide, and silicon oxide layers. Preferably, in some embodiments, the second passivation layer 520 includes a silicon oxide layer and a silicon nitride layer sequentially stacked on the second doped layer 700.

[0109] Preferably, in some embodiments, the second passivation layer 520 may not be provided, and only the TCO layer or other antireflection layer 800 may be provided, but this is not the only option.

[0110] Specifically, the second electrode 620 is disposed on the second passivation layer 520 and contacts the second doped layer 700 through a hole disposed on the second passivation layer 520.

[0111] Specifically, the thickness of the first tunneling layer 210 and the second tunneling layer 220 is 2nm to 10nm. Preferably, it is 3nm to 10nm, and more preferably, it is 3nm to 7nm. Based on this, passivation performance and conversion efficiency can be improved. It should be noted that the thickness of the first tunneling layer 210 and the second tunneling layer 220 can be the same or different.

[0112] Specifically, the thickness of the first diffusion barrier layer 310 and the second diffusion barrier layer 320 is 1 nm to 5 nm, preferably 1 nm to 3 nm. It should be noted that the thickness of the first diffusion barrier layer 310 and the second diffusion barrier layer 320 may be the same or different.

[0113] Specifically, the diffusion depth of the first inner expansion region 111 and the second inner expansion region 121 is ≥0.1μm, preferably 0.1μm~0.5μm, and more preferably 0.2μm~0.4μm. It should be noted that the diffusion depth of the first inner expansion region 111 and the second inner expansion region 121 may be the same or different.

[0114] Specifically, the doping concentration of the first inner expansion region 111 and the second inner expansion region 121 is ≥1×10⁻⁶. 18 cm -3 Preferably, it is 1×10 18 cm -3 ~5×10 19 cm -3 More preferably 5×10 18 cm -3 ~3×10 19 cm -3 It should be noted that the doping concentrations of the first inner expansion region 111 and the second inner expansion region 121 can be the same or different.

[0115] Specifically, the doping concentration of Part 1 (410) and Part 3 (710) is ≥1×10⁻⁶. 20 cm -3 Preferably, it is 3×10 20 cm -3 ~5×10 21 cm -3 More preferably 8×10 20 cm -3~3×10 21 cm -3 It should be noted that the doping concentrations of the first part 410 and the third part 710 can be the same or different.

[0116] Specifically, the doping concentration of Part 2 420 and Part 4 720 is ≤5×10⁻⁶. 20 cm -3 Preferably, it is 5×10 19 cm -3 ~5×10 20 cm -3 5×10 is more optimal. 19 cm -3 ~3×10 20 cm -3 It should be noted that the doping concentrations of Part 420 and Part 720 can be the same or different.

[0117] Specifically, the widths of the plurality of first portions 410 in the first doped layer 400 in the second direction may be the same or different. Specifically, they may be 2 μm to 100 μm. The widths of the plurality of third portions 710 in the second doped layer 700 in the second direction may be the same or different. Specifically, they may be 2 μm to 100 μm.

[0118] Accordingly, the widths of the plurality of second portions 420 in the first doped layer 400 in the second direction may be the same or different, specifically 30 μm to 100 μm. The widths of the plurality of fourth portions 720 in the second doped layer 700 in the second direction may be the same or different, specifically 30 μm to 100 μm.

[0119] Specifically, based on the above embodiments, the first doped layer 400 below the first electrode 610 is either a first portion 410 or a second portion 420, or both a first portion 410 and a second portion 420. The second doped layer 700 below the second electrode 620 is either a third portion 710 or a fourth portion 720, or both a third portion 710 and a fourth portion 720.

[0120] Preferably, in some embodiments, the plurality of first portions 410 have the same width in the second direction, and the plurality of second portions 420 have different widths in the second direction. Based on the above embodiments, the first doped layer 400 located below the first electrode 610 is the second portion 420, and the width of the first electrode 610 in the second direction is smaller than the width of the second portion 420. Based on this embodiment, the carrier transport path can be effectively controlled, the transport resistance can be reduced, recombination in the electrode region can be reduced, and the photoelectric conversion efficiency can be improved.

[0121] Preferably, in some embodiments, the plurality of third portions 710 have the same width in the second direction, and the plurality of fourth portions 720 have different widths in the second direction. Based on the above embodiments, the second doped layer 700 located below the second electrode 620 is the fourth portion 720, and the width of the second electrode 620 in the second direction is smaller than the width of the fourth portion 720. Based on this embodiment, the carrier transport path can be effectively controlled, the transport resistance reduced, and recombination in the electrode region reduced, thereby improving photoelectric conversion efficiency.

[0122] Preferably, in some embodiments, a plurality of pinholes are formed in the first tunneling layer 210, and the distribution density of pinholes located below the first part 410 is greater than the distribution density of pinholes located below the second part 420. Based on this embodiment, damage to the first doped layer 400 can be further reduced, passivation effect can be improved, and photoelectric conversion efficiency can be improved.

[0123] Preferably, in some embodiments, a plurality of pinholes are formed in the second tunneling layer 220, and the distribution density of pinholes located below the third part 710 is greater than the distribution density of pinholes located below the fourth part 720. Based on this embodiment, damage to the second doped layer 700 can be further reduced, passivation effect can be improved, and photoelectric conversion efficiency can be improved.

[0124] The method for preparing the solar cell in this embodiment includes the following steps: S311: Provides a silicon substrate and polishes and cleans its first and second surfaces; S312: A first initial tunneling layer, a first initial diffusion barrier layer, and a first doped layer are formed on the first surface after polishing and cleaning, and a second initial tunneling layer, a second initial diffusion barrier layer, and a second doped layer are formed on the second surface to obtain a first intermediate. S313: A first doped source layer is formed on one side of the first doped layer of the first intermediate; S314: A laser is used to advance the dopant source of the first doped source layer into the first doped layer, and at least one hole is formed on the first initial barrier diffusion layer. The dopant source of the first doped layer is then advanced into the silicon substrate through the hole to form at least one first inner expansion region. S315: Remove the remaining doped source layer to obtain the second intermediate; S316: A second doped source layer is formed on one side of the second doped layer of the second intermediate; S317: A laser is used to advance the dopant source of the second doped source layer into the second doped layer, and at least one via is formed on the second initial barrier diffusion layer. The dopant source of the second doped layer is then advanced into the silicon substrate through the via to form at least one second inner expansion region. S318: Remove the remaining second doped source layer to obtain the third intermediate; S319: A second passivation layer is formed on one side of the second doped source layer of the third intermediate, and a first passivation layer is formed on one side of the first doped layer of the third intermediate; S320: A first electrode is formed on the first passivation layer, a second electrode is formed on the second passivation layer, and then sintered.

[0125] Example 5 This embodiment provides a solar cell, the specific structure of which is as follows: Figures 8-9 As shown, the solar cell includes a silicon substrate 100, a first tunneling layer 210, a first diffusion barrier layer 310, a first doped layer 400, a first passivation layer 510, a first electrode 610, a second passivation layer 520, and a second electrode 620.

[0126] The silicon substrate 100 can be P-type or N-type single-crystal silicon, and includes a first surface 110 and a second surface 120 in the thickness direction. The second surface 120 of the silicon substrate 100 is the light-receiving surface, and an anti-reflection layer 800 may be disposed on the second surface 120, but is not limited thereto. The first surface 110 of the silicon substrate 100 is the backlight surface, and the first surface 110 includes a first region 130 and a second region 140 alternately arranged along a second direction; the first region 130 has a plurality of first inner expansion regions 111 along the second direction, which are formed by the diffusion of external doping elements into the silicon substrate 100. The doping elements may be the same as or different from the doping elements of the silicon substrate 100 itself. More specifically, the first inner expansion regions 111 are spaced apart along the second direction and extend along the first direction.

[0127] The first tunneling layer 210 is disposed within the first region 130. The first tunneling layer 210 is a stack formed of one or more of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, in some embodiments, the first tunneling layer 210 is a silicon oxide layer.

[0128] The first diffusion barrier layer 310 is disposed on the first tunneling layer 210, and a plurality of holes 311 are formed in the first diffusion barrier layer 310 to allow the dopant source of the first doped layer 400 to diffuse into the silicon substrate 100 through the holes 311, forming the first inner expansion region 111. The first diffusion barrier layer 310 is a stack formed of one or more of the following: silicon nitride layer, silicon carbide layer, silicon oxynitride layer, silicon oxycarbide layer, silicon carbide nitride layer, and aluminum oxide layer. Preferably, in some embodiments, the first diffusion barrier layer 310 is a silicon nitride layer or a silicon carbide layer.

[0129] The first doped layer 400 is disposed on the first diffusion barrier layer 310, and more specifically, on the side of the first diffusion barrier layer 310 facing away from the first tunneling layer 210. The first doped layer 400 may be a doped polycrystalline silicon layer, a doped amorphous silicon layer, or a doped microcrystalline silicon layer, but is not limited thereto. More specifically, the first doped layer 400 may be an N-type polycrystalline silicon layer, a P-type polycrystalline silicon layer, a P-type amorphous silicon layer, an N-type amorphous silicon layer, a P-type microcrystalline silicon layer, or an N-type microcrystalline silicon layer, but is not limited thereto. Preferably, the first doped layer 400 is an N-type polycrystalline silicon layer or a P-type polycrystalline silicon layer.

[0130] Specifically, the first doped layer 400 includes a plurality of first portions 410 and second portions 420 alternately distributed along a second direction, the first portions 410 and the second portions 420 extending along a first direction. The doping concentration of the first portion 410 is greater than that of the second portion 420, and the first inner expansion region 111 is correspondingly provided with the first portion 410.

[0131] Specifically, the first passivation layer 510 is disposed on the first doped layer 400, specifically on the side of the first doped layer 400 facing away from the first diffusion barrier layer 310. The first passivation layer 510 may be a stacked structure formed by one or more of silicon nitride, silicon oxynitride, aluminum oxide, and silicon oxide layers. Preferably, in some embodiments, the first passivation layer 510 includes an aluminum oxide layer and a silicon nitride layer sequentially stacked on the first doped layer 400.

[0132] Specifically, the first electrode 610 is disposed on the first passivation layer 510 and contacts the first doped layer 400 through a hole disposed on the first passivation layer 510.

[0133] Specifically, a second doped layer 700 is provided in the second region 140. The second doped layer 700 is an emitter formed by inward doping into the silicon substrate 100, and its polarity is opposite to that of the silicon substrate 100.

[0134] The second passivation layer 520 is disposed on the second doped layer 700, and the second passivation layer 520 may be a stacked structure formed by one or more of the following: silicon nitride layer, silicon oxynitride layer, aluminum oxide layer, and silicon oxide layer. Preferably, in some embodiments, the second passivation layer 520 includes an aluminum oxide layer and a silicon nitride layer sequentially stacked on the second doped layer 700.

[0135] Specifically, the second electrode 620 is disposed on the second passivation layer 520 and contacts the second doped layer 700 through a hole disposed on the second passivation layer 520.

[0136] Specifically, the thickness of the first tunneling layer 210 is 2nm to 10nm, preferably 3nm to 10nm, and more preferably 3nm to 7nm.

[0137] Specifically, the thickness of the first diffusion barrier layer 310 is 1nm to 5nm, preferably 1nm to 3nm.

[0138] Specifically, the diffusion depth of the first inner expansion region 111 is ≥0.1μm, preferably 0.1μm~0.5μm, and more preferably 0.2μm~0.4μm.

[0139] Specifically, the doping concentration of the first inner expansion region 111 is ≥1×10⁻⁶. 18 cm -3 Preferably, it is 1×10 18 cm -3 ~5×10 19 cm -3 More preferably 5×10 18 cm -3 ~3×10 19 cm -3 .

[0140] Specifically, the doping concentration of the first part 410 is ≥1×10 20 cm -3 Preferably, it is 3×10 20 cm -3 ~5×10 21 cm -3 More preferably 8×10 20 cm -3 ~3×10 21 cm -3 .

[0141] Specifically, the doping concentration of the first part 410 is ≥1×10 20 cm -3 Preferably, it is 3×10 20 cm -3 ~5×10 21 cm -3 More preferably 8×10 20 cm -3 ~3×10 21 cm -3 .

[0142] Specifically, the doping concentration of the second part 420 is ≤5×10 20 cm -3 Preferably, it is 5×10 19 cm -3 ~5×10 20 cm -3 More preferably 5×10 19 cm -3 ~3×10 20 cm -3 .

[0143] Specifically, the widths of the plurality of first portions 410 in the first doped layer 400 in the second direction may be the same or different. Specifically, they may be 2 μm to 100 μm. Correspondingly, the widths of the plurality of second portions 420 in the first doped layer 400 in the second direction may be the same or different, specifically 30 μm to 100 μm.

[0144] Specifically, based on the above embodiments, the first doped layer 400 below the first electrode 610 is either a first part 410 or a second part 420, or both a first part 410 and a second part 420.

[0145] Preferably, in some embodiments, the plurality of first portions 410 have the same width in the second direction, and the plurality of second portions 420 have different widths in the second direction. Based on the above embodiments, the first doped layer 400 located below the first electrode 610 is the second portion 420, and the width of the first electrode 610 in the second direction is smaller than the width of the second portion 420. Based on this embodiment, the carrier transport path can be effectively controlled, the transport resistance can be reduced, recombination in the electrode region can be reduced, and the photoelectric conversion efficiency can be improved.

[0146] Preferably, in some embodiments, a plurality of pinholes are formed in the first tunneling layer 210, and the distribution density of pinholes located below the first part 410 is greater than the distribution density of pinholes located below the second part 420. Based on this embodiment, damage to the first doped layer 400 can be further reduced, passivation effect can be improved, and photoelectric conversion efficiency can be improved.

[0147] The method for preparing the solar cell in this embodiment includes the following steps: S411: Provides a silicon substrate and polishes and cleans its second surface; S412: A first initial tunneling layer, a first initial diffusion barrier layer, and a first doped layer are formed on the first surface after polishing and cleaning to obtain a first intermediate; S413: A doped source layer is formed on one side of the first doped layer of the first intermediate; S414: A laser is used to advance the dopant source of the doped source layer to the first doped layer, and at least one hole is formed on the first initial barrier diffusion layer. The dopant source of the first doped layer is then advanced into the silicon substrate through the hole to form at least one first inner expansion region. S415: Remove the remaining doped source layer to obtain the second intermediate; S416: Remove the first tunneling layer, the first diffusion barrier layer and the first doped layer on the second region to obtain the third intermediate; S417: A first passivation layer and a second passivation layer are formed on one side of the first doped layer of the third intermediate; S418: An anti-reflection layer is formed on one side of the second surface of the third intermediate; S419: A first electrode is formed on the first passivation layer, a second electrode is formed on the second passivation layer, and then sintered.

[0148] Example 6 This embodiment provides a solar cell, the specific structure of which is as follows: Figures 10-11 As shown, the solar cell includes a silicon substrate 100, a first tunneling layer 210, a first diffusion barrier layer 310, a first doped layer 400, a first passivation layer 510, a first electrode 610, a second tunneling layer 220, a second diffusion barrier layer 320, a second doped layer 700, a second passivation layer 520, and a second electrode 620.

[0149] The silicon substrate 100 can be P-type or N-type single-crystal silicon, and includes a first surface 110 and a second surface 120 in the thickness direction. The first surface 110 of the silicon substrate 100 is a backlight surface, and the first surface 110 includes a first region 130 and a second region 140 alternately arranged along a second direction. The first region 130 has a plurality of first inner expansion regions 111 along the second direction, which are formed by the diffusion of external doping elements into the silicon substrate 100. The doping elements can be the same as or different from the doping elements of the silicon substrate 100 itself. More specifically, the first inner expansion regions 111 are spaced apart in the second direction and extend along the first direction. The second region 140 has a plurality of second inner expansion regions 121 along the second direction, which are formed by the diffusion of external doping elements into the silicon substrate 100. The doping elements can be the same as or different from the doping elements of the silicon substrate 100 itself. More specifically, the second inner expansion regions 121 are spaced apart in the second direction and extend along the first direction.

[0150] The first tunneling layer 210 is disposed within the first region 130. The first tunneling layer 210 is a stack formed of one or more of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, in some embodiments, the first tunneling layer 210 is a silicon oxide layer.

[0151] The first diffusion barrier layer 310 is disposed on the first tunneling layer 210, and a plurality of holes 311 are formed in the first diffusion barrier layer 310 to allow the dopant source of the first doped layer 400 to diffuse into the silicon substrate 100 through the holes 311, forming the first inner expansion region 111. The first diffusion barrier layer 310 is a stack formed of one or more of the following: silicon nitride layer, silicon carbide layer, silicon oxynitride layer, silicon oxycarbide layer, silicon carbide nitride layer, and aluminum oxide layer. Preferably, in some embodiments, the first diffusion barrier layer 310 is a silicon nitride layer or a silicon carbide layer.

[0152] The first doped layer 400 is disposed on the first diffusion barrier layer 310, and more specifically, on the side of the first diffusion barrier layer 310 facing away from the first tunneling layer 210. The first doped layer 400 may be a doped polycrystalline silicon layer, a doped amorphous silicon layer, or a doped microcrystalline silicon layer, but is not limited thereto. More specifically, the first doped layer 400 may be an N-type polycrystalline silicon layer, a P-type polycrystalline silicon layer, a P-type amorphous silicon layer, an N-type amorphous silicon layer, a P-type microcrystalline silicon layer, or an N-type microcrystalline silicon layer, but is not limited thereto. Preferably, the first doped layer 400 is an N-type polycrystalline silicon layer or a P-type polycrystalline silicon layer.

[0153] Specifically, the first doped layer 400 includes a plurality of first portions 410 and second portions 420 alternately distributed along a second direction, with the first portions 410 and second portions 420 extending along a first direction. The doping concentration of the first portions 410 is greater than that of the second portions 420, and a first inner expansion region 111 is correspondingly provided with the first portions 410.

[0154] Specifically, the first passivation layer 510 is disposed on the first doped layer 400, specifically on the side of the first doped layer 400 facing away from the first diffusion barrier layer 310. The first passivation layer 510 may be a stacked structure formed by one or more of silicon nitride, silicon oxynitride, aluminum oxide, and silicon oxide layers. Preferably, in some embodiments, the first passivation layer 510 includes an aluminum oxide layer and a silicon nitride layer sequentially stacked on the first doped layer 400.

[0155] Specifically, the first electrode 610 is disposed on the first passivation layer 510 and contacts the first doped layer 400 through a hole disposed on the first passivation layer 510.

[0156] The second tunneling layer 220 is disposed within the second region 140. The second tunneling layer 220 is a stack formed of one or more of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, in some embodiments, the second tunneling layer 220 is a silicon oxide layer.

[0157] The second diffusion barrier layer 320 is disposed on the second tunneling layer 220. Multiple through-holes 321 are formed in the second diffusion barrier layer 320 to allow the doping source of the second doped layer 700 to diffuse into the silicon substrate 100 through the through-holes 321, forming the second inner expansion region 121. The second diffusion barrier layer 320 is a stack of one or more of the following: silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon carbide nitride, and aluminum oxide. Preferably, in some embodiments, the second diffusion barrier layer 320 is a silicon nitride layer or a silicon carbide layer.

[0158] The second doped layer 700 is disposed on the second diffusion barrier layer 320, and more specifically, on the side of the second diffusion barrier layer 320 facing away from the second tunneling layer 220. The second doped layer 700 can be a doped polycrystalline silicon layer, a doped amorphous silicon layer, or a doped microcrystalline silicon layer, but is not limited thereto. More specifically, the second doped layer 700 can be an N-type polycrystalline silicon layer, a P-type polycrystalline silicon layer, a P-type amorphous silicon layer, an N-type amorphous silicon layer, a P-type microcrystalline silicon layer, or an N-type microcrystalline silicon layer, but is not limited thereto. Preferably, the second doped layer 700 is an N-type polycrystalline silicon layer or a P-type polycrystalline silicon layer.

[0159] Specifically, the second doped layer 700 includes a plurality of third portions 710 and fourth portions 720 alternately distributed along a second direction, and the third portions 710 and fourth portions 720 extend along a first direction. The doping concentration of the third portion 710 is greater than that of the fourth portion 720, and the second inner expansion region 121 is correspondingly provided with the third portion 710.

[0160] Specifically, the second passivation layer 520 is disposed on the second doped layer 700, specifically on the side of the second doped layer 700 opposite to the second diffusion barrier layer 320. The second passivation layer 520 may be a stacked structure formed by one or more of silicon nitride, silicon oxynitride, aluminum oxide, and silicon oxide layers. Preferably, in some embodiments, the second passivation layer 520 includes an aluminum oxide layer and a silicon nitride layer sequentially stacked on the second doped layer 700.

[0161] Specifically, the second electrode 620 is disposed on the second passivation layer 520 and contacts the second doped layer 700 through a hole disposed on the second passivation layer 520.

[0162] Specifically, the thickness of the first tunneling layer 210 and the second tunneling layer 220 is 2nm to 10nm. Preferably, it is 3nm to 10nm, and more preferably, it is 3nm to 7nm. Based on this, passivation performance and conversion efficiency can be improved. It should be noted that the thickness of the first tunneling layer 210 and the second tunneling layer 220 can be the same or different.

[0163] Specifically, the thickness of the first diffusion barrier layer 310 and the second diffusion barrier layer 320 is 1 nm to 5 nm, preferably 1 nm to 3 nm. It should be noted that the thickness of the first diffusion barrier layer 310 and the second diffusion barrier layer 320 may be the same or different.

[0164] Specifically, the diffusion depth of the first inner expansion region 111 and the second inner expansion region 121 is ≥0.1μm, preferably 0.1μm~0.5μm, and more preferably 0.2μm~0.4μm. It should be noted that the diffusion depth of the first inner expansion region 111 and the second inner expansion region 121 may be the same or different.

[0165] Specifically, the doping concentration of the first inner expansion region 111 and the second inner expansion region 121 is ≥1×10⁻⁶. 18 cm -3 Preferably, it is 1×10 18 cm -3 ~5×10 19 cm -3 More preferably 5×10 18 cm -3 ~3×10 19 cm -3 It should be noted that the doping concentrations of the first inner expansion region 111 and the second inner expansion region 121 can be the same or different.

[0166] Specifically, the doping concentration of Part 1 (410) and Part 3 (710) is ≥1×10⁻⁶. 20 cm -3 Preferably, it is 3×10 20 cm -3 ~5×10 21 cm -3 More preferably 8×10 20 cm -3 ~3×10 21 cm -3 It should be noted that the doping concentrations of the first part 410 and the third part 710 can be the same or different.

[0167] Specifically, the doping concentration of Part 2 420 and Part 4 720 is ≤5×10⁻⁶. 20 cm -3 Preferably, it is 5×10 19 cm -3 ~5×10 20 cm -3 5×10 is more optimal. 19 cm -3 ~3×10 20 cm -3 It should be noted that the doping concentrations of Part 420 and Part 720 can be the same or different.

[0168] Specifically, the widths of the plurality of first portions 410 in the first doped layer 400 in the second direction may be the same or different. Specifically, they may be 2 μm to 100 μm. The widths of the plurality of third portions 710 in the second doped layer 700 in the second direction may be the same or different. Specifically, they may be 2 μm to 100 μm.

[0169] Accordingly, the widths of the plurality of second portions 420 in the first doped layer 400 in the second direction may be the same or different, specifically 30 μm to 100 μm. The widths of the plurality of fourth portions 720 in the second doped layer 700 in the second direction may be the same or different, specifically 30 μm to 100 μm.

[0170] Specifically, based on the above embodiments, the first doped layer 400 below the first electrode 610 is either a first portion 410 or a second portion 420, or both a first portion 410 and a second portion 420. The second doped layer 700 below the second electrode 620 is either a third portion 710 or a fourth portion 720, or both a third portion 710 and a fourth portion 720.

[0171] Preferably, in some embodiments, the plurality of first portions 410 have the same width in the second direction, and the plurality of second portions 420 have different widths in the second direction. Based on the above embodiments, the first doped layer 400 located below the first electrode 610 is the second portion 420, and the width of the first electrode 610 in the second direction is smaller than the width of the second portion 420. Based on this embodiment, the carrier transport path can be effectively controlled, the transport resistance can be reduced, recombination in the electrode region can be reduced, and the photoelectric conversion efficiency can be improved.

[0172] Preferably, in some embodiments, the plurality of third portions 710 have the same width in the second direction, and the plurality of fourth portions 720 have different widths in the second direction. Based on the above embodiments, the second doped layer 700 located below the second electrode 620 is the fourth portion 720, and the width of the second electrode 620 in the second direction is smaller than the width of the fourth portion 720. Based on this embodiment, the carrier transport path can be effectively controlled, the transport resistance reduced, and recombination in the electrode region reduced, thereby improving photoelectric conversion efficiency.

[0173] Preferably, in some embodiments, a plurality of pinholes are formed in the first tunneling layer 210, and the distribution density of pinholes located below the first part 410 is greater than the distribution density of pinholes located below the second part 420. Based on this embodiment, damage to the first doped layer 400 can be further reduced, passivation effect can be improved, and photoelectric conversion efficiency can be improved.

[0174] Preferably, in some embodiments, a plurality of pinholes are formed in the second tunneling layer 220, and the distribution density of pinholes located below the third part 710 is greater than the distribution density of pinholes located below the fourth part 720. Based on this embodiment, damage to the second doped layer 700 can be further reduced, passivation effect can be improved, and photoelectric conversion efficiency can be improved.

[0175] The method for preparing the solar cell in this embodiment includes the following steps: S511: Provides a silicon substrate and polishes and cleans its second surface; S512: A first initial tunneling layer, a first initial diffusion barrier layer, and a first doped layer are formed on the first surface after polishing and cleaning to obtain a first intermediate; S513: A first doped source layer is formed on one side of the first doped layer of the first intermediate; S514: A laser is used to push the dopant source of the first doped source layer into the first doped layer, and at least one hole is formed on the first initial barrier diffusion layer. The dopant source of the first doped layer is pushed into the silicon substrate through the hole to form at least one first inner expansion region. S515: Remove the remaining first doped source layer to obtain the second intermediate; S516: Remove the first tunneling layer, the first diffusion barrier layer and the first doped layer on the second region to obtain the third intermediate; S517: A second initial tunneling layer, a second initial diffusion barrier layer, and a second doped layer are formed on one side of the first doped layer of the third intermediate to obtain the fourth intermediate; S518: A second doped source layer is formed on one side of the second doped layer of the fourth intermediate; S519: A laser is used to advance the dopant source of the second doped source layer into the second doped layer, and at least one via is formed on the second initial barrier diffusion layer. The dopant source of the second doped layer is then advanced into the silicon substrate through the via to form at least one second inner expansion region. S520: Remove the remaining second doped source layer to obtain the fifth intermediate; S521: Remove the first tunneling layer, the first diffusion barrier layer and the first doped layer on the second region to obtain the sixth intermediate; S522: A first passivation layer and a second passivation layer are formed on one side of the first doped layer of the sixth intermediate; S523: An anti-reflection layer is formed on one side of the second surface of the sixth intermediate; S524: A first electrode is formed on the first passivation layer, a second electrode is formed on the second passivation layer, and then sintered.

[0176] Example 7 Please see Figure 12 This embodiment provides a battery assembly 10, which includes the aforementioned solar cells. Multiple solar cells are connected by solder ribbons to form a battery string. The battery strings are connected to form the battery assembly 10. Accordingly, the battery assembly 10 also includes busbars for connecting multiple battery strings and connecting solder ribbons for connecting the busbars and the battery strings.

[0177] It is understood that in such embodiments, the battery assembly 10 may further include a frame, a backsheet, photovoltaic glass, and an encapsulating film. The encapsulating film may be filled between the front and back of the solar cell and between the photovoltaic glass, etc. As a filler, it may be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulating film may be an EVA film or a POE film, and the specific choice can be made according to the actual situation, without limitation.

[0178] Photovoltaic glass can be applied to the encapsulating film on the front of solar cells. This photovoltaic glass can be ultra-clear glass, characterized by high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 92%, protecting the solar cells while minimizing impact on their efficiency. Simultaneously, the encapsulating film bonds the photovoltaic glass and the solar cells together, providing sealing, insulation, and waterproofing / moisture protection for the solar cells.

[0179] The backsheet can be attached to the encapsulant film on the back of the solar cell. The backsheet protects and supports the solar cell, providing reliable insulation, water resistance, and aging resistance. Multiple backsheet options are available, typically including tempered glass, acrylic glass, and aluminum alloy TPT composite encapsulant film, etc. The specific choice depends on the specific circumstances and is not limited here. The backsheet, solar cell, encapsulant film, and photovoltaic glass can be integrated into a frame. The frame serves as the main external support structure for the entire solar module 10, providing stable support and installation. For example, the solar module 10 can be installed at the desired location via the frame.

[0180] Example 8 Please see Figure 13 This embodiment discloses a photovoltaic system 1, which includes the battery module 10 described in the above embodiment. In the photovoltaic system 1, the battery modules 10 can be electrically connected in parallel or in series, depending on actual needs.

[0181] In this embodiment, photovoltaic system 1 can be applied in photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants. It can also be applied to equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of photovoltaic system 1 are not limited to these; that is to say, photovoltaic system 1 can be applied in all fields that require the use of solar energy to generate electricity.

[0182] Taking a photovoltaic power generation system network as an example, the photovoltaic system 1 may include a photovoltaic array, a combiner box and an inverter. The photovoltaic array may be an array combination of multiple battery modules 1. For example, multiple battery modules 10 may form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can combine the current generated by the photovoltaic array. The combined current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to realize solar power supply.

[0183] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. The above embodiments only illustrate several implementation methods of the present invention to facilitate a specific and detailed understanding of the technical solution of the present invention, but should not be construed as limiting the scope of protection of the invention patent. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A solar cell, characterized in that, include: A silicon substrate having a first surface and a second surface disposed opposite to each other, wherein the first surface or the second surface has at least one first inner expansion region along a second direction; The first direction intersects the thickness direction of the silicon substrate; A first tunneling layer is disposed on the first surface; A first diffusion barrier layer is disposed on the first tunneling layer; The first diffusion barrier layer has at least one hole so that the doping source of the first doped layer diffuses into the silicon substrate through the hole to form the first inner expansion region; A first doped layer is disposed above the first tunneling layer; the first doped layer includes a first part and a second part that are alternately distributed along a second direction, the first part and the second part extend along the first direction, the doping concentration of the first part is greater than the doping concentration of the second part, the first part is disposed corresponding to the first inner expansion region; the first direction and the second direction intersect. A first passivation layer is disposed on the first doped layer; as well as The first electrode is disposed on the first passivation layer and is in contact with the first doped layer.

2. The solar cell as described in claim 1, characterized in that, The thickness of the first tunneling layer is 2nm~10nm; and / or The first tunneling layer is a stack formed by one or more of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer; The thickness of the first diffusion barrier layer is 1 nm to 5 nm; and / or The first diffusion barrier layer is a stack formed by one or more of the following: silicon nitride layer, silicon carbide layer, silicon oxynitride layer, silicon oxycarbonate layer, silicon carbide nitride layer, and aluminum oxide layer.

3. The solar cell as described in claim 1, characterized in that, The first tunneling layer is a silicon oxide layer with a thickness of 3nm to 10nm; and / or The thickness of the first diffusion barrier layer is 1 nm to 3 nm; and / or The first diffusion barrier layer is a silicon nitride layer or a silicon carbide layer.

4. The solar cell as described in claim 1, characterized in that, The depth of the first inner expansion region is ≥0.1 μm; and / or The doping concentration of the first inner expansion region is ≥1×10 18 cm -3 ; and / or The doping concentration of the first part is ≥1×10 20 cm -3 ; and / or The doping concentration of the second part is ≤5×10 20 cm -3 .

5. The solar cell as described in claim 1, characterized in that, The depth of the first inner expansion region is 0.1 μm to 0.5 μm; and / or The doping concentration of the first inner expansion region is 1×10 18 cm -3 ~5×10 19 cm -3 ; and / or The doping concentration of the first part is 3×10 20 cm -3 ~5×10 21 cm -3 ; and / or The doping concentration of the second part is 5×10 19 cm -3 ~5×10 20 cm -3 .

6. The solar cell as claimed in claim 1, characterized in that, The first doped layer includes a plurality of first portions and second portions that are alternately distributed along a second direction; the widths of the plurality of first portions in the second direction may be the same or different, and the widths of the plurality of second portions in the second direction may be the same or different. The first doped layer beneath the first electrode includes the first portion and / or the second portion.

7. The solar cell according to claim 1, characterized in that, The first doped layer includes a plurality of first portions and second portions that are alternately distributed along a first direction; the plurality of second portions have different widths in the second direction, and the plurality of first portions have the same width in the second direction; The first doped layer below the first electrode is the second part, and the width of the first electrode in the second direction is smaller than the width of the second part below it in the second direction.

8. The solar cell as claimed in claim 1, characterized in that, The width of the first part in the second direction is 2μm to 100μm, and the width of the second part in the second direction is 30μm to 100μm.

9. The solar cell according to claim 1, characterized in that, The pinhole distribution density of the first tunneling layer below the first part is greater than the pinhole distribution density of the first tunneling layer below the second part.

10. The solar cell according to any one of claims 1 to 9, characterized in that, The first inner expansion region, the first tunneling layer, the first diffusion barrier layer, the first doped layer, the first passivation layer, and the first electrode are all disposed on the first surface; The solar cell further includes a doped layer, a second passivation layer, an antireflection layer, and a second electrode sequentially disposed on the second surface, wherein the second electrode is in contact with the doped layer.

11. The solar cell according to any one of claims 1 to 9, characterized in that, The first tunneling layer, the first diffusion barrier layer, the first doped layer, the first passivation layer, and the first electrode are all disposed on the first surface; the first inner expansion region is disposed on the first surface and the second surface. The solar cell further includes a second tunneling layer, a second diffusion barrier layer, a second doped layer, a second passivation layer, and a second electrode sequentially disposed on the second surface; the second diffusion barrier layer has at least one via so that the doping source of the second doped layer diffuses into the silicon substrate through the via to form the first inner expansion region; the second doped layer includes at least one third part and at least one fourth part in a first direction, the doping concentration of the third part is greater than the doping concentration of the fourth part, and the third part is disposed corresponding to the first inner expansion region; the second electrode is in contact with the second doped layer.

12. The solar cell according to any one of claims 1 to 9, characterized in that, The first surface of the silicon substrate includes a first region and a second region alternately arranged along a second direction; The first inner expansion region, the first tunneling layer, the first diffusion barrier layer, the first doped layer, the first passivation layer, and the first electrode are all disposed within the first region; A passivation layer and a second electrode are sequentially stacked in the second region, and the second electrode is in contact with the silicon substrate.

13. The solar cell according to any one of claims 1 to 9, characterized in that, The first surface of the silicon substrate includes a first region and a second region alternately arranged along a second direction; The first inner expansion region, the first tunneling layer, the first diffusion barrier layer, the first doped layer, the first passivation layer, and the first electrode are all disposed within the first region; The second region is sequentially stacked with a second tunneling layer, a second diffusion barrier layer, a second doped layer, a second passivation layer, and a second electrode; the second region has at least one second inner expansion region along a first direction; the second diffusion barrier layer has at least one via so that the doping source of the second doped layer diffuses into the silicon substrate through the via to form the second inner expansion region; the second doped layer includes at least one third part and at least one fourth part in the first direction, the doping concentration of the third part is greater than the doping concentration of the fourth part, and the third part is correspondingly disposed with the first inner expansion region; the second electrode is in contact with the second doped layer.

14. A method for preparing a solar cell, used to prepare the solar cell according to any one of claims 1 to 13, characterized in that, include: Provide silicon substrate; A first initial tunneling layer, a first initial diffusion barrier layer, and a first doped layer are sequentially formed on the silicon substrate to obtain a first intermediate. A doped source layer is formed on the first intermediate; A laser is used to advance the dopant source of the doped source layer into the first doped layer, and at least one hole is formed on the first initial diffusion barrier layer. The dopant source of the first doped layer is then advanced into the silicon substrate through the hole to form at least one first inner expansion region. The first doped layer forms a first part and a second part after laser processing. The first initial diffusion barrier layer and the first initial tunneling layer form a first diffusion barrier layer and a first tunneling layer, respectively, after laser processing. The remaining doped source layer is removed to obtain the second intermediate. A first passivation layer is formed on the second intermediate; A first electrode is formed on the first passivation layer, and the first electrode is in contact with the first doped layer.

15. The method for preparing a solar cell as described in claim 14, characterized in that, The doped source layer is a phosphorus-silicon glass layer, a borosilicate glass layer, a boron-doped silicon slurry layer, a phosphorus-doped silicon slurry layer, a liquid phosphorus source layer, or a liquid boron source layer.

16. A battery assembly, characterized in that, Including the solar cell as described in any one of claims 1 to 13.

17. A photovoltaic system comprising the battery module as claimed in claim 16.

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