Bonding test structure and test method

Abstract

The invention relates to the technical field of semiconductor testing, in particular to a bonding test structure and method, and the structure comprises a first semiconductor structure which is provided with a first bonding surface, and is internally provided with a plurality of first conductive parts which are separated from each other, the first conductive part is exposed on the first bonding surface of the first semiconductor structure; the second semiconductor structure is in bonding connection with the first semiconductor structure, the second semiconductor structure is provided with a second bonding surface, the second bonding surface is bonded with the first bonding surface, a second conductive part is arranged in the second semiconductor structure, and the second conductive part is exposed out of the second bonding surface; and when the second semiconductor structure and the first semiconductor structure are in the standard bonding position, at least part of the surface of the second conductive part is in dislocation contact with at least part of the surface of the first conductive part, so that the hybrid bonding precision of the whole wafer can be quickly and effectively monitored.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor testing technology, specifically to a bonding test structure and testing method. Background Technology

[0002] Hybrid bonding, compared to traditional bonding technologies, offers advantages such as high-density interconnects, low resistance delay, good heat dissipation, and miniaturized high-performance packaging, making it one of the most important technologies in the semiconductor packaging field.

[0003] Bonding alignment accuracy is a key factor affecting bonding quality. Currently, the semiconductor manufacturing process often uses the measurement of nested alignment points (marks) to obtain alignment accuracy (overlay). However, this method is usually limited by the number of alignment points and measurement points on the entire wafer, and the measurement results cannot fully reflect the hybrid bonding alignment quality on the entire wafer.

[0004] In addition, after all the processing of the wafer is completed, the wafer needs to be tested by CP (Chip Probing). CP testing can also monitor the alignment accuracy (overlay) of all chips (chips / dies). However, CP testing of alignment accuracy (overlay) takes a long time, and CP testing is often used in the product packaging stage, so problems are discovered late. Summary of the Invention

[0005] This disclosure provides a bonding test structure and test method. By testing the bonding test structure during the wafer acceptance test (WAT) stage, the hybrid bonding accuracy of the entire wafer can be quickly and effectively monitored.

[0006] In a first aspect, this disclosure provides a bonding test structure, comprising: a first semiconductor structure having a first bonding surface and having a plurality of mutually discrete first conductive portions therein, the first conductive portions being exposed on the first bonding surface of the first semiconductor structure; a second semiconductor structure bonded to the first semiconductor structure, the second semiconductor structure having a second bonding surface bonded to the first bonding surface, the second semiconductor structure having a second conductive portion therein, the second conductive portion being exposed on the second bonding surface; when the second semiconductor structure and the first semiconductor structure are in a standard bonding position, at least a portion of the surface of the second conductive portion is in misaligned contact with at least a portion of the surface of the first conductive portion; and two mutually discrete test pads located within the first semiconductor structure, the two test pads being electrically connected through the first conductive portion and the second conductive portion when the second semiconductor structure and the first semiconductor structure are in a standard bonding position.

[0007] In some embodiments, the first conductive portion includes: a first bonding layer and a first interconnect layer located within a first semiconductor structure, the first bonding surface exposing the first bonding layer, and the first interconnect layer electrically connecting the first bonding layer to a corresponding test pad; the second conductive portion includes: a mutually discrete second bonding layer and a second interconnect layer located within a second semiconductor structure, the second bonding surface exposing the second bonding layer, and the second interconnect layer electrically connecting the second bonding layers.

[0008] In some embodiments, the first semiconductor structure further includes a first substrate and a first insulating layer, a first interconnect layer is located on the first substrate, the first insulating layer covers the first interconnect layer and the first substrate, the first insulating layer has a first opening that exposes the first interconnect layer, and a first bonding layer is disposed in the first opening; the second semiconductor structure further includes a second substrate and a second insulating layer, a second interconnect layer is located on the second substrate, the second insulating layer covers the second interconnect layer and the second substrate, the second insulating layer has a second opening that exposes the second interconnect layer, and a second bonding layer is disposed in the second opening.

[0009] In some embodiments, the second bonding layer has a first projection projected onto the second bonding surface; the second interconnect layer has a second projection projected onto the second bonding surface; the first projection is centrally symmetrically arranged based on the second projection.

[0010] In some embodiments, the first bonding layer has a third projection projected onto the second bonding surface; when the second semiconductor structure and the first semiconductor structure are at a standard bonding site, the first projection and the third projection have an overlapping area, and the overlapping area is centrally symmetrically arranged based on the second projection.

[0011] In some embodiments, the size of the overlapping area corresponding to different test pads is different.

[0012] In some embodiments, the shape of the first projection is the same as the shape of the third projection, and the size of the first projection is the same as the size of the third projection.

[0013] In some embodiments, when the second semiconductor structure and the first semiconductor structure are at a standard bonding site, the overlapping areas on both sides of the second projection have the same shape and the same size.

[0014] In a second aspect, this disclosure provides a testing method, comprising: providing the bonding test structure provided in the first aspect above; performing electrical tests on the bonding test structure to obtain electrical parameters of the test pads in the bonding test structure; and determining whether the semiconductor structure corresponding to the bonding test structure is aligned based on the electrical parameters of the test pads.

[0015] In some embodiments, the number of bonding test structures is multiple, and the size of the overlapping area corresponding to the test pads in different bonding test structures is different; the test method further includes: obtaining the alignment accuracy of the semiconductor structure corresponding to the bonding test structure based on the electrical parameters of different test pads.

[0016] For the bonding test structure provided in this embodiment, the preset alignment deviation is set by setting the first conductive part and the second conductive part to be misaligned under the standard bonding position. Then, the test parameters between the test pads are used to determine whether a path is formed between the first conductive part and the second conductive part to determine the relationship between the bonding deviation between the first semiconductor structure and the second semiconductor structure and the preset alignment deviation, thereby determining whether the bonding accuracy between the first semiconductor structure and the second semiconductor structure exceeds the preset value.

[0017] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the bonding test structure provided in an embodiment of the present disclosure;

[0020] Figure 2 A schematic diagram illustrating the arrangement of a first conductive part and a second conductive part provided in an embodiment of this disclosure;

[0021] Figure 3 A schematic diagram illustrating the arrangement of another first conductive part and a second conductive part provided in an embodiment of this disclosure;

[0022] Figure 4 This is a schematic diagram of the upper projection of the second bonding surface below the calibration bonding site provided in an embodiment of this disclosure;

[0023] Figure 5 The upper projection of the second bonding surface when the bonding error is large, as provided in the first embodiment of this disclosure;

[0024] Figure 6 The second projection of the second bonding surface when the bonding error is large, as provided in the embodiments of this disclosure;

[0025] Figure 7 The third type of upper projection of the second bonding surface when the bonding error is large, provided in the embodiments of this disclosure;

[0026] Figure 8 The fourth type of upper projection of the second bonding surface when the bonding error is large, as provided in the embodiments of this disclosure;

[0027] The structure includes a bonding test structure 10, a first semiconductor structure 100, a second semiconductor structure 200, a first conductive part 101, a first bonding surface A, a second conductive part 201, a second bonding surface B, a first bonding layer 112, a first interconnect layer 111, a second interconnect layer 211, a second bonding layer 212, a first substrate 113, a first insulating layer 114, a second substrate 213, a second insulating layer 214, an opening, and a metal part 400. Detailed Implementation

[0028] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0029] In the description of this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more described features. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0030] In this disclosure, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this disclosure is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this disclosure. In the following description, details are set forth for purposes of explanation. It should be understood that those skilled in the art will recognize that this disclosure can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of this disclosure with unnecessary detail. Therefore, this disclosure is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

[0031] Furthermore, this disclosure uses specific terms to describe embodiments of the present disclosure. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the present disclosure. Therefore, it should be emphasized and noted that references to "an embodiment," "one embodiment," or "an alternative embodiment" in different locations throughout this specification do not necessarily refer to the same embodiment. Moreover, certain features, structures, or characteristics in one or more embodiments of the present disclosure can be appropriately combined.

[0032] Similarly, it should be noted that, in order to simplify the description of this disclosure and thus aid in the understanding of one or more embodiments, the foregoing description of embodiments of this disclosure sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of this disclosure requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of a single embodiment disclosed above.

[0033] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should be considered for specifying significant digits and employing a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of range in some embodiments of this disclosure are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0034] For each patent, patent application, patent application publication, and other material such as articles, books, specifications, publications, and documents referenced in this disclosure, the entire contents of that publication are incorporated herein by reference, except for historical application documents that are inconsistent with or conflict with the content of this disclosure, and documents that limit the broadest scope of the claims of this disclosure (currently or subsequently appended to this disclosure). It should be noted that if there are any inconsistencies or conflicts between the descriptions, definitions, and / or terms used in the supplementary materials to this disclosure and the examples in this disclosure, the descriptions, definitions, and / or terms used in this disclosure shall prevail.

[0035] Wafer Acceptance Test (WAT) is conducted after wafer fabrication and before quality inspection, measuring the electrical parameters of specific test structures. The purpose of WAT is to inspect the process status of each wafer by testing the electrical parameters of these specific test structures, assess the quality and stability of the semiconductor manufacturing process, and determine whether the wafer meets the electrical specifications of the process technology platform. Furthermore, WAT data serves as quality documentation for wafer delivery and reflects the actual production status of the production line. Collecting and analyzing WAT data allows for monitoring the production line, identifying trends, and providing early warnings of potential problems.

[0036] This disclosure provides a bonding test structure that can quickly and effectively monitor the hybrid bonding accuracy of the entire wafer during the wafer acceptance test (WAT) phase. The bonding test structure provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0037] Figure 1 , Figure 1 This is a schematic diagram of the bonding test structure provided in this embodiment. The bonding test structure 10 includes: a first semiconductor structure 100 and a second semiconductor structure 200.

[0038] The first semiconductor structure 100 has a first bonding surface A, and has a plurality of mutually discrete first conductive portions 101, the first conductive portions 101 being exposed on the first bonding surface A of the first semiconductor structure 100; the second semiconductor structure 200 is bonded to the first semiconductor structure 100, the second semiconductor structure 200 has a second bonding surface B, the second bonding surface B being bonded to the first bonding surface A, and has a second conductive portion 201, the second conductive portion 201 being exposed on the second bonding surface B.

[0039] Specifically, the first bonding surface A serves as the bonding surface of the first semiconductor structure 100, and the second bonding surface B serves as the bonding surface of the second semiconductor structure 200. When the first semiconductor structure 100 and the second semiconductor structure 200 are bonded, the first bonding surface A and the second bonding surface B are bonded. More specifically, the surface of the first bonding surface A exposes a first conductive portion 101, and the surface of the second bonding surface B exposes a second conductive portion 201. The first bonding surface A and the second bonding surface B are bonded, that is, the first conductive portion 101 and the second conductive portion 201 are bonded.

[0040] refer to Figure 4For example, when the second semiconductor structure 200 and the first semiconductor structure 100 are in a standard bonding position, at least a portion of the surface of the second conductive portion 201 is in misaligned contact with at least a portion of the surface of the second conductive portion 201. Two separate test pads 300 located within the first semiconductor structure 100 are electrically connected through the first conductive portion 101 and the second conductive portion 201 when the second semiconductor structure 200 and the first semiconductor structure 100 are in a standard bonding position.

[0041] Specifically, when the first semiconductor structure 100 and the second semiconductor structure 200 are successfully bonded, the first conductive part 101 and the second conductive part 201 are electrically connected, and a conductive path is formed between the two test pads 300; when the first semiconductor structure 100 and the second semiconductor structure 200 are successfully bonded, the first conductive part 101 and the second conductive part 201 are disconnected, and a conductive path cannot be formed between the two test pads 300.

[0042] In one example, whether a conductive path is formed between the two test pads 300 can be used to determine whether the bonding between the first semiconductor structure 100 and the second semiconductor structure 200 is "successful" or "failed". In specific applications, the resistance value between the two test pads 300, whether current flows through them, and the magnitude of the voltage across them can be used to determine whether a conductive path is formed between the two test pads 300.

[0043] It should be noted that, in the above description, "successful bonding" means that the alignment deviation between the first semiconductor structure 100 and the second semiconductor structure 200 is less than a preset alignment deviation; "failed bonding" means that the alignment deviation between the first semiconductor structure 100 and the second semiconductor structure 200 is greater than the preset alignment deviation. It should also be noted that the "standard bonding bit" value in the above description indicates that the alignment deviation between the first semiconductor structure 100 and the second semiconductor structure 200 is 0.

[0044] In this embodiment, when the first semiconductor structure 100 and the second semiconductor structure 200 are in the calibration bonding position, there is a misaligned contact surface between the first conductive part 101 and the second conductive part 201, and the bonding between the first conductive part 101 and the second conductive part 201 is achieved through the misaligned contact surface; in addition, the misaligned contact surface is also used to measure the alignment deviation.

[0045] refer to Figure 4In one example, assuming that in the first direction, the width of the first conductive part 101 and the second conductive part 201 is X1, and the misalignment contact width of the first conductive part 101 and the second conductive part 201 under the standard bonding position is X, when the bonding deviation is greater than X, the first conductive part 101 and the second conductive part 201 cannot be electrically connected. At this time, the preset misalignment contact position is used to determine the preset alignment deviation in the first direction. Similarly, in the second direction, the width of the first conductive part 101 and the second conductive part 201 is Y1, and the misalignment contact width of the first conductive part 101 and the second conductive part 201 under the standard bonding position is Y. When the bonding deviation is greater than Y, the first conductive part 101 and the second conductive part 201 cannot be electrically connected. At this time, the preset misalignment contact position is used to determine the preset alignment deviation in the second direction.

[0046] This embodiment achieves the setting of a preset alignment deviation by setting the first conductive part 101 and the second conductive part 201 to be misaligned under the standard bonding position. Then, by testing the test parameters between the test pads 300, it is determined whether a path is formed between the first conductive part 101 and the second conductive part 201, thereby determining the relationship between the bonding deviation between the first semiconductor structure 100 and the second semiconductor structure 200 and the preset alignment deviation, and thus determining whether the bonding accuracy between the first semiconductor structure 100 and the second semiconductor structure 200 exceeds the preset value.

[0047] In some embodiments, a plurality of the aforementioned bonding test structures 10 are provided in the first semiconductor structure 100 and the second semiconductor structure 200 that are bonded together, and the misaligned contact area of ​​different bonding test structures 10 is different under the standard bonding site, thereby determining whether the bonding accuracy between the first semiconductor structure 100 and the second semiconductor structure 200 exceeds different preset values.

[0048] In some embodiments, the areas of misaligned contact of different bonding test structures 10 at standard bonding sites are set in a gradient, thereby accurately obtaining the bonding accuracy between the first semiconductor structure 100 and the second semiconductor structure 200 based on the preset value of the gradient setting.

[0049] refer to Figure 1 In some embodiments, the first conductive portion 101 includes a first bonding layer 112 and a first interconnect layer 111 located within the first semiconductor structure 100, a first bonding surface A exposing the first bonding layer 112, and the first interconnect layer 111 electrically connecting the first bonding layer 112 to the corresponding test pad 300; the second conductive portion 201 includes a mutually discrete second bonding layer 212 and a second interconnect layer 211 located within the second semiconductor structure 200, a second bonding surface B exposing the second bonding layer 212, and the second interconnect layer 211 electrically connecting the second bonding layers 212.

[0050] It should be noted that, Figure 1In this example, the arrangement of the first conductive part 101 and the second conductive part 201 is only used to illustrate the connection example between the two test pads 300 and does not constitute a limitation on this embodiment. (See reference) Figure 2 and Figure 3 , Figure 2 This is a schematic diagram illustrating the arrangement of a first conductive part and a second conductive part according to this embodiment. Figure 3 This is a schematic diagram illustrating another configuration of the first conductive part and the second conductive part provided in this embodiment.

[0051] At Figure 2 In the example, the first semiconductor structure 100 includes three first conductive portions 101, the second semiconductor includes two second conductive portions 201, and the two test pads 300 are electrically connected through the three first conductive portions 101 and the two second conductive portions 201. Based on this, those skilled in the art can make more extensions. As long as there is a test structure in which at least a portion of the surface of the second conductive portion 201 is in misaligned contact with at least a portion of the surface of the second conductive portion 201, it falls within the protection scope of this disclosure.

[0052] At Figure 3 In the example, each first conductive portion 101 includes two first bonding layers 112, and each second conductive portion 201 includes two second bonding layers 212. Based on this, those skilled in the art can make more extensions. As long as there is a test structure in which at least a portion of the surface of the second conductive portion 201 is in misaligned contact with at least a portion of the surface of the second conductive portion 201, it falls within the protection scope of this disclosure.

[0053] In some embodiments, the first semiconductor structure 100 further includes a first substrate 113 and a first insulating layer 114, a first interconnect layer 111 is located on the first substrate 113, the first insulating layer 114 covers the first interconnect layer 111 and the first substrate 113, the first insulating layer 114 has a first opening that exposes the first interconnect layer 111, and a first bonding layer 112 is disposed in the first opening; the second semiconductor structure 200 further includes a second substrate 213 and a second insulating layer 214, the second interconnect layer 211 is located on the second substrate 213, the second insulating layer 214 covers the second interconnect layer 211 and the second substrate 213, the second insulating layer 214 has a second opening that exposes the second interconnect layer 211, and a second bonding layer 212 is disposed in the second opening.

[0054] In some embodiments, the method of forming a first semiconductor structure 100 includes: providing a first substrate 113, forming a first interconnect film on the first substrate 113, and then patterning the first interconnect film to form a first interconnect layer 111; then forming a first insulating layer 114 covering the first interconnect layer 111 and the first substrate 113; patterning the first insulating layer 114 to form a first opening in the first insulating layer 114, and forming a first bonding layer 112 in the first opening. Correspondingly, the method of forming a second semiconductor structure 200 includes: providing a second substrate 213, forming a second interconnect film on the second substrate 213, and then patterning the second interconnect film to form a second interconnect layer 211; then forming a second insulating layer 214 covering the second interconnect layer 211 and the second substrate 213; patterning the second insulating layer 214 to form a second opening in the second insulating layer 214, and forming a second bonding layer 212 in the second opening.

[0055] In some embodiments, at least one of the first semiconductor structure 100 and the second semiconductor structure 200 is provided with an opening for exposing a corresponding test pad 300, so that when the test structure 10 needs to be tested, the test probe can contact the test pad 300 at the opening.

[0056] In some embodiments, the bonding test structure 10 further includes a metal portion 400 for filling the opening and being electrically connected to the test pad 300 to bring the interface of the test pad 300 out to the surface of the bonding test structure 10 so as to perform tests on the bonding test structure 10.

[0057] In some embodiments, the first substrate 113 and the second substrate 213 are formed based on semiconductor materials, the first insulating layer 114 and the second insulating layer 214 are formed based on insulating materials, and the first interconnect layer 111, the second interconnect layer 211, the first bonding layer 112 and the second bonding layer 212 are formed based on conductive materials.

[0058] refer to Figures 4-8 , Figure 4 This is a schematic diagram of the upper projection of the second bonding surface under the calibration bonding site provided in this embodiment. Figures 5-8 The above projection of the second bonding surface when the bonding error is large is provided in the example.

[0059] In some embodiments, the second bonding layer 212 has a first projection projected onto the second bonding surface B, and the second interconnect layer 211 has a second projection projected onto the second bonding surface B. The first projection is centrally symmetrically arranged based on the second projection.

[0060] refer to Figure 4Since the first projection is centrally symmetrically arranged based on the second projection, if the bonding error between the first semiconductor structure 100 and the second semiconductor structure 200 is less than the preset alignment error, if there is a bonding error to the left, the overlapping area on the left increases and the overlapping area on the right decreases, the overall overlapping area of ​​the first conductive part 101 and the second conductive part 201 does not change much, and the electrical parameters between the test pads 300 on both sides do not change much; if there is a bonding error to the right, the overlapping area on the right increases and the overlapping area on the left decreases, the overall overlapping area of ​​the first conductive part 101 and the second conductive part 201 does not change much, and the electrical parameters between the test pads 300 on both sides do not change much; if there is an upward bonding error, the overlapping area on the left increases and the overlapping area on the right decreases, the overall overlapping area of ​​the first conductive part 101 and the second conductive part 201 does not change much, and the electrical parameters between the test pads 300 on both sides do not change much; if there is a downward bonding error, the overlapping area on the right increases and the overlapping area on the left decreases, the overall overlapping area of ​​the first conductive part 101 and the second conductive part 201 does not change much, and the electrical parameters between the test pads 300 on both sides do not change much. As can be seen from the above discussion, since the first projection is centrally symmetrically set based on the second projection, if the bonding error between the first semiconductor structure 100 and the second semiconductor structure 200 is less than the preset alignment error, the change in electrical parameters between the test pads 300 on both sides is not significant, thereby improving the accuracy of the judgment between the bonding error and the preset alignment error.

[0061] In one example, refer to Figure 5 If the bonding error to the left between the first semiconductor structure 100 and the second semiconductor structure 200 is greater than the preset alignment error, the first projection and the second projection will shift to the left by at least X. At this time, the overlapping area on the right side becomes 0, and the electrical parameters between the test pads 300 on both sides will change abruptly.

[0062] In one example, refer to Figure 6 If the bonding error to the right between the first semiconductor structure 100 and the second semiconductor structure 200 is greater than the preset alignment error, the first projection and the second projection will shift to the right by at least X. At this time, the overlapping area on the left side becomes 0, and the electrical parameters between the test pads 300 on both sides will change abruptly.

[0063] In one example, refer to Figure 7 If the downward bonding error between the first semiconductor structure 100 and the second semiconductor structure 200 is greater than the preset alignment error, the first projection and the second projection will shift down by at least Y. At this time, the overlapping area on the left side becomes 0, and the electrical parameters between the test pads 300 on both sides will change abruptly.

[0064] In one example, refer to Figure 8If the upward bonding error between the first semiconductor structure 100 and the second semiconductor structure 200 is greater than the preset alignment error, the first projection and the second projection will shift upward by at least Y. At this time, the overlapping area on the right side becomes 0, and the electrical parameters between the test pads 300 on both sides will change abruptly.

[0065] Based on the above discussion, it can be seen that the symmetrical first projection and the symmetrical setting of the second projection center make the test effect of the alignment accuracy error on both sides in the same direction the same. In the process of judging the bonding error and the preset alignment error, it is only necessary to judge whether there is a sudden change in the electrical parameters between the test pads 300 on both sides. The test results are obvious and accurate.

[0066] In some embodiments, the first bonding layer 112 has a third projection that is projected onto the second bonding surface B. When the second semiconductor structure 200 and the first semiconductor structure 100 are at a standard bonding site, the first projection and the third projection have an overlapping area, and the overlapping area is centrally symmetrically arranged based on the second projection, so as to further improve the obviousness and accuracy of the test results.

[0067] It should be noted that since the first bonding surface A and the second bonding surface B are mutually bonding surfaces, the second bonding surface B and the first bonding surface A can be regarded as the same surface after bonding. Those skilled in the art can replace the second bonding surface B based on the first bonding surface A.

[0068] As described above, the first semiconductor structure 100 and the second semiconductor structure 200, which are bonded together, are provided with multiple bonding test structures 10 as described above. Different bonding test structures 10 have different misaligned contact areas at standard bonding sites, thereby determining whether the bonding accuracy between the first semiconductor structure 100 and the second semiconductor structure 200 exceeds different preset values, thus obtaining more accurate bonding accuracy. In this scenario, the overlapping area sizes corresponding to different test pads are different.

[0069] In some embodiments, the sizes of the overlapping areas corresponding to different test pads are set in a gradient, thereby accurately obtaining the bonding accuracy between the first semiconductor structure 100 and the second semiconductor structure 200 based on the preset value of the gradient setting.

[0070] In some embodiments, the shape of the first projection and the shape of the third projection are the same, as can be referenced. Figures 4-8 Example. In other embodiments, the shapes of the first projection and the third projection may also be set to different shapes; for example, the first projection may be a circle and the third projection may be a square; or, for example, the first projection may be a square and the third projection may be a regular hexagon.

[0071] In some embodiments, the size of the first projection and the size of the third projection are the same, as can be referenced. Figures 4-8Example. In other embodiments, the dimensions of the first projection and the third projection may also be set to different dimensions; for example, the size of the first projection may be set to be larger than the size of the third projection; or, for another example, the size of the third projection may be set to be larger than the size of the first projection.

[0072] In some embodiments, when the second semiconductor structure 200 and the first semiconductor structure 100 are at standard bonding sites, the overlapping areas on both sides of the second projection have the same shape and size, which can be referenced. Figures 4-8 Example. In other embodiments, the shape or size of the overlapping areas on both sides of the second projection can be set to the same or different styles. For example, the shape of the overlapping areas on both sides of the second projection can be a circle on one side and a square on the other; or the size of the overlapping areas on both sides of the second projection can be set to have slight differences on both sides, etc.

[0073] It should be noted that the specific shapes and sizes of the first projection, the second projection, and the third projection, as well as the shapes and sizes of the overlapping areas, can be adjusted by those skilled in the art based on the above discussion. However, as long as there is a test structure in which at least a portion of the surface of the second conductive part 201 is in misaligned contact with at least a portion of the surface of the second conductive part 201, it falls within the protection scope of this disclosure.

[0074] The bonding test structure provided in this embodiment achieves the setting of a preset alignment deviation by setting the first conductive part and the second conductive part to be misaligned under the standard bonding position. Then, by testing the test parameters between the test pads, it is determined whether a path is formed between the first conductive part and the second conductive part to determine the relationship between the bonding deviation between the first semiconductor structure and the second semiconductor structure and the preset alignment deviation, thereby determining whether the bonding accuracy between the first semiconductor structure and the second semiconductor structure exceeds the preset value.

[0075] It should be noted that, without conflict, the features disclosed in the bonding test structure 10 provided in the above embodiments can be randomly combined to obtain new embodiments of the bonding test structure 10.

[0076] Another embodiment of this disclosure also provides a testing method that can quickly and effectively monitor the hybrid bonding accuracy of the entire wafer by testing the bonding test structure during the wafer acceptance test (WAT) stage.

[0077] Specifically, the testing method is applied to the bonding test structure provided in the above embodiments. The testing method includes: performing typical tests on the test structure to obtain the electrical parameters of the test pads in the bonding test structure; and determining whether the semiconductor structure corresponding to the bonding test structure is aligned based on the electrical parameters of the test pads.

[0078] Among them, the electrical parameters can be the resistance value between the two test pads, whether current flows through them, and the magnitude of the voltage value at both ends.

[0079] When the bonding between the first semiconductor structure and the second semiconductor structure is "successful", the first conductive part and the second conductive part are electrically connected, and a conductive path is formed between the two test pads; when the bonding between the first semiconductor structure and the second semiconductor structure is "failed", the first conductive part and the second conductive part are disconnected, and a conductive path cannot be formed between the two test pads.

[0080] Specifically, whether the bonding between the first and second semiconductor structures is "successful" or "failed" can be determined by whether a conductive path is formed between the two test pads. The formation of a conductive path between the two test pads can be determined by obtaining the electrical parameters of the test pads.

[0081] By setting the first and second conductive parts to be misaligned under the standard bonding position, the preset alignment deviation is achieved. Then, by testing the test parameters between the test pads, it is determined whether a path is formed between the first and second conductive parts, thereby determining the relationship between the bonding deviation between the first and second semiconductor structures and the preset alignment deviation, and thus determining whether the bonding accuracy between the first and second semiconductor structures exceeds the preset value.

[0082] In some embodiments, the number of bonding test structures is multiple, and the size of the overlapping area corresponding to the test pads in different bonding test structures is different; the test method further includes: obtaining the alignment accuracy of the semiconductor structure corresponding to the bonding test structure based on the electrical parameters of different test pads.

[0083] The first and second semiconductor structures bonded together are provided with multiple bonding test structures as described above, and the misalignment contact area of ​​different bonding test structures under the standard bonding site is different, thereby determining whether the bonding accuracy between the first semiconductor structure and the second semiconductor structure exceeds different preset values.

[0084] The areas of misaligned contact of different bonding test structures under standard bonding sites are set in a gradient manner, thereby accurately obtaining the bonding accuracy between the first semiconductor structure and the second semiconductor structure based on the preset value of the gradient setting.

[0085] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the detailed descriptions of other embodiments above, which will not be repeated here.

[0086] The basic concepts have been described above. It is obvious that the detailed disclosure above is merely illustrative and does not constitute a limitation of this disclosure. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to this disclosure by those skilled in the art. Such modifications, improvements, and corrections are suggested in this disclosure and therefore remain within the spirit and scope of the exemplary embodiments of this disclosure.

[0087] The bonding test structure and test method provided by the embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A bonding test structure, characterized in that, include: A first semiconductor structure having a first bonding surface, and having a plurality of mutually discrete first conductive portions therein, the first conductive portions being exposed to the first bonding surface of the first semiconductor structure. A second semiconductor structure is bonded to the first semiconductor structure. The second semiconductor structure has a second bonding surface, and the second bonding surface is bonded to the first bonding surface. The second semiconductor structure has a second conductive portion, which is exposed to the second bonding surface. When the second semiconductor structure and the first semiconductor structure are at a standard bonding site, at least a portion of the surface of the second conductive portion is in misaligned contact with at least a portion of the surface of the first conductive portion. Two separate test pads located within the first semiconductor structure are electrically connected through the first conductive portion and the second conductive portion when the second semiconductor structure and the first semiconductor structure are in a standard bonding position.

2. The bonding test structure according to claim 1, characterized in that, The first conductive portion includes: a first bonding layer and a first interconnect layer located within the first semiconductor structure, the first bonding surface exposing the first bonding layer, and the first interconnect layer electrically connecting the first bonding layer to a corresponding test pad; The second conductive portion includes: a second bonding layer and a second interconnect layer located separately within the second semiconductor structure, the second bonding surface exposing the second bonding layer, and the second interconnect layer electrically connecting the second bonding layers.

3. The bonding test structure according to claim 2, characterized in that, The first semiconductor structure further includes a first substrate and a first insulating layer, the first interconnect layer is located on the first substrate, the first insulating layer covers the first interconnect layer and the first substrate, the first insulating layer has a first opening, the first opening exposes the first interconnect layer, and the first bonding layer is disposed in the first opening; The second semiconductor structure further includes a second substrate and a second insulating layer, the second interconnect layer is located on the second substrate, the second insulating layer covers the second interconnect layer and the second substrate, the second insulating layer has a second opening, the second opening exposes the second interconnect layer, and the second bonding layer is disposed in the second opening.

4. The bonding test structure according to claim 2, characterized in that, include: The second bonding layer has a first projection projected onto the second bonding surface; The second interconnect layer has a second projection projected onto the second bonding surface; The first projection is centrally symmetrically arranged based on the second projection.

5. The bonding test structure according to claim 4, characterized in that, include: The first bonding layer has a third projection projected onto the second bonding surface; When the second semiconductor structure and the first semiconductor structure are at standard bonding sites, the first projection and the third projection have an overlapping area, and the overlapping area is centrally symmetrically arranged based on the second projection.

6. The bonding test structure according to claim 5, characterized in that, The size of the overlapping area corresponding to different test pads is different.

7. The bonding test structure according to claim 5 or 6, characterized in that, The shape of the first projection is the same as the shape of the third projection, and the size of the first projection is the same as the size of the third projection.

8. The bonding test structure according to any one of claims 7, characterized in that, When the second semiconductor structure and the first semiconductor structure are at a standard bonding site, the overlapping areas on both sides of the second projection have the same shape and the same size.

9. A testing method, characterized in that, include: Provide several bonding test structures as described in any one of claims 1 to 8; Electrical tests are performed on the bonding test structure to obtain the electrical parameters of the test pads in the bonding test structure; Based on the electrical parameters of the test pads, it is determined whether the semiconductor structure corresponding to the bonding test structure is aligned.

10. The test method according to claim 9, characterized in that, include: The number of bonding test structures is multiple, and the size of the overlapping area corresponding to the test pads in different bonding test structures is different; The testing method further includes: obtaining the alignment accuracy of the semiconductor structure corresponding to the bonding test structure based on the electrical parameters of different test pads.

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