Semiconductor device and manufacturing method thereof
By planarizing the isolation material layer in the shallow trench isolation structure and making the oxide layer flush with the surface of the isolation material layer, the performance degradation caused by the edge trench is solved, and the electrical isolation effect and reliability of the device are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-04-16
- Publication Date
- 2026-05-12
AI Technical Summary
During the fabrication of shallow trench isolation structures, the presence of side trenches leads to a decrease in device performance, affecting electrical isolation and reliability. Moreover, the problem becomes more pronounced as the process technology advances.
By planarizing the remaining thickness of the isolation material layer on the nitride layer, and making the upper surface of the oxide layer flush with the upper surface of the isolation material layer in the shallow trench after removing the nitride layer, over-etching is avoided, forming a flat surface and thus preventing the formation of side trenches.
This improves device performance, prevents uneven thin film deposition and enhanced electric field caused by edge trenches, reduces subthreshold leakage current and breakdown risk, and enhances the long-term reliability of the device.
Smart Images
Figure CN122028718A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] In integrated circuit fabrication, shallow trench isolation (STI) structures have gradually replaced local field oxidation (RTO) and become the mainstream isolation technology due to their advantages such as flattened surfaces and smaller isolation dimensions.
[0003] In the fabrication of shallow trench isolation structures, an oxide layer and a nitride layer are first formed on a substrate. The nitride layer, oxide layer, and substrate are then etched to form shallow trenches. Next, an isolation material is formed, filling the shallow trenches and covering the nitride layer. The isolation material is then planarized to expose the nitride layer, and finally, the nitride and oxide layers are removed. However, during the oxide layer removal process, divots are typically formed at the top edge of the shallow trench isolation structure, leading to uneven subsequent thin film deposition and affecting device performance. Furthermore, with the advancement of advanced process nodes, the sensitivity to divots becomes increasingly pronounced. Summary of the Invention
[0004] The purpose of this invention is to provide a semiconductor device and its manufacturing method, which can avoid the generation of edge slots and improve device performance.
[0005] To address the aforementioned technical problems, according to a first aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising the following steps:
[0006] A substrate is provided, an oxide layer and a nitride layer are formed on the substrate, the nitride layer, the oxide layer and a portion of the substrate are etched to form shallow trenches, and an isolation material layer is formed that fills the shallow trenches and covers the nitride layer.
[0007] Planarize the insulating material layer to the remaining thickness of the insulating material layer on the nitride layer;
[0008] Remove the remaining insulating material layer and the nitride layer from the nitride layer so that the upper surface of the oxide layer is flush with the upper surface of the insulating material layer within the shallow trench; and
[0009] Remove the oxide layer and the insulating material layer flush with the oxide layer in the shallow trench to form a shallow trench isolation structure.
[0010] Optionally, the isolation material layer can be planarized using a chemical mechanical polishing process or a wet etching process.
[0011] Optionally, after planarization, the thickness of the remaining insulating material layer on the nitride layer is 200 Å to 500 Å.
[0012] Optionally, a dry etching process can be used to remove the remaining isolation material layer and the nitride layer on the nitride layer.
[0013] Optionally, in the dry etching process, the etching ratio of the isolation material layer to the nitride layer is 1:1.
[0014] Optionally, a wet etching process can be used to remove the oxide layer and the isolation material layer flush with the oxide layer in the shallow trench.
[0015] Optionally, the etching solution used in the wet etching process includes diluted hydrofluoric acid.
[0016] Optionally, before forming the oxide layer on the substrate, the method further includes: forming a barrier layer on the substrate, wherein the oxide layer is formed on the barrier layer;
[0017] After removing the oxide layer, the process further includes removing the barrier layer.
[0018] Optionally, the barrier layer may be made of spin-coated carbon; the barrier layer may be removed using oxygen plasma.
[0019] To solve the above-mentioned technical problems, according to a second aspect of the present invention, a semiconductor device is provided, which is manufactured using the semiconductor device manufacturing method described above.
[0020] In summary, the semiconductor device and its fabrication method provided by the present invention firstly provide a substrate, on which an oxide layer and a nitride layer are formed. The nitride layer, the oxide layer, and a portion of the substrate thickness are etched to form a shallow trench, forming an isolation material layer that fills the shallow trench and covers the nitride layer. Then, the isolation material layer is planarized to the remaining thickness of the isolation material layer on the nitride layer. Next, the remaining isolation material layer and the nitride layer on the nitride layer are removed so that the upper surface of the oxide layer is flush with the upper surface of the isolation material layer in the shallow trench. Finally, the oxide layer and the isolation material layer flush with the oxide layer in the shallow trench are removed to form a shallow trench isolation structure. An unexpected effect of this invention is that by planarizing the isolation material layer to the remaining thickness of the isolation material layer on the nitride layer, and then removing the remaining isolation material layer and the nitride layer on the nitride layer, the upper surface of the exposed oxide layer is flush with the upper surface of the isolation material layer in the shallow trench. That is, after removing the nitride layer, the substrate has a flat surface. When the oxide layer is removed, the flat surface can avoid excessive etching of the edges of the isolation material layer in the shallow trench, and avoid the formation of side trenches at the top edge of the shallow trench isolation structure, thereby improving device performance.
[0021] Furthermore, a barrier layer is first formed on the substrate before the oxide layer is formed. Even if a trench is generated during the etching process to remove the oxide layer, the presence of the barrier layer ensures that the position of the trench is higher than the surface of the substrate, thereby avoiding any impact on device performance. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of the structure after the formation of the insulating material layer, as provided in one embodiment.
[0023] Figure 2 This is a schematic diagram of the structure after planarizing the isolation material layer, as provided in one embodiment.
[0024] Figure 3 This is a schematic diagram of the structure after the nitride layer has been removed, as provided in one embodiment.
[0025] Figure 4 This is a schematic diagram of the structure after the oxide layer has been removed, as provided in one embodiment.
[0026] Figure 5 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.
[0027] Figure 6 This is a schematic diagram of the structure after the formation of the isolation material layer according to an embodiment of the present invention.
[0028] Figure 7 This is a schematic diagram of the structure after planarization of the isolation material layer according to an embodiment of the present invention.
[0029] Figure 8 This is a schematic diagram of the structure after the nitride layer has been removed, according to an embodiment of the present invention.
[0030] Figure 9 This is a schematic diagram of the structure after removing the oxide layer according to an embodiment of the present invention.
[0031] Explanation of reference numerals in the attached figures:
[0032] 10-Substrate; 11-Oxide layer; 12-Nitride layer; 13-Shallow trench; 14-Isolation material layer; 15-Shallow trench isolation structure; 16-Side trench. Detailed Implementation
[0033] Figures 1 to 4 This is a schematic diagram illustrating the steps of a semiconductor device fabrication method according to an embodiment. Please refer to... Figure 1 As shown, a substrate 10 is first provided, and an oxide layer 11 and a nitride layer 12 are formed on the substrate 10. The oxide layer 11 is, for example, a silicon oxide layer, and the nitride layer 12 is, for example, a silicon nitride layer. Then, the nitride layer 12, the oxide layer 11, and a portion of the thickness of the substrate 10 are etched to form a shallow trench 13. Next, an isolation material layer 14 is formed, which fills the shallow trench 13 and covers the nitride layer 12. The material of the isolation material layer 14 is, for example, silicon oxide.
[0034] Please refer to Figure 2 As shown, the isolation material layer 14 is planarized to expose the nitride layer 12, for example by chemical mechanical polishing. Since the isolation material layer 14 above the nitride layer 12 needs to be completely removed, over-polishing is required, which causes the upper surface of the isolation material layer 14 in the shallow trench 13 to be recessed inward.
[0035] Please refer to Figure 2 and Figure 3 As shown, the nitride layer 12 is removed, exposing the oxide layer 11. The nitride layer 12 is typically removed using a wet etching process, for example, by using thermal phosphoric acid.
[0036] Please refer to Figure 3 and Figure 4 As shown, the oxide layer 11 is removed, forming a shallow trench isolation structure 15 within the substrate 10. The oxide layer 11 is typically removed using a wet etching process, for example, by using a hydrofluoric acid solution.
[0037] However, while the etching solution removes the oxide layer 11, it also etches the isolation material layer 14. Since the upper surface of the isolation material layer 14 in the shallow trench 13 is higher than the upper surface of the oxide layer 11, the etching solution will etch the isolation material layer 14 from the exposed sidewalls around it, causing the isolation material layer 14 to be over-etched. This results in the formation of a side groove 16 at the top edge of the shallow trench isolation structure 15, i.e., a depression is formed at the junction of the substrate 10 and the shallow trench isolation structure 15.
[0038] The presence of the edge trench 16 can lead to uneven subsequent thin film deposition, affecting device performance. For example, it can cause the trench depth of the shallow trench isolation structure 15 to become shallower, weakening the electrical isolation effect between adjacent devices and potentially forming parasitic conductive channels, resulting in a significant increase in the subthreshold leakage current (Ioff) of adjacent devices. Furthermore, the sharp morphology at the edge trench 16 may cause localized enhancement of the electric field (similar to tip discharge), accelerating dielectric layer breakdown, leading to a decrease in breakdown voltage. This makes the device more susceptible to failure in high-voltage applications, increasing long-term reliability risks. The presence of the edge trench 16 may also lead to other risks, such as uneven gate oxide layer formation, parasitic transistor effects, abnormal source / drain expansion regions, and short circuits in contact holes.
[0039] To address the aforementioned problems, this invention provides a semiconductor device and its fabrication method. An unexpected advantage is that by planarizing the isolation material layer to the remaining thickness of the isolation material layer on top of the nitride layer, and then removing the remaining isolation material layer and the nitride layer on top of the nitride layer, the upper surface of the exposed oxide layer is flush with the upper surface of the isolation material layer within the shallow trench. That is, after removing the nitride layer, the substrate has a flat surface. When removing the oxide layer, the flat surface prevents excessive etching of the edges of the isolation material layer within the shallow trench, avoiding the formation of edge trenches at the top edge of the shallow trench isolation structure, thereby improving device performance.
[0040] Specifically, the present invention provides a method for fabricating a semiconductor device, comprising the following steps: providing a substrate, forming an oxide layer and a nitride layer on the substrate, etching the nitride layer, the oxide layer, and a portion of the substrate thickness to form a shallow trench, forming an isolation material layer that fills the shallow trench and covers the nitride layer; planarizing the isolation material layer to the remaining thickness of the isolation material layer on the nitride layer; removing the remaining isolation material layer and the nitride layer on the nitride layer such that the upper surface of the oxide layer is flush with the upper surface of the isolation material layer in the shallow trench; and removing the oxide layer and the isolation material layer flush with the oxide layer in the shallow trench to form a shallow trench isolation structure.
[0041] Accordingly, the present invention provides a semiconductor device manufactured using the semiconductor device manufacturing method described above.
[0042] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0043] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.
[0044] Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Please refer to it. Figure 5 As shown, the method for fabricating a semiconductor device provided in this embodiment of the invention includes the following steps:
[0045] S1: Provide a substrate, form an oxide layer and a nitride layer on the substrate, etch the nitride layer, the oxide layer and a portion of the substrate to form shallow trenches, and form an isolation material layer that fills the shallow trenches and covers the nitride layer;
[0046] S2: Planarize the insulating material layer to the remaining thickness of the insulating material layer on the nitride layer;
[0047] S3: Remove the remaining insulating material layer and the nitride layer from the nitride layer so that the upper surface of the oxide layer is flush with the upper surface of the insulating material layer within the shallow trench; and
[0048] S4: Remove the oxide layer and the isolation material layer flush with the oxide layer in the shallow trench to form a shallow trench isolation structure.
[0049] Figures 6 to 9 This is a schematic diagram illustrating the structural steps of a semiconductor device fabrication method according to an embodiment of the present invention. Next, we will combine... Figure 5 and Figures 6 to 9 The method for fabricating the semiconductor device provided in the embodiments of the present invention will be described in detail.
[0050] In step S1, please refer to Figure 6 As shown, a substrate 10 is provided, an oxide layer 11 and a nitride layer 12 are formed on the substrate 10, the nitride layer 12, the oxide layer 11 and a portion of the thickness of the substrate 10 are etched to form a shallow trench 13, and an isolation material layer 14 is formed to fill the shallow trench 13 and cover the nitride layer 12.
[0051] The substrate 10 can be made of silicon, germanium, germanium-silicon, silicon carbide, gallium arsenide, or indium gallium arsenide, or it can be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 10 is preferably made of silicon.
[0052] Please refer to Figure 6 As shown, an oxide layer 11 and a nitride layer 12 are first formed on the substrate 10.
[0053] The oxide layer 11 is made of, but is not limited to, silicon oxide, and can be formed by any suitable process such as thermal oxidation, chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
[0054] The material of the nitride layer 12 includes, but is not limited to, silicon nitride. The nitride layer 12 can be formed using any suitable process, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
[0055] The oxide layer 11 is used to repair defects on the surface of the substrate 10, improve the adhesion between the nitride layer 12 and the substrate 10, and prevent the nitride layer 12 from peeling off from the substrate 10 due to poor adhesion. Additionally, the nitride layer 12 has stress; when the material of the nitride layer 12 is silicon nitride, the oxide layer 11 acts as an isolation layer between the nitride layer 12 and the substrate 10 to prevent the stress in the nitride layer 12 from affecting the substrate 10. The nitride layer 12 can also serve as a mask layer for subsequent shallow trench formation and as a polishing stop layer during chemical mechanical polishing.
[0056] Next, a photoresist layer is formed on the nitride layer 12. The photoresist layer is exposed and developed to form a patterned photoresist layer. The patterned photoresist layer is used as a mask to etch the nitride layer 12, the oxide layer 11 and the substrate 10 to form a shallow trench 13 that penetrates the nitride layer 12 and the oxide layer 11 and extends into the substrate 10. Then the patterned photoresist layer is removed.
[0057] Then, an insulating material layer 14 is formed, which fills the shallow trench 13 and covers the nitride layer 12, forming a structure as shown in the figure. Figure 6 The structure is shown. Of course, since the insulating material layer 14 fills the shallow trench 13, the insulating material layer 14 above the shallow trench 13 has a downwardly recessed surface.
[0058] In this embodiment, the isolation material layer 14 can be formed using HARP (High Aspect Ratio Process), and the material of the isolation material layer 14 includes, but is not limited to, silicon oxide.
[0059] In one embodiment of the present invention, the thickness of the nitride layer 12 is 800 Å to 1000 Å, the thickness of the oxide layer 11 is 100 Å to 130 Å, the depth of the shallow trench 13 is 2600 Å to 2800 Å, and the thickness of the insulating material layer 14 is 4000 Å to 7000 Å (wherein the thickness of the insulating material layer 14 refers to the thickness of the deposited insulating material layer 14, which is the thickness from the bottom of the shallow trench 13 to the top of the insulating material layer 14), and the upper surface of the insulating material layer 14 is much higher than the upper surface of the nitride layer 12. Of course, the thickness of each material layer is not limited to these values.
[0060] In step S2, please refer to Figure 7 As shown, the insulating material layer 14 is planarized to the remaining thickness of the insulating material layer 14 on the nitride layer 12.
[0061] In one embodiment of the present invention, a chemical mechanical polishing process is used to planarize the isolation material layer 14. In another embodiment of the present invention, a wet etching process is used to planarize the isolation material layer 14, for example, using a hydrofluoric acid solution.
[0062] In this embodiment, the isolation material layer 14 is planarized to the remaining thickness of the nitride layer 12. Since the planarization is performed on the same material (isolation material layer 14), the nitride layer 12 is not exposed. Therefore, the isolation material layer 14 has a flat surface.
[0063] In one embodiment of the present invention, after planarization, the thickness of the remaining insulating material layer 14 on the nitride layer 12 is 200 Å to 500 Å, but it is not limited to this. If the remaining insulating material layer 14 on the nitride layer 12 is relatively thick, it will increase the time spent on removing the remaining insulating material layer 14, thereby increasing the process time. If the remaining insulating material layer 14 on the nitride layer 12 is relatively thin, it will be difficult to form a smooth surface after planarization. The thickness of the remaining insulating material layer 14 on the nitride layer 12 can be determined according to the actual process and actual requirements.
[0064] In step S3, please refer to Figure 8 As shown, the remaining insulating material layer 14 and the nitride layer 12 on the nitride layer 12 are removed so that the upper surface of the oxide layer 11 is flush with the upper surface of the insulating material layer 14 in the shallow trench 13.
[0065] In this embodiment, the remaining insulating material layer 14 on the nitride layer 12 and the insulating material layer 14 at the top of the shallow trench 13 are first removed. That is, the thickness of the insulating material layer 14 removed in different areas is the same. The insulating material layer 14 is removed downward from the upper surface of the insulating material layer 14 until the insulating material layer 14 on the nitride layer 12 is removed. The remaining nitride layer 12 and the insulating material layer 14 in the shallow trench 13 form a flat surface. Then, the nitride layer 12 and the insulating material layer 14 are removed until the nitride layer 12 is removed, exposing the oxide layer 11. At the same time, the insulating material layer 14 above the shallow trench 13 (the insulating material layer 14 located between adjacent oxide layers 11) is also removed. The upper surface of the oxide layer 11 is flush with the upper surface of the remaining insulating material layer 14 in the shallow trench 13.
[0066] In other words, while removing the insulating material layer 14 on the nitride layer 12, the flush insulating material layer 14 in the shallow trench 13 is also removed, and while removing the nitride layer 12, the flush insulating material layer 14 in the shallow trench 13 is also removed, so that the upper surface of the exposed oxide layer 11 is flush with the upper surface of the insulating material layer 14 in the shallow trench 13.
[0067] In one embodiment of the present invention, a dry etching process is used to remove the remaining isolation material layer 14 and the nitride layer 12 on the nitride layer 12. Preferably, the etching selectivity ratio of the isolation material layer 14 to the nitride layer 12 is 1:1, so that the isolation material layer 14 is etched away at the same etching rate as the nitride layer 12, thereby making the upper surface of the exposed oxide layer 11 flush with the upper surface of the isolation material layer 14 in the shallow trench 13.
[0068] In one embodiment, carbon- and fluorine-containing gases can be used to etch the insulating material layer 14 and the nitride layer 12.
[0069] In one embodiment, endpoint detection (EPD) can be used to detect the attenuation of the nitrogen signal to ensure that the nitride layer 12 is completely removed.
[0070] In step S4, please refer to Figure 9 As shown, the oxide layer 11 and the isolation material layer 14 flush with the oxide layer 11 in the shallow trench 13 are removed to form a shallow trench isolation structure 15.
[0071] In this embodiment, a wet etching process is used to remove the oxide layer 11 and the isolation material layer 14 flush with the oxide layer 11 within the shallow trench 13. For example, a diluted hydrofluoric acid (DHF) solution can be used to etch the oxide layer 11 and the isolation material layer 14. Low concentrations of hydrofluoric acid can effectively control the etching rate and ensure etching accuracy.
[0072] Since the oxide layer 11 and the isolation material layer 14 are of the same height, when using the wet etching process, the etching solution is etched from the top of the material. Therefore, it is possible to avoid over-etching of the edge of the isolation material layer 14 in the shallow trench 13 and to avoid the formation of side trenches at the top edge of the shallow trench isolation structure 15, thereby improving device performance.
[0073] In the semiconductor device fabrication method provided by the present invention, a substrate 10 is first provided, an oxide layer 11 and a nitride layer 12 are formed on the substrate 10, the nitride layer 12, the oxide layer 11 and a portion of the thickness of the substrate 10 are etched to form a shallow trench 13, an isolation material layer 14 is formed that fills the shallow trench 13 and covers the nitride layer 12, then the isolation material layer 14 is planarized to the remaining thickness of the isolation material layer 14 on the nitride layer 12, then the remaining isolation material layer 14 and the nitride layer 12 on the nitride layer 12 are removed so that the upper surface of the oxide layer 11 is flush with the upper surface of the isolation material layer 14 in the shallow trench 13, and then the oxide layer 11 and the isolation material layer 14 flush with the oxide layer 11 in the shallow trench 13 are removed to form a shallow trench isolation structure 15.
[0074] An unexpected effect of this invention is that by planarizing the isolation material layer 14 to the remaining thickness of the isolation material layer 14 on the nitride layer 12, and then removing the remaining isolation material layer 14 and the nitride layer 12 on the nitride layer 12, the upper surface of the exposed oxide layer 11 is flush with the upper surface of the isolation material layer 14 in the shallow trench 13. That is, after removing the nitride layer 12, the substrate 10 has a flat surface. When the oxide layer 11 is then removed, the flat surface can avoid over-etching the edges of the isolation material layer 14 in the shallow trench 13, and avoid forming a side trench at the top edge of the shallow trench isolation structure 15, thereby improving device performance.
[0075] In one embodiment of the present invention, a barrier layer (not shown) may be formed on the substrate 10 before the oxide layer 11 is formed, and the oxide layer 11 is formed on the barrier layer. The process further includes removing the barrier layer after removing the oxide layer 11.
[0076] In one embodiment, the barrier layer is made of spin-coated carbon (SOC), which can be subsequently removed using oxygen plasma. The oxygen plasma reacts chemically with the carbon to generate volatile products, thereby removing the barrier layer. This ensures a high selectivity for the substrate 10, resulting in a smooth surface for the shallow trench isolation structure 15.
[0077] In another embodiment, the barrier layer is made of silicon nitride and can be subsequently removed by dry etching or wet etching. For example, the barrier layer can be removed by wet etching, and the etching solution may contain thermal phosphoric acid.
[0078] The isolation material layer 14 within the shallow trench 13 is not etched during the removal of the barrier layer. After the barrier layer is removed, the upper surface of the shallow trench isolation structure 15 is higher than the upper surface of the substrate 10. Even if side trenches are generated within the shallow trench isolation structure 15 during the etching process to remove the oxide layer 11, the presence of the barrier layer ensures that the position of the side trenches is higher than the surface of the substrate 10, thereby avoiding any impact on device performance.
[0079] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.
[0080] In summary, the semiconductor device and its fabrication method provided by the present invention firstly provide a substrate, on which an oxide layer and a nitride layer are formed. The nitride layer, the oxide layer, and a portion of the substrate thickness are etched to form a shallow trench, forming an isolation material layer that fills the shallow trench and covers the nitride layer. Then, the isolation material layer is planarized to the remaining thickness of the isolation material layer on the nitride layer. Next, the remaining isolation material layer and the nitride layer on the nitride layer are removed so that the upper surface of the oxide layer is flush with the upper surface of the isolation material layer in the shallow trench. Finally, the oxide layer and the isolation material layer flush with the oxide layer in the shallow trench are removed to form a shallow trench isolation structure. An unexpected effect of this invention is that by planarizing the isolation material layer to the remaining thickness of the isolation material layer on the nitride layer, and then removing the remaining isolation material layer and the nitride layer on the nitride layer, the upper surface of the exposed oxide layer is flush with the upper surface of the isolation material layer in the shallow trench. That is, after removing the nitride layer, the substrate has a flat surface. When the oxide layer is removed, the flat surface can avoid excessive etching of the edges of the isolation material layer in the shallow trench, and avoid the formation of side trenches at the top edge of the shallow trench isolation structure, thereby improving device performance.
[0081] Furthermore, a barrier layer is first formed on the substrate before the oxide layer is formed. Even if a trench is generated during the etching process to remove the oxide layer, the presence of the barrier layer ensures that the position of the trench is higher than the surface of the substrate, thereby avoiding any impact on device performance.
[0082] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, an oxide layer and a nitride layer are formed on the substrate, the nitride layer, the oxide layer and a portion of the substrate are etched to form shallow trenches, and an isolation material layer is formed that fills the shallow trenches and covers the nitride layer. Planarize the insulating material layer to the remaining thickness of the insulating material layer on the nitride layer; Remove the remaining insulating material layer and the nitride layer from the nitride layer so that the upper surface of the oxide layer is flush with the upper surface of the insulating material layer in the shallow trench; as well as Remove the oxide layer and the insulating material layer flush with the oxide layer in the shallow trench to form a shallow trench isolation structure.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The isolation material layer is planarized using a chemical mechanical polishing process or a wet etching process.
3. The method for fabricating a semiconductor device according to claim 1, characterized in that, After planarization, the thickness of the remaining insulating material layer on the nitride layer is 200 Å to 500 Å.
4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The remaining isolation material layer and the nitride layer on the nitride layer are removed using a dry etching process.
5. The method for fabricating a semiconductor device according to claim 4, characterized in that, In the dry etching process, the etching selectivity ratio of the isolation material layer to the nitride layer is 1:
1.
6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The oxide layer and the isolation material layer flush with the oxide layer in the shallow trench are removed by a wet etching process.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The wet etching process uses an etching solution including diluted hydrofluoric acid.
8. A method for manufacturing a semiconductor device according to any one of claims 1 to 7, characterized in that, Before forming the oxide layer on the substrate, the method further includes: forming a barrier layer on the substrate, wherein the oxide layer is formed on the barrier layer; After removing the oxide layer, the process further includes removing the barrier layer.
9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The barrier layer is made of spin-coated carbon; the barrier layer is removed using oxygen plasma.
10. A semiconductor device, characterized in that, It is manufactured using the method for manufacturing a semiconductor device as described in any one of claims 1 to 9.