Wiring board and method for manufacturing wiring board

Abstract

The invention provides a wiring substrate and a method for manufacturing the wiring substrate. The wiring substrate has high quality. The wiring substrate includes: a first resin insulating layer having a first surface, a second surface, and a cavity extending from the first surface to the second surface; a second resin insulating layer having a third surface and a fourth surface and formed on the first resin insulating layer; a member which has an electrode facing the fourth surface and is housed in the cavity; and a third resin insulating layer having a fifth surface and a sixth surface and formed on the first resin insulating layer. The cavity has an opening on the first surface side and an opening on the second surface side. The second resin insulating layer closes the opening on the first surface side, and the third resin insulating layer closes the opening on the second surface side. The second resin insulating layer is closer to a mounting surface on which the electronic component is mounted than the third resin insulating layer. A part of the third resin insulating layer fills a gap between the inner wall of the cavity and the component. The cross-sectional shape of the cavity is substantially trapezoidal, and the distance between the opposing legs substantially decreases from the second surface toward the first surface.

Description

Technical Field

[0001] The technology disclosed in this specification relates to wiring substrates. Background Technology

[0002] Patent document 1 discloses an electronic component embedded substrate in which electronic components are embedded in a cavity formed in a resin insulating layer.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2015-106610

[0004] [The issue of patent document 1]

[0005] As in patent document 1 Figure 1 As shown, the electronic component embedded substrate of Patent Document 1 has a core substrate and an upper laminate. The electronic component is housed in a cavity within the upper laminate. The cross-sectional shape of the cavity is shown in Figure 5(B) of Patent Document 1. According to Figure 5(B) of Patent Document 1, the walls of the cavity in Patent Document 1 are inclined. Furthermore, the distance between opposing walls decreases towards the core substrate. Therefore, as an explanation of the cross-sectional shape of the cavity in Patent Document 1, an inverted trapezoid is considered appropriate. It is believed that when the electronic component embedded substrate of Patent Document 1 is subjected to thermal shock, the flatness of the upper surface of the upper laminate decreases. Summary of the Invention

[0006] The wiring substrate of the present invention comprises: a first resin insulating layer having a first surface, a second surface opposite to the first surface, and a cavity extending from the first surface to the second surface; a second resin insulating layer having a third surface and a fourth surface opposite to the third surface, the second resin insulating layer being formed on the first resin insulating layer with the fourth surface facing the first surface; a component having an electrode facing the fourth surface, the component being housed within the cavity; and a third resin insulating layer having a fifth surface and a sixth surface opposite to the fifth surface, the third resin insulating layer being formed on the first resin insulating layer with the fifth surface facing the second surface. The cavity has an opening on the first surface side of the first surface and an opening on the second surface side of the second surface. The second resin insulating layer closes the opening on the first surface side, and the third resin insulating layer closes the opening on the second surface side. The second resin insulating layer is closer to the mounting surface for mounting the electronic component than the third resin insulating layer. A portion of the third resin insulating layer fills the gap between the inner wall of the cavity and the component within the cavity. The cross-sectional shape of the cavity is essentially trapezoidal. Among the four sides of the trapezoid, the sides other than the upper and lower bases are opposite legs, and the distance between the opposite legs substantially decreases from the second face toward the first face.

[0007] The method for manufacturing a wiring substrate according to the present invention includes the following steps: forming a metal layer on a support plate; forming a first alignment mark on the metal layer; stacking a second resin insulating layer having a third side and a fourth side opposite to the third side on the first alignment mark and the metal layer with the third side facing the metal layer; forming a first conductor layer on the fourth side of the second resin insulating layer; forming an uppermost first resin insulating layer on the first conductor layer and the second resin insulating layer; forming a second conductor layer on the uppermost first resin insulating layer; forming a lowermost first resin insulating layer on the uppermost first resin insulating layer and the second conductor layer; forming a cavity penetrating the uppermost first resin insulating layer and the lowermost first resin insulating layer; receiving a component in the cavity; forming a third resin insulating layer on the lowermost first resin insulating layer; forming a third conductor layer on the third resin insulating layer; removing the support plate and the metal layer; and forming a first opening penetrating the second resin insulating layer and exposing the electrode of the component, wherein the position of the first opening is associated with the position of the first alignment mark, and the position of the component is associated with the position of the first alignment mark.

[0008] In the wiring substrate of the embodiment of the present invention, the cross-sectional shape of the cavity is substantially trapezoidal, and the distance between the opposing legs substantially decreases from the second surface of the first resin insulating layer toward the first surface. The space between the inner wall of the cavity and the component inside the cavity substantially decreases from the second surface toward the first surface. The size of the outlet of the space on the second surface side is larger than the size of the outlet of the space on the first surface side. Even if the resin in the space expands due to thermal shock, the expanded resin is difficult to flow out of the space through the outlet on the first surface side. The expanded resin is difficult to press against the second resin insulating layer. The flatness of the mounting surface is difficult to reduce. When electronic components are mounted on the wiring substrate of the embodiment, it is easy to mount the electronic components. The embodiment can improve the connection reliability between the wiring substrate of the embodiment and the electronic components mounted on the wiring substrate of the embodiment. Due to thermal shock, the connection reliability between the wiring substrate of the embodiment and the electronic components mounted on the wiring substrate of the embodiment is difficult to reduce. The embodiment can provide a wiring substrate with stable performance. Attached Figure Description

[0009] Figure 1 This is a schematic cross-sectional view of the wiring substrate of an embodiment.

[0010] Figure 2A This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0011] Figure 2B This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0012] Figure 2C This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0013] Figure 2D This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0014] Figure 2E This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0015] Figure 2F This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0016] Figure 2G This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0017] Figure 2H This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0018] Figure 2I This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0019] Figure 2J This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0020] Figure 3 This is a schematic cross-sectional view of a wiring substrate with a modified example.

[0021] Label Explanation

[0022] 2, 2x: Wiring substrate; 20: First resin insulating layer; 20a: First side; 20b: Second side; 22: Uppermost first resin insulating layer; 24: Lowermost first resin insulating layer; 50: Cavity; 50a: Opening on the first side; 50b: Opening on the second side; 52: Gap; 60: Component; 62: Electrode; 70: Adhesive film; 80: Third resin insulating layer; 80a: Fifth side; 80b: Sixth side; 100: Via conductor; 102: Opening; 110: Fourth resin insulating layer; 110a: Seventh side; 110b: Eighth side; 112: Reinforcing material; 140: Second solder resist layer; 200: Second resin insulating layer; 200a: Third side; 200b: Fourth side; 210: Conductor layer; 220: Via conductor; 230: Via conductor; 350: First solder resist layer. Detailed Implementation

[0023] [Wiring substrate 2 in the embodiment]

[0024] Figure 1This is a cross-sectional view illustrating the wiring substrate 2 of the embodiment. (See attached image.) Figure 1 As shown, the wiring substrate 2 has an upper surface 2a and a lower surface 2b. The upper surface 2a is a mounting surface on which electronic components are mounted. Examples of electronic components include logic ICs, memory, etc. The wiring substrate 2 includes a first resin insulating layer 20, a second resin insulating layer 200, a third resin insulating layer 80, a fourth resin insulating layer 110, and a second solder resist layer 140. An example of the second resin insulating layer 200 is the first solder resist layer. The second resin insulating layer 200 is the outermost resin insulating layer.

[0025] The first resin insulating layer 20 has a first surface 20a and a second surface 20b opposite to the first surface 20a. The second resin insulating layer 200 has a third surface 200a and a fourth surface 200b opposite to the third surface 200a. The third resin insulating layer 80 has a fifth surface 80a and a sixth surface 80b opposite to the fifth surface 80a. The fourth resin insulating layer 110 has a seventh surface 110a and an eighth surface 110b opposite to the seventh surface 110a. The second solder resist layer 140 has a ninth surface 140a and a tenth surface 140b opposite to the ninth surface 140a. The upper surface 2a of the wiring substrate 2 is the same surface as the third surface 200a of the second resin insulating layer 200. The lower surface 2b of the wiring substrate 2 is the same surface as the tenth surface 140b of the second solder resist layer 140. The first surface 20a is opposite to the fourth surface 200b of the second resin insulating layer 200. The second surface 20b faces the fifth surface 80a of the third resin insulating layer 80. The first resin insulating layer 20 includes an uppermost first resin insulating layer 22 and a lowermost first resin insulating layer 24. The surface of the uppermost first resin insulating layer 22 that contacts the second resin insulating layer 200 is the first surface 20a. The surface of the lowermost first resin insulating layer 24 that contacts the third resin insulating layer 80 is the second surface 20b. The first resin insulating layer 20 may include other resin insulating layers between the uppermost first resin insulating layer 22 and the lowermost first resin insulating layer 24. The number of resin insulating layers forming the first resin insulating layer 20 may also be three or more. The resin insulating layers forming the first resin insulating layer 20 are formed of resin and inorganic particles dispersed within the resin. An example of resin is a thermosetting resin. Inorganic particles are, for example, silicon dioxide or aluminum oxide. The resin insulating layers forming the first resin insulating layer 20 do not have a reinforcing material composed of fibers. An example of a reinforcing material is glass cloth. The second resin insulating layer 200 and the third resin insulating layer 80 do not have a reinforcing material.

[0026] The wiring substrate 2 also includes conductor layers 10 and 30 and via conductors 40. Conductor layers 10 and 30 and resin insulating layers 22 and 24 are alternately stacked. The via conductor 40 passes through the resin insulating layer 22 sandwiched between adjacent conductor layers 10 and 30, connecting adjacent conductor layers 10 and 30. Conductor layer 10 is formed between a first surface 20a of the first resin insulating layer 20 and a fourth surface 200b of the second resin insulating layer 200. Conductor layer 10 is sandwiched between the second resin insulating layer 200 and the uppermost first resin insulating layer 22. Conductor layer 10 includes a frame-shaped cavity conductor circuit 14a. Conductor layer 30 is formed between the uppermost first resin insulating layer 22 and the lowermost first resin insulating layer 24. Conductor layer 30 is sandwiched between the uppermost first resin insulating layer 22 and the lowermost first resin insulating layer 24. The via conductor 40 connects conductor layer 10 and conductor layer 30. The via conductor 40 is formed in the opening 42 that penetrates the uppermost first resin insulating layer 22.

[0027] The first resin insulating layer 20 has a cavity 50 extending from a first surface 20a to a second surface 20b. The cavity 50 passes through the first resin insulating layer 20 and the cavity conductor circuit 14a. The cavity 50 has an opening 50a on the first surface 20a side and an opening 50b on the second surface 20b side. A component 60 is housed within the cavity 50. An adhesive film 70 is formed between the component 60 and the fourth surface 200b of the second resin insulating layer 200. The component 60 is fixed to the fourth surface 200b of the second resin insulating layer 200 by the adhesive film 70. The component 60 has an electrode 62 opposite to the fourth surface 200b. The second resin insulating layer 200 closes the opening 50a on the first surface 20a side. A third resin insulating layer 80 closes the opening 50b on the second surface 20b side. A portion of the third resin insulating layer 80 fills the gap 52 between the inner wall of the cavity 50 and the component 60.

[0028] The cross-sectional shape of the cavity 50 is substantially trapezoidal. The distance between the opposing legs (leg distance) substantially decreases from the second surface 20b toward the first surface 20a. In the four sides of the trapezoid, the legs are the sides other than the upper and lower bases. The leg distance substantially decreases toward the mounting surface. In Patent Document 1 and the embodiment, the leg distance is reversed. In Patent Document 1, the leg distance increases toward the mounting surface. The size of the opening 50a on the first surface 20a side of the cavity 50 is smaller than the size of the opening 50b on the second surface 20b side.

[0029] The third resin insulating layer 80 is formed on the second surface 20b of the first resin insulating layer 20. The fifth surface 80a is opposite to the second surface 20b of the first resin insulating layer 20. The sixth surface 80b is opposite to the seventh surface 110a of the fourth resin insulating layer 110. The third resin insulating layer 80 is formed of resin and inorganic particles dispersed within the resin.

[0030] The wiring substrate 2 also has a conductor layer 90 and a via conductor 100. The conductor layer 90 is formed on the sixth surface 80b of the third resin insulating layer 80. The via conductor 100 connects the conductor layer 30 and the conductor layer 90. The via conductor 100 is formed in an opening 102 that penetrates the third resin insulating layer 80 and the lowermost first resin insulating layer 24. The opening 102 penetrates only the third resin insulating layer 80 and the lowermost first resin insulating layer 24. The via conductor 100 is an example of a second via conductor.

[0031] A fourth resin insulating layer 110 is formed on the sixth surface 80b of the third resin insulating layer 80 and the conductor layer 90. The fourth resin insulating layer 110 contacts the second solder resist layer 140 and is formed inside the second solder resist layer 140. A seventh surface 110a faces the sixth surface 80b of the third resin insulating layer 80. An eighth surface 110b faces the ninth surface 140a of the second solder resist layer 140. The fourth resin insulating layer 110 is formed of resin and inorganic particles dispersed within the resin. The fourth resin insulating layer 110 may also have a reinforcing material 112. The reinforcing material 112 is only included in the fourth resin insulating layer 110; the first resin insulating layer 20, the third resin insulating layer 80, the second resin insulating layer 200, and the second solder resist layer 140 do not contain reinforcing material. The fourth resin insulating layer 110 is formed, for example, using a prepreg. The thickness of the resin insulating layer containing reinforcing material 112 is greater than the distance between the first surface 20a and the second surface 20b of the first resin insulating layer 20 (the thickness of the first resin insulating layer 20) (Relationship 1). An example of a resin insulating layer containing reinforcing material 112 is a fourth resin insulating layer 110. The resin insulating layer containing reinforcing material 112 is in contact with the second solder resist layer 140. The thickness of the first resin insulating layer 20 can also be the distance between the conductor layer 10 in contact with the first surface 20a and the second surface 20b (…). Figure 1 K1 in the text). The thickness of the fourth resin insulating layer 110 is represented by the distance between the conductor layers sandwiching the fourth resin insulating layer 110. The thickness of the resin insulating layer including the reinforcing material 112 is represented by the distance between the conductor layers sandwiching the resin insulating layer including the reinforcing material 112. Figure 1 (K2 in the example) is used as an example. When there are multiple resin insulating layers containing reinforcing material, one layer satisfies relation 1. Alternatively, two layers satisfy relation 1. Alternatively, all layers satisfy relation 1. The wiring substrate 2 also has a conductor layer 120 and a via conductor 130. The conductor layer 120 is formed on the eighth surface 110b of the fourth resin insulating layer 110. The via conductor 130 is formed within an opening 132 penetrating the fourth resin insulating layer 110. The via conductor 130 connects the conductor layer 90 and the conductor layer 120.

[0032] A second solder resist layer 140 is formed on the eighth surface 110b of the fourth resin insulating layer 110 and the conductor layer 120. The second solder resist layer 140 is formed at the position furthest from the second resin insulating layer 200. A ninth surface 140a is opposite to the eighth surface 110b of the fourth resin insulating layer 110. A tenth surface 140b forms the lower surface 2b of the wiring substrate 2. The second solder resist layer 140 has an opening 162 that exposes the conductor layer 120.

[0033] A second resin insulating layer 200 is formed on the first surface 20a of the first resin insulating layer 20. The second resin insulating layer 200 is formed on the first resin insulating layer 20 with its fourth surface 200b facing the first surface 20a. The wiring substrate 2 also has a conductor layer 210 and via conductors 220 and 230. The conductor layer 210 is formed on the third surface 200a of the second resin insulating layer 200. The conductor layer 210 includes mounting electrodes 212 and 213. An alignment mark (first alignment mark) 8 is formed on the third surface 200a of the second resin insulating layer 200. The conductor layer 210 and the alignment mark 8 are not formed simultaneously. They are formed separately. The alignment mark 8 is embedded in the second resin insulating layer 200. The conductor layer 210, which includes the mounting electrodes 212 and 213, is not embedded in the second resin insulating layer 200. The conductor layer 210 protrudes from the second resin insulating layer 200. A conductor 9 is formed in an opening 9a that penetrates the second resin insulating layer 200. Conductor 9 connects the first alignment mark 8 and the conductor layer 10. A via conductor 220 is formed within an opening 222 penetrating the second resin insulating layer 200. Opening 222 exposes the conductor layer 10. The via conductor 220 connects the mounting electrode 212 and the conductor layer 10. A via conductor 230 is formed within an opening 232 penetrating the second resin insulating layer 200 and the adhesive film 70. Opening 232 exposes the electrode 62 of the component 60. The via conductor 230 connects the mounting electrode 213 and the electrode 62. The via conductor 230 is an example of a first via conductor. A tin plating layer may also be formed on the upper surface of the conductor layer 210. The mounting electrodes 212 and 213 function as protrusions for mounting electronic components.

[0034] The second resin insulating layer 200 has openings 222, 232, and 9a penetrating the second resin insulating layer 200. The lengths of each opening 222, 232, and 9a are different. The length of opening 232 is longer than the length of opening 222. The length of opening 222 is longer than the length of opening 9a. The length of opening 222 is the distance between the third surface 200a and the fourth surface 200b. The length of opening 232 is the distance between the third surface 200a and the electrode 62. The length of opening 9a is the distance between the alignment mark 8 and the fourth surface 200b. Thus, the second resin insulating layer 200 has three types of openings 222, 232, and 9a, and the lengths of these three types of openings are all different.

[0035] [Manufacturing method of wiring substrate 2 according to the embodiment]

[0036] Figures 2A to 2J The manufacturing method of the wiring substrate 2 according to the embodiment is shown. Figures 2A to 2J It is a sectional view. Figures 2A to 2I In the diagram, the vertical direction is... Figure 1 , Figure 2J Conversely, it means the opposite. Figure 2A The diagram shows a support plate 4, a metal layer 6 formed on the support plate 4, and alignment marks (first alignment marks) 8 formed on the metal layer 6. The metal layer 6 is, for example, copper foil. The metal layer 6 is pre-formed on the support plate 4. A resist is formed on the metal layer 6. The alignment mark 8 is formed on the metal layer 6 exposed from the resist by copper electroplating. Preferably, no conductive circuits other than the alignment mark 8 are formed on the metal layer 6. The metal layer 6 functions as a seed layer for forming the alignment mark 8. Afterward, the resist is removed.

[0037] A second resin insulating layer 200 is formed on the metal layer 6 and the alignment mark 8. The second resin insulating layer 200 has a third surface 200a and a fourth surface 200b opposite to the third surface 200a. The third surface 200a of the second resin insulating layer 200 is opposite to the metal layer 6. An opening 9a is formed in the second resin insulating layer 200, penetrating the second resin insulating layer 200 and exposing the alignment mark 8. The opening 9a is formed with reference to the alignment mark 8. The opening 9a is formed by laser or photographic techniques. The opening 9a penetrates only the second resin insulating layer 200. A seed layer is formed on the fourth surface 200b of the second resin insulating layer 200 and within the opening 9a. A resist is formed on the seed layer with reference to the alignment mark 8. Alternatively, the resist can be formed on the seed layer with reference to the opening 9a. An electroplated copper layer is formed on the seed layer exposed from the resist. The resist is removed. The seed layer exposed from the electroplated copper layer is removed. Figure 2B As shown, a conductor layer 10 is formed on the fourth surface 200b of the second resin insulating layer 200. The conductor layer 10 includes a cavity conductor circuit 14. The conductor layer 10 may also have alignment marks (second alignment marks). The positions of each conductor circuit within the conductor layer 10 are associated with the positions of the first alignment marks 8. The cavity conductor circuit 14 and the second alignment marks are contained within the conductor circuits in the conductor layer 10. The positions of the first alignment marks 8 are associated with the positions of the second alignment marks. The positions of the first alignment marks 8 are related to the positions of the cavity conductor circuit 14. The cavity conductor circuit 14 serves as a stop for forming the cavity 50. The size of the cavity conductor circuit 14 is preferably larger than the size of the opening 50a on the first surface 20a side of the cavity 50. A conductor 9 is formed simultaneously with the conductor layer 10 to fill the opening 9a. The conductor 9 connects the alignment marks 8 and the conductor layer 10.

[0038] A topmost first resin insulating layer 22 is formed on the fourth surface 200b of the conductor layer 10 and the second resin insulating layer 200. A laser is irradiated onto the topmost first resin insulating layer 22. The laser is irradiated based on the position of the conductor circuit within the conductor layer 10. For example, the laser is irradiated based on a second alignment mark. The laser penetrates the topmost first resin insulating layer 22. An opening 42 for a via conductor 40, exposing the conductor layer 10, is formed in the topmost first resin insulating layer 22. The position of the opening 42 for the via conductor 40 is associated with the position of the first alignment mark 8. A seed layer is formed on the topmost first resin insulating layer 22 and within the opening 42. A resist is formed on the seed layer based on the position of the conductor circuit within the conductor layer 10. For example, the resist is formed based on the second alignment mark. A copper plating layer is formed on the seed layer exposed from the resist. The resist is removed. The seed layer exposed from the copper plating layer is removed. Simultaneously, a conductor layer 30 and a via conductor 40 are formed. The conductor layer 30 may also have a third alignment mark. The positions of each conductor circuit within conductor layer 30 are associated with the position of the first alignment mark 8. The position of the third alignment mark is associated with the position of the first alignment mark 8. The position of the via conductor 40 is associated with the position of the first alignment mark 8. The via conductor 40 fills the opening 42. The via conductor 40 connects conductor layer 10 and conductor layer 30. The lowermost first resin insulating layer 24 is formed on the uppermost first resin insulating layer 22 and conductor layer 30. Figure 2CAs shown, a first resin insulating layer 20 is formed on the fourth surface 200b of the second resin insulating layer 200 and the conductor layer 10. The first resin insulating layer 20 has a first surface 20a and a second surface 20b opposite to the first surface 20a. The first surface 20a of the first resin insulating layer 20 faces the fourth surface 200b of the second resin insulating layer 200. The first resin insulating layer 20 is formed by an uppermost first resin insulating layer 22 and a lowermost first resin insulating layer 24. The conductor layer 30 is sandwiched between the uppermost first resin insulating layer 22 and the lowermost first resin insulating layer 24. The uppermost first resin insulating layer 22 and the lowermost first resin insulating layer 24 have a first surface and a second surface opposite to the first surface. The first surface of the uppermost first resin insulating layer 22 faces the fourth surface 200b of the second resin insulating layer 200. The first surface of the uppermost first resin insulating layer 22 forms the same surface as the first surface 20a of the first resin insulating layer 20. The first surface of the lowermost first resin insulating layer 24 faces the second surface of the uppermost first resin insulating layer 22. The second surface of the lowermost first resin insulating layer 24 forms the same surface as the second surface 20b of the first resin insulating layer 20. The thickness of the uppermost first resin insulating layer 22 is preferably greater than the thickness of the lowermost first resin insulating layer 24. The ratio of the thickness of the uppermost first resin insulating layer 22 to the thickness of the lowermost first resin insulating layer 24 (thickness of the uppermost first resin insulating layer 22 / thickness of the lowermost first resin insulating layer 24) is preferably 1.2 or more and 1.5 or less. The thickness of the uppermost first resin insulating layer 22 is the distance between the conductor layer 10 and the conductor layer 30. The uppermost first resin insulating layer 22 is sandwiched between the conductor layer 10 and the conductor layer 30. The thickness of the lowermost first resin insulating layer 24 is the distance between the conductor layer 30 and the second surface of the lowermost first resin insulating layer 24. The conductor layer 30 is sandwiched between the uppermost first resin insulating layer 22 and the lowermost first resin insulating layer 24.

[0039] A laser beam is irradiated from the second surface 20b of the first resin insulating layer 20. The laser beam is irradiated based on the position of the conductor circuit within the conductor layer 30. For example, the laser beam is irradiated based on a third alignment mark. The laser beam penetrates the first resin insulating layer 20. Figure 2D As shown, an opening 51 is formed that penetrates the first resin insulating layer 20 and reaches the first opening conductor circuit 14. The laser penetrates all the resin insulating layers 22 and 24 belonging to the first resin insulating layer 20 and reaches the cavity conductor circuit 14. The cavity conductor circuit 14 is exposed from the opening 51. The position of the opening 51 is associated with the position of the first alignment mark 8. The laser does not reach the second resin insulating layer 200 through the cavity conductor circuit 14. For example, the laser can be obliquely irradiated relative to the cavity conductor circuit 14 by forming the wall of the opening 51 at an angle relative to the cavity conductor circuit 14. The cross-sectional shape of the opening 51 is substantially trapezoidal. Figure 2D The cross-sectional shape of the opening 51 depicted is approximately an inverted trapezoid. The distance between the opposing legs substantially decreases from the second surface 20b toward the first surface 20a.

[0040] The cavity conductor circuit 14 exposed from the opening 51 is removed by etching. The etched cavity conductor circuit 14a has a frame-like planar shape. The frame-like cavity conductor circuit 14a is covered by the uppermost first resin insulating layer 22. Figure 2E As shown, a cavity 50 is formed that simultaneously penetrates the first resin insulating layer 20 and the cavity conductor circuit 14a. The cross-sectional shape of the cavity 50 is substantially trapezoidal. Figure 2E The cross-sectional shape of the cavity 50 depicted is approximately an inverted trapezoid. The distance between the opposing legs substantially decreases from the second surface 20b toward the first surface 20a. The size of the opening 50a on the first surface 20a side is smaller than the size of the opening 50b on the second surface 20b side. The fourth surface 200b of the second resin insulating layer 200 protrudes from the cavity 50. The second resin insulating layer 200 closes the opening 50a on the first surface 20a side of the cavity 50. The opening 50a of the cavity 50 is closed by the fourth surface 200b of the second resin insulating layer 200. The second resin insulating layer 200 is an example of a component used to close the opening 50a.

[0041] like Figure 2F As shown, a component 60 is fixed to the fourth surface 200b of the second resin insulating layer 200 exposed from the cavity 50, with an adhesive film 70 in between. For example, the component 60 is fixed to the fourth surface 200b of the second resin insulating layer 200 based on a third alignment mark. Alternatively, the component 60 is fixed to the fourth surface 200b of the second resin insulating layer 200 based on the position of the cavity 50. The position of the component 60 is associated with the position of the first alignment mark 8. The adhesive film 70 is pre-installed on the component 60. The component 60 with the adhesive film 70 is fixed to the fourth surface 200b exposed from the cavity 50. The component 60 is fixed within the cavity 50. While fixing the component 60, the component 60 is surrounded by the first resin insulating layer 20. The component 60 is protected by the first resin insulating layer 20. The upper surface 601 of the component 60 does not protrude from the opening 50b. The upper surface 601 of the component 60 is located lower than the second surface 20b of the first resin insulating layer 20. The upper surface 601 of component 60 is not located above the second surface 20b of the first resin insulating layer 20. Preferably, the upper surface 601 of component 60 is located above the first surface of the lowermost first resin insulating layer 24. The upper surface 601 of component 60 is located between the first surface and the second surface of the lowermost first resin insulating layer 24. A gap 52 is formed between component 60 and the inner wall surface of cavity 50.

[0042] like Figure 2GAs shown, a third resin insulating layer 80 is formed on the second surface 20b of the first resin insulating layer 20. The third resin insulating layer 80 has a fifth surface 80a and a sixth surface 80b opposite to the fifth surface 80a. The fifth surface 80a of the third resin insulating layer 80 is opposite to the second surface 20b. The third resin insulating layer 80 closes the opening 50b on the second surface 20b side of the cavity 50. The opening 50b of the cavity 50 is closed by the fifth surface 80a of the third resin insulating layer 80. The third resin insulating layer 80 fills the gap 52.

[0043] A laser (first laser) is irradiated from the sixth surface 80b of the third resin insulating layer 80, based on the position of the conductor circuit within the conductor layer 30. For example, the first laser is irradiated based on a third alignment mark. The first laser simultaneously penetrates both the third resin insulating layer 80 and the lowermost first resin insulating layer 24, forming an opening 102 in the conductor layer 30 that penetrates both the third resin insulating layer 80 and the lowermost first resin insulating layer 24. Figure 2H As shown, a conductor layer 90 is formed on the sixth surface 80b of the third resin insulating layer 80. A via conductor 100 is formed simultaneously with the conductor layer 90. For example, the conductor layer 90 and the via conductor 100 are formed by a semi-additive process. The via conductor 100 fills the opening 102. The via conductor 100 connects the conductor layer 30 and the conductor layer 90.

[0044] When component 60 has electrodes on both the front and back sides, a laser (second laser) is irradiated toward component 60 from the sixth surface 80b of the third resin insulating layer 80, according to the position of the conductor circuit within the conductor layer 30. For example, the second laser is irradiated based on a third alignment mark. The second laser penetrates only the third resin insulating layer 80. The second laser does not penetrate the bottommost first resin insulating layer 24. An opening for a via conductor is formed in the third resin insulating layer 80, penetrating the third resin insulating layer 80 to reach the component 60. Only the opening for the via conductor penetrates the third resin insulating layer 80 to reach the electrode of component 60. The third resin insulating layer 80 can have two types of openings for via conductors. The depths of the two openings (the opening reaching the conductor layer 30 and the opening reaching the electrode of the component) are different. When forming the via conductor 100, a via conductor connecting component 60 to conductor layer 90 is formed within the via conductor opening that exposes the electrode of component 60.

[0045] A fourth resin insulating layer 110 is formed on the sixth surface 80b of the third resin insulating layer 80 and the conductor layer 90. The seventh surface 110a of the fourth resin insulating layer 110 faces the sixth surface 80b. The fourth resin insulating layer 110 includes a reinforcing material 112. An opening 132 is formed in the fourth resin insulating layer 110. Figure 2IAs shown, a conductor layer 120 is formed on the eighth surface 110b of the fourth resin insulating layer 110. For example, the conductor layer 120 and the via conductor 130 are formed by a semi-additive process. The via conductor 130 is formed simultaneously with the conductor layer 120. The via conductor 130 fills the opening 132. The via conductor 130 connects the conductor layer 90 and the conductor layer 120.

[0046] In this embodiment, a resin insulating layer with reinforcing material (the additional resin insulating layer) can be added between the third resin insulating layer 80 and the fourth resin insulating layer 110. A conductor layer is formed between the additional resin insulating layer and the fourth resin insulating layer 110. A through-hole conductor is formed through the additional resin insulating layer. The thickness of the resin insulating layer with reinforcing material, such as the fourth resin insulating layer 110, is preferably greater than the thickness of the first resin insulating layer 20.

[0047] Remove the support plate 4 and the metal layer 6. The third surface 200a of the second resin insulating layer 200 is exposed. Alignment mark 8 is exposed. A second solder resist layer 140 is formed on the eighth surface 110b of the fourth resin insulating layer 110. The second solder resist layer 140 is preferably formed directly above the fourth resin insulating layer 110. The ninth surface 140a is in contact with the eighth surface 110b. The ninth surface 140a of the second solder resist layer 140 is opposite to the eighth surface 110b. Figure 2J As shown, an opening 162 is formed in the second solder mask layer 140 to expose the conductor layer 120. For example, the opening 162 is formed by photographic technique.

[0048] A laser (third laser) is irradiated from the third surface 200a of the second resin insulating layer 200. The third laser is irradiated based on the first alignment mark 8. The third laser simultaneously penetrates the second resin insulating layer 200 and the adhesive film 70, forming an opening 232. The position of the opening 232 is associated with the position of the first alignment mark 8. The opening 232 penetrates the second resin insulating layer 200 and the adhesive film 70, exposing the electrode 62 of the component 60. The position of the opening 232 is associated with the position of the component 60. Therefore, the position of the electrode 62 of the component 60 is highly aligned with the position of the opening 232. Furthermore, a laser (fourth laser) is irradiated from the third surface 200a of the second resin insulating layer 200. The fourth laser is irradiated based on the first alignment mark 8. The fourth laser penetrates the second resin insulating layer 200. The fourth laser penetrates only the second resin insulating layer 200, forming an opening 222. The opening 222 penetrates only the second resin insulating layer 200. The position of the opening 222 is associated with the position of the first alignment mark 8. Opening 222 penetrates the second resin insulating layer 200, exposing the conductor layer 10. A conductor layer 210 is formed on the third surface 200a. The conductor layer 210 includes mounting electrodes 212 and 213. Via conductors 220 and 230 are formed simultaneously with the conductor layer 210. At this time, alignment marks 8 have already been formed. The conductor layer 210 and alignment marks 8 are not formed simultaneously. The conductor layer 210 and alignment marks 8 are formed separately. Via conductor 220 fills opening 222. Via conductor 220 connects the conductor layer 10 and the mounting electrode 212. Via conductor 230 fills opening 232. Via conductor 230 connects the electrode 62 and the mounting electrode 213. The position of opening 232 and the position of component 60 are related to the position of the first alignment mark 8. Therefore, the wiring substrate 2 of this embodiment can improve the connection reliability between the via conductor 230 and the electrode 62 of component 60. The wiring substrate 2 manufactured in this embodiment improves the reliability of the connection between electronic components and components 60 via mounting electrodes 213 and via conductors 230. A tin plating layer is formed on the upper surface of the conductor layer 210. The wiring substrate 2 of this embodiment is thus obtained.

[0049] In the wiring substrate 2 of the embodiment, the cross-sectional shape of the cavity 50 is substantially trapezoidal, and the distance between the opposing legs substantially decreases from the second surface 20b of the first resin insulating layer 20 towards the first surface 20a. The space between the inner wall of the cavity 50 and the component 60 within the cavity 50 substantially decreases from the second surface 20b towards the first surface 20a. The size of the outlet of the space on the second surface 20b side is larger than the size of the outlet of the space on the first surface 20a side. Even if the resin in the space expands due to thermal shock, the expanded resin is difficult to discharge out of the space through the outlet on the first surface 20a side. The expanded resin is difficult to expose out of the space through the opening 50a on the first surface 20a side. The expanded resin is difficult to press against the second resin insulating layer 200. The flatness of the mounting surface is difficult to reduce. When electronic components are mounted on the wiring substrate 2 of the embodiment, it is easy to mount the electronic components. The embodiment can improve the connection reliability between the wiring substrate 2 of the embodiment and the electronic components mounted on the wiring substrate 2 of the embodiment. The reliability of the connection between the wiring substrate 2 of the embodiment and the electronic components mounted on the wiring substrate 2 of the embodiment is unlikely to be reduced due to thermal shock. The embodiment can provide a wiring substrate 2 with stable performance.

[0050] The via conductors 220 and 230 penetrating the second resin insulating layer 200 gradually taper towards the lower surface 2b of the wiring substrate 2. The via conductors 40, 100, and 130 penetrating the resin insulating layers 22, 24, 80, and 110 outside the second resin insulating layer 200 are tapered towards the upper surface 2a of the wiring substrate 2. The orientation of the via conductors penetrating the second resin insulating layer is opposite to the orientation of the via conductors penetrating the resin insulating layers outside the second resin insulating layer.

[0051] [Modified Wiring Board 2x and Manufacturing Method]

[0052] Figure 3This is a cross-sectional view showing a modified wiring substrate 2x. The reference numerals are the same in the figure where the elements forming the modified wiring substrate 2x are the same as those forming the wiring substrate 2 of the embodiment. Detailed descriptions related to elements common to the embodiment are omitted. The modified wiring substrate 2x is obtained by adding a first solder resist layer 350, a conductor layer 360, and a via conductor 370 to the wiring substrate 2 of the embodiment. The first solder resist layer 350 is formed on the second resin insulating layer 200, the conductor layer 210, and the alignment mark 8. No tin plating layer is formed on the conductor layer 210. The conductor layer 360 is formed on the first solder resist layer 350. A via conductor 370 is formed through the first solder resist layer 350 and connects the conductor layer 210 and the conductor layer 360. The conductor layer 360 and the via conductor 370 are formed simultaneously by a semi-additive method. In the embodiment, the second resin insulating layer 200 also serves as the first solder resist layer, but in the modified example, the first solder resist layer 350 exists separately from the second resin insulating layer 200. In the embodiment, conductor layer 210 includes conductor circuitry for mounting electronic components; however, in the modified embodiment, conductor layer 210 does not include conductor circuitry for mounting electronic components. In the modified embodiment, conductor layer 360 includes conductor circuitry for mounting electronic components. In the embodiment, the second resin insulating layer 200 is one of the outermost resin insulating layers; however, in the modified embodiment, the first solder resist layer 350 is one of the outermost resin insulating layers.

[0053] A first solder resist layer 350 is formed on the third surface 200a of the second resin insulating layer 200. The first solder resist layer 350 has an eleventh surface 350a and a twelfth surface 350b opposite to the eleventh surface 350a. The twelfth surface 350b is opposite to the third surface 200a. In a modified example, the upper surface 2a of the wiring substrate 2x is the same surface as the eleventh surface 350a of the first solder resist layer 350. The first solder resist layer 350 does not contain reinforcing material. The reinforcing material 112 is only contained in the fourth resin insulating layer 110, and the first resin insulating layer 20, the third resin insulating layer 80, the second resin insulating layer 200, the first solder resist layer 350, and the second solder resist layer 140 do not contain reinforcing material. A conductor layer 360 is formed on the eleventh surface 350a of the first solder resist layer 350. The conductor layer 360 includes mounting electrodes 362 and 363. A via conductor 370 is formed in an opening 372 penetrating the first solder resist layer 350. Opening 372 exposes conductor layer 210. A tin plating layer may also be formed on the upper surface of conductor layer 360. Mounting electrodes 362 and 363 function as protrusions for mounting electronic components.

[0054] The cross-sectional shape of the cavity 50 in the modified wiring substrate 2 is also substantially trapezoidal, and the distance between the opposing legs substantially decreases from the second surface 20b of the first resin insulating layer 20 toward the first surface 20a. The modified wiring substrate 2x has the same effect as the wiring substrate 2 of the embodiment.

[0055] In both the implementation and the modified examples, the via conductors are oriented in the same direction. The via conductor 370 penetrating the first solder mask layer 350 gradually tapers toward the lower surface 2b of the wiring substrate 2x. In both the implementation and the modified examples, the orientation of the via conductor above the first surface 20a of the first resin insulating layer 20 is opposite to the orientation of the via conductor below the first surface 20a of the first resin insulating layer 20.

[0056] In both the implementation method and the modified example, the contents related to thickness and length are the same. The relationships related to thickness and length are the same in both the implementation method and the modified example.

Claims

1. A wiring substrate, comprising: A first resin insulating layer has a first surface, a second surface opposite to the first surface, and a cavity extending from the first surface to the second surface; A second resin insulating layer having a third side and a fourth side opposite to the third side is formed on the first resin insulating layer with the fourth side facing the first side; A component having an electrode facing the fourth face, the component being housed within the cavity; as well as A third resin insulating layer, having a fifth surface and a sixth surface opposite to the fifth surface, is formed on the first resin insulating layer with the fifth surface facing the second surface. in, The cavity has an opening on a first side of the first surface and an opening on a second side of the second surface. The second resin insulating layer seals the opening on the first side, and the third resin insulating layer seals the opening on the second side. The second resin insulating layer is closer to the mounting surface for mounting electronic components than the third resin insulating layer. A portion of the third resin insulating layer fills the gap between the inner wall of the cavity and the component within the cavity. The cross-sectional shape of the cavity is essentially trapezoidal. Among the four sides of the trapezoid, the sides other than the upper and lower bases are opposite legs, and the distance between the opposite legs substantially decreases from the second face toward the first face.

2. The wiring substrate according to claim 1, wherein, The first resin insulating layer comprises multiple resin insulating layers, and the resin insulating layer that is in contact with the second resin insulating layer is the uppermost first resin insulating layer. The resin insulating layer that is in contact with the third resin insulating layer among the plurality of resin insulating layers is the lowest first resin insulating layer. The surface of the uppermost first resin insulating layer that contacts the second resin insulating layer is the first surface, and the surface of the lowermost first resin insulating layer that contacts the third resin insulating layer is the second surface. The cavity extends through the multiple resin insulating layers.

3. The wiring substrate according to claim 1, wherein, The second resin insulating layer also serves as the outermost resin insulating layer.

4. The wiring substrate according to claim 3, wherein, The outermost resin insulation layer is the first solder resist layer.

5. The wiring substrate according to claim 1, wherein, The wiring substrate further includes an outermost resin insulating layer formed on the third surface of the second resin insulating layer. The outermost resin insulating layer is in contact with the third surface.

6. The wiring substrate according to claim 5, wherein, The outermost resin insulating layer also serves as the first solder resist layer.

7. The wiring substrate according to claim 1, wherein, The wiring substrate also features: An adhesive film is formed between the second resin insulating layer and the electrode; and A first via conductor, which simultaneously penetrates the second resin insulating layer and the adhesive film to reach the electrode.

8. The wiring substrate according to claim 2, wherein, The wiring substrate also has a second via conductor that simultaneously penetrates the third resin insulating layer and the bottommost first resin insulating layer.

9. The wiring substrate according to claim 1, wherein, The wiring substrate also has an adhesive film formed between the second resin insulating layer and the electrode. The component is fixed to the fourth surface of the second resin insulating layer by the adhesive film.

10. The wiring substrate according to claim 2, wherein, The plurality of resin insulating layers do not include any resin insulating layers other than the uppermost first resin insulating layer and the lowermost first resin insulating layer.

11. The wiring substrate according to claim 8, wherein, The second via conductor penetrates only the third resin insulation layer and the bottommost first resin insulation layer.

12. The wiring substrate according to claim 6, wherein, The wiring substrate also features: A second solder mask layer is formed at the position furthest from the first solder mask layer; and The fourth resin insulating layer, which is in contact with the second solder resist layer, is formed at a position that is more inner than the second solder resist layer. The fourth resin insulation layer contains reinforcing material. The first resin insulating layer, the second resin insulating layer, and the third resin insulating layer do not contain reinforcing material.

13. The wiring substrate according to claim 12, wherein, Neither the first nor the second solder mask layer contains reinforcing material. The thickness of the fourth resin insulating layer is greater than the thickness of the first resin insulating layer.

14. The wiring substrate according to claim 4, wherein, The wiring substrate also features: A second solder mask layer is formed at the position furthest from the first solder mask layer; and The fourth resin insulating layer, which is in contact with the second solder resist layer, is formed at a position that is more inner than the second solder resist layer. The fourth resin insulation layer contains reinforcing material. Neither the first resin insulation layer nor the third resin insulation layer contains reinforcing material.

15. The wiring substrate according to claim 1, wherein, Alignment marks are formed on the third surface of the second resin insulating layer.

16. A method for manufacturing a wiring substrate, comprising the following steps: A metal layer is formed on the support plate; A first alignment mark is formed on the metal layer; A second resin insulating layer having a third side and a fourth side opposite to the third side is stacked on the first alignment mark and the metal layer with the third side facing the metal layer; A first conductor layer is formed on the fourth surface of the second resin insulating layer; The uppermost first resin insulating layer is formed on the first conductor layer and the second resin insulating layer; A second conductor layer is formed on the uppermost first resin insulating layer; The lowermost first resin insulating layer is formed on the uppermost first resin insulating layer and the second conductor layer; A cavity is formed that extends through the uppermost first resin insulating layer and the lowermost first resin insulating layer; The component is housed within the cavity; A third resin insulating layer is formed on the bottommost first resin insulating layer; A third conductor layer is formed on the third resin insulating layer; Remove the support plate and the metal layer; as well as A first opening is formed that penetrates the second resin insulating layer and exposes the electrodes of the component. in, The position of the first opening is associated with the position of the first alignment mark, and the position of the component is associated with the position of the first alignment mark.

17. The method for manufacturing a wiring substrate according to claim 16, wherein, The method for manufacturing the wiring substrate also includes the following steps: A second opening is formed, penetrating the third resin insulating layer and the lowermost first resin insulating layer to reach the second conductor layer; and A via conductor is formed within the second opening to connect the second conductor layer to the third conductor layer.

18. The method for manufacturing a wiring substrate according to claim 16, wherein, The method for manufacturing the wiring substrate further includes the following step: forming a via conductor that fills the first opening.

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