Method for improving flatness and surface microcosmic nanometer morphology of silicon wafer

Abstract

The invention relates to the technical field of semiconductor processing, in particular to a method for improving flatness and surface microscopic nano morphology of a silicon wafer, which comprises the following steps: S1, arranging at least three sensors on a static pressure plate, and at least corresponding to three positions r1, r2 and r3 in the radial direction of a silicon wafer area from outside to inside, obtaining warping data Wp before and Bp after before the silicon wafer is processed through a sensor; s2, according to the front relation between the vertical inclination angle VH and the vertical inclination angle Bp of the grinding wheel, the needed vertical inclination angle of the grinding wheel is calculated and then automatically adjusted; s3, carrying out double-sided grinding processing on the silicon wafer; s4, after the double-sided grinding processing is finished, the warping data Wp and Bp of the silicon wafer after the double-sided grinding processing is finished are obtained through a sensor; s5, calculating a value difference before and after PV2, and judging whether a C-Mark risk exists or not; and calculating a value difference before and after the PV1 to judge whether a B-ring risk exists or not.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processing technology, and in particular to a method for improving the flatness and surface micro-nano morphology of silicon wafers. Background Technology

[0002] Global IC manufacturing technology is progressing towards Moore's Law, characterized by increasingly higher integration density and narrower linewidths. As device feature sizes continue to shrink, IC manufacturing places increasingly stringent demands on substrate material surfaces. Besides demanding higher levels of local surface flatness, it has been discovered that the surface morphology of silicon wafers also affects device processing quality and yield. Research has shifted from simply pursuing high flatness to studying the surface at a more microscopic scale. For future IC processes with even narrower features, highly precise inspection of silicon wafer surface morphology at the nanometer scale is becoming increasingly important.

[0003] IC manufacturing is characterized by a long supply chain and complex processes. While downstream technologies are constantly upgrading and iterating, upstream and midstream technologies must also be updated simultaneously to jointly drive technological development. For narrower linewidths that demand higher surface quality, research on improving the surface nanomorphology of silicon wafers mainly focuses on CMP polishing, with limited research on the impact of the silicon wafer's shape itself.

[0004] Surface nanomorphology is defined as an unevenness or deviation on the surface of a silicon wafer within a spatial approximate wavelength range of 0.2–20 mm; such as protrusions, depressions, or ripples on the silicon wafer surface, with the height variation between the highest and lowest points ranging from several to several hundred nanometers. Research has found that when the silicon wafer has a special shape, pattern transfer can occur on the surface during polishing, leading to localized higher nanomorphic areas. In the DDG (double-sided grinding) process, the silicon wafer is kept naturally perpendicular by air pressure from two static pressure plates during processing, and two grinding wheels simultaneously grind and thin the wafer on both sides. If the wheel angle does not match the silicon wafer shape, special morphologies will occur, such as… Figure 5 The B-ring and C-mark shown lead to the problem of inflated nano-morphology.

[0005] The grinding process involves using air pressure from two static pressure plates to fix the silicon wafer in the middle position. Figure 1 The silicon wafer is then rotated by a carrier ring at a speed of 30 r / min; the grinding wheel rotates at high speed via the spindle at a speed of 4000 r / min, continuously approaching the silicon wafer to achieve a thinning effect. Figure 2 Ideally, the silicon wafer and grinding wheel remain parallel, achieving uniform removal in the middle of the static pressure plate. Figure 4 As shown in a); in reality, the shape of silicon wafers that are wire-cut upstream cannot be kept absolutely flat, and there will generally be a large warp, which is usually characterized by the Warp value (warp degree) and the Bow value (bending degree); if the positive (negative) BOW silicon wafers are processed directly without adjustment, the action of the left and right grinding wheels on the silicon wafer will be uneven ( Figure 4 As shown in b and c), B-ring or C-mark problems occur; as the grinding wheel wears and deviates, the problem becomes more and more serious in subsequent processing; usually, the warpage of the silicon wafer is measured first during processing, and then the grinding wheel tilt angle is adjusted; this process requires a very high level of skill from the technicians, and each processing batch must be confirmed, which consumes a lot of dummy wafers. The different levels of skill of the technicians will also lead to different debugging and confirmation times, affecting production efficiency. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for improving the flatness and surface micro-nano morphology of silicon wafers.

[0007] The technical solution of the present invention is as follows: A method for improving the flatness and surface micro / nano morphology of silicon wafers, comprising the following steps: S1. Set at least three sensors on the static pressure plate to measure the distance between the sensor and the silicon wafer, corresponding to at least three radial positions r1, r2, and r3 from the outside to the inside of the silicon wafer region. Rotate the silicon wafer at least one revolution and measure the distance between the sensor and the silicon wafer to obtain the warp and BOW before silicon wafer processing, denoted as Wp. 前 and Bp 前 ; S2, based on the vertical tilt angle VH and Bp of the grinding wheel 前 Based on the relationship, the required vertical tilt angle of the grinding wheel is calculated and then automatically adjusted; S3. Perform double-sided grinding on the silicon wafer; S4. After the double-sided grinding process is completed, the silicon wafer is rotated at least one revolution, and the gap between the wafer and the sensor is measured to obtain the Warp and BOW of the silicon wafer after the double-sided grinding process, which are recorded as Wp. 后 and Bp 后 ; S5. Define the Warp difference between positions r1 and r2 as PV1, and the Warp difference between positions r2 and r3 as PV2. Calculate PV2 before processing 前 and processed PV2 后 The difference in value is used to determine whether there is a C-Mark risk. When the difference in value |△| < 5μm, it is determined that there is no C-Mark risk; otherwise, it is determined that there is a C-Mark risk. Before processing PV1 前 and processed PV1 后 The value difference is used to determine whether there is a B-ring risk. When the absolute value of the value difference is less than 4.5 μm, it is considered that there is no B-ring risk; when the absolute value of the value difference is greater than 4.5 μm, it is considered that there is a B-ring risk. S6. When there is a C-Mark risk, the machine alarms and processing is suspended. The grinding wheel position is then manually adjusted and confirmed. When there is a risk of B-ring, if the Bp of the silicon wafer... 后 To make it positive, adjust the left grinding wheel to the left. If the Bp of the silicon wafer is positive... 后 If the value is negative, adjust the right grinding wheel to the right.

[0008] In a further scheme, in step S1, the three positions corresponding to the three sensors are r1=145mm, r2=100mm, and r3=10mm.

[0009] In a further embodiment, in step S1, the silicon wafer rotates at 60 r / min for 5 seconds.

[0010] In a further proposed solution, the double-sided grinding process is divided into at least two stages. In the first stage, the grinding wheel removes deeper waveness from the silicon wafer surface using a relatively high feed rate. In the second stage, a relatively low feed rate thins the silicon wafer while ensuring surface flatness. In a further embodiment, in step S3, the first stage grinding wheel feed speed is 100 μm / min, the grinding wheel rotation speed is 4000 r / min, and the silicon wafer rotation speed is 30 r / min.

[0011] In a further embodiment, in step S3, the second stage grinding wheel feed speed is 60 μm / min, the grinding wheel rotation speed is 4000 r / min, and the silicon wafer rotation speed is 30 r / min.

[0012] In a further embodiment, in step S4, the silicon wafer rotates at 60 r / min for 5 seconds.

[0013] The beneficial effects of this invention are: This invention measures the warpage data of silicon wafers before and after processing using sensors to determine the presence of B-ring and C-mark risks. Based on this, the angle and position of the grinding wheel are adjusted, reducing the occurrence of special shapes (referring to C-mark and B-ring morphologies) caused by grinding. This plays an important role in improving the process level, while also reducing the requirements for technicians on the manufacturing site and improving production efficiency.

[0014] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0015] Figure 1 This is a schematic diagram showing the positional relationship between the static pressure plate, the silicon wafer, and the grinding wheel in this invention.

[0016] Figure 2 This is a schematic diagram illustrating the installation method of the silicon wafer and the position of the grinding wheel during silicon wafer grinding in this invention.

[0017] Figure 3 This is a schematic diagram showing the position of the sensor in this invention.

[0018] Figure 4 This is a schematic diagram showing the positional relationship between the silicon wafer and the grinding wheel during silicon wafer grinding in this invention.

[0019] Figure 5 This is a schematic diagram of the B-ring or C-mark morphology in this invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0021] like Figures 1-4 This invention installs three sensors in the middle of the static pressure plate to measure the gap distance. When the three sensors are working, the corresponding wafer areas (r=0~150mm) are r1=145, r2=100, and r3=10. Figure 3 At the start of processing, the carrier ring first rotates the silicon wafer at 60 r / min for 5 seconds (5 revolutions in 5 seconds). During the rotation, the sensor collects the gap distance data of r1, r2, and r3 in the circumferential direction, and further obtains the warp and BOW of the silicon wafer before processing, which are denoted as Wp. 前 and Bp 前 .

[0022] By the vertical tilt angle VH and Bp of the grinding wheel 前 After the relationship calculation, the grinding wheel tilt angle is automatically adjusted according to the calculation results to the vertical tilt angle VH of the grinding wheel (i.e., the tilt angle of the silicon wafer relative to the vertical direction of the silicon wafer, which is adjustable on the machine). After adjustment, double-sided grinding begins. In order to better eliminate surface defects and make the surface smoother and flatter, the double-sided grinding process is divided into two stages; in the first stage, the grinding wheel feed speed is 100μm / min, the grinding wheel speed is 4000r / min, and the wafer speed is 30r / min; the first stage mainly removes the deeper waveness on the surface (referring to the surface ripples after wire cutting in silicon wafer processing) by using a larger feed speed; in the second stage, the grinding wheel feed speed is 60μm / min, the grinding wheel speed is 4000r / min, and the wafer speed is 30r / min; the second stage mainly thins the surface while ensuring surface flatness.

[0023] After processing, the carrier ring first rotates the silicon wafer at 60 r / min for 5 seconds. The sensor acquires the warp and BOW of the wafer after processing, which are recorded as Wp. 后 and Bp 后 ; Define the warp difference between positions r1 and r2 as PV1, and the warp difference between positions r2 and r3 as PV2; Calculate PV2 before processing 前 and processed PV2 后 The difference in value is used to determine whether there is a C-Mark risk. When the difference in value |△| < 5μm, it is determined that there is no C-Mark risk; otherwise, it is determined that there is a C-Mark risk, the machine alarms, processing is suspended, and the grinding wheel position is adjusted and confirmed manually. In grinding, in addition to ensuring that the wafer is parallel to the grinding wheel, it is also necessary to ensure that the wafer is positioned both in the middle of the grinding wheel and on the central axis of the grinding wheel. If the wafer is not on the central axis of the grinding wheel, such as if the wafer is offset to the left of the central axis of the grinding wheel, the left side of the grinding wheel will contact the wafer first during grinding, resulting in uneven removal of material on the right and left sides of the wafer under the specified processing conditions. This ultimately manifests as an upward curling of the outer ring, i.e., the B-ring problem.

[0024] This invention determines whether a B-ring has occurred after each wafer is machined by the PV1 value difference and adjusts the grinding wheel position accordingly, ensuring that the wafer remains on the grinding wheel's central axis throughout the machining process. Before machining, the PV1 value difference... 前 and processed PV1 后 If the absolute value of the difference is less than 4.5μm, the wafer is located near the processing center (ideally, the silicon wafer is located in the middle of two grinding wheels and parallel to the two grinding wheels, and the processing center is the location where the processed product has no defects), it is judged to have no B-ring risk.

[0025] Before processing PV1 前 and processed PV1 后 When the absolute value of the difference is greater than 4.5, the wafer deviates from the processing center, indicating a risk of B-ring. If Bp 后 To be positive, the left grinding wheel needs to be adjusted to the left (horizontal direction). When Bp 后 If the value is negative, adjust the right grinding wheel to the right.

[0026] The above methods significantly reduce the occurrence of special shapes caused by the grinding process, while also reducing the demands on technicians in the manufacturing area and improving production efficiency.

[0027] The above description is only a specific embodiment of the present invention, but the structural features of the present invention are not limited thereto. Any changes or modifications made by those skilled in the art within the scope of the present invention are covered by the patent scope of the present invention.

Claims

1. A method for improving the flatness and surface micro / nano morphology of silicon wafers, characterized in that, Includes the following steps: S1. Set at least three sensors on the static pressure plate to measure the distance between the sensor and the silicon wafer, corresponding to at least three radial positions r1, r2, and r3 from the outside to the inside of the silicon wafer region. Rotate the silicon wafer at least one revolution and measure the distance between the sensor and the silicon wafer to obtain the warp and BOW before silicon wafer processing, denoted as Wp. 前 and Bp 前 ; S2, based on the vertical tilt angle VH and Bp of the grinding wheel 前 Based on the relationship, the required vertical tilt angle of the grinding wheel is calculated and then automatically adjusted; S3. Perform double-sided grinding on the silicon wafer; S4. After the double-sided grinding process is completed, the silicon wafer is rotated at least one revolution, and the gap between the wafer and the sensor is measured to obtain the Warp and BOW of the silicon wafer after the double-sided grinding process, which are recorded as Wp. 后 and Bp 后 ; S5. Define the Warp difference between positions r1 and r2 as PV1, and the Warp difference between positions r2 and r3 as PV2. Calculate PV2 before processing 前 and processed PV2 后 The difference in value is used to determine whether there is a C-Mark risk. When the difference in value |△| < 5μm, it is determined that there is no C-Mark risk; otherwise, it is determined that there is a C-Mark risk. Before processing PV1 前 and processed PV1 后 The value difference is used to determine whether there is a B-ring risk. When the absolute value of the value difference is less than 4.5 μm, it is considered that there is no B-ring risk; when the absolute value of the value difference is greater than 4.5 μm, it is considered that there is a B-ring risk. S6. When there is a C-Mark risk, the machine alarms and processing is suspended. The grinding wheel position is then manually adjusted and confirmed. When there is a risk of B-ring, if the Bp of the silicon wafer... 后 To make it positive, adjust the left grinding wheel to the left. If the Bp of the silicon wafer is positive... 后 If the value is negative, adjust the right grinding wheel to the right.

2. The method for improving the flatness and surface micro / nano morphology of silicon wafers according to claim 1, characterized in that, In step S1, at the three positions corresponding to the three sensors, r1=145mm, r2=100mm, and r3=10mm.

3. The method for improving the flatness and surface micro / nano morphology of silicon wafers according to claim 1, characterized in that, In step S1, the silicon wafer rotates at 60 r / min for 5 seconds.

4. The method for improving the flatness and surface micro / nano morphology of silicon wafers according to claim 1, characterized in that, In step S3, the double-sided grinding process is divided into at least two stages. In the first stage, the grinding wheel removes the deep waveness on the surface of the silicon wafer by using a relatively large feed speed. In the second stage, the silicon wafer is thinned by a relatively small feed speed while ensuring surface flatness.

5. The method for improving the flatness and surface micro / nano morphology of a silicon wafer according to claim 4, characterized in that, In the first stage, the grinding wheel feed speed is 100 μm / min, the grinding wheel speed is 4000 r / min, and the silicon wafer speed is 30 r / min.

6. The method for improving the flatness and surface micro / nano morphology of a silicon wafer according to claim 5, characterized in that, In the second stage, the grinding wheel feed speed is 60 μm / min, the grinding wheel speed is 4000 r / min, and the silicon wafer speed is 30 r / min.

7. The method for improving the flatness and surface micro / nano morphology of a silicon wafer according to claim 1, characterized in that, In step S4, the silicon wafer rotates at 60 r / min for 5 seconds.

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