Access control extension aiming at RISC-V access limited memory area and implementation method thereof

Abstract

The invention discloses an access control extension aiming at an RISC-V access limited memory area and an implementation method thereof, which comprises the following steps that: a user transmits a specified parameter to a system through calling a configuration instruction to specify a memory area range as an access limited area which is specially required to be protected and a trusted code area; after a system passes a series of parameter verification and environment check, storing corresponding configuration data in a specified area, updating a configuration state, and finally completing related configuration of the access limited area; after configuration is completed, the processor checks the access authorization state every time the memory is subjected to write access, and when it is found that codes outside the credible area currently are subjected to write access to the limited area, abnormity is thrown out; and otherwise, releasing the normal access of the current access. The configuration level of the access authorization state is divided into a global level and a local level, so that undifferentiated access control protection can be ensured, and additional protection services can be provided for individual requirements of certain processes.

Description

Technical Field

[0001] This invention relates to the field of computer processor technology, and in particular to an access control extension for RISC-V access to restricted memory regions and its implementation method. Background Technology

[0002] With the West imposing technological blockades in many key areas and the rising tide of domestic production, more and more open-source technologies and architectures are gaining support and adoption from numerous enterprises and institutions, with RISC-V being particularly prominent. RISC-V is an open-source processor instruction set architecture. Its strong scalability, low power consumption, modularity, and customizability have led to widespread research by many academic institutions and enterprises in China. Currently, the number of RISC-V extensions is enormous, allowing many manufacturers to develop entirely new extensions or select from existing ones to manufacture chips. In terms of the software ecosystem, compiler toolchains such as GCC and LLVM, as well as simulators like QEMU, GEM5, and SPIKE, all support the RISC-V architecture. Many of these software programs also benefit from open-source support, especially SPIKE. As the official RISC-V simulator, SPIKE not only continuously updates its software features along with the development of RISC-V, but its codebase is also publicly available on GitHub for future developers and researchers to reference and use.

[0003] In practical applications, kernel memory problems frequently occur, such as memory overflow, memory leaks, program memory overload, and memory fragmentation. These problems not only waste valuable memory resources but can also severely impact program efficiency and even lead to system malfunctions, sometimes resulting in system memory exhaustion and complete system crashes. To address these issues, numerous memory protection technologies have emerged, including memory access control (MACC) technology. MACC effectively prevents information leakage and tampering caused by malicious memory access by checking and restricting permissions and environmental context during each memory access, safeguarding critical information in the system from malicious read / write access.

[0004] With the advent of the digital economy era, data security has received increasing attention. As a critical resource for storing data, memory's security directly impacts the overall system security. Therefore, memory access control plays a crucial role, ensuring memory security by restricting certain memory read, write, and execution activities, identifying threats through behavioral analysis, and promptly reporting memory security behavior logs and alarm information. Summary of the Invention

[0005] To address the frequent problem of malicious memory access in current systems, this invention proposes an access control extension and its implementation method for restricted memory regions in RISC-V. Developed using C++ on the RISC-V official simulator SPIKE, the extension focuses on monitoring and adds several necessary control status registers and memory space partitioning layouts to help the system control write access to designated restricted regions. This effectively and promptly detects malicious write accesses and throws exceptions, thereby protecting the designated memory space.

[0006] This invention proposes an access control extension for RISC-V restricted memory regions and its implementation method. This extension focuses on a specified restricted memory region and is developed using the Spike simulator as the architectural foundation. The extension includes control status registers specifically tailored for restricted access control, page table entries and reuse of existing control status registers, memory space layout, configuration instructions, and a newly added access authorization check process. The method implements write access control for restricted memory regions through global and local level configuration and runtime checks, specifically including:

[0007] Through configuration instructions or system calls, parameters are configured for global / local access-restricted areas and trusted code areas respectively. After privilege level verification, parameter parsing and legality verification, the configuration information is stored in the corresponding register group or memory area and the status is updated.

[0008] Before each memory write access, the processor triggers a check process, performing global / local level checks based on the access address type to determine whether the accessed region is a restricted region and whether the source of the code is trustworthy. Normal memory access is only allowed if the check passes; otherwise, an exception is thrown.

[0009] In this invention, the customized control status register includes a status recording register and a program counter status register;

[0010] The status recording register records the following contents: Physical Memory Protection (PMP) register group reuse index and access-restricted status cache bits. These contents can play a role in state storage during the update and protection of access-restricted areas.

[0011] The program counter status register is used to store the physical address pointed to by the program counter when prefetching instructions, so as to check whether the currently executed instruction comes from trusted code during write access.

[0012] The control status register is mainly used to store a series of states after access authorization checks are enabled, so as to ensure the normal operation of access-restricted area protection.

[0013] The reuse of page table entries and existing control status registers is mainly used to store access-restricted memory regions specified during configuration, which facilitates access authorization control checks during memory access.

[0014] The memory space layout is a special address space that stores the location information of special trusted code regions. These trusted code regions have the privilege to access specified restricted regions in order to achieve special access to the restricted regions.

[0015] Configuration instructions are primarily used by the kernel to pass parameters when adding or deleting specified restricted / trusted regions, thereby ensuring more flexible configuration and protection of restricted regions.

[0016] The reuse of the customized page table entries and the existing control status registers are achieved by modifying the original page table entries and the existing control status registers respectively, so as to add the function of recording access-restricted states without affecting the original functions.

[0017] The reuse of page table entries means that for processes that need to perform address translation, some reserved bits are specified in the original page table entries to record whether the page pointed to is a restricted page.

[0018] The reuse of the existing control status registers means that, for the global system, the unused physical memory protection register group is used to record the location information of specific access-restricted areas.

[0019] In this invention, the customized memory space layout allocates a memory space (hereinafter referred to as the trusted location storage area) in the system to record trusted code location information of the content of the modifiable access-restricted region. This memory space can be divided into a trusted location storage area for locally (process) access-restricted regions and a trusted location storage area for globally access-restricted regions, wherein:

[0020] The trusted location storage area for locally (process-specific) restricted access regions serves only a single process, with each process having its own dedicated restricted access region. This storage space specifically stores trusted code location information that can write to and access the restricted access region of this process.

[0021] The trusted location storage area for globally restricted access regions serves the entire system. The system has a complete set of restricted access regions, which are independent of process-restricted access regions. This storage space stores trusted code location information that can be written to and accessed from the globally restricted access regions.

[0022] In this invention, the configuration instruction is the moncf instruction, which is used to configure the global / local (process) access-restricted region and trusted code region, including input register RS1, input register RS2 and an output register RD.

[0023] Input register RS1 is the starting address of the memory space containing the starting address and size of the restricted / trusted code region for storing records; input register RS2 contains storage operation option parameters, including add, delete, and clear; output register RD contains the result of the storage instruction execution (configuration success / failure and the reason for failure).

[0024] In this invention, the newly added access authorization check process is executed every time memory is accessed for writing. Each access authorization check first determines whether address translation is required for the current write access. If so, a local access authorization check is performed first, and a global access authorization check is performed only after the check passes; otherwise, a global access authorization check is performed directly. Only when all checks pass can the current write access proceed normally to the subsequent processes; otherwise, the current access fails and an exception is thrown.

[0025] In this invention, the global-level configuration process includes access-restricted region configuration and trusted code region configuration, specifically as follows:

[0026] Global access restricted area configuration: The moncf instruction is called by the kernel in M ​​mode or without address translation. After the processor verifies the privilege level (not lower than S mode) and the validity of the parameters, the configuration information is stored in the idle PMP register group and the PMP register group reuse index of the status record register is updated. If the PMP register group is full or the parameters are invalid, the configuration failure is returned.

[0027] Global trusted code region configuration: The moncf instruction is called by the kernel in M ​​mode or without address translation. After the processor verifies the privilege level and the validity of the parameters, the configuration information is stored in the global trusted location storage area, and the number of regions in the MAGIC segment is updated. If the storage area is full or the parameters are invalid, the configuration fails.

[0028] In this invention, the configuration process at the local level includes configuration of restricted access regions and trusted code regions, specifically as follows:

[0029] Local access-restricted region configuration: User-space processes pass parameters to the kernel via system calls, the kernel modifies the access-restricted bits of the corresponding page table entries, and returns the configuration result to the user process;

[0030] Local Trusted Code Region Configuration: User-mode processes pass configuration requests and parameters to the kernel via system calls. After obtaining the base address of the process's root page table, the kernel calls the moncf instruction. The processor verifies the privilege level and the validity of the parameters, stores the configuration information in the process's TR region, and updates the number of trusted regions recorded in the page table entry. If the TR region is full or the parameters are invalid, configuration failure is returned.

[0031] The global-level access authorization check process includes:

[0032] Step 1: Global-level memory write access begins, with the access address being the physical address; Step 2: Based on the PMP register group multiplexing index of the status record register, the corresponding PMP register group is traversed. If the area recorded in a register group matches the access address, it is determined to be an access-restricted area, and proceed to Step 3; otherwise, it is a normal memory area, the check ends, and normal memory access is performed.

[0033] Step 3: Access the global trusted location storage area. If the number of regions recorded in the MAGIC segment is 0, throw an exception; otherwise, compare the current PC physical address with all trusted region locations. If they match, access the storage normally; otherwise, throw an exception.

[0034] The local-level access authorization check process includes:

[0035] Step a: Perform address translation on the virtual address of the write memory access. When accessing the last-level page table, check the access restriction bit. If it is set to 1, it is an access-restricted page, and proceed to step b; otherwise, proceed to the global level check process.

[0036] Step b: Read the trusted code location information of the process's TR region and compare it with the current PC value. If they match, proceed to the global level check process; if they do not match, throw an exception for page table write access.

[0037] This invention also includes a memory region checking and access-restricted state caching mechanism:

[0038] Memory region check: When the memory management unit accesses memory, it verifies whether the translated physical address is within the trusted location storage area. If it is, and it is not a necessary comparison operation, an exception is thrown. During PMP check, PMP register groups used to record access-restricted areas are excluded, and page table entries storing TR physical addresses are excluded during address translation.

[0039] Restricted access state cache: Each time a process accesses memory, it updates the restricted access state of the accessed page to the cache and TLB, and records the state through a dedicated cache line and status bit.

[0040] This invention discloses an extension to access control for RISC-V restricted memory regions and its implementation method, comprising the following steps: The user passes specified parameters to the system via a configuration instruction to designate a memory region range as a restricted access region requiring special protection and a trusted code region. After a series of parameter verifications and environment checks, the system stores the corresponding configuration data in the specified region and updates the configuration status, ultimately completing the configuration of the restricted access region. After configuration, the processor checks the access authorization status each time it performs a write access to memory. If it finds that code outside the trusted region is attempting to write to the restricted access region, it throws an exception; otherwise, it allows normal memory access. The access authorization status configuration of this invention is divided into a global level and a local level, ensuring both indiscriminate access control protection and providing additional protection services for the personalized needs of certain processes, further satisfying the system's security and stability.

[0041] The access control extension and its implementation method for RISC-V access-restricted memory regions proposed in this invention have the following advantages:

[0042] This invention triggers an access authorization check before each memory write access, accurately identifies untrusted code's illegal write operations on restricted areas, and promptly throws exceptions, effectively preventing sensitive data from being tampered with or leaked, providing reliable protection for critical data in memory, and improving the memory security of RISC-V systems from the underlying architecture level.

[0043] This invention achieves uniform protection without discrimination through the PMP register group and the global trusted location storage area, ensuring the security of sensitive data at the system level; local protection is applied to individual processes, and through page table entry configuration and process-specific TR areas, it meets the personalized protection needs of different processes for specific memory regions, thus covering both global system security and adapting to process-differentiated scenarios.

[0044] This invention reuses unused PMP register groups and reserved bits of original page table entries, avoiding significant changes to the original RISC-V hardware architecture and instruction set; the newly added control status register and moncf instruction are compatible with the original system, the configuration process does not interfere with the original memory access logic, and the deployment and migration costs are reduced.

[0045] This invention avoids system malfunctions, program crashes, or system downtime caused by malicious memory operations by promptly intercepting illegal write accesses. At the same time, privilege-level verification and parameter validity verification during the configuration phase, as well as cache optimization at runtime, ensure the reliability of the protection mechanism while reducing additional performance overhead.

[0046] The access control extension of this invention is not subject to unauthorized access by low-privilege users, and the configuration interface is singular and only open to high-privilege users, thus avoiding the risk of the extension itself being tampered with or abused. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is the overall flowchart of the present invention for the extension of access control for RISC-V access to restricted memory regions.

[0049] Figure 2 This is a flowchart illustrating the overall configuration of the access control extension for RISC-V access to restricted memory regions in this invention.

[0050] Figure 3 This is a flowchart illustrating the global-level configuration of the access control extension for RISC-V access to restricted memory regions in this invention.

[0051] Figure 4 This is a flowchart illustrating the process-level configuration of the access control extension for RISC-V access to restricted memory regions according to the present invention.

[0052] Figure 5 This is a flowchart illustrating the overall access authorization check for the access control extension of the present invention for access-restricted memory regions in RISC-V.

[0053] Figure 6 This is a flowchart illustrating the global-level access authorization check process for the access control extension of RISC-V access to restricted memory regions in this invention.

[0054] Figure 7 This is a flowchart illustrating the process-level access authorization check for the extended access control for RISC-V access to restricted memory regions according to the present invention. Detailed Implementation

[0055] The invention will be further described in detail below with reference to the specific embodiments and accompanying drawings. Except for the contents specifically mentioned below, the processes, conditions, and experimental methods for implementing the invention are all common knowledge and general knowledge in the art, and the invention does not have any particular limitations.

[0056] This invention proposes an access control extension for restricted memory regions in RISC-V and its implementation method. The method first analyzes and summarizes the malicious write-to-memory access problems existing in restricted memory regions, considering the use of extensions to prevent such problems from the underlying architecture perspective. It also analyzes and proposes the necessary elements and main logic required for the new extension, proposing an access control extension without affecting the existing stable RISC-V extension architecture. The new extension is implemented in C++ on the official RISC-V architecture simulator SPIKE. Next, the logical and structural elements of the invention are refined, dividing the overall execution logic into two main parts: configuration and check execution. Access control-related elements include control status registers, related memory space and layout, and new configuration instructions. The execution logic and element components complement and depend on each other, jointly ensuring the security of sensitive data.

[0057] This invention proposes an extended implementation method for access control of restricted memory regions in RISC-V. The extension mainly aims to prevent and control the potential for system crashes caused by tampering in memory. By inserting necessary access checks of restricted regions during processor write accesses and promptly throwing an exception when untrusted code attempts to modify the content of the restricted region, the system is notified of potential malicious access risks in the restricted region, thereby improving the security of memory data.

[0058] To achieve precise access control, this invention divides the functional implementation into two levels: global access-restricted area access control and local (process) access-restricted access control. The implementation of each level can be divided into two parts: configuration and runtime checks.

[0059] The configuration requires configuring two zones: a restricted access zone and a trusted code zone. The former stores sensitive data and rejects modifications from untrusted sources, only accepting modifications from trusted code. The latter stores the trusted code specified during system configuration. The specific configuration steps for each zone at each level are as follows.

[0060] 1. Configuration of globally restricted access areas

[0061] Step 1: The user inputs the address space information and operation options that need to be specified as the restricted region into the input parameter register, and calls the moncf instruction to provide them to the processor;

[0062] Step 2: Upon receiving the configuration instruction, the processor first checks whether the current privilege level is appropriate. If it is, the parameters are parsed; otherwise, an instruction call exception is thrown.

[0063] Step 3: The system begins to parse and verify the parameters stored in the input parameter register. Only if the parameter configuration is valid and conforms to the current configuration status will the configuration be recorded and the configuration content be recorded in the corresponding PMP register group. The new access restricted area will take effect, and the system will return a configuration success after updating the status record register; otherwise, the system will return a configuration failure, and the configuration will be invalid.

[0064] Step 4: By accessing the return register in the parameters, the user can obtain the return result of this configuration and decide whether to continue configuring or reconfigure based on the error reason.

[0065] In the global-level configuration process of the access control extension and implementation method for RISC-V access-restricted memory regions described in this invention, step one includes:

[0066] The `moncf` instruction is used to configure access-restricted regions that require access control. The location information of these access-restricted regions is stored by the user in a memory space. The starting address of this memory space is then placed into one of the parameter registers. The operations performed on this location information are then placed into another parameter register. The operations are divided into addition, deletion, and clearing: When the operation is addition, the memory space of the first parameter register stores the starting address and size of the access-restricted region to be added; when the operation is deletion, the memory space of the first parameter register also stores the starting address and size of the access-restricted region to be deleted, representing the deletion of the access-restricted region that matches the parameter; when the operation is clearing, the first parameter register does not need to store any content, and all access-restricted regions are cleared directly.

[0067] In the global-level configuration process of the access control extension and implementation method for RISC-V access-restricted memory regions described in this invention, step two includes:

[0068] After receiving the instruction, the processor begins to check the current privilege level mode of the system. If the privilege level mode is lower than S mode, it is considered that the current operation is an unauthorized call to a privileged instruction by a low privilege level, and an instruction call exception is thrown; otherwise, it continues to parse the contents of the parameter register and selects an appropriate handling method.

[0069] In the configuration process of the access control extension for RISC-V access-restricted memory regions and its implementation method described in this invention, step three includes:

[0070] The system checks the input parameters, first examining the second parameter value: if it represents a clear operation, it directly clears all the contents of the PMP register set used to store restricted access areas and returns configuration complete; if it represents an add operation, it first checks if the PMP register set is full: it finds the actual stored content of the PMP register set corresponding to the index in the status record register. If the PMP register set already contains content, it means that the register set is already used for physical memory protection and cannot be used to store restricted access area location information. The PMP register set is full, and no new restricted access area configuration can be added. In this case, the system returns the configuration result: configuration failed, the available configuration register set is full. Otherwise, if the PMP register set pointed to by the index is found to be empty, it means there are spare register sets available to store the location of the restricted region. Then, the memory space of the first parameter is read, and the starting address and size of the restricted region are read from this space. After reading, it is compared with the trusted location storage area. If there is no overlapping part, it means that the content to be configured is valid and can be stored in the spare register set. After storing, the PMP register set reuse index in the status record register is updated to point to the next PMP register set, and finally, the configuration is returned as complete. If it represents a deletion operation, first check whether the PMP register set reuse index value in the status record register represents the first PMP register set used to record the location of the restricted region. If it is... If no PMP register set is found for accessing restricted regions, the system will return: Configuration failed, no register set exists for configuration. Otherwise, the system will read the starting address and size from the memory space specified in the first parameter, and start traversing from the first PMP register set used to record the location of the restricted region to the PMP register set pointed to by the PMP register set multiplexing index in the status record register. If a matching restricted region location is found, the value of the PMP register set containing it will be cleared, and the value of the subsequent PMP register sets will be shifted forward by one register set. Finally, the PMP register set multiplexing index in the status record register will be updated, and the system will return that the configuration is complete. If no matching region is found, the system will return: Configuration failed, target region not found.

[0071] 2. Configuration of process-level access restricted areas

[0072] Step 1: The user-mode process passes the parameters of the restricted pages to be set / cleared to the kernel via a system call;

[0073] Step 2: After receiving these parameters, whether the kernel needs to configure its own process or help a user process configure access-restricted areas, it will configure the PTE corresponding to the page and modify its permission bits. After the modification is completed, the configuration is finished, and the kernel will feed back the modified PTE as the configuration result to the user.

[0074] Step 3: After returning to the user process, subsequent user attempts to access the page will be treated as accessing a restricted page / normal page based on the previous configuration.

[0075] 3. Configuration of trusted zones at the global level

[0076] Step 1: The user inputs the address space information and operation options that need to be designated as trusted code regions into the input parameter register, and calls the moncf instruction to provide them to the processor;

[0077] Step 2: Upon receiving the configuration instruction, the processor first checks whether the current privilege level is appropriate. If it is, the parameters are parsed; otherwise, an instruction call exception is thrown.

[0078] Step 3: The system begins to parse and verify the parameters stored in the input parameter register. Only if the parameter configuration is valid and conforms to the current existing configuration state will the configuration be recorded and the configuration content be recorded in the trusted location storage area. The new trusted code area will take effect and the system will return a configuration success message. Otherwise, the system will return a configuration failure message and the configuration will be disregarded.

[0079] Step 4: By accessing the return register in the parameters, the user can obtain the return result of this configuration and decide whether to continue configuring or reconfigure based on the error reason.

[0080] In the global-level trusted region configuration process of the access control extension and implementation method for RISC-V access-restricted memory regions described in this invention, step one includes:

[0081] The `moncf` instruction is used to configure trusted regions. The location information of the trusted regions is stored by the user in a memory space. Then, the starting address of this memory space is placed into one of the parameter registers. The operations performed on this location information are then placed into another parameter register. The operations are divided into addition, deletion, and clearing: When the operation is addition, the memory space of the first parameter register stores the starting address and size of the trusted region to be added; when the operation is deletion, the memory space of the first parameter register also stores the starting address and size of the trusted region to be deleted, representing the deletion of a trusted region that matches the parameters; when the operation is clearing, the first parameter register does not need to store any content, and all restricted regions are cleared directly.

[0082] In the global-level trusted region configuration process of the access control extension and implementation method for RISC-V access-restricted memory regions described in this invention, step two is the same as step two of the global-level access-restricted region configuration, and will not be repeated here; step three includes:

[0083] The system checks the input parameters, first examining the second parameter value: if it represents a clear operation, it directly clears all the contents of the trusted region location information section in the trusted location storage area and returns configuration complete; if it represents an add operation, it first checks if the trusted region location information in the trusted location storage area is full: it checks the number of regions by checking the MAGIC segment at the beginning of the trusted location storage area. If the number of regions has reached the limit, no new trusted region configuration can be added. In this case, the system returns the configuration result: configuration failed, available configuration space is full; otherwise, it indicates that there is still space available to store trusted region locations. Then, the memory space of the first parameter is read. The starting address and size of the trusted region are read from this space and compared with the trusted location storage area. If there is no overlapping part, it means that the content to be configured is valid, and the trusted region location information can be added. After storing it, the number of MAGIC segment regions is updated, and finally, the configuration is returned as complete. If it represents a deletion operation, the count of MAGIC segment regions at the beginning of the trusted location storage area is checked first. If it is 0, it means that there is no trusted region, and the configuration is returned directly: configuration failed, no existing trusted region exists. Otherwise, the starting address and size are read from the memory space of the first parameter, and the count group of position information is traversed from the trusted region location information part. If a matching restricted access region position is found, the position information value is cleared, and the subsequent position information is moved forward by one unit length. Finally, the number of MAGIC segment regions is updated, and the configuration is returned as complete. If none of them are found, the configuration is returned as failed, the target deletion region was not found.

[0084] 4. Configuration of trusted regions at the process level

[0085] Step 1: The user-space process sends the request to configure a trusted zone, along with the location information of the trusted zone to be set / cleared, to the kernel via a system call;

[0086] Step 2: After receiving these parameters, whether the kernel needs to configure its own process or help the user process configure the trusted region, it will store these location information along with the root page table base address of the initiating process in a memory space, store the start address of this memory space and the operation to be performed in the input parameter register, and finally call the moncf instruction to send it to the processor to prepare for the configuration action.

[0087] Step 3: When the processor receives the configuration instruction, it first checks whether the current privilege level is appropriate. If it is, it then parses the parameters; otherwise, it throws an instruction call exception.

[0088] Step 4: The system begins to parse and verify the parameters stored in the input parameter register. Only if the parameter configuration is valid and conforms to the current existing configuration state will the configuration be recorded and the configuration content be recorded in the process-specific trusted location storage area (hereinafter referred to as TR). The new trusted code area takes effect and returns a configuration success; otherwise, the system returns a configuration failure and the configuration is not counted.

[0089] Step 5: By accessing the return register in the parameters, the user can obtain the return result of this configuration and decide whether to continue configuring or reconfigure based on the error reason.

[0090] In the process-level trusted region configuration process of the access control extension and implementation method for RISC-V access-restricted memory regions described in this invention, step one includes:

[0091] The kernel exposes the system call for configuring trusted regions to user-mode processes. User-mode processes can use this system call to send a request to the kernel, along with the location information of the trusted regions they need to modify, including the starting address and size, as well as the operations to be performed (add / delete / clear).

[0092] In the process-level trusted region configuration process of the access control extension and implementation method for RISC-V access-restricted memory regions described in this invention, step two includes:

[0093] The kernel can receive system calls from user-mode processes requesting configuration and invoke the `moncf` instruction to configure them. Kernel processes themselves can also invoke the `moncf` instruction to configure trusted zones when needed. The parameters provided when invoking the `moncf` instruction are similar to those in the previous configuration processes, but the memory space pointed to by the first parameter register needs to initially record the root page table base address of the process that actually needs to configure the trusted zone: for user-mode processes, the root page table base address is obtained from the context in the system call handler; for kernel processes, it is directly read from the `satp` control status register.

[0094] In the process-level trusted region configuration process of the access control extension and implementation method for RISC-V access-restricted memory regions described in this invention, step three is the same as step two of the global-level access-restricted region configuration, and will not be repeated here; step four includes:

[0095] The system first reads the root page table base address from the parameter register. Starting from the root page table base address, it finds the first page table entry of each level of page table to access the next level of page table, until the last level of leaf page table. Finally, it reads the lower 56 bits of the first page table entry as the TR physical address (the higher 7 bits represent the number of trusted regions). If a problem occurs when accessing the page table during this process, it indicates that the root page table base address provided in the parameters is incorrect, and a configuration failure is returned. Next, the system checks the input parameters. First, it checks the value of the second parameter: if it represents a clear operation, it directly clears all the contents of the trusted region location information in the TR and returns configuration complete; if it represents an add operation, it first checks whether the number of trusted regions is full. If the number of regions has reached the limit, no new trusted region configuration can be added. At this point, the configuration result can be returned: configuration failure, the available configuration space is full; otherwise, it means that there is still space available to store trusted region locations. Then, the memory space of the first parameter is read. The starting address and size of the trusted region are retrieved from this space and compared with the trusted location storage area. If there is no overlap, the configuration is valid, and the trusted region location information can be added. After storage, the number of trusted regions stored in the page table entry is updated, and finally, configuration completion is returned. If it represents a deletion operation, the number of trusted locations is checked first: if it is 0, it means there is no trusted region, and configuration fails because no trusted region exists. Otherwise, the starting address and size are read from the memory space of the first parameter, and the location information of the `count` group is traversed from the trusted region location information section. If a matching restricted access region location is found, the location information value is cleared, and the subsequent location information is shifted forward by one unit. Finally, the number of regions is updated, and configuration completion is returned. If no region is found, configuration failure is returned because the target region to be deleted was not found. In addition, the last-level page table here requires the kernel to map the first page table entry of the leaf page table to the TR during process creation; otherwise, errors will occur during configuration.

[0096] The runtime inspection process is divided into global and local (process) levels, and the inspection occurs before each memory write access. The main difference between the global and local levels is that memory access at the global level only uses physical addresses, while memory access at the local level requires translating the virtual address into a physical address through a page table before proceeding with memory access.

[0097] 5. The overall inspection process is as follows:

[0098] Step 1: Global-level memory write access begins; at this point, the accessed address is a physical address.

[0099] Step 2: Access the PMP register set multiplexing index value in the access status record register, and access the corresponding PMP register set according to the index value. Traverse from the current register set to the register set with the largest index. If the region location recorded in a register set during the traversal matches the currently accessed address, it means that the current access is a restricted region, and proceed to the next step to check whether the source of the code pointed to by the PC physical value is trusted code; otherwise, if all register sets do not match the current access address, it means that the access is a normal memory region, end the check, and normal memory access can be performed.

[0100] Step 3: Access the trusted location storage area. Check the number of MAGIC segment regions (count) at the beginning of the trusted location storage area. If it is 0, it means there is no trusted region at present, and an exception write access is thrown directly. Otherwise, access the trusted region locations of count records according to the count value and compare them with the physical address of the current PC. If the physical address of the PC matches the location information of a trusted region, it means that there is a trusted code accessing a restricted region, and normal storage access can be performed. The check ends. Otherwise, if none of the count regions match, it means that the current code comes from untrusted code, and an exception write access is thrown.

[0101] 6. The local (process) level inspection process is as follows:

[0102] Step 1: Perform address translation on the virtual address of the write memory access. When accessing the last level page table, check if its access restriction bit is set to 1. If it is, it means that the corresponding page is an access-restricted page and needs to be checked in the next trusted code step. Otherwise, it means that this page is not an access-restricted page at the process level and directly enters the global level check step 1 to continue the subsequent checks.

[0103] Step 2: Check if the current PC value matches a trusted code location information in TR. If it matches, it means that trusted code at the process level is accessing the process-level access-restricted area, and proceed to Step 1 of the global level check to continue the subsequent checks; otherwise, it means that the code accessing the access-restricted area is not trusted, and throw an exception page table write access.

[0104] In the scanning process of the access control extension for RISC-V access-restricted memory regions and its implementation method described in this invention, step two includes:

[0105] Starting from the root page table base address, the system finds the first page table entry in each level of the page table and accesses the next level page table until it reaches the last level leaf page table. Finally, it reads the lower 56 bits of the first page table entry as the TR physical address and takes the higher 7 bits as the number of trusted regions. It reads the location information of all trusted regions from the TR and compares it with the current PC value. Only when the PC value matches the location information of a trusted region does it mean that the access control check for accessing the restricted region at the process level has been passed, and then it enters the global level check; otherwise, it means that the current code may be at risk of maliciously tampering with the content of the restricted region, and an exception will be thrown directly for the kernel to handle.

[0106] In addition to the two main processes of configuration and scanning mentioned above, this invention expands upon SPIKE by adding several components. For example, it adds memory region checking during the memory management unit addressing process, access-restricted state caching during memory access, new configuration instructions, and new control status registers. Specifically:

[0107] The memory region check involves examining the translated physical address when the memory management unit accesses memory. If the accessed memory is outside the trusted location storage area, the memory access will not affect the normal operation of access control and will proceed as a normal memory access. Otherwise, the memory access itself is unsafe (except for memory access performed during necessary comparison operations in the access control check), and an exception is thrown directly. A PMP check is performed during each memory access. Since part of the PMP register set is used to record the location information of the access-restricted region, when reading the PMP register set for PMP check, the PMP register set used to record the access-restricted region will be excluded based on the PMP register set reuse index in the status record register. In addition, when using page table translation, the page table entry used to store the TR physical address also needs to be excluded. Therefore, the kernel needs to allocate a fixed memory space when the process is created and store the starting address in the lower 56 bits of the page table entry, and does not allow the process to access any address of the page containing 0x0, ensuring that no process will cause an access exception due to accessing this address.

[0108] The access-restricted status cache for memory access refers to the process updating the access-restricted status of the page to be accessed to the cache and TLB (Translation Lookaside Buffer) every time it accesses memory. At the same time, special status bits are reserved in the cache line and TLB table to record the access-restricted status. This way, the access-restricted status of the current access address can be determined even when the address does not need to be translated by the memory management unit.

[0109] The new monitor configuration command, namely the moncf command mentioned above, has already indicated its purpose and command process, and will not be elaborated further here;

[0110] The new control status register includes a status record register and a program count status register. The status record register records a PMP register set multiplexing index, used to record the boundaries of PMP checks and access-restricted region records within the PMP register set; and a temporary storage bit used during the page table entry access-restricted status update to the cache / TLB, whose function, as the name suggests, temporarily stores the access-restricted status and is reset to zero after the update to the cache / TLB. The program count status register records the physical value corresponding to the current PC storage address and is specifically used to compare globally trusted regions during global access authorization checks.

[0111] The present invention proposes an access control extension for RISC-V access-restricted memory regions. This extension is not subject to access by any user with low privilege level, has a single configuration interface, ensures its independence and security, and the protected access-restricted regions can be flexibly configured, are compatible with the original system without conflict, and have the characteristics of compatibility, flexibility and modularity.

[0112] The element component mainly consists of a control status register, related memory space and its layout, and dedicated configuration instructions. Among them:

[0113] The monitor's control status register includes two control status registers: a status record register and a program counter status register. Wherein:

[0114] The status record register records some necessary states. It mainly records the limits of PMP checks and access-restricted region records in the PMP register group, as well as temporary storage bits during the process of updating page table entry access-restricted states to the cache / TLB.

[0115] The program counter status register is specifically used to record the physical value corresponding to the current PC storage address and to compare the global trusted region during global access authorization checks.

[0116] The relevant memory space and its layout: the system allocates a region in memory specifically for use as a trusted location storage area.

[0117] The monitor-specific configuration instruction, namely the moncf instruction, is an R-type instruction. It accepts two input parameter registers, RS1 and RS2, which store a space and the operation to be performed. The space stores the starting address and size of the access-restricted / trusted region to be operated on; and the RD destination output register is used to store the configuration result after the instruction is called.

[0118] like Figure 1 As shown, the present invention includes the following steps in its application:

[0119] Step 1: (Configuration Process) The system / process configures instruction parameters according to its own needs and passes these parameters to the processor by calling configuration instructions. After receiving the instruction, the processor checks the current state and the validity of the parameters;

[0120] Step Two: (Configuration Process) After confirming that the parameters are correct, configure the corresponding memory regions / control status registers. Once the configuration of the PMP register group / page table entry / trusted region location storage memory / user process memory is completely correct, the system will update the corresponding effective regions and enable access control during the first configuration, which will then take effect during subsequent normal operation.

[0121] Step 3: (Check Process) The processor triggers the check process every time a memory write access is performed. Based on the current system environment and conditions, it first accesses the PMP register set / page table entry to compare the memory address being accessed. If the two match, it means that the current access is to a restricted area, and then it starts to check whether the source of the code is trustworthy; otherwise, it means that the access is to a normal memory area, and normal memory access can be performed.

[0122] Step 4: (Check Process) After confirming that the current access is to a restricted area, start accessing the trusted area location storage memory / user process memory and compare the current PC value. When the two match, it means that the current access to the restricted area is by trusted code and memory access can be performed normally; otherwise, it means that the current access to the restricted area is by untrusted code and will trigger a write memory access exception.

[0123] The configuration process can be further divided into global-level configuration and local-level configuration, such as... Figure 2 As shown.

[0124] At the global level, the restricted and trusted regions are configured by calling the `moncf` instruction. Specifically, this instruction configures the restricted region by setting the PMP register set and configures the trusted code region by writing to the trusted location storage area. At the local level, the configuration of restricted and trusted regions differs. Specifically, the process configures the restricted region by requesting the kernel to set the restricted status bit of the page table entry through a system call, and configures the trusted code region by calling the `moncf` instruction to store the trusted code location information in the process's TR region.

[0125] The global-level configuration is as follows Figure 3As shown. First, there's the configuration of restricted access regions. In M-mode / (address translation-free) kernel, the `moncf` instruction is called to pass parameters to the processor. Upon receiving the instruction, the processor parses the parameters and checks the usage of the PMP register set. If there are free PMP register sets, the parameters are filled into the corresponding PMP register set, the PMP register set reuse index in the status record register is updated, and finally, configuration success is returned; otherwise, configuration failure is returned. Second, there's the configuration of trusted code regions. Similarly, in M-mode / (address translation-free) kernel, the `moncf` instruction is called to pass parameters to the processor. Upon receiving the instruction, the processor parses the parameters and checks the usage of trusted location storage areas. If there is remaining space, the parameters are filled into the remaining space, the number of trusted regions is updated, and finally, configuration success is returned; otherwise, configuration failure is returned.

[0126] The local level configuration is as follows: Figure 4 As shown. First, the restricted access region is configured. When the page table is created, the kernel process sets the restricted access status bit of the corresponding page table entry for the current page according to the attached permission parameters, and returns a successful configuration. Second, the trusted code region is configured. Similarly, the kernel process calls the moncf instruction to pass parameters, and then the processor parses the parameters and checks the TR region where the process stores the trusted code location: if there is still space in the TR, the memory management unit accesses the TR region, stores the new trusted code region location information in the TR region, updates the corresponding page table entry information, and returns a successful configuration; otherwise, it returns a configuration failure.

[0127] The inspection process, such as Figure 5 As shown, the checks can be divided into global-level checks and process-level checks. Specifically, the process first determines whether to proceed to a process-level check or a global-level check by determining whether the current memory access address is a physical address. If the current address is not a physical address, the process-level check is initiated. If the check fails, the access is deemed to have failed and an exception is thrown. Otherwise, the process proceeds to a global-level check. Similarly, if the global-level check fails, the access is deemed to have failed and an exception is thrown. Otherwise, the access is deemed successful and memory is accessed normally. If the current address is a physical address, the process can proceed directly to a global-level check.

[0128] The global-level checks, such as Figure 6As shown, this process occurs during physical address memory access (either address access without translation or physical address access obtained through address translation). First, the PMP register set is checked: it determines whether the current access location is in a restricted region. If so, it checks whether the trusted location memory area matches the PC physical address. Only if they match can memory be accessed normally; otherwise, it indicates untrusted code accessing the restricted region and throws an exception write memory access. If it is not in a restricted region, it means the access is to a normal memory area, and normal memory access is possible.

[0129] The process-level checks, such as Figure 7 As shown, this process occurs when address translation via page tables is required. First, the access-restricted status bit in the page table entry is checked to determine if the page pointed to by the entry is an access-restricted page. If not, the translated physical address is used to enter the global-level check; otherwise, the process's TR region is accessed, and the location of the trusted code stored therein is compared with the current PC value. If they do not match, it indicates untrusted code has accessed the restricted region, and an exception write access is thrown. Otherwise, the process-level check ends, and the translated physical address is used to enter the global-level check.

[0130] Example

[0131] This example uses Figure 6 Taking the global check process shown as an example, this paper simulates and analyzes the access authorization check during a memory write access after configuring a globally restricted area and a trusted area. The test cases are designed as follows:

[0132] The restricted access zone is set to address 0x80090000, size 0x1000, PMP register group index 63, and there is only one restricted access zone globally. The PMP register group multiplexing index value recorded in the status log register is 62. The trusted zone is set to address 0x30001000, size 0x304, and stored in the trusted location storage area. There is only one trusted zone globally.

[0133] When the PC points to 0x30000800 and attempts to write memory to 0x80090008, a global check is triggered. The system first checks whether the access address 0x80090008 is in a restricted region: It obtains the first PMP register group for recording restricted regions by incrementing the PMP register group multiplexing index value recorded in the status record register by 1. It then traverses this register group up to the maximum index value 63, comparing the restricted region recorded in each register group with the currently accessed address. In this example, the restricted region ranges from 0x80090000 to 0x800a0000, and the access address is 0x80090008, which is within the restricted region. Next, it determines whether the PC physical address is in a trusted region. It accesses the trusted location storage area and compares it with the current PC physical address. In this example, the trusted region ranges from 0x30001000 to 0x30001304, while the PC physical address is 0x30000800, which is not in a trusted region. This indicates that the access to the restricted region is being made by untrusted code. At this point, an exception is thrown: Write Memory Access Exception. The processor catches the exception and then jumps to the corresponding exception handler for processing. The exception handler is beyond the scope of this patent and will not be elaborated on further.

[0134] The key point of this invention is to propose an access control extension for restricted memory regions in RISC-V and its implementation method. It successfully performs write access permission checks on the memory regions specified in the example and promptly identifies potential tampering threats and throws exceptions, which helps to provide guarantees for RISC-V memory security, further confirms the security and stability of the system running on RISC-V, and enhances the architecture of the RISC-V memory protection mechanism to be more secure and reliable when the user has the option.

[0135] The scope of protection of this invention is not limited to the above embodiments. Any variations and advantages that can be conceived by those skilled in the art without departing from the spirit and scope of the inventive concept are included in this invention and are protected by the appended claims.

Claims

1. An access control extension for RISC-V access to restricted memory regions and its implementation method, characterized in that, The extension, with access control for specified restricted regions as its core objective, is developed based on the RISC-V official simulator SPIKE architecture. The extension includes control status registers, reuse of page table entries and existing control status registers, memory space layout, configuration instructions, and a newly added access authorization check process. The method implements write access control for restricted regions through global and local level configuration and runtime checks, specifically including: Through configuration instructions or system calls, parameters are configured for global / local access-restricted areas and trusted code areas respectively. After privilege level verification, parameter parsing and legality verification, the configuration information is stored in the corresponding register group or memory area and the status is updated. Before each memory write access, the processor triggers a check process, performing global / local level checks based on the access address type to determine whether the accessed region is a restricted region and whether the source of the code is trustworthy. Normal memory access is only allowed if the check passes; otherwise, an exception is thrown.

2. The access control extension and its implementation method according to claim 1, characterized in that, The control status register includes a status recording register and a program counter status register, wherein: The status record register records the PMP register group multiplexing index and access-restricted status cache bits, and is used for status storage during access-restricted area updates and protection processes. The program counter status register stores the physical address pointed to by the program counter during instruction prefetching and is used to verify whether the currently executing instruction originates from trusted code during write access.

3. The access control extension and its implementation method according to claim 1, characterized in that, The page table entry reuse is used for processes that require address translation, utilizing some reserved bits of the original page table entry to record whether the corresponding page is an access-restricted page; The existing control status register is reused to record the location information of globally access-restricted areas using the underutilized PMP register set.

4. The access control extension and its implementation method according to claim 1, characterized in that, The memory space layout includes a partitioned trusted location storage area, which is divided into: Global Trusted Location Storage Area: Provides global services for the system, stores trusted code location information for globally restricted areas that can be writably accessed, and includes a MAGIC segment to record the number of trusted areas; Local Trusted Location Storage Area: This area is dedicated to a single process and stores the location information of trusted code that can be written to and accessed by the process in restricted areas. Its physical address is obtained from the lower 56 bits of the first page table entry of the last-level leaf page table of the process, while the higher 7 bits record the number of trusted areas.

5. The access control extension and its implementation method according to claim 1, characterized in that, The configuration instruction is the moncf instruction, which is an R-type instruction. It includes an input register RS1, an input register RS2, and an output register RD, wherein: The input register RS1 is the starting address of the memory space that stores the starting address and size of the restricted / trusted code region for storing records. The input register RS2 stores operation option parameters, including add, delete, and clear. The output register RD stores the result of the instruction execution.

6. The access control extension and its implementation method according to claim 1, characterized in that, The global configuration process includes configuration of restricted access zones and trusted code zones, specifically as follows: Global access restricted area configuration: The moncf instruction is called by the kernel in M ​​mode or without address translation. After the processor verifies the privilege level and the validity of the parameters, the configuration information is stored in the idle PMP register group, and the PMP register group reuse index of the status record register is updated. If the PMP register group is full or the parameters are invalid, the configuration failure is returned. Global trusted code region configuration: The moncf instruction is called by the kernel in M ​​mode or without address translation. After the processor verifies the privilege level and the validity of the parameters, the configuration information is stored in the global trusted location storage area, and the number of regions in the MAGIC segment is updated. If the storage area is full or the parameters are invalid, the configuration fails.

7. The access control extension and its implementation method according to claim 1, characterized in that, The local-level configuration process includes access-restricted region configuration and trusted code region configuration, specifically as follows: Local access-restricted region configuration: User-space processes pass parameters to the kernel via system calls, the kernel modifies the access-restricted bits of the corresponding page table entries, and returns the configuration result to the user process; Local Trusted Code Region Configuration: User-mode processes pass configuration requests and parameters to the kernel via system calls. After obtaining the base address of the process's root page table, the kernel calls the moncf instruction. After the processor verifies the privilege level and the validity of the parameters, it stores the configuration information in the process's TR region and updates the number of trusted regions recorded in the page table entry. If the TR area is full or the parameters are invalid, the configuration will fail.

8. The access control extension and its implementation method according to claim 1, characterized in that, The global-level access authorization check process includes: Step 1: Global-level memory write access is initiated, and the access address is the physical address; Step 2: Based on the PMP register group multiplexing index of the status record register, traverse the corresponding PMP register group. If the area recorded in a register group matches the access address, it is determined to be an access-restricted area, and proceed to Step 3; otherwise, it is a normal memory area, the check ends and normal memory access is performed. Step 3: Access the global trusted location storage area. If the number of regions recorded in the MAGIC segment is 0, throw an exception; otherwise, compare the current PC physical address with all trusted region locations. If they match, access the storage normally; otherwise, throw an exception.

9. The access control extension and its implementation method according to claim 1, characterized in that, The local-level access authorization check process includes: Step a: Perform address translation on the virtual address of the write memory access. When accessing the last-level page table, check the access restriction bit. If it is set to 1, it is an access-restricted page, and proceed to step b; otherwise, proceed to the global level check process. Step b: Read the trusted code location information of the process's TR region and compare it with the current PC value. If they match, proceed to the global level check process; if they do not match, throw an exception for page table write access.

10. The access control extension and its implementation method according to claim 1, characterized in that, It also includes memory region checking and access-restricted state caching mechanisms: Memory region check: When the memory management unit accesses memory, it checks whether the translated physical address is within the trusted location storage area. If it is, and it is not a necessary comparison operation, an exception is thrown. During PMP checks, PMP register sets used for recording restricted access regions are excluded; during address translation, page table entries storing TR physical addresses are excluded. Restricted access state cache: Each time a process accesses memory, it updates the restricted access state of the accessed page to the cache and TLB, and records the state through a dedicated cache line and status bit.

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