A method and system for dynamic allocation of data buffer for T / R chips

Abstract

The application relates to the technical field of radio frequency communication, and discloses a T / R chip data cache dynamic allocation method and system.The method comprises the following steps: obtaining a task queue of target chip data, and performing structured analysis to obtain task parameters; performing task-oriented division according to the task parameters to obtain an initial cache quota scheme; performing self-adaptive decomposition on the target chip data to obtain a characteristic basis vector, and performing sparse coding based on the characteristic basis vector to obtain a dynamic decision of the target chip data; performing strategy optimization on the initial cache quota scheme according to the dynamic decision to obtain an optimized cache quota scheme; performing space configuration on target cache resources of the target chip data according to the optimized cache quota scheme to obtain a storage result; performing performance evaluation on the storage result to obtain a cache performance benchmark value, and determining a final cache quota scheme based on the cache performance benchmark value; and the application can improve the T / R chip data cache allocation efficiency.

Description

Technical Field

[0001] This invention relates to the field of radio frequency communication technology, and in particular to a method and system for dynamic allocation of data buffer in a T / R chip. Background Technology

[0002] Existing cache allocation technologies mostly use fixed rules to set quota schemes, which cannot accurately adapt to dynamically changing task loads. This leads to a disconnect between cache resource allocation and actual needs, resulting in resource redundancy in some logical partitions and resource shortages in others. At the same time, traditional technologies do not extract data features deeply enough, making it difficult to accurately capture the core attributes of the data. This results in unreasonable cache address mapping, which easily leads to conflicts and delays during data read and write processes, affecting the overall processing smoothness.

[0003] Traditional technologies lack real-time monitoring and dynamic adjustment mechanisms for cache operation, failing to respond promptly to changes in task queues and load fluctuations. This results in difficulty improving cache hit rates and maintaining low resource utilization. Furthermore, the failure to effectively eliminate interference from correlations between features during data processing leads to insufficient accuracy in subsequent decision-making, further reducing the scientific rigor and effectiveness of cache allocation. Therefore, improving the data cache allocation efficiency of T / R chips has become an urgent problem to be solved. Summary of the Invention

[0004] This invention provides a method and system for dynamic allocation of data cache in T / R chips to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides a dynamic allocation method for T / R chip data buffer, comprising:

[0006] S1. Obtain the task queue of target chip data, and perform structured parsing on the task queue to obtain the task parameters of the target chip data;

[0007] S2. Based on the task parameters, the target chip data is divided into task-oriented partitions to obtain logical partitions of the target chip data, and capacity quota planning is performed on the logical partitions to obtain the initial cache quota scheme of the target chip data.

[0008] S3. Adaptively decompose the target chip data to obtain the feature basis vector of the target chip data, and perform sparse encoding on the target chip data based on the feature basis vector to obtain the sparse coefficient vector of the target chip data, so as to obtain the dynamic decision of the target chip data.

[0009] S4. Based on the dynamic decision, optimize the initial cache quota scheme to obtain an optimized cache quota scheme for the target chip data;

[0010] S5. Based on the optimized cache quota scheme, the target cache resources of the target chip data are configured in space to obtain the storage result of the target chip data;

[0011] S6. Evaluate the performance of the storage results to obtain the cache performance benchmark value of the target chip data, and determine the final cache quota scheme of the target chip data based on the cache performance benchmark value.

[0012] In a preferred embodiment, the task queue for acquiring target chip data, and the structured parsing of the task queue to obtain task parameters for the target chip data, include:

[0013] Content extraction is performed on the task queue of the target chip data to obtain the task description of the target chip data;

[0014] Based on the task description, bit field mapping is performed on the task queue to obtain the original task tuple of the task queue;

[0015] The original task tuple is subjected to time-frequency domain dual feature extraction to obtain the time-frequency domain feature representation of the original task tuple;

[0016] Based on the time-frequency domain feature representation, the original task tuple is parameter-normalized to obtain the task parameters of the target chip data.

[0017] In a preferred embodiment, the step of performing task-oriented partitioning of the target chip data according to the task parameters to obtain logical partitions of the target chip data, and performing capacity quota planning on the logical partitions to obtain an initial cache quota scheme for the target chip data, includes:

[0018] The task parameters are deconstructed and analyzed to obtain the basis for dividing the task parameters;

[0019] Based on the aforementioned division criteria, the target chip data is aggregated into tasks to obtain similar attribute task clusters of the target chip data;

[0020] The target chip data is logically partitioned by dividing the similar attribute task clusters by boundaries.

[0021] The load is evaluated on the logical partition to obtain the concurrency characteristics of the target chip data;

[0022] Based on the concurrency characteristics, capacity is allocated to the logical partition to obtain the initial cache quota scheme for the target chip data.

[0023] In a preferred embodiment, the step of adaptively decomposing the target chip data to obtain the feature basis vector of the target chip data, and sparsely encoding the target chip data based on the feature basis vector to obtain the sparse coefficient vector of the target chip data, so as to obtain the dynamic decision of the target chip data, includes:

[0024] The target chip data is subjected to whitening transformation to obtain the decorrelation feature set of the target chip data;

[0025] Based on the decorrelation feature set, orthogonal basis extraction is performed to obtain the feature basis vector of the target chip data;

[0026] The feature basis vector is projected onto the target chip data to obtain the sparse coefficient vector of the target chip data.

[0027] Decision mapping is performed on the sparse coefficient vector to obtain the decision indication of the target chip data;

[0028] The decision indication is compared with a preset set of dynamic thresholds to select the optimal one, thereby obtaining a dynamic decision on the target chip data.

[0029] In a preferred embodiment, the step of extracting orthogonal basis vectors from the decorrelation feature set to obtain the feature basis vectors of the target chip data includes:

[0030] The variance contribution of the feature vectors in the decorrelation feature set is evaluated to obtain the contribution value of the decorrelation feature set;

[0031] The contribution values ​​are sorted in descending order to obtain an ordered feature sequence in the decorrelation feature set;

[0032] The ordered feature sequence is iteratively orthogonalized to obtain the orthogonal basis vectors in the decorrelation feature set;

[0033] Based on the ordered feature sequence, the projection relationship between the decorrelated feature set and the orthogonal basis vectors is calculated to obtain the projection components in the decorrelated feature set. The calculation formula for the projection components is as follows:

[0034] ;

[0035] in, For the projection component, For the first in the decorrelation feature set One feature vector to be processed, The first of the orthogonal basis vectors orthogonal basis vectors For vector dot product operation, Let be the number of iterations of the orthogonal basis vectors;

[0036] The projection component is linearly synthesized with the generated orthogonal basis vectors in the decorrelation feature set to obtain the projection representation vector in the decorrelation feature set.

[0037] The projection representation vector is reconstructed using an orthogonal basis set to obtain the feature basis vectors of the target chip data.

[0038] In a preferred embodiment, the step of optimizing the initial cache quota scheme based on the dynamic decision to obtain an optimized cache quota scheme for the target chip data includes:

[0039] The dynamic decision is encoded and reconstructed to obtain the strategy instruction of the dynamic decision;

[0040] According to the policy instruction, the initial cache quota scheme is adaptively optimized to obtain the adjusted quota scheme of the initial cache quota scheme;

[0041] Resource conflict resolution is performed on the adjusted quota scheme to obtain the effective quota scheme of the adjusted quota scheme;

[0042] The effective quota scheme is optimized to obtain an optimized cache quota scheme for the target chip data.

[0043] In a preferred embodiment, the step of adaptively optimizing the initial cache quota scheme according to the policy instruction to obtain the adjusted quota scheme of the initial cache quota scheme includes:

[0044] The strategy instruction is parsed using a parameter vector to obtain the adjustable parameter vector of the strategy instruction;

[0045] The adjustable parameter vector is mapped to the quota adjustment strategy of the target chip data;

[0046] According to the quota adjustment strategy, the initial cache quota scheme is reconstructed to adapt the quota, resulting in the adjusted quota scheme for the target chip data.

[0047] In a preferred embodiment, the step of configuring the target cache resources of the target chip data according to the optimized cache quota scheme to obtain the storage result of the target chip data includes:

[0048] The optimized cache quota scheme is parsed by partition quota to obtain the cache capacity quota of the logical partition;

[0049] Based on the cache capacity quota, quota adaptation addressing is performed on the target cache resources of the target chip data to obtain the initial selected address range of the target chip data.

[0050] The initial address segment is filtered by continuous domains to obtain a continuous address space block of the target chip data;

[0051] By performing correlation analysis between the contiguous address space blocks and the logical partitions, the logical physical address mapping relationship of the target chip data is obtained;

[0052] Based on the logical physical address mapping relationship, the target chip data is stored in the contiguous address space block according to the logical partition, thus obtaining the storage result of the target chip data.

[0053] In a preferred embodiment, the step of evaluating the storage results to obtain a cache performance benchmark value for the target chip data, and determining the final cache quota scheme for the target chip data based on the cache performance benchmark value, includes:

[0054] The status of the cache partition of the stored results is monitored to obtain the real-time load parameters of the stored results;

[0055] The real-time load parameters are subjected to state feature extraction to obtain the cache state information of the real-time load parameters;

[0056] The cache status information is matched with the preset re-evaluation condition instruction to trigger a cache allocation re-evaluation instruction for the target chip data.

[0057] Based on the cache allocation re-evaluation instruction, the current task queue and cache status of the target chip data are jointly analyzed to obtain the final cache quota scheme for the target chip data.

[0058] To address the above problems, the present invention also provides a dynamic allocation system for T / R chip data cache, the system comprising:

[0059] The task parsing module is used to acquire the task queue of target chip data and perform structured parsing on the task queue to obtain the task parameters of the target chip data.

[0060] The task-oriented partitioning module is used to perform task-oriented partitioning of the target chip data according to the task parameters, obtain logical partitions of the target chip data, and perform capacity quota planning on the logical partitions to obtain the initial cache quota scheme of the target chip data.

[0061] The dynamic decision module is used to adaptively decompose the target chip data to obtain the feature basis vector of the target chip data, and perform sparse encoding on the target chip data based on the feature basis vector to obtain the sparse coefficient vector of the target chip data, so as to obtain the dynamic decision of the target chip data.

[0062] The strategy optimization module is used to optimize the initial cache quota scheme based on the dynamic decision to obtain an optimized cache quota scheme for the target chip data.

[0063] The space configuration module is used to configure the target cache resources of the target chip data according to the optimized cache quota scheme, so as to obtain the storage result of the target chip data;

[0064] The feedback control module is used to evaluate the performance of the storage results, obtain the cache performance benchmark value of the target chip data, and determine the final cache quota scheme of the target chip data based on the cache performance benchmark value.

[0065] Compared with the prior art, the present invention has the following beneficial effects:

[0066] 1. This technology achieves precise task aggregation and scientific logical partitioning by deeply analyzing and extracting features from the target chip's data task queue. Combined with real-time load monitoring and dynamic decision-making mechanisms, it enables the cache quota scheme to accurately match the actual needs of different tasks, significantly improving the utilization rate of cache resources, while reducing latency during data transmission and ensuring efficient and stable chip data processing.

[0067] 2. This technology enhances the representation capability of data features through orthogonalization and feature basis vector construction, providing a reliable basis for cache allocation decisions. Then, through address adaptation and mapping, it achieves orderly data storage. Combined with continuous status monitoring and quota optimization, it enhances the dynamic adaptability of cache allocation, effectively avoids resource conflicts and waste, and further improves the overall data processing performance and operating efficiency of the chip. Attached Figure Description

[0068] Figure 1 This is a flowchart illustrating a dynamic allocation method for T / R chip data cache according to an embodiment of the present invention.

[0069] Figure 2 A functional block diagram of a dynamic allocation system for T / R chip data cache provided in an embodiment of the present invention;

[0070] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0071] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0072] This application provides a method for dynamically allocating T / R chip data cache. The executing entity of this method includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the method for dynamically allocating T / R chip data cache can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster. The server can be an independent server or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0073] Reference Figure 1 The diagram shown is a flowchart illustrating a dynamic allocation method for T / R chip data cache according to an embodiment of the present invention. In this embodiment, the dynamic allocation method for T / R chip data cache includes:

[0074] S1. Obtain the task queue of target chip data, and perform structured parsing on the task queue to obtain the task parameters of the target chip data;

[0075] In this embodiment of the invention, the task queue for acquiring target chip data, and the structured parsing of the task queue to obtain task parameters for the target chip data, include:

[0076] Content extraction is performed on the task queue of the target chip data to obtain the task description of the target chip data;

[0077] Based on the task description, bit field mapping is performed on the task queue to obtain the original task tuple of the task queue;

[0078] The original task tuple is subjected to time-frequency domain dual feature extraction to obtain the time-frequency domain feature representation of the original task tuple;

[0079] Based on the time-frequency domain feature representation, the original task tuple is parameter-normalized to obtain the task parameters of the target chip data.

[0080] The task queue of target chip data is scanned line by line to extract core information related to data processing, including key information such as data transmission direction, data processing type, data priority, and processing time limit requirements. This extracted core information is then integrated in a logical order to form a complete and accurate task description of the target chip data.

[0081] Based on the obtained task description, the range of binary bit fields corresponding to each key information in the task is determined. Each core element in the task description is mapped one by one to the preset bit field structure. Each element occupies a corresponding fixed bit field position. Through this one-to-one mapping method, the original task tuple containing all the key information of the task is formed.

[0082] For the data in the original task tuple, features are extracted from the time dimension and the frequency dimension respectively. In the time dimension, the occurrence pattern, duration and trend of the data at different time nodes are analyzed. In the frequency dimension, the frequency repetition period of the data and its frequency correlation with other data are analyzed. The features extracted from the two dimensions are integrated to form the time-frequency domain feature representation of the original task tuple.

[0083] Based on the time-frequency domain feature representation, the information in the original task tuple is standardized to unify the information format and expression, remove redundant and invalid content, and supplement the missing necessary information to ensure logical consistency between the information. After such standardization, the task parameters of the target chip data are finally obtained.

[0084] The beneficial effect is that through a progressively refined processing procedure, the task parameters of the target chip data can be extracted and organized from the task queue in a comprehensive and accurate manner. This ensures that the task parameters can fully reflect the core requirements and key characteristics of the task queue, providing reliable and accurate data support for subsequent target chip data logical partitioning and cache quota planning based on task parameters, thereby improving the accuracy and effectiveness of the entire dynamic cache allocation process.

[0085] S2. Based on the task parameters, the target chip data is divided into task-oriented partitions to obtain logical partitions of the target chip data, and capacity quota planning is performed on the logical partitions to obtain the initial cache quota scheme of the target chip data.

[0086] In this embodiment of the invention, the step of performing task-oriented partitioning of the target chip data according to the task parameters to obtain logical partitions of the target chip data, and performing capacity quota planning on the logical partitions to obtain an initial cache quota scheme for the target chip data, includes:

[0087] The task parameters are deconstructed and analyzed to obtain the basis for dividing the task parameters;

[0088] Based on the aforementioned division criteria, the target chip data is aggregated into tasks to obtain similar attribute task clusters of the target chip data;

[0089] The target chip data is logically partitioned by dividing the similar attribute task clusters by boundaries.

[0090] The load is evaluated on the logical partition to obtain the concurrency characteristics of the target chip data;

[0091] Based on the concurrency characteristics, capacity is allocated to the logical partition to obtain the initial cache quota scheme for the target chip data.

[0092] The task parameters are comprehensively broken down, separating core components such as data processing type, data priority, processing time limit, and data volume. The role and impact of each component in the task execution process are analyzed, the relationship between different components is clarified, and in combination with the actual needs of T / R chip data cache allocation, key indicators that can distinguish different task types and affect cache resource allocation are selected from these components. These key indicators are determined as the basis for dividing task parameters.

[0093] Based on a defined classification standard, the corresponding attributes of all tasks in the target chip data are compared one by one. Tasks with completely identical attributes or whose attribute differences are within a preset range are grouped together. Through this classification method, the scattered target chip data tasks are integrated together to form multiple task sets with the same or similar attributes, thus obtaining the similar attribute task clusters of the target chip data.

[0094] For each cluster of similar attribute tasks, the scope and characteristics of the tasks it contains are clearly defined. Based on the attribute boundaries of the tasks and the logical correlation of data processing, clear partitioning rules are set. The start and end nodes of each cluster of similar attribute tasks are defined according to these rules to ensure that the boundaries between different task clusters are clear and there is no overlap or omission. Through such boundary partitioning operations, logical partitions of the target chip data are formed.

[0095] A comprehensive statistical analysis is conducted on the tasks within each logical partition, recording information such as task execution frequency, data transmission rate, and the number of tasks executed simultaneously. The task operation pressure reflected by this information is analyzed. By summarizing this information reflecting the operation pressure, key content that can reflect the parallel execution characteristics of tasks in that logical partition is extracted, thereby obtaining the concurrency characteristics of the target chip data.

[0096] Based on the concurrency characteristics of logical partitions and the total capacity of cache resources, and according to the number of concurrent tasks and data transmission requirements of different logical partitions, a matching cache capacity is allocated to each logical partition to ensure that each logical partition can obtain sufficient cache resources during operation, while avoiding the waste of cache resources. Through such capacity allocation operations, the initial cache quota scheme for the target chip data is finally obtained.

[0097] The beneficial effects are that by deeply deconstructing and rationally dividing the task parameters, the task is accurately aggregated and the logical partitions are scientifically divided. Combined with the concurrency characteristics obtained from the load assessment, targeted capacity allocation is carried out, so that the initial cache quota scheme can accurately match the actual needs of each logical partition. This not only ensures the rationality and efficiency of the T / R chip data cache allocation, but also lays a solid foundation for subsequent cache quota optimization, effectively improving the utilization rate of cache resources.

[0098] S3. Adaptively decompose the target chip data to obtain the feature basis vector of the target chip data, and perform sparse encoding on the target chip data based on the feature basis vector to obtain the sparse coefficient vector of the target chip data, so as to obtain the dynamic decision of the target chip data.

[0099] In this embodiment of the invention, the step of adaptively decomposing the target chip data to obtain the feature basis vector of the target chip data, and performing sparse encoding on the target chip data based on the feature basis vector to obtain the sparse coefficient vector of the target chip data, so as to obtain the dynamic decision of the target chip data, includes:

[0100] The target chip data is subjected to whitening transformation to obtain the decorrelation feature set of the target chip data;

[0101] Based on the decorrelation feature set, orthogonal basis extraction is performed to obtain the feature basis vector of the target chip data;

[0102] The feature basis vector is projected onto the target chip data to obtain the sparse coefficient vector of the target chip data.

[0103] Decision mapping is performed on the sparse coefficient vector to obtain the decision indication of the target chip data;

[0104] The decision indication is compared with a preset set of dynamic thresholds to select the optimal one, thereby obtaining a dynamic decision on the target chip data.

[0105] The step of extracting orthogonal basis vectors from the target chip data based on the decorrelation feature set includes:

[0106] The variance contribution of the feature vectors in the decorrelation feature set is evaluated to obtain the contribution value of the decorrelation feature set;

[0107] The contribution values ​​are sorted in descending order to obtain an ordered feature sequence in the decorrelation feature set;

[0108] The ordered feature sequence is iteratively orthogonalized to obtain the orthogonal basis vectors in the decorrelation feature set;

[0109] Based on the ordered feature sequence, the projection relationship between the decorrelated feature set and the orthogonal basis vectors is calculated to obtain the projection components in the decorrelated feature set. The calculation formula for the projection components is as follows:

[0110] ;

[0111] in, For the projection component, For the first in the decorrelation feature set One feature vector to be processed, The first of the orthogonal basis vectors orthogonal basis vectors For vector dot product operation, Let be the number of iterations of the orthogonal basis vectors;

[0112] The projection component is linearly synthesized with the generated orthogonal basis vectors in the decorrelation feature set to obtain the projection representation vector in the decorrelation feature set.

[0113] The projection representation vector is reconstructed using an orthogonal basis set to obtain the feature basis vectors of the target chip data.

[0114] The target chip data is processed to eliminate the linear correlation between different features in the data, making each feature statistically independent, and unifying the variance of all features to the same level. After such processing, the decorrelation feature set of the target chip data is obtained.

[0115] Each eigenvector in the decorrelation feature set is analyzed one by one, and the contribution of each eigenvector to the variance of the entire dataset is calculated. By measuring the proportion of the overall data variation that the eigenvector can explain, the specific value corresponding to each eigenvector is determined, which is the contribution value in the decorrelation feature set.

[0116] All contribution values ​​are arranged in descending order. During the sorting process, the correlation between each contribution value and its corresponding feature vector is not broken, ensuring that the sorted feature vectors can still correspond to the original contribution values, ultimately forming an ordered feature sequence in the decorrelation feature set.

[0117] The first feature vector in the ordered feature sequence is selected as the initial vector. After standardization, it is used as the first orthogonal basis vector. Then, the next feature vector in the sequence is selected in turn, and the projection component of the feature vector on all the generated orthogonal basis vectors is subtracted. The result is then standardized to obtain a new orthogonal basis vector. This process is repeated until all feature vectors in the ordered feature sequence have been traversed, and the orthogonal basis vectors in the decorrelation feature set are obtained.

[0118] Taking the ordered feature sequence as a reference, for each feature vector in the decorrelation feature set, the degree of correlation between the feature vector and each orthogonal basis vector is calculated. By determining the projection magnitude of the feature vector in the direction of each orthogonal basis vector, a specific result that can accurately reflect the projection relationship between the two is obtained, that is, the projection component in the decorrelation feature set is obtained.

[0119] The parameters of the projected components all come from the process of extracting orthogonal basis based on the decorrelation feature set. The feature vector to be processed is a single feature vector that is clearly defined in the decorrelation feature set. The orthogonal basis vector is the result obtained by iteratively orthogonalizing the ordered feature sequence. The number of iterations is the cumulative number of times the iterative orthogonalization operation is performed.

[0120] The significance of this formula lies in calculating the projection of the eigenvector to be processed onto each of the generated orthogonal basis vectors, and then integrating all these projections to obtain a projection component that accurately reflects the projection relationship between the eigenvector to be processed and the generated orthogonal basis vectors. The higher the correlation between the eigenvector to be processed and the orthogonal basis vectors, the larger the value represented by the calculated projection component. As the number of iterations increases, the number of orthogonal basis vectors involved in the calculation increases, and the value of the projection component will change accordingly based on the correlation between the eigenvector to be processed and the newly added orthogonal basis vectors. If the correlation between the eigenvector to be processed and the newly added orthogonal basis vectors is strong, the value increases; if the correlation is weak, the value does not change significantly.

[0121] Each projection component is combined with the corresponding orthogonal basis vector generated in the decorrelation feature set. The projection component and the orthogonal basis vector are superimposed and fused according to a fixed ratio so that the fused result can retain the key features of both, forming the projection representation vector in the decorrelation feature set.

[0122] Collect all projected representation vectors, and recombine and reconstruct these projected representation vectors according to the generation order and correlation of orthogonal basis vectors to form a complete and mutually orthogonal basis vector set. This vector set can comprehensively characterize the core features of the target chip data, that is, obtain the feature basis vectors of the target chip data.

[0123] Using the obtained feature basis vectors as reference standards, each data point in the target chip data is mapped to the space formed by the feature basis vectors. For each data point, the correlation strength between the data point and each feature basis vector is sequentially obtained. The specific value of this correlation strength is the magnitude of the component of the data point in the direction of the corresponding feature basis vector. By determining the magnitude of the component of each data point in each feature basis vector direction, a set of numerical vectors that can concisely represent the target chip data is obtained, namely, the sparse coefficient vector of the target chip data.

[0124] Establish the correspondence between sparse coefficient vectors and decision rules. Based on the characteristics such as the magnitude and distribution of each value in the sparse coefficient vector, and in accordance with the preset mapping rules, convert the sparse coefficient vector into instruction information with clear guiding significance, that is, obtain the decision instructions for the target chip data.

[0125] A dynamic threshold set containing multiple different thresholds is pre-defined. The obtained decision indication is compared and analyzed with each threshold in the set to determine the degree of matching between the decision indication and each threshold. The decision result corresponding to the threshold with the highest matching degree and meeting the data processing requirements is selected as the dynamic decision for the target chip data.

[0126] The beneficial effect is that through a series of coherent and precise processing steps, feature basis vectors that can accurately represent the core features of the data are extracted from the target chip data. Then, through sparse coding and decision mapping, scientific and reasonable dynamic decisions are obtained, ensuring that the dynamic decisions can accurately reflect the actual characteristics and processing requirements of the target chip data. This provides a reliable basis for the subsequent optimization of the initial cache quota scheme and effectively improves the dynamic adaptability and accuracy of cache allocation.

[0127] S4. Based on the dynamic decision, optimize the initial cache quota scheme to obtain an optimized cache quota scheme for the target chip data;

[0128] In this embodiment of the invention, the step of optimizing the initial cache quota scheme based on the dynamic decision to obtain an optimized cache quota scheme for the target chip data includes:

[0129] The dynamic decision is encoded and reconstructed to obtain the strategy instruction of the dynamic decision;

[0130] According to the policy instruction, the initial cache quota scheme is adaptively optimized to obtain the adjusted quota scheme of the initial cache quota scheme;

[0131] Resource conflict resolution is performed on the adjusted quota scheme to obtain the effective quota scheme of the adjusted quota scheme;

[0132] The effective quota scheme is optimized to obtain an optimized cache quota scheme for the target chip data.

[0133] The step of adaptively optimizing the initial cache quota scheme according to the policy instruction to obtain the adjusted quota scheme includes:

[0134] The strategy instruction is parsed using a parameter vector to obtain the adjustable parameter vector of the strategy instruction;

[0135] The adjustable parameter vector is mapped to the quota adjustment strategy of the target chip data;

[0136] According to the quota adjustment strategy, the initial cache quota scheme is reconstructed to adapt the quota, resulting in the adjusted quota scheme for the target chip data.

[0137] The key information, such as the core intent, adjustment direction, and constraints of dynamic decision-making, is comprehensively sorted out. This information is then converted into standardized instruction codes according to preset coding rules. During the coding process, it is ensured that each decision point has a corresponding unique instruction identifier, and the logical relationship and execution order between instructions are clearly defined. Through this coding reconstruction process, abstract dynamic decisions are transformed into executable dynamic decision-making strategy instructions.

[0138] For the obtained policy instructions, the instruction code contained therein is parsed segment by segment to identify various parameter information related to cache quota adjustment, including the quota adjustment range, the target object of adjustment, the triggering conditions of adjustment, and the boundary restrictions of adjustment. These parameter information are organized and arranged according to a preset vector structure to ensure that each parameter has a fixed position and clear meaning in the vector, thereby forming an adjustable parameter vector of the policy instructions.

[0139] A mapping rule is established between adjustable parameter vectors and quota adjustment strategies. This rule clarifies the specific cache quota adjustment methods corresponding to different parameter combinations. Based on the specific values ​​of each parameter in the adjustable parameter vector, the corresponding adjustment operations are matched one by one according to the mapping rule, including operations such as increasing, decreasing, or keeping the cache capacity of a specific logical partition unchanged. At the same time, the execution order and priority of the adjustment operations are determined. These matched adjustment operations are integrated to form the quota adjustment strategy for the target chip data.

[0140] Guided by the quota adjustment strategy, a comprehensive analysis of the cache capacity allocation of each logical partition in the initial cache quota scheme is conducted. Combining the adjustment direction and magnitude specified in the strategy, the initial cache quota scheme is restructured in a targeted manner. For logical partitions that need to increase cache capacity, the corresponding share is allocated from the overall cache resources according to the magnitude specified in the strategy. For logical partitions that need to reduce cache capacity, the excess portion is reclaimed to the overall cache resource pool. For logical partitions that remain unchanged, their original quota is maintained. Through this restructuring process, the adjusted quota scheme for the target chip data is obtained.

[0141] A comprehensive resource conflict detection was conducted on the adjusted quota scheme. Each logical partition was examined to identify any conflicts such as overlapping cache resource usage, uneven allocation, or exceeding the total cache resource limit. For each detected conflict type, a corresponding resolution plan was developed. If resource overlap conflicts existed, the resource usage range of the relevant logical partitions was redefined. If uneven allocation conflicts existed, resources were reallocated according to the actual needs of each partition. If conflicts exceeded the total limit, the quotas of each partition were reasonably reduced according to priority until all conflicts were completely resolved, forming an effective quota scheme for the adjusted quota scheme.

[0142] We collect execution data of effective quota schemes in similar past scenarios and environmental parameters of the current chip operation, including key performance indicators such as cache read / write speed, data transmission latency, and resource utilization. We conduct in-depth analysis of this data to identify potential optimization points in the effective quota schemes that may affect performance. We then take targeted optimization measures for these optimization points, such as optimizing the allocation ratio of cache resources to improve overall read / write efficiency and adjusting the resource scheduling mechanism between partitions to reduce data transmission latency. Through a series of performance optimization operations, we further improve the rationality and efficiency of the scheme, and finally obtain an optimized cache quota scheme for the target chip data.

[0143] The beneficial effects are that by gradually transforming dynamic decisions and optimizing the initial cache quota scheme in multiple rounds, it ensures that the adjusted quota scheme can accurately respond to the needs of dynamic decisions, effectively solves the resource conflict problem and improves the execution efficiency of the scheme, so that the optimized cache quota scheme can better meet the actual processing needs of the target chip data, and significantly improves the utilization efficiency of cache resources and the overall performance of data processing.

[0144] S5. Based on the optimized cache quota scheme, the target cache resources of the target chip data are configured in space to obtain the storage result of the target chip data;

[0145] In this embodiment of the invention, the step of configuring the target cache resources of the target chip data according to the optimized cache quota scheme to obtain the storage result of the target chip data includes:

[0146] The optimized cache quota scheme is parsed by partition quota to obtain the cache capacity quota of the logical partition;

[0147] Based on the cache capacity quota, quota adaptation addressing is performed on the target cache resources of the target chip data to obtain the initial selected address range of the target chip data.

[0148] The initial address segment is filtered by continuous domains to obtain a continuous address space block of the target chip data;

[0149] By performing correlation analysis between the contiguous address space blocks and the logical partitions, the logical physical address mapping relationship of the target chip data is obtained;

[0150] Based on the logical physical address mapping relationship, the target chip data is stored in the contiguous address space block according to the logical partition, thus obtaining the storage result of the target chip data.

[0151] The optimized cache quota scheme is broken down in a comprehensive and detailed manner, clarifying the cache resource allocation rules and specific quota standards set for each logical partition in the scheme. The cache capacity value corresponding to each logical partition is extracted one by one to ensure that the cache capacity information of each logical partition is accurate, and finally the cache capacity quota of all logical partitions is obtained.

[0152] Based on the cache capacity quota of each logical partition, all target cache resources of the target chip data are traversed to retrieve the address range that can meet the cache capacity requirements of each logical partition. According to the distribution of cache resources and capacity adaptation conditions, address ranges that match the cache capacity quota of each logical partition are initially selected. These address ranges are the initial selected address segments of the target chip data.

[0153] For each initially selected address segment, check whether its address is continuous and without breaks. Remove any parts with address gaps or discontinuities, and retain complete and continuous address segments. At the same time, ensure that the capacity of the selected continuous address segments can completely cover the cache capacity quota of the corresponding logical partition. Through this selection process, a continuous address space block of the target chip data is obtained.

[0154] The physical address information of each contiguous address space block is compared and correlated with the corresponding logical partition information one by one to clarify the specific contiguous address space block corresponding to each logical partition, and to determine the one-to-one correspondence between the identifier of the logical partition and the physical address of the contiguous address space block. By systematically sorting out these correspondences, the logical physical address mapping relationship of the target chip data is formed.

[0155] According to the correspondence rules defined by the logical physical address mapping relationship, the data belonging to each logical partition in the target chip data is classified and organized, and the data of each logical partition is transferred to its corresponding contiguous address space block. This ensures that the correspondence between logical partitions and contiguous address space blocks is strictly followed during the data storage process. After the data storage is completed, the storage result of the target chip data is obtained.

[0156] The beneficial effects are that by accurately parsing quotas, adapting addressing, filtering contiguous addresses, establishing mapping relationships, and storing data by partition, the target chip data can be stored in an orderly and efficient manner in the cache resources. This not only ensures the independence and integrity of data storage in each logical partition, but also makes full use of the contiguous address space to improve data read and write speed, effectively improving the stability and efficiency of T / R chip data cache storage.

[0157] S6. Evaluate the performance of the storage results to obtain the cache performance benchmark value of the target chip data, and determine the final cache quota scheme of the target chip data based on the cache performance benchmark value.

[0158] In this embodiment of the invention, the step of evaluating the storage results to obtain a cache performance benchmark value for the target chip data, and determining the final cache quota scheme for the target chip data based on the cache performance benchmark value, includes:

[0159] The status of the cache partition of the stored results is monitored to obtain the real-time load parameters of the stored results;

[0160] The real-time load parameters are subjected to state feature extraction to obtain the cache state information of the real-time load parameters;

[0161] The cache status information is matched with the preset re-evaluation condition instruction to trigger a cache allocation re-evaluation instruction for the target chip data.

[0162] Based on the cache allocation re-evaluation instruction, the current task queue and cache status of the target chip data are jointly analyzed to obtain the final cache quota scheme for the target chip data.

[0163] Continuous status monitoring is performed on each cache partition corresponding to the storage results. Key operational data such as data storage volume, data read / write frequency, data transfer rate, and cache resource usage ratio of each cache partition are recorded in real time. These real-time recorded data are compiled and summarized to form real-time load parameters of the storage results that can accurately reflect the current operating load of the cache partition.

[0164] For the collected real-time load parameters, we conduct in-depth analysis of the core features that reflect the cache's operating status, remove redundant and duplicate information from the parameters, and extract key content directly related to cache performance, including the load saturation level of the cache partition, the trend of read and write response efficiency, and the remaining amount of resources. We then systematically integrate these extracted key features to obtain the cache status information of the real-time load parameters.

[0165] A pre-defined re-evaluation condition instruction is set, which includes specific judgment criteria such as cache partition load limit threshold, read / write response time threshold, and resource remaining amount threshold. The obtained cache status information is compared with these preset thresholds one by one. If any indicator in the cache status information reaches or exceeds the corresponding preset threshold, the cache allocation re-evaluation instruction is triggered to generate the cache allocation re-evaluation instruction for the target chip data.

[0166] Triggered by a cache allocation re-evaluation instruction, the system comprehensively acquires the current task queue information of the target chip data, including the type, priority, data volume, and processing time limit of new tasks. Simultaneously, it collects the overall operating status of the current cache system, covering the real-time load, resource usage distribution, and idle resource status of each cache partition. The system then comprehensively analyzes and judges the current task queue information and cache status, and adjusts and optimizes the original cache quota scheme based on the matching degree between task requirements and cache resources, ultimately determining the final cache quota scheme for the target chip data.

[0167] The beneficial effects are that by monitoring and dynamically evaluating the status of cache partitions in real time, load changes and performance fluctuations during cache operation can be detected in a timely manner. Based on the actual operating conditions, a re-evaluation and collaborative analysis can be triggered, so that the final cache quota scheme can accurately adapt to the current task queue and cache status, effectively avoiding the problem of cache resource waste or insufficiency, and significantly improving the dynamic adaptability and overall operating efficiency of T / R chip data cache allocation.

[0168] like Figure 2The diagram shown is a functional block diagram of a dynamic allocation system for T / R chip data cache provided in an embodiment of the present invention.

[0169] The T / R chip data cache dynamic allocation system 100 described in this invention can be installed in an electronic device. Depending on the functions implemented, the T / R chip data cache dynamic allocation system 100 may include a task parsing module 101, a task-oriented partitioning module 102, a dynamic decision-making module 103, a strategy optimization module 104, a space allocation module 105, and a feedback control module 106. The modules described in this invention can also be referred to as units, which are a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, stored in the memory of the electronic device.

[0170] In this embodiment, the functions of each module / unit are as follows:

[0171] The task parsing module 101 is used to acquire the task queue of the target chip data and perform structured parsing on the task queue to obtain the task parameters of the target chip data.

[0172] The task-oriented partitioning module 102 is used to perform task-oriented partitioning of the target chip data according to the task parameters, obtain logical partitions of the target chip data, and perform capacity quota planning on the logical partitions to obtain an initial cache quota scheme for the target chip data.

[0173] The dynamic decision module 103 is used to adaptively decompose the target chip data to obtain the feature basis vector of the target chip data, and perform sparse encoding on the target chip data based on the feature basis vector to obtain the sparse coefficient vector of the target chip data, so as to obtain the dynamic decision of the target chip data.

[0174] The strategy optimization module 104 is used to optimize the initial cache quota scheme based on the dynamic decision to obtain an optimized cache quota scheme for the target chip data.

[0175] The space configuration module 105 is used to configure the space of the target cache resources of the target chip data according to the optimized cache quota scheme, so as to obtain the storage result of the target chip data;

[0176] The feedback control module 106 is used to evaluate the performance of the storage result, obtain the cache performance benchmark value of the target chip data, and determine the final cache quota scheme of the target chip data based on the cache performance benchmark value.

[0177] In the several embodiments provided by this invention, it should be understood that the disclosed methods and systems can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.

[0178] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0179] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0180] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The embodiments of this application can be based on artificial intelligence technology to acquire and process relevant data. Artificial intelligence is the theory, method, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0181] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for dynamically allocating data cache in a T / R chip, characterized in that, The method includes: S1. Obtain the task queue of target chip data, and perform structured parsing on the task queue to obtain the task parameters of the target chip data; The target chip data is T / R chip data; S2. Based on the task parameters, perform task-oriented partitioning of the target chip data to obtain logical partitions of the target chip data, and perform capacity quota planning on the logical partitions to obtain an initial cache quota scheme for the target chip data, including: The task parameters are deconstructed and analyzed to obtain the basis for dividing the task parameters; Based on the aforementioned division criteria, the target chip data is aggregated into tasks to obtain similar attribute task clusters of the target chip data; The target chip data is logically partitioned by dividing the similar attribute task clusters by boundaries. The load is evaluated on the logical partition to obtain the concurrency characteristics of the target chip data; Based on the concurrency characteristics, capacity is allocated to the logical partition to obtain an initial cache quota scheme for the target chip data; S3. Adaptively decompose the target chip data to obtain the feature basis vector of the target chip data, and perform sparse encoding on the target chip data based on the feature basis vector to obtain the sparse coefficient vector of the target chip data, so as to obtain the dynamic decision of the target chip data, including: The target chip data is subjected to whitening transformation to obtain the decorrelation feature set of the target chip data; Based on the decorrelation feature set, orthogonal basis extraction is performed to obtain the feature basis vector of the target chip data; The feature basis vector is projected onto the target chip data to obtain the sparse coefficient vector of the target chip data. By determining the magnitude of the components of each data point in each feature basis vector direction, a set of numerical vectors that can concisely represent the target chip data is obtained, namely the sparse coefficient vector of the target chip data. Decision mapping is performed on the sparse coefficient vector to obtain the decision indication of the target chip data; Establish the correspondence between sparse coefficient vectors and decision rules. Based on the magnitude and distribution characteristics of each value in the sparse coefficient vector, and according to the preset mapping rules, convert the sparse coefficient vector into instruction information with clear guiding significance, that is, obtain the decision instructions for the target chip data. The decision indication is compared with a preset set of dynamic thresholds to select the optimal one, thereby obtaining a dynamic decision on the target chip data; S4. Based on the dynamic decision, optimize the initial cache quota scheme to obtain an optimized cache quota scheme for the target chip data; S5. Based on the optimized cache quota scheme, the target cache resources of the target chip data are configured in space to obtain the storage result of the target chip data; S6. Evaluate the performance of the storage results to obtain the cache performance benchmark value of the target chip data, and determine the final cache quota scheme of the target chip data based on the cache performance benchmark value.

2. The T / R chip data cache dynamic allocation method as described in claim 1, characterized in that, The task queue for acquiring target chip data, and the task parameters for obtaining the target chip data by performing structured parsing on the task queue, include: Content extraction is performed on the task queue of the target chip data to obtain the task description of the target chip data; Based on the task description, bit field mapping is performed on the task queue to obtain the original task tuple of the task queue; The original task tuple is subjected to time-frequency domain dual feature extraction to obtain the time-frequency domain feature representation of the original task tuple; Based on the time-frequency domain feature representation, the original task tuple is parameter-normalized to obtain the task parameters of the target chip data.

3. The T / R chip data cache dynamic allocation method as described in claim 1, characterized in that, The step of extracting orthogonal basis vectors from the target chip data based on the decorrelation feature set includes: The variance contribution of the feature vectors in the decorrelation feature set is evaluated to obtain the contribution value of the decorrelation feature set; The contribution values ​​are sorted in descending order to obtain an ordered feature sequence in the decorrelation feature set; The ordered feature sequence is iteratively orthogonalized to obtain the orthogonal basis vectors in the decorrelation feature set; Based on the ordered feature sequence, the projection relationship between the decorrelated feature set and the orthogonal basis vectors is calculated to obtain the projection components in the decorrelated feature set. The calculation formula for the projection components is as follows: ； in, For the projection component, For the first in the decorrelation feature set One feature vector to be processed, The first of the orthogonal basis vectors orthogonal basis vectors For vector dot product operation, Let be the number of iterations of the orthogonal basis vectors; The projection component is linearly synthesized with the generated orthogonal basis vectors in the decorrelation feature set to obtain the projection representation vector in the decorrelation feature set. The projection representation vector is reconstructed using an orthogonal basis set to obtain the feature basis vectors of the target chip data.

4. The T / R chip data cache dynamic allocation method as described in claim 1, characterized in that, The step of optimizing the initial cache quota scheme based on the dynamic decision to obtain an optimized cache quota scheme for the target chip data includes: The dynamic decision is encoded and reconstructed to obtain the strategy instruction of the dynamic decision; According to the policy instruction, the initial cache quota scheme is adaptively optimized to obtain the adjusted quota scheme of the initial cache quota scheme; Resource conflict resolution is performed on the adjusted quota scheme to obtain the effective quota scheme of the adjusted quota scheme; The effective quota scheme is optimized to obtain an optimized cache quota scheme for the target chip data.

5. The T / R chip data cache dynamic allocation method as described in claim 4, characterized in that, The step of adaptively optimizing the initial cache quota scheme according to the policy instruction to obtain the adjusted quota scheme includes: The strategy instruction is parsed using a parameter vector to obtain the adjustable parameter vector of the strategy instruction; The adjustable parameter vector is mapped to the quota adjustment strategy of the target chip data; According to the quota adjustment strategy, the initial cache quota scheme is reconstructed to adapt the quota, resulting in the adjusted quota scheme for the target chip data.

6. The method for dynamic allocation of data cache in a T / R chip as described in claim 1, characterized in that, The step of configuring the target cache resources for the target chip data according to the optimized cache quota scheme to obtain the storage result of the target chip data includes: The optimized cache quota scheme is parsed by partition quota to obtain the cache capacity quota of the logical partition; Based on the cache capacity quota, quota adaptation addressing is performed on the target cache resources of the target chip data to obtain the initial selected address range of the target chip data. The initial address segment is filtered by continuous domains to obtain a continuous address space block of the target chip data; By performing correlation analysis between the contiguous address space blocks and the logical partitions, the logical physical address mapping relationship of the target chip data is obtained; Based on the logical physical address mapping relationship, the target chip data is stored in the contiguous address space block according to the logical partition, thus obtaining the storage result of the target chip data.

7. The method for dynamic allocation of data cache in a T / R chip as described in claim 1, characterized in that, The step of evaluating the storage results to obtain a cache performance benchmark value for the target chip data, and determining the final cache quota scheme for the target chip data based on the cache performance benchmark value, includes: The status of the cache partition of the stored results is monitored to obtain the real-time load parameters of the stored results; The real-time load parameters are subjected to state feature extraction to obtain the cache state information of the real-time load parameters; The cache status information is matched with the preset re-evaluation condition instruction to trigger a cache allocation re-evaluation instruction for the target chip data. Based on the cache allocation re-evaluation instruction, the current task queue and cache status of the target chip data are jointly analyzed to obtain the final cache quota scheme for the target chip data.

8. A dynamic allocation system for data cache in a T / R chip, characterized in that, The system for implementing the dynamic allocation method for T / R chip data cache as described in claim 1 includes: The task parsing module is used to acquire the task queue of target chip data and perform structured parsing on the task queue to obtain the task parameters of the target chip data. The target chip data is T / R chip data; A task-oriented partitioning module is used to perform task-oriented partitioning of the target chip data according to the task parameters, obtain logical partitions of the target chip data, and perform capacity quota planning on the logical partitions to obtain an initial cache quota scheme for the target chip data, including: The task parameters are deconstructed and analyzed to obtain the basis for dividing the task parameters; Based on the aforementioned division criteria, the target chip data is aggregated into tasks to obtain similar attribute task clusters of the target chip data; The target chip data is logically partitioned by dividing the similar attribute task clusters by boundaries. The load is evaluated on the logical partition to obtain the concurrency characteristics of the target chip data; Based on the concurrency characteristics, capacity is allocated to the logical partition to obtain an initial cache quota scheme for the target chip data; A dynamic decision-making module is used to adaptively decompose the target chip data to obtain the feature basis vector of the target chip data, and to perform sparse encoding on the target chip data based on the feature basis vector to obtain the sparse coefficient vector of the target chip data, so as to obtain the dynamic decision of the target chip data, including: The target chip data is subjected to whitening transformation to obtain the decorrelation feature set of the target chip data; Based on the decorrelation feature set, orthogonal basis extraction is performed to obtain the feature basis vector of the target chip data; The feature basis vector is projected onto the target chip data to obtain the sparse coefficient vector of the target chip data. By determining the magnitude of the components of each data point in each feature basis vector direction, a set of numerical vectors that can concisely represent the target chip data is obtained, namely the sparse coefficient vector of the target chip data. Decision mapping is performed on the sparse coefficient vector to obtain the decision indication of the target chip data; Establish the correspondence between sparse coefficient vectors and decision rules. Based on the magnitude and distribution characteristics of each value in the sparse coefficient vector, and according to the preset mapping rules, convert the sparse coefficient vector into instruction information with clear guiding significance, that is, obtain the decision instructions for the target chip data. The decision indication is compared with a preset set of dynamic thresholds to select the optimal one, thereby obtaining a dynamic decision on the target chip data; The strategy optimization module is used to optimize the initial cache quota scheme based on the dynamic decision to obtain an optimized cache quota scheme for the target chip data. The space configuration module is used to configure the target cache resources of the target chip data according to the optimized cache quota scheme, so as to obtain the storage result of the target chip data; The feedback control module is used to evaluate the performance of the storage results, obtain the cache performance benchmark value of the target chip data, and determine the final cache quota scheme of the target chip data based on the cache performance benchmark value.

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