LLC resonant converter and control method

Abstract

The invention relates to an LLC resonant converter and a control method. The control method comprises the steps that an input voltage sampling circuit selects a working mode by sampling an input voltage; the resonance current sampling circuit outputs a resonance current feedback signal; the secondary side sampling feedback circuit samples secondary side load information and feeds back the load size; the feedback signal compensation circuit receives a sampling signal and a feedback signal, compensates a feedback voltage signal at the moment of full-bridge switching to half-bridge switching or half-bridge switching to full-bridge switching, and prevents overshoot and undershoot of an output voltage; and the PWM control circuit compares the resonance current feedback signal with the compensated feedback voltage signal to generate a first bridge arm control signal and a second bridge arm control signal so as to control the starting time of the switching tube. According to the scheme provided by the invention, the overshoot or undershoot of the output voltage caused by gain abrupt change can be effectively inhibited, the stability and reliability of the output voltage are improved, the input voltage adaptation range of the converter is expanded, and the working frequency adjustment interval is optimized.

Description

Technical Field

[0001] This application relates to the field of switching power supply converter technology, and more particularly to LLC resonant converters and control methods. Background Technology

[0002] LLC resonant converters are widely used in medium- and high-power switching converters due to their high power density, high conversion efficiency, and soft-switching capabilities. However, in practical applications, to cope with more complex usage scenarios, the converter needs to accommodate input voltage and output power variations as broadly as possible, which places more stringent requirements on the overall system design.

[0003] Typically, LLC resonant converters control the energy transferred from the primary to the secondary side by controlling the conduction time of the switching transistors, ensuring the stability of the output voltage across different power ranges. Engineers in this field can anticipate that the LLC resonant converter will operate at its minimum frequency when the input voltage is minimum and the output power is maximum; conversely, it will operate at its maximum frequency when the input voltage is maximum and the output power is minimum. This presents two design challenges: First, when the input voltage range is wide, the operating frequency adjustment range also needs to be large to meet the requirements of all operating conditions, which is detrimental to improving the converter's power density. Second, when the LLC resonant converter operates at too low a frequency, it is difficult to achieve zero-voltage turn-on; when the operating frequency is too high, it is difficult to achieve zero-current turn-off, which is detrimental to improving the converter's conversion efficiency.

[0004] To address this issue, a common technical solution is to introduce a full-bridge / half-bridge switching control strategy. This involves setting full-bridge to half-bridge switching thresholds and half-bridge to full-bridge switching thresholds after determining the upper and lower limits of the converter input voltage. When the LLC resonant converter input voltage is lower than the full-bridge to half-bridge switching threshold, it operates in full-bridge mode; when the LLC resonant converter input voltage is higher than the half-bridge to full-bridge switching threshold, it operates in half-bridge mode. In half-bridge mode, the LLC resonant converter gain is only half that in full-bridge mode, and under the same operating conditions, the operating frequency can be reduced to half that in full-bridge mode. This control strategy effectively reduces the range of operating frequency variations.

[0005] However, when the input voltage of the LLC resonant converter is near the switching threshold, under the same input voltage and output power, the LLC resonant converter switching from full-bridge control to half-bridge control or vice versa will cause a sudden change in gain, resulting in overshoot or undershoot of the output voltage. This is not conducive to the stability of the output voltage and the electromagnetic interference (EMI) protection of the whole system.

[0006] Therefore, there is an urgent need for an LLC resonant converter circuit and control method that can achieve a smooth transition during the switching between full-bridge and half-bridge modes and suppress output voltage disturbances caused by sudden gain changes. Summary of the Invention

[0007] To address or partially address the problems existing in related technologies, this application provides an LLC resonant converter and control method, aiming to solve the problems of smooth transition during full-half-bridge control switching and over / undershoot of output voltage.

[0008] The first aspect of this application provides an LLC resonant converter, comprising: LLC resonant main power module and LLC resonant control module. The LLC resonant main power module includes a resonant circuit connected to the first bridge arm and the second bridge arm, a transformer connected to the resonant circuit, and a rectifier circuit set on the secondary side of the transformer. The LLC resonant control module includes an input voltage sampling circuit, a resonant current sampling circuit, a secondary-side sampling feedback circuit, a feedback signal compensation circuit, and a PWM control circuit. The input terminal of the input voltage sampling circuit is connected to the positive power input terminal of the LLC resonant main power module, and its output terminal is connected to the input terminals of the feedback signal compensation circuit and the PWM control circuit, respectively. The input terminal of the resonant current sampling circuit is connected to the resonant circuit, and its output terminal is connected to the PWM control circuit. The input terminal of the secondary-side sampling feedback circuit is connected to the output terminals of the rectifier circuit and the feedback signal compensation circuit, respectively, and its output terminal is connected to the input terminal of the PWM control circuit. The output terminal of the PWM control circuit is connected to the first bridge arm and the second bridge arm. The feedback signal compensation circuit receives the output signal from the input voltage sampling circuit and the output signal from the secondary sampling feedback circuit. When switching from a full bridge to a half bridge or from a half bridge to a full bridge, the feedback voltage signal is compensated, so that the feedback voltage signal transitions quickly and smoothly in the opposite direction to the gain change, thus offsetting the response lag caused by the sudden gain change and suppressing the generation of overshoot or undershoot of the LLC resonant converter output voltage.

[0009] Optional, the input voltage sampling circuit includes: The system comprises a first comparator, a first D flip-flop, a first NOT gate, and a first selector. The VP terminal of the first comparator is connected to the positive terminal of the power input, and the output terminal is connected to the D port of the first D flip-flop and the S port of the first selector. The S0 and S1 ports of the first selector are connected to the full-bridge to half-bridge switching threshold Vth_FTH and the half-bridge to full-bridge switching threshold Vth_HTF, respectively. The input terminal of the first NOT gate receives the drive signal output by the PWM control circuit, and the output terminal is connected to the CP terminal of the first D flip-flop. The Q output terminal of the first D flip-flop outputs the half-bridge mode control signal HBMODE, and the Q_ output terminal outputs the full-bridge mode control signal FBMODE.

[0010] Optional, the secondary-side sampling feedback circuit includes: First error amplifier, first resistor, second resistor, third resistor, first capacitor, second capacitor; The first resistor and the second resistor are connected in series. The other end of the first resistor is connected to the voltage output terminal, and the other end of the second resistor is grounded. The junction of the first resistor and the second resistor is connected to the VN input port of the first error amplifier. The VP input port of the first error amplifier is connected to the reference voltage Vref. The output port of the first error amplifier is connected to the third resistor and the second capacitor. The other end of the third resistor is connected to one end of the first capacitor. The other ends of the first capacitor and the second capacitor are both grounded. The first capacitor, the third resistor, and the second capacitor constitute the compensation circuit of the first error amplifier.

[0011] Optional, the feedback signal compensation circuit includes: Switch between the compensation control module, the transconductance amplifier module, and the current mirror module; The switching compensation control module includes a first LEB, a second LEB, a second D flip-flop, a third D flip-flop, a first transmission gate, a second transmission gate, a first OR gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a fifteenth N-type MOSFET, a third capacitor, and a charging current source Icharge. One end of the first LEB is connected to the output of the input voltage sampling circuit and the fourth inverter, and the other end of the first LEB is connected to the input of the first OR gate and the first inverter. One end of the second LEB is connected to the output of the input voltage sampling circuit and the second inverter, and the other end of the second LEB is connected to the input of the OR gate and the third inverter. The CP port of the second D flip-flop is connected to the output of the first inverter, and the Clr port of the second D flip-flop is connected to the output of the first inverter. The first D flip-flop's CP port is connected to the output of the second inverter; the third D flip-flop's Clr port is connected to the output of the fourth inverter; the D ports of both the second and third D flip-flops are connected to the positive power supply VCC of the control module; the Q output port and Q_ output port of the second D flip-flop 1043 are connected to the OP_H and OP_L ports of the first transmission gate, respectively; the Q output port and Q_ output port of the third D flip-flop are connected to the OP_H and OP_L ports of the second transmission gate, respectively; the output of the first OR gate is connected to the gate of the fifteenth N-type MOS transistor via the fifth inverter; the fifteenth N-type MOS transistor and the third capacitor are connected in parallel, with the source terminal grounded and the drain terminal connected to the charging current source Icharge; The transconductance amplifier module and current mirror module include a first P-type MOSFET, a second P-type MOSFET, a third P-type MOSFET, a fourth P-type MOSFET, a fifth P-type MOSFET, a sixth P-type MOSFET, a seventh P-type MOSFET, an eighth P-type MOSFET, a ninth P-type MOSFET, a tenth P-type MOSFET, an eleventh P-type MOSFET, a twelfth P-type MOSFET, a first N-type MOSFET, a second N-type MOSFET, a third N-type MOSFET, a fourth N-type MOSFET, a fifth N-type MOSFET, a sixth N-type MOSFET, a seventh N-type MOSFET, an eighth N-type MOSFET, a ninth N-type MOSFET, a tenth N-type MOSFET, an eleventh N-type MOSFET, a twelfth N-type MOSFET, a thirteenth N-type MOSFET, a fourteenth N-type MOSFET, and a bias current Ibiasp; The gates of the first, second, and third P-type MOSFETs are connected to the drain of the third P-type MOSFET, and their sources are connected to the positive power supply VCC of the control module. The gates of the fourth, fifth, and sixth P-type MOSFETs are connected to the drain of the sixth P-type MOSFET, and their sources are connected to the drains of the first, second, and third P-type MOSFETs, respectively. The gates of the third and fourth N-type MOSFETs are connected to the drain of the fourth N-type MOSFET, and their sources are connected to the negative power supply VSS of the control module. The gates of the first and second N-type MOSFETs are connected to the drain of the second N-type MOSFET, and the drain of the second N-type MOSFET is connected to the drain of the fifth P-type MOSFET. The drains of the fourth P-type MOSFET and the first N-type MOSFET are connected to one end of the first and second transmission gates, respectively, and the other ends of the first and second transmission gates are connected to the feedback voltage signal. The gates of the seventh and eighth P-type MOSFETs are connected to the drain of the eighth P-type MOSFET, and their sources are connected to the positive power supply VCC of the control module. The gates of the ninth and tenth P-type MOSFETs are connected to the drain of the tenth P-type MOSFET, and their sources are connected to the drains of the seventh and eighth P-type MOSFETs, respectively. The sources of the eleventh and twelfth P-type MOSFETs are connected to the drain of the ninth P-type MOSFET. The gates of the fifth, sixth, ninth, eleventh, and thirteenth N-type MOSFETs are connected to the drain of the thirteenth N-type MOSFET. The drain of the fifth N-type MOSFET is connected to the drain of the sixth P-type MOSFET, the drain of the sixth N-type MOSFET is connected to the drain of the eleventh P-type MOSFET, the drain of the ninth N-type MOSFET is connected to the drain of the twelfth P-type MOSFET, and the drain of the eleventh N-type MOSFET is connected to the drain of the tenth P-type MOSFET. The drain of the OS transistor; the gates of the seventh and eighth N-type MOSFETs are connected to the drain of the sixth N-type MOSFET, the gate of the tenth N-type MOSFET is connected to the drain of the ninth N-type MOSFET, the gates of the twelfth and fourteenth N-type MOSFETs are connected to the drain of the fourteenth N-type MOSFET, the drains of the seventh, eighth, tenth, twelfth, and fourteenth N-type MOSFETs are connected to the sources of the fifth, sixth, ninth, eleventh, and thirteenth N-type MOSFETs respectively, and the sources are connected to the negative terminal VSS of the control module power supply; the gate of the eleventh P-type MOSFET MP11 is connected to the drain of the fifteenth N-type MOSFET, the gate of the twelfth P-type MOSFET is connected to the reference power supply Vref, and the drain of the thirteenth N-type MOSFET is connected to the bias current Ibiasp.

[0012] Optional, PWM control circuitry, including: First oscillator, fourth D flip-flop, fifth D flip-flop, second comparator, fifth inverter, first AND gate and second OR gate; The output of the first oscillator is connected to the CP port of the fifth D flip-flop and to the CP port of the fourth D flip-flop via the fifth inverter; the Q port of the fourth D flip-flop outputs a drive signal G1, which is also connected to the input of the first AND gate. The other input of the first AND gate receives the full-bridge mode control signal and outputs a drive signal G3; the Q port of the fifth D flip-flop outputs a drive signal G2, which is also connected to the input of the second OR gate. The other input of the second OR gate receives the half-bridge mode control signal and outputs a drive signal G4.

[0013] Optional, the secondary-side sampling feedback circuit includes: Fourth resistor, fifth resistor, sixth resistor, seventh resistor, eighth resistor, ninth resistor, fourth capacitor, fifth capacitor, sixth capacitor, first optocoupler and TL431; One end of the fourth and fifth resistors is connected to the voltage output terminal, and the other end of the fourth resistor is connected to the seventh resistor. The junction of the fourth and seventh resistors is connected to the reference pin of the TL431. The other end of the fifth resistor is connected to the anode of the first optocoupler, and the cathode of the first optocoupler is connected to the cathode of the TL431. The other end of the seventh resistor and the secondary side of the anode of the TL431 are grounded. The two ends of the fourth capacitor are connected to the junction of the fourth and seventh resistors and the cathode of the TL431, respectively. One end of the fifth capacitor is connected to the junction of the fourth and seventh resistors, and the other end is connected to the sixth resistor. The other end of the sixth resistor is connected to the cathode of the TL431. The collector of the first optocoupler is connected to the eighth and ninth resistors, respectively. The other end of the eighth resistor is connected to the positive terminal VCC of the control module power supply, and the other end of the ninth resistor is connected to the sixth capacitor. The other end of the sixth capacitor and the emitter of the first optocoupler are connected to the primary side ground.

[0014] A second aspect of this application provides a control method for an LLC resonant converter, comprising: When the LLC resonant converter is powered on at its input, the input voltage sampling circuit compares the input voltage with the internally set full-bridge to half-bridge threshold. If the input voltage is less than the full-bridge to half-bridge threshold, the converter operates in full-bridge mode. If the input voltage is further increased to make it greater than the full-bridge to half-bridge threshold, the half-bridge mode control signal HBMODE output by the input voltage sampling circuit will turn high, and the full-bridge mode control signal FBMODE will turn low. If the input voltage is greater than the half-bridge to full-bridge threshold, the converter operates in half-bridge mode. If the input voltage is further decreased to make it less than the half-bridge to full-bridge threshold, the half-bridge mode control signal HBMODE output by the input voltage sampling circuit will turn low, and the full-bridge mode control signal FBMODE will turn high. When the LLC resonant circuit is working normally, the resonant current sampling circuit samples the voltage signal on the resonant inductor to obtain the resonant current feedback signal CS, which can be used to feed back the resonant current, and then transmits it to the PWM control circuit. The secondary-side sampling feedback circuit generates a feedback voltage signal FB by sampling the output voltage signal; The feedback signal compensation circuit receives the half-bridge mode control signal HBMODE and the full-bridge mode control signal FBMODE output from the input voltage sampling circuit. When the LLC resonant converter switches from a full-bridge to a half-bridge, the gain of the LLC resonant converter is reduced to half of its original value, and the feedback voltage signal FB will increase. This provides compensation for the feedback voltage signal FB, quickly pulling the feedback voltage signal FB high. When the LLC resonant converter switches from a half-bridge to a full-bridge, the gain of the LLC resonant converter is increased to twice its original value, and the feedback voltage signal FB will decrease. This provides compensation for the feedback voltage signal FB, quickly pulling the feedback voltage signal FB low. The compensated feedback voltage signal FB is sent to the PWM control circuit. The resonant current feedback signal CS and the compensated feedback voltage signal FB are compared to generate a gate control signal for the switching transistor. By controlling the turn-on time of the switching transistor, the energy transferred from the primary side to the secondary side of the LLC resonant main power module is controlled to maintain the stability of the output voltage.

[0015] Optionally, the threshold for switching from a full-bridge to a half-bridge is greater than the threshold for switching from a half-bridge to a full-bridge, and a hysteresis interval is provided between the two to prevent frequent switching of working modes near the threshold.

[0016] Optionally, the feedback signal compensation circuit includes a switching compensation control module, a transconductance amplifier module, and a current mirror module. The switching compensation control module receives the mode switching signal and performs logic processing to control the injection of compensation current. The transconductance amplifier module and the current mirror module generate sink current and spool current for compensation. When the LLC resonant converter switches from a full-bridge to a half-bridge, the sink current is applied to the feedback voltage signal FB, which quickly pulls the feedback voltage signal FB high. When the LLC resonant converter switches from a half-bridge to a full-bridge, the spool current is applied to the feedback voltage signal FB, which quickly pulls the feedback voltage signal FB low.

[0017] Optionally, in full-bridge mode, drive signal G3 follows drive signal G1 synchronously, and drive signal G4 follows drive signal G2 synchronously; in half-bridge mode, drive signal G3 controls the corresponding bridge arm to remain off, and drive signal G4 controls the corresponding bridge arm to remain on; there is a certain dead time between the bridge arms controlled by G1 and G2, so they will not be turned on at the same time, and the switching frequency increases together with the increase of feedback voltage signal FB, and decreases together with the decrease of feedback voltage signal FB.

[0018] The technical solution provided in this application may include the following beneficial effects: By introducing a real-time feedback compensation mechanism during the switching between full-bridge and half-bridge modes, and dynamically adjusting the feedback voltage signal through the feedback signal compensation circuit, the overshoot or undershoot of the output voltage caused by sudden gain changes is effectively suppressed, thereby improving the stability of the output voltage and the reliability of the system. At the same time, combined with the input voltage adaptive mode switching strategy, the input voltage adaptation range of the converter is expanded, the operating frequency adjustment range is optimized, soft switching is achieved and losses are reduced, thus achieving both high conversion efficiency and high power density over a wide input voltage range.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0020] The above and other objects, features and advantages of this application will become more apparent from the more detailed description of exemplary embodiments thereof in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments thereof.

[0021] Figure 1 This is a schematic diagram of the LLC resonant converter shown in the embodiments of this application; Figure 2 This is a schematic diagram of the input voltage sampling circuit of an LLC resonant converter shown in an embodiment of this application; Figure 3 This is a schematic diagram of the secondary sampling feedback circuit of an LLC resonant converter shown in an embodiment of this application; Figure 4 This is a schematic diagram of the feedback signal compensation circuit of an LLC resonant converter shown in an embodiment of this application; Figure 5 This is a schematic diagram of the PWM control circuit of an LLC resonant converter shown in an embodiment of this application; Figure 6 This is another schematic diagram of the secondary sampling feedback circuit of the LLC resonant converter shown in the embodiments of this application; Figure 7 This is a schematic diagram illustrating the change trend of the feedback voltage signal of the LLC resonant converter during mode switching, as shown in the embodiments of this application. Detailed Implementation

[0022] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make this application more thorough and complete, and to fully convey the scope of this application to those skilled in the art.

[0023] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0024] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0025] Figure 1 This is a schematic diagram of the LLC resonant converter shown in the embodiments of this application.

[0026] In some implementations, see Figure 1 An LLC resonant converter, comprising: LLC resonant main power module and LLC resonant control module; The LLC resonant main power module achieves primary-secondary isolation through a transformer and relies on the transformer to transfer energy from the primary side to the secondary side. The LLC resonant control module precisely controls the switching on and off of the switching transistors based on feedback from the secondary side load and input voltage, ensuring the power required by the secondary side load while maintaining stable output voltage.

[0027] The LLC resonant main power module is divided into two parts: the primary side and the secondary side. The primary side includes four transistors: Q1, Q2, Q3, and Q4. Transistors Q1 and Q4 are paired, as are transistors Q2 and Q3. Transistors Q1 and Q2 form the first bridge arm, and Q3 and Q4 form the second bridge arm. The resonant inductor Lr, resonant capacitor Cr, and magnetizing inductor Lm together form the LLC resonant circuit. The secondary side includes rectifier diodes D1 and D2 and an output capacitor Co. The primary and secondary sides are connected by a transformer, which includes a primary winding Np, a secondary winding Ns1, and a secondary winding Ns2. The two secondary windings are connected to rectifier diodes D1 and D2, respectively.

[0028] The LLC resonant control module includes an input voltage sampling circuit 101, a resonant current sampling circuit 102, a secondary-side sampling feedback circuit 103, a feedback signal compensation circuit 104, and a PWM control circuit 105. The input terminal of the input voltage sampling circuit 101 is connected to the positive power input terminal Vin of the LLC resonant main power module, and its output terminal is connected to the input terminals of the feedback signal compensation circuit 104 and the PWM control circuit 105, respectively. The input terminal of the resonant current sampling circuit 102 is connected to both ends of the resonant inductor Lr of the resonant circuit, and its output terminal is connected to the PWM control circuit 105. The input terminal of the secondary-side sampling feedback circuit 103 is connected to the rectifier circuit output Vout and the output terminal of the feedback signal compensation circuit 104, respectively, and its output terminal is connected to the input terminal of the PWM control circuit 105. The output terminal of the PWM control circuit 105 is connected to the first bridge arm and the second bridge arm.

[0029] like Figure 2 As shown, the input voltage sampling circuit 101 includes a first comparator 1011, a first D flip-flop 1012, a first NOT gate 1013, and a first selector 1014. The VP terminal of the first comparator 1011 is connected to the input voltage detection signal Vin-samp, and its output terminal is connected to the D port of the first D flip-flop 1012 and the S port of the first selector 1014. The S0 and S1 ports of the first selector 1014 are respectively connected to the full-bridge to half-bridge switching threshold Vth_FTH and the half-bridge to full-bridge switching threshold Vth_HTF. The input terminal of the first NOT gate 1013 receives the drive signal output by the PWM control circuit 105, and its output terminal is connected to the CP terminal of the first D flip-flop 1012. The Q output terminal of the first D flip-flop 1012 outputs the half-bridge mode control signal HBMODE, and the Q_ output terminal outputs the full-bridge mode control signal FBMODE.

[0030] like Figure 3 As shown, the secondary sampling feedback circuit 103 includes a first error amplifier 1031, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, and a second capacitor C2. The first resistor R1 and the second resistor R2 are connected in series. The other end of the first resistor R1 is connected to the output voltage Vout, and the other end of the second resistor R2 is grounded. The junction of the first resistor R1 and the second resistor R2 is connected to the VN port of the first error amplifier 1031. The VP port of the first error amplifier 1031 is connected to the external reference voltage Vref. The output port of the first error amplifier 1031 is connected to the third resistor R3 and the second capacitor C2. The other end of the third resistor R3 is connected to the first capacitor C1. The other ends of the first capacitor C1 and the second capacitor C2 are both grounded. The first capacitor C1, the third resistor R3, and the second capacitor C2 together form the compensation circuit of the first error amplifier 1031.

[0031] like Figure 4As shown, the feedback signal compensation circuit 104 includes a switching compensation control module, a transconductance amplifier module, and a current mirror module.

[0032] The switching compensation control module includes a first LEB 1041, a second LEB 1042, a second D flip-flop 1043, a third D flip-flop 1044, a first transmission gate 1045, a second transmission gate 1046, a first OR gate 1047, a first inverter 1048, a second inverter 1049, a third inverter 10410, a fourth inverter 10411, a fifth inverter 10412, a fifteenth N-type MOSFET MN15, a third capacitor C3, and a charging current source Icharge.

[0033] The HBMODE signal, after passing through the first LEB 1041, is connected to the inputs of the first OR gate 1047 and the first inverter 1048. Simultaneously, after being inverted by the fourth inverter 10411, it is connected to the Clr port of the third D flip-flop 1044. The FBMODE signal, after passing through the second LEB 1042, is connected to the inputs of the first OR gate 1047 and the third inverter 10410. Simultaneously, after being inverted by the second inverter 1049, it is connected to the Clr port of the second D flip-flop 1043. The CP ports of the second D flip-flop 1043 and the third D flip-flop 1044 are connected to the outputs of the first inverter 1048 and the third inverter 10410, respectively. The D ports are both connected to VCC. The Q output port and Q_ output port of the second D flip-flop 1043 are connected to the OP_H and OP_L ports of the first transmission gate 1045, respectively. The Q output port and Q_ output port of the third D flip-flop 1044 are connected to the OP_H and OP_L ports of the second transmission gate 1046, respectively. The fifteenth N-type MOSFET MN15 and the third capacitor C3 are connected in parallel, with one end grounded and the other end connected to the charging current source Icharge. The gate of the fifteenth N-type MOSFET MN15 is connected to the output of the fifth inverter 10412. The input of the fifth inverter 10412 is the output of the first OR gate 1047.

[0034] The transconductance amplifier module (OTA) and the current mirror module work together to achieve compensation on the fiber through the generated pull-in / sink current. The specific circuit structure includes: The first P-type MOSFET MP1, the second P-type MOSFET MP2, the third P-type MOSFET MP3, the fourth P-type MOSFET MP4, the fifth P-type MOSFET MP5, the sixth P-type MOSFET MP6, the seventh P-type MOSFET MP7, the eighth P-type MOSFET MP8, the ninth P-type MOSFET MP9, the tenth P-type MOSFET MP10, the eleventh P-type MOSFET MP11, the twelfth P-type MOSFET MP12, the first N-type MOSFET MN1, the second N-type MOSFET MN2, the third N-type MOSFET MN3, the fourth N-type MOSFET MN4, the fifth N-type MOSFET MN5, the sixth N-type MOSFET MN6, the seventh N-type MOSFET MN7, the eighth N-type MOSFET MN8, the ninth N-type MOSFET MN9, the tenth N-type MOSFET MN10, the eleventh N-type MOSFET MN11, the twelfth N-type MOSFET MN12, the thirteenth N-type MOSFET MN13, the fourteenth N-type MOSFET MN14, and the bias current Ibiasp.

[0035] The gates of the first P-type MOSFET MP1, the second P-type MOSFET MP2, and the third P-type MOSFET MP3 are connected to the drain of the third P-type MOSFET MP3, and their sources are connected to the positive power supply VCC of the control module; the gates of the fourth P-type MOSFET MP4, the fifth P-type MOSFET MP5, and the sixth P-type MOSFET MP6 are connected to the drain of the sixth P-type MOSFET MP6, and their sources are connected to the drains of the first P-type MOSFET MP1, the second P-type MOSFET MP2, and the third P-type MOSFET MP3, respectively; the gates of the third N-type MOSFET MN3 and the fourth N-type MOSFET M... The gate of N4 is connected to the drain of the fourth N-type MOSFET MN4, and the source is connected to the negative terminal VSS of the control module power supply; the gates of the first N-type MOSFET MN1 and the second N-type MOSFET MN2 are connected to the drain of the second N-type MOSFET MN2, and the drain of the second N-type MOSFET MN2 is connected to the drain of the fifth P-type MOSFET MP5; the drains of the fourth P-type MOSFET MP4 and the first N-type MOSFET MN1 are respectively connected to one end of the first transmission gate 1045 and the second transmission gate 1046, and the other end of the first transmission gate 1045 and the second transmission gate 1046 are connected to the feedback voltage signal.

[0036] The gates of the seventh P-type MOSFET MP7 and the eighth P-type MOSFET MP8 are connected to the drain of the eighth P-type MOSFET MP8, and their sources are connected to the positive power supply VCC of the control module; the gates of the ninth P-type MOSFET MP9 and the tenth P-type MOSFET MP10 are connected to the drain of the tenth P-type MOSFET MP10, and their sources are connected to the drains of the seventh P-type MOSFET MP7 and the eighth P-type MOSFET MP8, respectively; the sources of the eleventh P-type MOSFET MP11 and the twelfth P-type MOSFET MP12 are connected to the drain of the ninth P-type MOSFET MP9; the fifth N-type M The gates of MOSFETs MN5, MN6 (sixth N-type MOSFET), MN9 (ninth N-type MOSFET), MN11 (eleventh N-type MOSFET), and MN13 are connected to the drain of MN13. The drain of MN5 is connected to the drain of MP6 (sixth P-type MOSFET), and the drain of MN6 is connected to the drain of MP11 (eleventh P-type MOSFET). The drain of MN9 is connected to the drain of MP12 (twelfth P-type MOSFET), and the drain of MN11 is connected to the drain of MP13 (eleventh P-type MOSFET). The drain of the N-type MOSFET MP10 is connected to the drain of the 7th N-type MOSFET MN7 and the 8th N-type MOSFET MN8. The gate of the 10th N-type MOSFET MN10 is connected to the drain of the 9th N-type MOSFET MN9. The gate of the 12th N-type MOSFET MN12 and the 14th N-type MOSFET MN14 is connected to the drain of the 14th N-type MOSFET MN14. The drain of the 7th N-type MOSFET MN7, the 8th N-type MOSFET MN8, the 10th N-type MOSFET MN10, the 12th N-type MOSFET MN12, and the 14th N-type MOSFET MN14 is connected to the drain of the 14th N-type MOSFET MN14. The drain of the N-type MOSFET MN14 is connected to the sources of the fifth N-type MOSFET MN5, the sixth N-type MOSFET MN6, the ninth N-type MOSFET MN9, the eleventh N-type MOSFET MN11, and the thirteenth N-type MOSFET MN13, respectively. The source is connected to the negative terminal VSS of the control module power supply. The gate of the eleventh P-type MOSFET MP11 is connected to the drain of the fifteenth N-type MOSFET MN15. The gate of the twelfth P-type MOSFET MP12 is connected to the reference power supply Vref. The drain of the thirteenth N-type MOSFET MN13 is connected to the bias current Ibiasp.

[0037] like Figure 5As shown, the PWM control circuit 105 includes a first oscillator 1051, a fourth D flip-flop 1052, a fifth D flip-flop 1053, a second comparator 1054, a fifth inverter 1055, a first AND gate 1056, and a second OR gate 1057. The output of the first oscillator 1051 is connected to the CP port of the fifth D flip-flop 1053, and after being inverted by the fifth inverter 1055, it is connected to the CP port of the fourth D flip-flop 1052. The Q port of the fourth D flip-flop 1052 outputs a drive signal G1, which is also connected to the input of the first AND gate 1056. The other input of the first AND gate 1056 is connected to the full-bridge mode control signal FBMODE and outputs a drive signal G3. The Q port of the fifth D flip-flop 1053 outputs a drive signal G2, which is also connected to the input of the second OR gate 1057. The other input of the second OR gate 1057 is connected to the half-bridge mode control signal HBMODE and outputs a drive signal G4.

[0038] In some implementations, the secondary-side sampling feedback circuit can also employ another structure, such as Figure 6 As shown, it includes: Fourth resistor R4, fifth resistor R5, sixth resistor R6, seventh resistor R7, eighth resistor R8, ninth resistor R9, fourth capacitor C4, fifth capacitor C5, sixth capacitor C6, first optocoupler and TL431; The fourth resistor R4 and the fifth resistor R5 are connected at one end to the voltage output terminal. The other end of the fourth resistor R4 is connected to the seventh resistor R7. The junction of the fourth resistor R4 and the seventh resistor R7 is connected to the reference pin of TL431. The other end of the fifth resistor R5 is connected to the anode of the first optocoupler. The cathode of the first optocoupler is connected to the cathode of TL431. The other end of the seventh resistor R7 and the anode secondary side of TL431 are grounded.

[0039] The fourth capacitor C4 is connected to the junction of the fourth resistor R4 and the seventh resistor R7 and the cathode of TL431, respectively. The fifth capacitor C5 is connected to the junction of the fourth resistor R4 and the seventh resistor R7 at one end, and to the sixth resistor R6 at the other end. The other end of the sixth resistor R6 is connected to the cathode of TL431.

[0040] The collector of the first optocoupler is connected to the eighth resistor R8 and the ninth resistor R9 respectively. The other end of the eighth resistor R8 is connected to the positive terminal VCC of the control module power supply, and the other end of the ninth resistor R9 is connected to the sixth capacitor C6. The other end of the sixth capacitor C6 is connected to the primary ground of the emitter of the first optocoupler.

[0041] The TL431 can output a high-precision 2.5V reference voltage, and the output voltage Vout is set by using the fourth resistor R4 and the seventh resistor R7 in a voltage divider. (1) The output voltage Vout can be calculated using formula (1).

[0042] In some embodiments, corresponding to the aforementioned application function implementation device embodiments, this application also provides an LLC resonant converter control method including the application of the above-described LLC resonant converter.

[0043] A control method for an LLC resonant converter, comprising: When the LLC resonant converter is powered on at its input, the input voltage sampling circuit compares the input voltage with the internally set full-bridge to half-bridge threshold. If the input voltage is less than the full-bridge to half-bridge threshold, the converter operates in full-bridge mode. If the input voltage is further increased to make it greater than the full-bridge to half-bridge threshold, the half-bridge mode control signal HBMODE output by the input voltage sampling circuit will go high, and the full-bridge mode control signal FBMODE will go low. If the input voltage is greater than the half-bridge to full-bridge threshold, the converter operates in half-bridge mode. If the input voltage is further decreased to make it less than the half-bridge to full-bridge threshold, the half-bridge mode control signal HBMODE output by the input voltage sampling circuit will go low, and the full-bridge mode control signal FBMODE will go high.

[0044] Specifically, at the instant the LLC resonant converter input is powered on, the input voltage sampling circuit first compares the input voltage with the internally set full-bridge to half-bridge threshold. If the input voltage is less than the full-bridge to half-bridge threshold, the converter operates in full-bridge mode. If the input voltage is further increased to exceed the full-bridge to half-bridge threshold, the output signal of the first comparator flips high, and the result is sent to the output of the first D flip-flop when the next drive signal G1 arrives, causing the half-bridge mode control signal HBMODE to go high and the full-bridge mode control signal FBMODE to go low. Similarly, if the input voltage is greater than the half-bridge to full-bridge threshold, the converter operates in half-bridge mode. If the input voltage is further decreased to less than the half-bridge to full-bridge threshold, the output signal of the first comparator flips low, and the result is sent to the output of the first D flip-flop when the next drive signal G1 arrives, causing the half-bridge mode control signal HBMODE to go low and the full-bridge mode control signal FBMODE to go high. The threshold for switching from a full bridge to a half bridge is greater than the threshold for switching from a half bridge to a full bridge. The difference between the two is used to achieve hysteresis, preventing the output of the first comparator from flipping back and forth near the switching threshold.

[0045] When the LLC resonant circuit is working normally, the resonant current sampling circuit samples the voltage signal on the resonant inductor to obtain the resonant current feedback signal CS, which can be used to feed back the resonant current, and then transmits it to the PWM control circuit. Specifically, when the LLC resonant circuit is working normally, the resonant current flowing through the resonant inductor Lr is converted into a voltage on the resonant inductor. The resonant current sampling circuit samples the resonant current by sampling the voltage signal on the resonant inductor. Since the resonant current has two directions, positive and negative, the voltage on the resonant inductor Lr is also a positive and negative voltage with 0V as the reference. The resonant current sampling circuit first reverses the negative voltage signal, and then integrates the positive and negative voltages respectively to obtain the CS signal that can feed back the resonant current. The CS signal is not directional and only reflects the magnitude of the resonant current.

[0046] The secondary-side sampling feedback circuit generates a feedback voltage signal FB by sampling the output voltage signal.

[0047] Specifically, the secondary-side sampling feedback circuit samples the output voltage signal, divides it using the first resistor R1 and the second resistor R2, and then amplifies the difference between the divided voltage and Vref using the first error amplifier to generate the feedback signal FB. Thus, the secondary-side sampling feedback circuit achieves two functions: First, the output voltage Vout of the LLC resonant converter is set using the first resistor R1, the second resistor R2, and the reference voltage Vref. (2) Secondly, we obtained the FB signal, which can provide feedback on the load size.

[0048] The feedback signal compensation circuit receives the half-bridge mode control signal HBMODE and the full-bridge mode control signal FBMODE output from the input voltage sampling circuit. When the LLC resonant converter switches from a full-bridge to a half-bridge, the gain of the LLC resonant converter is reduced to half of its original value, and the feedback voltage signal FB will increase. This provides compensation for the feedback voltage signal FB, quickly pulling the feedback voltage signal FB high. When the LLC resonant converter switches from a half-bridge to a full-bridge, the gain of the LLC resonant converter increases to twice its original value, and the feedback voltage signal FB will decrease. This provides compensation for the feedback voltage signal FB, quickly pulling the feedback voltage signal FB low.

[0049] Specifically, the feedback signal compensation circuit receives the HBMODE and FBMODE signals output by the input voltage sampling circuit. At the instant the full bridge switches to half bridge, the voltage on the third capacitor C3 is cleared to zero by the sharp pulse width output by the first LEB. At the instant the half bridge switches to full bridge, the voltage on the third capacitor C3 is cleared to zero by the sharp pulse width output by the second LEB. After the third capacitor C3 is cleared to zero, the charging current Icharge starts to charge the third capacitor C3 and sends the voltage to the transconductance amplifier module OTA. A set of pull-up current and a set of sink current are generated through the current mirror. As the voltage on the third capacitor C3 continues to rise, the pull-up and sink currents will continue to decrease until they are 0, at which point the compensation ends. When the circuit switches from a full-bridge to a half-bridge, the HBMODE signal goes high and the FBMODE signal goes low. At this time, since the gain of the LLC resonant converter is reduced to half of its original value, the feedback signal FB will rise. However, due to the compensation and time required for the loop response of the FB signal, the FB signal cannot immediately keep up with the changes in system operating conditions at the moment of switching, which will cause the load-carrying capacity to weaken for a short time, resulting in undershoot of the output voltage. At this time, the second D flip-flop controls the first transmission gate to open, so that current is injected into the feedback voltage signal FB, providing compensation for the feedback voltage signal FB and quickly pulling the feedback voltage signal FB high. When the circuit switches from a half-bridge to a full-bridge, the HBMODE signal goes low and the FBMODE signal goes high. At this time, since the gain of the LLC resonant converter increases to twice its original value, the feedback signal FB will decrease. Similarly, due to the compensation and loop time required for the FB signal, FB cannot immediately keep up with the changes in system operating conditions at the moment of switching, which will cause the load-carrying capacity to increase for a short time, resulting in an overshoot in the output voltage. At this time, the third D flip-flop controls the second transmission gate to open, so that the pull-up current is connected to the feedback voltage signal FB, providing compensation for the feedback voltage signal FB and quickly pulling the feedback voltage signal FB low.

[0050] The compensated feedback voltage signal FB is sent to the PWM control circuit. The resonant current feedback signal CS and the compensated feedback voltage signal FB are compared to generate a gate control signal for the switching transistor. By controlling the turn-on time of the switching transistor, the energy transferred from the primary side to the secondary side of the LLC resonant main power module is controlled to maintain the stability of the output voltage.

[0051] Specifically, the compensated feedback voltage signal FB is sent to the PWM control circuit. The second comparator compares the CS signal with the compensated feedback voltage signal FB. When the CS signal is greater than the FB signal, the second comparator flips low, providing a reset signal to the fourth and fifth D flip-flops, setting the output low. The first oscillator generates a clock signal to provide a set signal to the fourth and fifth D flip-flops. The first oscillator circuit signal is related to the FB and CS signals, ensuring that there is a certain dead time between G1 and G2 to prevent them from interconnecting. Furthermore, the frequency increases with the increase of the FB signal and decreases with the decrease of the FB signal. Since the positive and negative periods of the resonant current are symmetrical, the complementary relationship between G1 and G2 is ensured. In full-bridge mode, the FBMODE signal is high and the HBMODE signal is low, causing G3 to turn on and off along with G1, and G4 to turn on and off along with G2. In half-bridge mode, the FBMODE signal is low and the HBMODE signal is low-high, keeping G3 normally off and G4 normally on.

[0052] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An LLC resonant converter, comprising an LLC resonant main power module and an LLC resonant control module, wherein the LLC resonant main power module includes a resonant circuit connected to a first bridge arm and a second bridge arm, a transformer connected to the resonant circuit, and a rectifier circuit disposed on the secondary side of the transformer, characterized in that: The LLC resonant control module includes an input voltage sampling circuit, a resonant current sampling circuit, a secondary-side sampling feedback circuit, a feedback signal compensation circuit, and a PWM control circuit. The input terminal of the input voltage sampling circuit is connected to the positive power input terminal of the LLC resonant main power module, and the output terminal of the input voltage sampling circuit is connected to the input terminals of the feedback signal compensation circuit and the PWM control circuit, respectively. The input terminal of the resonant current sampling circuit is connected to the resonant circuit, and the output terminal of the resonant current sampling circuit is connected to the PWM control circuit. The input terminal of the secondary-side sampling feedback circuit is connected to the output terminal of the rectifier circuit and the output terminal of the feedback signal compensation circuit, respectively, and the output terminal of the secondary-side sampling feedback circuit is connected to the input terminal of the PWM control circuit. The output terminal of the PWM control circuit is connected to the first bridge arm and the second bridge arm. The feedback signal compensation circuit receives the output signal from the input voltage sampling circuit and the output signal from the secondary sampling feedback circuit. When switching from a full bridge to a half bridge or from a half bridge to a full bridge, the feedback voltage signal is compensated, so that the feedback voltage signal transitions quickly and smoothly in the opposite direction to the gain change, thus offsetting the response lag caused by the sudden gain change and suppressing the generation of overshoot or undershoot of the LLC resonant converter output voltage.

2. The LLC resonant converter according to claim 1, characterized in that, The feedback signal compensation circuit includes: Switch between the compensation control module, the transconductance amplifier module, and the current mirror module; The switching compensation control module includes a first LEB, a second LEB, a second D flip-flop, a third D flip-flop, a first transmission gate, a second transmission gate, a first OR gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a fifteenth N-type MOSFET, a third capacitor, and a charging current source Icharge. One end of the first LEB is connected to the output of the input voltage sampling circuit and the fourth inverter, and the other end of the first LEB is connected to the input of the first OR gate and the first inverter. One end of the second LEB is connected to the output of the input voltage sampling circuit and the second inverter, and the other end of the second LEB is connected to the input of the OR gate and the third inverter. The CP port of the second D flip-flop is connected to the output of the first inverter, and the Clr port of the second D flip-flop is connected to the output of the second inverter. The CP port of the third D flip-flop is connected to the output of the third inverter, and the Clr port of the third D flip-flop is connected to the output of the fourth inverter. The D ports of both the second and third D flip-flops are connected to the positive VCC of the control module power supply. The Q output port and Q_ output port of the second D flip-flop 1043 are respectively connected to the OP_H and OP_L ports of the first transmission gate; The Q output port and Q_ output port of the third D flip-flop are respectively connected to the OP_H and OP_L ports of the second transmission gate; The output of the first OR gate is connected to the gate of the fifteenth N-type MOS transistor via the fifth inverter; the fifteenth N-type MOS transistor and the third capacitor are connected in parallel, with the source terminal grounded and the drain terminal connected to the charging current source Icharge; The transconductance amplifier module and current mirror module include a first P-type MOSFET, a second P-type MOSFET, a third P-type MOSFET, a fourth P-type MOSFET, a fifth P-type MOSFET, a sixth P-type MOSFET, a seventh P-type MOSFET, an eighth P-type MOSFET, a ninth P-type MOSFET, a tenth P-type MOSFET, an eleventh P-type MOSFET, a twelfth P-type MOSFET, a first N-type MOSFET, a second N-type MOSFET, a third N-type MOSFET, a fourth N-type MOSFET, a fifth N-type MOSFET, a sixth N-type MOSFET, a seventh N-type MOSFET, an eighth N-type MOSFET, a ninth N-type MOSFET, a tenth N-type MOSFET, an eleventh N-type MOSFET, a twelfth N-type MOSFET, a thirteenth N-type MOSFET, a fourteenth N-type MOSFET, and a bias current Ibiasp; The gates of the first, second, and third P-type MOSFETs are connected to the drain of the third P-type MOSFET, and their sources are connected to the positive power supply VCC of the control module. The gates of the fourth, fifth, and sixth P-type MOSFETs are connected to the drain of the sixth P-type MOSFET, and their sources are connected to the drains of the first, second, and third P-type MOSFETs, respectively. The gates of the third and fourth N-type MOSFETs are connected to the drain of the fourth N-type MOSFET, and their sources are connected to the negative power supply VSS of the control module. The gates of the first and second N-type MOSFETs are connected to the drain of the second N-type MOSFET, and the drain of the second N-type MOSFET is connected to the drain of the fifth P-type MOSFET. The drains of the fourth P-type MOSFET and the first N-type MOSFET are connected to one end of the first and second transmission gates, respectively, and the other ends of the first and second transmission gates are connected to the feedback voltage signal. The gates of the seventh and eighth P-type MOSFETs are connected to the drain of the eighth P-type MOSFET, and their sources are connected to the positive power supply VCC of the control module. The gates of the ninth and tenth P-type MOSFETs are connected to the drain of the tenth P-type MOSFET, and their sources are connected to the drains of the seventh and eighth P-type MOSFETs, respectively. The sources of the eleventh and twelfth P-type MOSFETs are connected to the drain of the ninth P-type MOSFET. The gates of the fifth, sixth, ninth, eleventh, and thirteenth N-type MOSFETs are connected to the drain of the thirteenth N-type MOSFET. The drain of the fifth N-type MOSFET is connected to the drain of the sixth P-type MOSFET, the drain of the sixth N-type MOSFET is connected to the drain of the eleventh P-type MOSFET, the drain of the ninth N-type MOSFET is connected to the drain of the twelfth P-type MOSFET, and the drain of the eleventh N-type MOSFET is connected to the drain of the tenth P-type MOSFET. The drain of the OS transistor; the gates of the seventh and eighth N-type MOSFETs are connected to the drain of the sixth N-type MOSFET, the gate of the tenth N-type MOSFET is connected to the drain of the ninth N-type MOSFET, the gates of the twelfth and fourteenth N-type MOSFETs are connected to the drain of the fourteenth N-type MOSFET, the drains of the seventh, eighth, tenth, twelfth, and fourteenth N-type MOSFETs are connected to the sources of the fifth, sixth, ninth, eleventh, and thirteenth N-type MOSFETs respectively, and the sources are connected to the negative terminal VSS of the control module power supply; the gate of the eleventh P-type MOSFET MP11 is connected to the drain of the fifteenth N-type MOSFET, the gate of the twelfth P-type MOSFET is connected to the reference power supply Vref, and the drain of the thirteenth N-type MOSFET is connected to the bias current Ibiasp.

3. The LLC resonant converter according to claim 1, characterized in that, The PWM control circuit includes: First oscillator, fourth D flip-flop, fifth D flip-flop, second comparator, fifth inverter, first AND gate and second OR gate; The output of the first oscillator is connected to the CP port of the fifth D flip-flop and the CP port of the fourth D flip-flop through the fifth inverter. The Q port of the fourth D flip-flop outputs a drive signal G1, which is simultaneously connected to the input of the first AND gate. The other input of the first AND gate receives the full-bridge mode control signal and outputs a drive signal G3. The Q port of the fifth D flip-flop outputs a drive signal G2, which is simultaneously connected to the input of the second OR gate. The other input of the second OR gate receives the half-bridge mode control signal and outputs a drive signal G4.

4. The LLC resonant converter according to claim 1, characterized in that, The input voltage sampling circuit includes: The system comprises a first comparator, a first D flip-flop, a first NOT gate, and a first selector. The VP terminal of the first comparator is connected to the positive terminal of the power input, and the output terminal is connected to the D port of the first D flip-flop and the S port of the first selector. The S0 and S1 ports of the first selector are connected to the full-bridge to half-bridge switching threshold Vth_FTH and the half-bridge to full-bridge switching threshold Vth_HTF, respectively. The input terminal of the first NOT gate receives the drive signal output by the PWM control circuit, and the output terminal is connected to the CP terminal of the first D flip-flop. The Q output terminal of the first D flip-flop outputs the half-bridge mode control signal HBMODE, and the Q_ output terminal outputs the full-bridge mode control signal FBMODE.

5. The LLC resonant converter according to claim 1, characterized in that, The secondary-side sampling feedback circuit includes: First error amplifier, first resistor, second resistor, third resistor, first capacitor, second capacitor; The first resistor and the second resistor are connected in series. The other end of the first resistor is connected to the voltage output terminal, and the other end of the second resistor is grounded. The junction of the first resistor and the second resistor is connected to the VN input port of the first error amplifier. The VP input port of the first error amplifier is connected to the reference voltage Vref. The output port of the first error amplifier is connected to the third resistor and the second capacitor. The other end of the third resistor is connected to one end of the first capacitor. The other ends of the first capacitor and the second capacitor are both grounded. The first capacitor, the third resistor, and the second capacitor form the compensation circuit of the first error amplifier.

6. The LLC resonant converter according to claim 1, characterized in that, The secondary-side sampling feedback circuit includes: Fourth resistor, fifth resistor, sixth resistor, seventh resistor, eighth resistor, ninth resistor, fourth capacitor, fifth capacitor, sixth capacitor, first optocoupler and TL431; One end of the fourth and fifth resistors is connected to the voltage output terminal, the other end of the fourth resistor is connected to the seventh resistor, the junction of the fourth and seventh resistors is connected to the reference pin of TL431, the other end of the fifth resistor is connected to the anode of the first optocoupler, the cathode of the first optocoupler is connected to the cathode of TL431, and the other end of the seventh resistor and the secondary side of the anode of TL431 are grounded. The fourth capacitor is connected to the junction of the fourth and seventh resistors and the cathode of the TL431, respectively. One end of the fifth capacitor is connected to the junction of the fourth and seventh resistors, and the other end is connected to the sixth resistor. The other end of the sixth resistor is connected to the cathode of the TL431. The collector of the first optocoupler is connected to the eighth resistor and the ninth resistor respectively. The other end of the eighth resistor is connected to the positive terminal VCC of the control module power supply. The other end of the ninth resistor is connected to the sixth capacitor. The other end of the sixth capacitor is connected to the primary ground of the emitter of the first optocoupler.

7. A control method for an LLC resonant converter, applicable to the LLC resonant converter according to any one of claims 1-6, characterized in that, include: When the LLC resonant converter is powered on at its input, the input voltage sampling circuit compares the input voltage with the internally set full-bridge to half-bridge threshold. If the input voltage is less than the full-bridge to half-bridge threshold, the converter operates in full-bridge mode. If the input voltage is further increased to make it greater than the full-bridge to half-bridge threshold, the half-bridge mode control signal HBMODE output by the input voltage sampling circuit will turn high, and the full-bridge mode control signal FBMODE will turn low. If the input voltage is greater than the half-bridge to full-bridge threshold, the converter operates in half-bridge mode. If the input voltage is further decreased to make it less than the half-bridge to full-bridge threshold, the half-bridge mode control signal HBMODE output by the input voltage sampling circuit will turn low, and the full-bridge mode control signal FBMODE will turn high. When the LLC resonant circuit is working normally, the resonant current sampling circuit samples the voltage signal on the resonant inductor to obtain the resonant current feedback signal CS, which can be used to feed back the resonant current, and then transmits it to the PWM control circuit. The secondary-side sampling feedback circuit generates a feedback voltage signal FB by sampling the output voltage signal; The feedback signal compensation circuit receives the half-bridge mode control signal HBMODE and the full-bridge mode control signal FBMODE output from the input voltage sampling circuit. When the LLC resonant converter switches from a full-bridge to a half-bridge, the gain of the LLC resonant converter is reduced to half of its original value, and the feedback voltage signal FB will increase. This provides compensation for the feedback voltage signal FB, quickly pulling the feedback voltage signal FB high. When the LLC resonant converter switches from a half-bridge to a full-bridge, the gain of the LLC resonant converter is increased to twice its original value, and the feedback voltage signal FB will decrease. This provides compensation for the feedback voltage signal FB, quickly pulling the feedback voltage signal FB low. The compensated feedback voltage signal FB is sent to the PWM control circuit. The resonant current feedback signal CS and the compensated feedback voltage signal FB are compared to generate a gate control signal for the switching transistor. By controlling the turn-on time of the switching transistor, the energy transferred from the primary side to the secondary side of the LLC resonant main power module is controlled to maintain the stability of the output voltage.

8. The LLC resonant converter control method according to claim 7, characterized in that: The threshold for switching from a full-bridge to a half-bridge is greater than the threshold for switching from a half-bridge to a full-bridge. A hysteresis interval is provided between the two to prevent frequent switching of the working mode near the threshold.

9. The LLC resonant converter control method according to claim 7, characterized in that: The feedback signal compensation circuit includes a switching compensation control module, a transconductance amplifier module, and a current mirror module; The switching compensation control module receives the mode switching signal and performs logic processing to control the injection of compensation current; the transconductance amplifier module and the current mirror module generate the sink current and pull current for compensation. When the LLC resonant converter switches from a full-bridge to a half-bridge, the sink current is connected to the feedback voltage signal FB, which quickly pulls the feedback voltage signal FB high. When the LLC resonant converter switches from a half-bridge to a full-bridge, the current is drawn into the feedback voltage signal FB, which quickly pulls the feedback voltage signal FB low.

10. The LLC resonant converter control method according to claim 7, characterized in that: In full-bridge mode, drive signal G3 follows drive signal G1 synchronously, and drive signal G4 follows drive signal G2 synchronously. In half-bridge mode, drive signal G3 controls the corresponding bridge arm to remain off, and drive signal G4 controls the corresponding bridge arm to remain on. There is a certain dead time between the bridge arms controlled by G1 and G2, so they will not be turned on at the same time. The switching frequency increases together with the increase of the feedback voltage signal FB and decreases together with the decrease of the feedback voltage signal FB.

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