Power converter and control circuit and frequency compensation method thereof

Abstract

The invention discloses a power converter and a control circuit and a frequency compensation method thereof. The power converter includes a power stage and an output filter network coupled thereto, the power stage including a main inductor and a plurality of switches for controlling charging and discharging processes of the main inductor. The control circuit comprises a first compensation unit which generates a first compensation signal according to a DC output parameter of the power converter; the second compensation unit is used for generating a second compensation signal according to the inlet voltage of the output filter network; the synthesis unit is used for synthesizing the first compensation signal and the second compensation signal into a system compensation signal; and the logic unit is used for generating a switch control signal of the plurality of switches, and the duty ratio of the switch control signal is related to the system compensation signal, so that the dynamic adjustment of the direct current output parameter is realized based on the duty ratio of the switch control signal, and the double-pole compensation is carried out on the power converter.

Description

Technical Field

[0001] This disclosure relates to the field of power electronics technology, and in particular to frequency compensation circuits and methods for power converters. Background Technology

[0002] Power converters are widely used in power electronic systems, and their stability and dynamic response performance directly affect the quality of output power. The main performance indicators of power converters typically include output voltage ripple, load regulation, and transient response speed. Among these, output voltage ripple directly reflects the smoothness of the output voltage.

[0003] A power converter may include, for example, a power stage circuit for converting input electrical energy into a stable output voltage and a control circuit for regulating the power stage circuit. The power stage circuit may include, for example, an inductor, which stores and transfers energy through the periodic charging and discharging process of the inductor during a switching cycle; the control circuit forms a closed-loop control by adjusting the on and off times of the switching devices to maintain a stable output voltage.

[0004] An output capacitor is typically connected to the output of a power stage circuit to filter out high-frequency ripple components introduced by switching operations and to provide instantaneous current support during sudden changes in load current. When the load changes rapidly, the output capacitor works in conjunction with the inductor to suppress transient fluctuations in the output voltage. However, the inherent parasitic parameters of the inductor and output capacitor (such as equivalent series resistance and parasitic capacitance) can introduce additional phase delay under certain conditions, thereby adversely affecting the stability of the control loop.

[0005] To further suppress ripple components in DC output parameters, simply using a single output capacitor at the power stage circuit output is insufficient for high-performance applications. Existing technologies have proposed using CLC filters to replace single filter capacitors. The CLC filter consists of two capacitors and an inductor positioned between them, forming a π-type low-pass filter structure, which can effectively attenuate high-frequency ripple components, thereby improving the stability of DC output parameters. However, introducing a CLC filter also introduces an additional resonant point into the system, reducing the system's phase margin and increasing the risk of oscillations in the control loop.

[0006] US Patent Application US 2014 / 0210434 A1 discloses a power converter using a split inductor design, comprising a main inductor and a ferrite bead inductor connected in series. Under high-frequency operating conditions, the ferrite bead inductor, due to the inherent parasitic capacitance characteristics of its winding structure and packaging, can form a resonant network with the equivalent parasitic capacitance of its preceding and following circuit nodes. This results in an equivalent filtering effect similar to a CLC filter network within a certain frequency range, thereby suppressing high-frequency noise.

[0007] However, in the aforementioned US patent application, the split inductor design primarily focuses on attenuating high-frequency noise using passive components. Its technical solution does not effectively suppress or regulate the resonance peaks introduced by parasitic parameters and the resonant network, nor does it address techniques for frequency compensation of the control loop based on the resonant characteristics. Therefore, under specific operating conditions, this split inductor structure may still adversely affect the loop stability of the system. Summary of the Invention

[0008] In view of the above problems, the purpose of this disclosure is to provide a power converter and its control circuit and frequency compensation method, which generate compensation signals based on the DC output parameters of the power converter and the input voltage of the output filter network, and perform double pole compensation on the power converter to suppress the influence of the resonance peak introduced by the output filter network on the loop stability.

[0009] According to one aspect of this disclosure, a control circuit for a power converter is provided. The power converter includes a power stage and an output filter network coupled thereto. The power stage includes a main inductor and a plurality of switches for controlling the charging and discharging processes of the main inductor. The control circuit includes: a first compensation unit for generating a first compensation signal based on DC output parameters of the power converter; a second compensation unit for generating a second compensation signal based on the input voltage of the output filter network; a synthesis unit for synthesizing the first compensation signal and the second compensation signal into a system compensation signal; and a logic unit for generating switch control signals for the plurality of switches, wherein the duty cycle of the switch control signals is related to the system compensation signal, thereby achieving dynamic adjustment of the DC output parameters and performing double-pole compensation on the power converter based on the duty cycle of the switch control signals.

[0010] Optionally, the second compensation unit includes: an input filter network coupled to the input of the output filter network for extracting a high-frequency sampling signal from the input voltage of the output filter network; and a first error amplifier for comparing the high-frequency sampling signal with a first reference voltage to generate the second compensation signal, wherein the second compensation signal is a current signal.

[0011] Optionally, the input filtering network includes at least one filtering stage, each of which includes an input capacitor and an input resistor connected in series.

[0012] Optionally, the second compensation unit includes: an input capacitor coupled to the inlet of the output filter network for extracting a high-frequency sampling signal from the inlet voltage of the output filter network; and a first operational amplifier for amplifying the differential signal between the high-frequency sampling signal and the first reference voltage to generate the second compensation signal, wherein the second compensation signal is a voltage signal.

[0013] Optionally, the first reference voltage is ground potential.

[0014] Optionally, the synthesis unit includes: an isolation resistor, a first end of which is coupled to the first compensation signal, a second end of which is coupled to the second compensation signal, and provides the system compensation signal.

[0015] Optionally, the synthesis unit includes: a voltage follower; and an isolation resistor, a first terminal of which is coupled to the output terminal of the voltage follower, wherein the input terminal of the voltage follower is coupled to the first compensation signal, and a second terminal of the isolation resistor is coupled to the second compensation signal and provides the system compensation signal.

[0016] Optionally, the first compensation unit includes: a second error amplifier for comparing the feedback signal of the DC output parameter with a second reference voltage to generate an error signal; and a compensation network coupled to the output of the second error amplifier for converting the error signal into the first compensation signal, wherein the first compensation signal is a voltage signal.

[0017] Optionally, the DC output parameters are at least one of the DC output voltage and DC output current of the power converter.

[0018] According to another aspect of this disclosure, a power converter is provided, comprising: a power stage including a main inductor and a plurality of switches for controlling the charging and discharging processes of the main inductor; an output filter network coupled between the main inductor and the output terminal of the power converter; and the control circuit described above.

[0019] Optionally, the output filter network is a high-order filter network containing at least two filter elements.

[0020] Optionally, the output filtering network includes: a filter inductor; a first filter capacitor coupled between a first terminal of the filter inductor and ground; and a second filter capacitor coupled between a second terminal of the filter inductor and ground.

[0021] Optionally, the filter inductor is a ferrite bead inductor.

[0022] Optionally, the power converter is selected from any one of the following topologies: BUCK type, BOOST type, BUCK-BOOST type, and flyback topology.

[0023] Optionally, the plurality of switches includes a first switch and a second switch connected in series between the input terminal of the power converter and ground, a first end of the main inductor being coupled to the intermediate node between the first switch and the second switch, and a second end being coupled to the inlet of the output filter network.

[0024] According to another aspect of this disclosure, a frequency compensation method for a power converter is provided. The power converter includes a power stage and an output filter network coupled thereto. The power stage includes a main inductor and a plurality of switches for controlling the charging and discharging processes of the main inductor. The frequency compensation method includes: generating a first compensation signal based on DC output parameters of the power converter; generating a second compensation signal based on the input voltage of the output filter network in the power converter; combining the first compensation signal and the second compensation signal into a system compensation signal; and generating switch control signals for the plurality of switches, wherein the duty cycle of the switch control signals is related to the system compensation signal, thereby achieving dynamic adjustment of the DC output parameters based on the duty cycle of the switch control signals, and performing double-pole compensation on the power converter.

[0025] Optionally, the step of generating the second compensation signal includes: extracting a high-frequency sampling signal from the input voltage of the output filter network; and comparing the high-frequency sampling signal with a first reference voltage to generate the second compensation signal, wherein the second compensation signal is a current signal or a voltage signal.

[0026] Optionally, the step of combining the first compensation signal and the second compensation signal into a system compensation signal includes: linearly superimposing the first compensation signal and the second compensation signal, wherein the linear superposition includes any one or more of current summation, voltage summation, current differential, voltage differential, and signal selection.

[0027] According to the power converter and its control circuit and frequency compensation method of the present disclosure, two compensation signals are generated based on the DC output parameters of the power converter and the input voltage of the output filter network to perform double pole compensation on the power converter, so as to suppress the influence of the resonance peak introduced by the output filter network on the loop stability.

[0028] This solution effectively offsets the additional phase lag introduced by the output filter network (such as the CLC structure), significantly widens the loop bandwidth, and improves the system's phase margin and stability. This allows the power converter to maintain good dynamic response speed while outputting a cleaner, less rippled DC voltage, quickly suppressing voltage fluctuations caused by load transients, thereby improving overall power density and power quality. This solution is applicable to various topologies, including BUCK, BOOST, BUCK-BOOST, and flyback topologies, demonstrating strong versatility.

[0029] Furthermore, this scheme significantly enhances the design freedom of the output filter network, resolving the contradiction of sacrificing loop stability in pursuit of superior filtering performance. In traditional designs, to avoid the destructive effect of resonance peaks on stability, engineers often need to strictly limit the order, component parameters, or topology of the filter network, sometimes even sacrificing filtering performance for stability. However, according to the active compensation mechanism of this disclosure, the design of the output filter network can optimize filtering performance indicators, such as high-frequency attenuation characteristics, size, and cost, without excessive concern about their negative impact on loop stability. Whether using a standard CLC structure, components with special frequency characteristics such as ferrite bead inductors, or higher-order or non-standard filter network topologies, this control circuit can effectively suppress the introduced resonance peaks through appropriate compensation signal generation and synthesis methods, thereby providing design space for optimizing the output filter network. Attached Figure Description

[0030] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings.

[0031] Figure 1 A schematic circuit diagram of a BUCK-type power converter according to a first embodiment of the present disclosure is shown.

[0032] Figure 2 A schematic circuit diagram of a BUCK-type power converter according to a second embodiment of the present disclosure is shown.

[0033] Figure 3 Show Figure 1 and Figure 2 The diagram shows the waveforms of the main signals of the BUCK-type power converter.

[0034] Figure 4 Show Figure 1 and Figure 2 The equivalent circuit diagram of the BUCK-type power converter is shown.

[0035] Figure 5 Show Figure 1 The diagram shows a schematic circuit of the first compensation unit of the BUCK-type power converter.

[0036] Figure 6 Show Figure 1 The diagram shows a schematic circuit of the first example of the second compensation unit in the BUCK-type power converter.

[0037] Figure 7 Show Figure 1 The schematic circuit diagram shows a second example of the second compensation unit in the BUCK-type power converter.

[0038] Figure 8 Show Figure 1 The schematic circuit diagram shows a third example of the second compensation unit in the BUCK-type power converter.

[0039] Figure 9 Show Figure 1 The schematic circuit diagram shows a first example of the combining unit in the BUCK-type power converter.

[0040] Figure 10 Show Figure 1 The schematic circuit diagram shows a second example of the combining unit in the BUCK-type power converter.

[0041] Figure 11a , Figure 11b , Figure 11c and Figure 11d Equivalent circuit diagrams of power converters with different topologies applying the frequency compensation scheme of this disclosure are shown.

[0042] Figure 12 A flowchart of a frequency compensation method according to a third embodiment of the present disclosure is shown. Detailed Implementation

[0043] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various portions in the drawings are not drawn to scale.

[0044] In this document, the term "output filter network" refers to a circuit structure installed in a power converter for spectral shaping of voltage or current signals and suppression of high-frequency noise. The output filter network includes at least two or more filter elements, including inductors, capacitors, and / or resistors, and is configured as a high-order output filter network through series, parallel, or combinations thereof, such as, but not limited to, LC filter networks and CLC filter networks.

[0045] The term "pole" refers to the dynamic characteristic of a power converter's output as a function of frequency, reflecting the response delay or resonant behavior introduced by energy storage elements in the circuit. The term "zero" refers to the dynamic characteristic in the frequency response that can cancel or mitigate the pole effect, improving the system's stability and transient response by introducing phase lead or gain adjustment.

[0046] The following explanation mainly uses the BUCK-type power converter as an example; however, this disclosure is not limited thereto.

[0047] Figure 1 A schematic circuit diagram of a BUCK-type power converter according to a first embodiment of the present disclosure is shown.

[0048] The power converter 100 includes a main circuit 101, an output filter network 102, and a control circuit 103.

[0049] The main circuit 101 includes switching transistors S1 and S2 connected in series between the DC voltage input terminal and ground, and a main inductor L1 connected to the switching node between the switching transistors S1 and S2.

[0050] The output filter network 102 is connected between the main inductor L1 and the output terminal of the power converter 100. The output filter network 102 includes a first filter capacitor C1, a filter inductor L2, and a second filter capacitor C2 connected in a CLC filter network. Specifically, the first terminal of the filter inductor L2 is connected to the main inductor L1, and its second terminal is connected to the output terminal of the power converter 100; the first filter capacitor C1 is connected between the first terminal of the filter inductor L2 and ground, and the second filter capacitor C2 is connected between the second terminal of the filter inductor L2 and ground.

[0051] The DC output voltage Vo of the power converter 100 is the output voltage of the output filter network 102. The load RL is connected between the output terminal of the power converter 100 and ground. Further, a voltage sampling network samples the DC output voltage Vo to generate a voltage feedback signal VFB characterizing the DC output voltage Vo of the power converter 100. Figure 1 In the illustrated embodiment, the voltage sampling network includes sampling resistors R11 and R12 connected in series between the output terminal of the power converter 100 and ground, with a voltage feedback signal VFB provided at the intermediate node to characterize the DC output voltage Vo of the power converter 100. However, those skilled in the art should understand that the implementation of the voltage sampling network is not limited to this. Figure 1 The specific circuit shown, any voltage feedback signal that samples the DC output voltage to generate a characterizing DC output voltage of the power converter, should fall within the protection scope of this disclosure.

[0052] The filter inductor L2 exhibits nonlinear impedance characteristics in the high-frequency range, with its equivalent impedance initially increasing and then decreasing as the frequency rises. The CLC filter network, formed by the filter inductor L2, the first filter capacitor C1, and the second filter capacitor C2, exhibits low-pass filtering characteristics, allowing DC and low-frequency signals to pass through the passband. In the high-frequency range, although there are resonance peaks caused by parasitic parameters, the attenuation characteristics of the output filter network rapidly increase above these resonant frequencies, effectively suppressing high-frequency switching noise generated by the main circuit. Therefore, this CLC filter network provides excellent noise suppression performance over a wide high-frequency range, maintaining strong attenuation capabilities, especially in the high-frequency range after the resonance peak, thereby improving the stability of the output voltage and electromagnetic compatibility.

[0053] In the embodiments of this disclosure, the filter inductor L2 can be implemented using a ferrite bead inductor. Ferrite bead inductors typically exhibit frequency-varying composite impedance characteristics in the high-frequency range, providing strong attenuation of high-frequency noise components, thereby improving the electromagnetic interference suppression capability of the power converter. However, it should be understood that this disclosure is not limited to using a ferrite bead inductor as the filter inductor L2. In other embodiments, the filter inductor L2 can also be other passive filter elements or inductor structures with equivalent inductance characteristics, as long as they can provide corresponding impedance characteristics within a predetermined frequency range and cooperate with the first filter capacitor C1 and the second filter capacitor C2 to achieve the filtering function of the output filter network, all of which should fall within the protection scope of this disclosure.

[0054] Those skilled in the art should also understand that, in other embodiments, the structure of the output filter network is not limited to the CLC structure described above. The output filter network can be any filter network containing at least two filter elements. For example, as an optional embodiment, the output filter network can be a filter network including two or more filter inductors. As another optional embodiment, the output filter network can omit filter inductors and use resistors instead. As a preferred embodiment, the second filter capacitor C2 can also serve as an energy storage capacitor at the output of the power converter 100 to reduce the number of external components and simplify the circuit structure.

[0055] The control circuit 103 includes a first compensation unit 11, a second compensation unit 12, a synthesis unit 13, a comparator 14, a logic unit 15, and a driver 16.

[0056] The first compensation unit 11 generates a first compensation signal COMP1 based on the DC output voltage Vo of the power converter 100, which is used to introduce feedforward compensation related to low-frequency poles. The first compensation unit 11 mainly operates in the low-frequency range and is used to dynamically compensate for the low-frequency poles formed by the load resistor RL and the equivalent filter capacitors C1 and C2 at the output of the power converter 100.

[0057] The second compensation unit 12 generates a second compensation signal COMP2 based on the input voltage VL of the output filter network, which is used to introduce feedforward compensation dynamically related to high-frequency poles. The second compensation unit 12 mainly operates in the high-frequency range and is used to dynamically compensate for high-frequency poles introduced by the CLC filter network.

[0058] Those skilled in the art will understand that, in one embodiment, the second compensation unit 12 has a wider closed-loop bandwidth than the first compensation unit 11 to better achieve dynamic compensation of high-frequency poles. In other embodiments, the bandwidth relationship between the first compensation unit 11 and the second compensation unit 12 is not limited. For example, in one embodiment, the bandwidth of the first compensation unit 11 is smaller so that even if the double poles are outside the bandwidth of the first compensation unit 11, the second compensation unit 12 can still dynamically compensate for the high-frequency poles.

[0059] Those skilled in the art should understand that the generation of the second compensation signal based on the input voltage of the output filter network as described throughout this disclosure can be as shown in the illustrated embodiments herein, where the second compensation unit 12 is connected to the common node of the main inductor and the output filter network, and the input voltage of the output filter network is sampled to generate the second compensation signal. In other embodiments, the situation in which a signal characterizing the input voltage of the output filter network is generated by circuit simulation, and the second compensation signal is further generated based on the signal, should also fall within the protection scope of this disclosure.

[0060] The synthesis unit 13 is connected to the first compensation unit 11 and the second compensation unit 12, and combines the first compensation signal COMP1 and the second compensation signal COMP2 into a system compensation signal COMP. Due to the synergistic effect of the first compensation unit 11 and the second compensation unit 12, the system compensation signal COMP achieves dual compensation for low-frequency and high-frequency poles in the frequency domain, that is, it achieves the function of dual-pole compensation for the power converter 100.

[0061] Those skilled in the art should understand that in this embodiment and other embodiments of this disclosure, low frequency and high frequency refer to the relative high and low of two frequencies, that is, the high frequency is higher than the low frequency. Low frequency and high frequency do not specifically refer to a certain frequency band. Of course, in some embodiments, the high frequency can be a common high frequency band, and the low frequency can be a common low frequency band. These embodiments should all fall within the scope of protection of this disclosure. By introducing a double zero point in the compensation network, the loop can effectively cancel or alleviate the phase lag caused by the low frequency pole, improve the loop gain in the low frequency band, thereby enhancing the steady-state regulation accuracy of the DC output voltage Vo, and suppressing the output voltage deviation caused by low frequency and high frequency disturbances.

[0062] Further, in the control circuit 103, comparator 14 compares the system compensation signal COMP with the current detection signal ISEN obtained via the current loop to obtain a reset signal, which is used to control the output state of logic unit 15 to flip. The current detection signal ISEN is a current detection signal obtained via the current loop, used to characterize the inductor current iL. This current detection signal ISEN is, for example, a voltage signal corresponding to the magnitude of the inductor current iL. Logic unit 15 is, for example, an RS flip-flop, whose set terminal receives the clock signal CLK, its reset terminal receives the reset signal from comparator 14, and its output terminal generates a modulation signal PWM. The modulation signal PWM is amplified by driver 16 to generate non-overlapping switch control signals VGH and VGL, used to control the conduction states of switches S1 and S2.

[0063] In a preferred embodiment, the control circuit 10 may further include a slope compensation unit. The slope compensation unit is used to superimpose a slope signal synchronized with the clock signal CLK onto the current detection signal ISEN to suppress the instability of slope oscillation when the duty cycle is greater than 50%, ensuring that the system operates stably over a wide range of input voltage and load variations.

[0064] In this embodiment, the clock signal CLK is used to generate a fixed switching cycle, the system compensation signal COMP is used to set the duty cycle reference in each switching cycle, and the current detection signal ISEN reflects the inductor current in real time. When the two reach a balance in comparator 14, a reset action is triggered, thereby adjusting the pulse width of the PWM signal and realizing precise control of the DC output voltage Vo.

[0065] This embodiment is based on a voltage-current dual-loop control architecture to achieve peak current control of a BUCK-type power converter; however, this disclosure is not limited thereto. This disclosure can be applied to any control method, including but not limited to peak current control, valley current control, constant on-time control, constant off-time control, average current mode control, voltage mode control, etc., as long as a first voltage feedback loop already exists in the control circuit.

[0066] In this embodiment, the control circuit 103 dynamically adjusts the duty cycle of switches S1 and S2 according to the voltage feedback signal VFB of the DC output voltage Vo of the power converter 100, so as to counteract the effects of input voltage fluctuations and load changes, thereby realizing and stabilizing a constant DC output voltage Vo at the output terminal.

[0067] Figure 2 A schematic circuit diagram of a BUCK-type power converter according to a second embodiment of the present disclosure is shown.

[0068] The power converter 200 includes a main circuit 101, an output filter network 102, and a control circuit 203. The main circuit 101 and output filter network 102 of the BUCK-type power converter 200 according to the second embodiment are the same as those of the BUCK-type power converter 100 according to the first embodiment, and will not be described in detail here. Furthermore, the control circuit 203 of the BUCK-type power converter 200 according to the second embodiment has the same internal circuitry as the control circuit 103 of the BUCK-type power converter 100 according to the first embodiment, and will not be described in detail here.

[0069] The control circuit 203 of the BUCK-type power converter 200 according to the second embodiment acquires a current feedback signal IFB of the DC output current Io of the power converter 200. The current feedback signal IFB is a current detection signal obtained through a current loop and is used to characterize the DC output current Io of the power converter 200. This current feedback signal IFB is, for example, a voltage signal corresponding to the magnitude of the DC output current Io.

[0070] The first compensation unit 11 generates a first compensation signal COMP1 based on the DC output current Io of the power converter 100, which is used to introduce feedforward compensation related to low-frequency poles. The first compensation unit 11 mainly operates in the low-frequency range and is used to dynamically compensate for the low-frequency poles formed by the load resistor RL and the equivalent filter capacitors C1 and C2 at the output of the power converter 100.

[0071] The second compensation unit 12 generates a second compensation signal COMP2 based on the input voltage VL of the output filter network, which is used to introduce feedforward compensation dynamically related to high-frequency poles. The second compensation unit 12 mainly operates in the high-frequency range and is used to dynamically compensate for high-frequency poles introduced by the CLC filter network.

[0072] In this embodiment, the control circuit 203 dynamically adjusts the duty cycle of switches S1 and S2 according to the current feedback signal IFB of the DC output current Io of the power converter 200 to counteract the effects of input voltage fluctuations and load changes, thereby realizing and maintaining a constant DC output current Io at the output terminal.

[0073] Figure 3 Show Figure 1 and Figure 2 The diagram shows the operating waveforms of the main signals of the BUCK-type power converter. In the diagram, VGH represents the switching control signal of the switching transistor S1, iL represents the current flowing through the main inductor L1, and VL represents the input voltage of the output filter network 102.

[0074] In operation, the power converter's switching transistor S1 receives the switching control signal VGH, and S2 receives a switching control signal complementary to VGH. During each switching cycle, transistors S1 and S2 alternately conduct, thereby controlling the charging and discharging process of the main inductor L1. When transistor S1 is on, the main inductor L1 is charged using the DC input voltage Vin, and the inductor current iL increases linearly. When transistor S2 is on, the main inductor L1 discharges to ground, and the inductor current iL decreases linearly. The DC output voltage Vo is the voltage smoothed by the output filter network 102, and its amplitude is determined by the duty cycle of transistor S1. Under steady-state conditions, the output voltage Vo is approximately the product of the input voltage Vin and the duty cycle D, i.e., Vo ≈ D·Vin.

[0075] The input voltage VL of the output filter network 102 contains both DC and AC components, while the output voltage Vo primarily contains a DC component. The output filter network 102 significantly attenuates AC components above the cutoff frequency, effectively suppressing high-frequency noise in the output voltage. In the input voltage VL of the output filter network 102, the DC component approximately corresponds to the DC output voltage Vo, while the AC component mainly consists of high-frequency harmonics introduced by switching operations. The peak position of this AC component occurs when the inductor current iL rises or falls to a value close to the average value of the load current, which can be considered as the midpoint between the peak and valley values ​​of the inductor current. At this time, the charging and discharging state of the main inductor L1 reverses, causing a significant jump in the input voltage VL of the output filter network 102, manifested as enhanced transient fluctuations in the input voltage VL.

[0076] See Figure 4 The equivalent circuit diagram of the BUCK-type power converter is shown in the figure. Under small-signal conditions, the frequency domain approximation analysis of the filter network shows that the relationship between the input voltage VL of the output filter network 102 and the main inductor current iL can be expressed as formula (1):

[0077] (1)

[0078] Where VL represents the input voltage of the filter network, iL represents the inductance current flowing through the main inductor L1, RL represents the equivalent resistance of the load, C1 and C2 represent the capacitance values ​​of the two filter capacitors in the filter network, L2 represents the inductance value of the ferrite bead inductor L2 in the filter network, and s represents the complex frequency domain variable in the Laplace transform, where s = jω, and ω is the angular frequency.

[0079] The approximate transfer function between the DC output voltage Vo of the power converter, i.e. the output voltage of the output filter network 102, and the input voltage VL can be further expressed as formula (2):

[0080] (2)

[0081] The input voltage VL of the filter network mainly depends on the charging and discharging process of the main inductor L1. This input voltage VL always includes the superposition of DC and AC components. Equation (1) above reflects the first-order low-pass characteristic formed by the load resistor and parallel filter capacitor on the main inductor current under the condition that the filter inductor L2 is approximately low impedance in the low-frequency range. Equation (2) above reflects that under the condition that the impedance of the filter inductor L2 increases significantly in the high-frequency range, the filter inductor L2, the first filter capacitor C1, and the second filter capacitor C2 together form a CLC filter network, forming a second-order low-pass filter. The cutoff frequency of this filter network is determined by the parameters of L2, C1, and C2. In the case of frequencies higher than the cutoff frequency, high-frequency harmonic components are significantly attenuated, thereby effectively suppressing ripple and noise in the output voltage.

[0082] According to formulas (1) and (2), when the output filter network 102 of the power converter is connected between the main inductor L1 and the output terminal of the power converter, the DC output voltage Vo includes the combined effect of low-frequency pole terms and high-frequency pole terms.

[0083] On the one hand, under the condition that the filter inductor L2 is approximately low impedance in the low-frequency range, the inductance current of the main inductor L1 passes through the load resistor RL and the equivalent parallel capacitor network formed by the first filter capacitor C1 and the second filter capacitor C2, causing the output voltage to exhibit a first-order low-pass characteristic as the frequency changes, thus forming the inherent output pole of the BUCK power converter. In formula (2), the expression for the low-frequency pole term is: .

[0084] On the other hand, the filter inductor L2, the first filter capacitor C1, and the second filter capacitor C2 constitute a filter sub-network containing three independent energy storage elements. This filter sub-network exhibits second-order dynamic characteristics in the high-frequency range and forms a pair of poles under the damping effect of the load resistor RL. Thus, the output filter network 102, while suppressing high-frequency noise, also introduces additional high-frequency poles into the output transfer characteristics of the power converter 100. In formula (2), the expression for the high-frequency pole term is: .

[0085] Due to the presence of the two pole terms mentioned above, existing power converters will exhibit a sharp phase lag near the natural frequencies corresponding to the poles. Without frequency compensation, the loop phase margin will be insufficient, potentially leading to system instability or even oscillation.

[0086] The following combination Figure 1 The BUCK-type power converter shown in the diagram details the double-pole compensation mechanism in its control circuit. It can be understood that this double-pole compensation mechanism can also be applied to... Figure 2 The BUCK-type power converter shown here has a detailed description of its control circuit, with the only difference being some component parameters in the formula.

[0087] Figure 5 Show Figure 1 The diagram shows a schematic circuit of the first compensation unit of the BUCK-type power converter.

[0088] The first compensation unit 11 obtains the voltage feedback signal VFB from the resistor voltage divider network outside the control circuit 103. The voltage divider network is composed of resistors R11 and R12 connected in series.

[0089] In the first compensation unit 11, the inverting input of the error amplifier 111 receives the voltage feedback signal VFB, and the non-inverting input receives the reference voltage REF1. The compensation resistor Rc and the compensation capacitor Cc are connected in series between the output of the error amplifier 111 and ground.

[0090] Those skilled in the art should understand that, Figure 1 In the embodiment shown, the compensation network of the first compensation unit 11 is formed by connecting the compensation resistor Rc and the compensation capacitor Cc in series. In other embodiments, any compensation network that can work in conjunction with the error amplifier 111 to dynamically compensate the low-frequency poles of the power converter should fall within the protection scope of this disclosure.

[0091] The error signal generated by error amplifier 111 is converted into a first compensation signal COMP1 by a compensation network. In this example, the first compensation signal COMP1 is a voltage signal.

[0092] The first compensation signal COMP1 generated by the first compensation unit 11 is shown in formula (3):

[0093] (3)

[0094] Where g1 represents the transconductance gain of the first compensation unit 11, R11 and R12 are the sampling resistors for the DC output voltage Vo, and Rc and Cc represent the resistance values ​​of the compensation resistor and the capacitance values ​​of the compensation capacitor in the compensation network. This represents the transfer function of the first compensation unit 11.

[0095] According to formula (3), the compensation resistor Rc and the compensation capacitor Cc together introduce integral characteristics and phase compensation zero point, which are used to adjust the frequency response of the first compensation unit 11, thereby alleviating the phase lag effect introduced by the inherent low frequency pole of the power converter within a certain frequency range, so as to improve the closed-loop stability of the power converter and improve its dynamic response performance.

[0096] Figures 6 to 8 Show Figure 1 The diagram shows schematic circuit diagrams of different examples of the second compensation unit of a BUCK-type power converter. The second compensation unit obtains the input voltage VL of the output filter network 102 and generates a second compensation signal COMP2 based on the input voltage VL of the filter network.

[0097] In the example of the second compensation unit described below, a reference voltage REF2 is used as a voltage reference. In a preferred embodiment, the reference voltage REF2 is, for example, ground potential, so that the error amplifier 12 acquires the high-frequency fluctuation component of the filter network input voltage VL relative to ground.

[0098] See Figure 6 The second compensation unit 12 includes an input filter network 121 and an error amplifier 122.

[0099] The input filter network 121 includes an input capacitor C21 and an input resistor R21. The input capacitor C21 and the input resistor R21 are connected in series between the intermediate node between the main inductor L1 and the output filter network 102 and the reference voltage REF2, forming a first-order RC filter network used to obtain a high-frequency sampling signal of the filter network's input voltage VL. The inverting input of the error amplifier 122 is connected to the intermediate node of capacitor C21 and resistor R21 to receive this high-frequency sampling signal, while the non-inverting input receives the reference voltage REF2. The output of the error amplifier 122 provides a second compensation signal COMP2, which reflects the high-frequency variation characteristics of the filter network's input voltage VL. In this example, the second compensation signal COMP2 is a current signal.

[0100] See Figure 7The second compensation unit 22 includes an input filter network 221 and an error amplifier 122.

[0101] The input filter network 221 includes input capacitors C21 and C22, and input resistors R21 and R22. Input capacitor C21 and input resistor R21 are connected in series between the intermediate node between the main inductor L1 and the output filter network 102 and the reference voltage REF2. Input resistor C22 and input resistor R22 are connected in series between the intermediate node between input capacitor C21 and input resistor R21 and the reference voltage REF2, forming a second-order RC filter network used to obtain a high-frequency sampling signal of the filter network's input voltage VL. The inverting input of the error amplifier 122 is connected to the intermediate node between input capacitor C22 and input resistor R22 to receive this high-frequency sampling signal, while the non-inverting input receives the reference voltage REF2. The output of the error amplifier 122 provides a second compensation signal COMP2, which reflects the high-frequency variation characteristics of the filter network's input voltage VL. In this example, the second compensation signal COMP2 is a current signal.

[0102] and Figure 6 Compared to the first example shown, in Figure 7 In the second example shown, the use of a second-order RC filter network can more effectively attenuate low- and mid-frequency interference components, thereby improving the detection sensitivity to high-frequency resonant peaks. This structure can also be improved from second-order filtering to higher-order filtering, making the high-frequency components in the sampled signal purer. This is beneficial for the error amplifier 122 to accurately capture rapid changes in the filter network's input voltage VL, thus improving the load transient response speed.

[0103] See Figure 8 The second compensation unit 32 includes an operational amplifier 131, an input capacitor C31, an input resistor R31, and a feedback resistor R32.

[0104] The inverting input of operational amplifier 131 is connected to the intermediate node between the main inductor L1 and the output filter network 102 via a series-connected input capacitor C31 and input resistor R31, while the non-inverting input receives the reference voltage REF2. Further, the inverting input of operational amplifier 131 is connected to its output via a feedback resistor R32. In the second compensation unit 32, the input capacitor C31 and input resistor R31 serve as filtering elements, forming a high-pass filter structure to extract the high-frequency signal component of the filter network's input voltage VL. In this example, the second compensation signal COMP2 is a voltage signal.

[0105] Figures 9 to 10 Show Figure 1 The diagram shows schematic circuit diagrams of different examples of the combining unit of a BUCK-type power converter. The combining unit combines the first compensation signal COMP1 and the second compensation signal COMP2 into the system compensation signal COMP.

[0106] See Figure 9 The synthesis unit 13 includes an isolation resistor R13. The first end of the isolation resistor R13 is coupled to the first compensation signal COMP1, and the second end is coupled to the second compensation signal COMP2 and the system compensation signal COMP.

[0107] In the first example, the isolation resistor R13 serves both to linearly superimpose the first compensation signal COMP1 and the second compensation signal COMP2, and to isolate the first compensation unit 11 and the second compensation unit 12. If both the first compensation signal COMP1 and the second compensation signal COMP2 are current signals, the current summation of the first compensation signal COMP1 and the second compensation signal COMP2 is achieved at the second terminal of the isolation resistor R13. If both the first compensation signal COMP1 and the second compensation signal COMP2 are voltage signals, the signal selection of the first compensation signal COMP1 and the second compensation signal COMP2 is achieved at the second terminal of the isolation resistor R13.

[0108] See Figure 10 The synthesis unit 23 includes an operational amplifier 131 and an isolation resistor R23. The inverting input and output of the operational amplifier 131 are connected, and its non-inverting input is connected to the output of the first compensation unit 11 to receive the first compensation signal COMP1. Therefore, the operational amplifier 131 constitutes a voltage follower structure. The output of the operational amplifier 131 is connected to the output of the second compensation unit via the isolation resistor R23. Furthermore, the output of the second compensation unit 12 is connected to the output of the synthesis unit 23, thereby achieving the merging of the first compensation signal COMP1 and the second compensation signal COMP2 at the output of the synthesis unit 23. In this embodiment, the voltage follower structure effectively isolates the mutual interference between the first compensation signal COMP1 and the second compensation signal COMP2, ensuring the accuracy of signal merging and system stability.

[0109] In the second example, the voltage follower and isolation resistor in the synthesis unit 23 serve the dual functions of linearly superimposing the first compensation signal COMP1 and the second compensation signal COMP2, and isolating the first compensation unit 11 and the second compensation unit 12. The first compensation signal COMP1 and the second compensation signal COMP2 are a voltage signal and a current signal, respectively. The voltage follower and isolation resistor convert the first compensation signal COMP1 into a first compensation current, and the second compensation signal COMP2 into a second compensation current. The output of the synthesis unit 23 sums the first compensation current and the second compensation current to obtain the system compensation signal.

[0110] The first example described above illustrates a synthesis unit used to perform current summation and signal selection for the first compensation signal COMP1 and the second compensation signal COMP2. However, this disclosure is not limited thereto; the synthesis unit can be any circuit that linearly superimposes the first compensation signal COMP1 and the second compensation signal COMP2, including but not limited to any one or more of current summation, voltage summation, current differential calculation, voltage differential calculation, and selection.

[0111] The system compensation signal COMP generated by the above synthesis units 13 and 23 is shown in formula (4):

[0112] (4)

[0113] Where g1 and g2 are the transconductance gains of the first compensation unit 11 and the second compensation unit 12, respectively; R11 and R12 represent the resistance values ​​of the sampling resistor for the DC output voltage Vo; and R13 represents the resistance value of the isolation resistor inside the synthesis unit 13.

[0114] In the compensation model of formula (4), under the design matching condition, the zero-point term introduced by the first compensation unit 11 Low-frequency poles of the power stage The zero-point terms introduced by the second compensation unit 12 mutually cancel out or mitigate their effects. High-frequency poles of the filter network They cancel each other out or mitigate their effects. At this point, the frequency dependence of the system compensation signal COMP in the control circuit is mainly determined by sCc, and the overall closed-loop response approaches that of a single-pole system.

[0115] In this embodiment, the power stage of the power converter exhibits high-order characteristics due to the CLC filter. The second compensation unit 12 directly samples the input voltage VL(s) of the filter network and generates the second compensation signal COMP2(s) based on it. Since VL(s) is located at the front end of the output filter network, its dynamic changes occur earlier than the output voltage Vo(s), enabling it to reflect high-frequency disturbance information more promptly. More importantly, the transmission path of the second compensation unit 12 naturally contains a double-zero structure corresponding to the high-frequency poles of the filter network, and its frequency position is highly matched with the C1-L2-C2 resonant mode. When the system enters the high-frequency region, this double-zero structure effectively cancels out the high-frequency poles introduced by the filter network, significantly suppressing the occurrence of resonance peaks and improving the phase characteristics near the cross-frequency. Through the coordinated control of the first compensation unit 11 and the second compensation unit 12, the control system of the power converter is effectively reconstructed into a first-order frequency response system with excellent stability and fast response capability.

[0116] Figure 11a , Figure 11b , Figure 11cand Figure 11d Equivalent circuit diagrams of power converters with different topologies applying the frequency compensation scheme of this disclosure are shown.

[0117] See Figure 11a In the BUCK-type power converter, switches S1 and S2 are connected in series between the DC voltage input terminal and ground. The main inductor L1 is connected between the intermediate node of switches S1 and S2 and the input of the output filter network 102. The output of the output filter network 102 is connected to the DC voltage output terminal. The load RL is connected between the DC voltage output terminal and ground.

[0118] See Figure 11b In the BOOST power converter, switches S1 and S2 are connected in series between the input of the output filter network 102 and ground. The main inductor L1 is connected between the DC voltage input terminal and the intermediate node of switches S1 and S2. The output of the output filter network 102 is connected to the DC voltage output terminal. The load RL is connected between the DC voltage output terminal and ground.

[0119] See Figure 11c In the first example of the BUCK-BOOST power converter, switches S1 and S2 are connected in series between the DC voltage input terminal and ground, and switches S3 and S4 are connected in series between the input of the output filter network 102 and ground. The first end of the main inductor L1 is connected to the intermediate node between switches S1 and S2, and the second end is connected to the intermediate node between switches S3 and S4. The output filter network 102 is connected between the intermediate node of switches S3 and S4 and the DC voltage output terminal. The load RL is connected between the DC voltage output terminal and ground. In this example, the DC output voltage Vo provided at the DC voltage output terminal is a positive voltage.

[0120] See Figure 11d In the second example of the BUCK-BOOST power converter, switches S1 and S2 are connected in series between the DC voltage input terminal and the input of the output filter network 102. The first terminal of the main inductor L1 is connected to the intermediate node between switches S1 and S2, and the second terminal is grounded. The output filter network 102 is connected between switch S2 and the DC voltage output terminal. The load RL is connected between the DC voltage output terminal and ground. In this example, the DC output voltage Vo provided at the DC voltage output terminal is negative.

[0121] In the example above, the output filter network 102 includes a first filter capacitor C1, a filter inductor L2, and a second filter capacitor C2 connected in a CLC filter network. Specifically, the first filter capacitor C1 is connected between the first terminal of the filter inductor L2 and ground, and the second filter capacitor C2 is connected between the second terminal of the filter inductor L2 and ground.

[0122] In the example above, the first compensation unit 11 in the control circuit performs low-frequency pole compensation based on the DC output voltage Vo, and the second compensation unit 12 performs high-frequency pole compensation based on the input voltage VL of the output filter network 102. The control circuit generates switching control signals for multiple switches in the power converter. The duty cycle of this switching control signal is related to the system compensation signal, thereby enabling dynamic adjustment of the DC output parameters and performing dual-pole compensation on the power converter based on the duty cycle of the switching control signal.

[0123] Figure 12 A flowchart of a frequency compensation method according to a third embodiment of this disclosure is shown. The power converter includes a power stage and an output filter network coupled thereto. The power stage includes a main inductor and a plurality of switches for controlling the charging and discharging processes of the main inductor.

[0124] The frequency compensation method includes steps S01 to S04.

[0125] In step S01, a first compensation signal COMP1 is generated based on the DC output parameters of the power converter (DC output voltage Vo, and / or DC output current Io). The first compensation signal COMP1 is a current signal or a voltage signal.

[0126] In step S02, a second compensation signal COMP2 is generated based on the input voltage VL of the output filter network in the power converter.

[0127] Preferably, the step of generating the second compensation signal COMP2 includes: extracting a high-frequency sampling signal from the input voltage VL of the output filter network; and comparing the high-frequency sampling signal with a first reference voltage to generate the second compensation signal COMP2, wherein the second compensation signal COMP2 is a current signal or a voltage signal.

[0128] In step S03, the first compensation signal COMP1 and the second compensation signal COMP2 are combined into the system compensation signal COMP.

[0129] Preferably, the step of combining the first compensation signal COMP1 and the second compensation signal COMP2 into a system compensation signal COMP includes: linearly superimposing the first compensation signal COMP1 and the second compensation signal COMP2, wherein linear superposition includes any one or more of current summation, voltage summation, current difference, voltage difference, and signal selection.

[0130] In step S04, switching control signals VGH and VGL for multiple switches are generated. The duty cycles of the switching control signals VGH and VGL are related to the system compensation signal COMP, thereby enabling dynamic adjustment of DC output parameters based on the duty cycles of the switching control signals VGH and VGL, and performing double-pole compensation on the power converter.

[0131] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0132] As described above, these embodiments of the present disclosure do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present disclosure, thereby enabling those skilled in the art to make good use of the present disclosure and modifications based on it. This disclosure is limited only by the claims and their full scope and equivalents.

Claims

1. A control circuit for a power converter, the power converter including a power stage and an output filter network coupled thereto, the power stage including a main inductor and a plurality of switches for controlling the charging and discharging processes of the main inductor, the control circuit including: The first compensation unit generates a first compensation signal based on the DC output parameters of the power converter. The second compensation unit generates a second compensation signal based on the input voltage of the output filter network. A synthesis unit is configured to synthesize the first compensation signal and the second compensation signal into a system compensation signal; and A logic unit is used to generate switching control signals for the plurality of switches. The duty cycle of the switch control signal is related to the system compensation signal, thereby enabling dynamic adjustment of the DC output parameters and double-pole compensation of the power converter based on the duty cycle of the switch control signal.

2. The control circuit according to claim 1, wherein, The second compensation unit includes: An input filter network, coupled to the input of the output filter network, is used to extract a high-frequency sampling signal from the input voltage of the output filter network; and A first error amplifier is used to compare the high-frequency sampled signal with a first reference voltage to generate a second compensation signal, wherein the second compensation signal is a current signal.

3. The control circuit according to claim 2, wherein, The input filtering network includes at least one filtering stage, and each of the at least one filtering stage includes an input capacitor and an input resistor connected in series.

4. The control circuit according to claim 1, wherein, The second compensation unit includes: An input capacitor, coupled to the input of the output filter network, is used to extract a high-frequency sampling signal from the input voltage of the output filter network; and A first operational amplifier is used to amplify the differential signal between the high-frequency sampling signal and the first reference voltage to generate the second compensation signal, wherein the second compensation signal is a voltage signal.

5. The control circuit according to any one of claims 2 to 4, wherein, The first reference voltage is the ground potential.

6. The control circuit according to any one of claims 1 to 4, wherein, The synthesis unit includes: An isolation resistor, wherein a first end of the isolation resistor is coupled to the first compensation signal, a second end is coupled to the second compensation signal, and a system compensation signal is provided.

7. The control circuit according to any one of claims 1 to 4, wherein, The synthesis unit includes: Voltage follower; and An isolation resistor, the first end of which is coupled to the output terminal of the voltage follower. The input terminal of the voltage follower is coupled to the first compensation signal, and the second terminal of the isolation resistor is coupled to the second compensation signal and provides the system compensation signal.

8. The control circuit according to any one of claims 1 to 4, wherein, The first compensation unit includes: A second error amplifier is used to compare the feedback signal of the DC output parameters with a second reference voltage to generate an error signal; and A compensation network, coupled to the output of the second error amplifier, is used to convert the error signal into the first compensation signal, which is a voltage signal.

9. The control circuit according to claim 1, wherein, The DC output parameters are at least one of the DC output voltage and DC output current of the power converter.

10. A power converter, comprising: A power stage, the power stage including a main inductor and a plurality of switches for controlling the charging and discharging process of the main inductor; An output filter network is coupled between the main inductor and the output terminal of the power converter; as well as The control circuit according to any one of claims 1 to 9.

11. The power converter according to claim 10, wherein, The output filter network is a high-order filter network containing at least two filter elements.

12. The power converter according to claim 11, wherein, The output filtering network includes: Filter inductor; A first filter capacitor coupled between the first terminal of the filter inductor and ground; and A second filter capacitor is coupled between the second terminal of the filter inductor and ground.

13. The power converter according to claim 12, wherein, The filter inductor is a ferrite bead inductor.

14. The power converter according to claim 10, wherein, The power converter is selected from any one of the following topologies: BUCK type, BOOST type, BUCK-BOOST type, and flyback topology.

15. The power converter according to claim 14, wherein, The plurality of switches includes a first switch and a second switch connected in series between the input terminal of the power converter and ground. The first end of the main inductor is coupled to the intermediate node between the first switch and the second switch, and the second end is coupled to the inlet of the output filter network.

16. A frequency compensation method for a power converter, the power converter including a power stage and an output filter network coupled thereto, the power stage including a main inductor and a plurality of switches for controlling the charging and discharging process of the main inductor, the frequency compensation method comprising: A first compensation signal is generated based on the DC output parameters of the power converter; A second compensation signal is generated based on the input voltage of the output filter network in the power converter; The first compensation signal and the second compensation signal are combined into a system compensation signal; as well as Generate switching control signals for the plurality of switches. The duty cycle of the switch control signal is related to the system compensation signal, thereby enabling dynamic adjustment of the DC output parameters and double-pole compensation of the power converter based on the duty cycle of the switch control signal.

17. The frequency compensation method according to claim 16, wherein, The steps for generating the second compensation signal include: High-frequency sampling signals are extracted from the input voltage of the output filter network; and The high-frequency sampling signal is compared with a first reference voltage to generate the second compensation signal, which is a current signal or a voltage signal.

18. The frequency compensation method according to claim 16, wherein, The step of combining the first compensation signal and the second compensation signal into a system compensation signal includes: The first compensation signal and the second compensation signal are linearly superimposed. The linear superposition includes any one or more of the following: current summation, voltage summation, current difference, voltage difference, and signal selection.

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