Radio frequency power amplifier circuit, radio frequency front-end chip and radio frequency front-end module

Abstract

The invention provides a radio frequency power amplifier circuit, a radio frequency front-end chip and a radio frequency front-end module, and relates to the technical field of radio frequency power amplifiers. In the first gain mode, the biasing circuit can control all transistors in all power amplifiers to be switched on; and in the second gain mode, the biasing circuit can control all transistors between the cascade output ports and the grounding end in all the multiplexing power amplifiers to be switched on, and the switching circuit can control cascade connection among all the multiplexing power amplifiers and output a target radio frequency signal through the output matching circuit. Therefore, a high-gain first gain mode is realized by controlling all the transistors in all the cascaded power amplifiers to work, and a low-gain second gain mode is realized by controlling part of the transistors in the multiplexing power amplifiers to work, so that multi-gain mode work of the radio frequency power amplifier circuit is realized; the radio frequency power amplifier circuit is prevented from working in a deep rollback state, and high efficiency of the radio frequency power amplifier circuit in different gain modes is ensured.

Description

Technical Field

[0001] This application relates to the field of radio frequency power amplifier technology, and more specifically, to a radio frequency power amplifier circuit, a radio frequency front-end chip, and a radio frequency front-end module. Background Technology

[0002] The radio frequency (RF) front-end is a core component of modern wireless communication devices such as mobile phones, base stations, and routers. Its main function is to process and receive signals. RF front-end circuits typically include low-noise amplifiers (LNOA), power amplifiers, band switches, and filters. The LNOA and power amplifiers amplify the RF signal to a sufficiently high power to drive the antenna to radiate electromagnetic waves. The band switch and filter work together to control the switching of the RF signal between different frequency bands. Currently, when RF front-end power amplifiers achieve multi-gain mode operation, external control to reduce bias and supply voltage is usually used. However, for cascaded multi-stage power amplifiers, achieving a low-gain mode through external control of bias and supply voltage is difficult, making multi-gain mode operation impossible. Summary of the Invention

[0003] In view of this, this application provides an RF power amplifier circuit, an RF front-end chip, and an RF front-end module, which effectively solves the technical problems existing in the prior art. It achieves a high-gain first gain mode by controlling the operation of all transistors in all cascaded power amplifiers, and a low-gain second gain mode by controlling the operation of some transistors in multiplexed power amplifiers. This realizes the multi-gain mode operation of the RF power amplifier circuit and ensures that the RF power amplifier circuit has high efficiency in different gain modes.

[0004] To achieve the above objectives, the technical solution provided in this application is as follows:

[0005] A radio frequency power amplifier circuit, comprising:

[0006] At least two cascaded power amplifiers, each power amplifier including at least two transistors connected in series between a power supply voltage terminal and a ground terminal; the input terminal of the first-stage power amplifier is connected to an input radio frequency signal via an input matching circuit, and the output terminal of the previous-stage power amplifier is connected to the input terminal of the next-stage power amplifier via an inter-stage matching circuit; the output terminal of the last-stage power amplifier outputs a target radio frequency signal via an output matching circuit; starting from the second-stage power amplifier and along the cascade sequence of the power amplifiers, all power amplifiers include at least one multiplexed power amplifier;

[0007] A bias circuit is electrically connected to the gate of the transistor; the bias circuit is used to control all transistors in all power amplifiers to be turned on in a first gain mode; and the bias circuit is used to control all transistors between the cascaded output port and the ground terminal in all multiplexed power amplifiers to be turned on in a second gain mode, wherein the cascaded output port is the connection terminal of two pre-set adjacent transistors connected in series in the multiplexed power amplifier; wherein the gain in the second gain mode is less than the gain in the first gain mode;

[0008] The RF power amplifier circuit includes an auxiliary matching circuit and a switching circuit. The auxiliary matching circuit is used to receive the input RF signal, and the switching circuit is used to stop operating in the first gain mode. When the RF power amplifier circuit includes one stage of the multiplexed power amplifier, the switching circuit is activated in the second gain mode, controlling the inter-stage matching circuit electrically connected to the input terminal of the multiplexed power amplifier to connect with the auxiliary matching circuit, and simultaneously controlling the cascaded output port of the multiplexed power amplifier to connect with the output matching circuit. Alternatively, when the RF power amplifier circuit includes at least two stages of the multiplexed power amplifier, the switching circuit is activated in the second gain mode, controlling the inter-stage matching circuit electrically connected to the input terminal of the first stage of the multiplexed power amplifier to connect with the auxiliary matching circuit, controlling the cascaded output port of the previous stage of the multiplexed power amplifier to connect with the inter-stage matching circuit electrically connected to the input terminal of the next stage of the multiplexed power amplifier, and simultaneously controlling the cascaded output port of the last stage of the multiplexed power amplifier to connect with the output matching circuit.

[0009] Optionally, the at least two transistors are defined as the first transistor to the Nth transistor, and the power amplifier includes a resistor;

[0010] The first end of the resistor is electrically connected to the power supply voltage terminal, the second end of the resistor is electrically connected to the first end of the first transistor as the output terminal of the power amplifier, the second end of the i-th transistor is electrically connected to the first end of the (i+1)-th transistor, the second end of the N-th transistor is electrically connected to the ground terminal, the gates of the first transistor to the N-th transistor are all electrically connected to the bias circuit, and the gate of the N-th transistor is the input terminal of the power amplifier, where i is a positive integer less than N.

[0011] Optionally, the RF power amplifier circuit includes at least two stages of the multiplexed power amplifier;

[0012] Each pair of adjacent multiplexed power amplifiers includes at least one stage of the power amplifier; or, all of the multiplexed power amplifiers are power amplifiers cascaded in succession.

[0013] Optionally, the bias circuit includes:

[0014] A bias control unit, wherein the bias control unit is configured to output a first bias control signal in a first gain mode; and the bias control unit is configured to output a second bias control signal in a second gain mode;

[0015] A bias power supply unit is configured to control all transistors in all power amplifiers to be turned on based on a first bias control signal; and the bias power supply unit is configured to control all transistors between the cascaded output port and the ground terminal in all multiplexed power amplifiers to be turned on based on a second bias control signal.

[0016] Optionally, the bias power supply unit includes:

[0017] At least two bias power supply modules are provided, one of which is electrically connected to the gates of all the transistors in the power amplifier; the bias power supply module is used to control all the transistors in the power amplifier to be turned on based on the first bias control signal; and when the power amplifier electrically connected to the bias power supply module is the multiplexed power amplifier, the bias power supply module is used to control all the transistors between the cascaded output port and the ground terminal in the multiplexed power amplifier to be turned on based on the second bias control signal.

[0018] Optionally, the bias control unit includes:

[0019] At least two bias control modules are provided, one of which is electrically connected to a bias power supply module. The bias control module is configured to output a first bias control signal in the first gain mode and to output a second bias control signal in the second gain mode.

[0020] Optionally, the switching circuit includes:

[0021] A switch control unit, wherein the switch control unit is configured to output a first switch control signal in a first gain mode; and the switch control unit is configured to output a second switch control signal in a second gain mode;

[0022] At least two switching units are provided, wherein the switching units are configured to control shutdown based on the first switching control signal and to control turn-on based on the second switching control signal; wherein, when the RF power amplifier circuit includes a single-stage multiplexed power amplifier, one switching unit is electrically connected between the output terminal of the auxiliary matching circuit and the input terminal of the inter-stage matching circuit electrically connected to the input terminal of the multiplexed power amplifier, and another switching unit is electrically connected between the cascaded output port of the multiplexed power amplifier and the input terminal of the output matching circuit; or, when the RF power amplifier circuit includes at least two stages of the multiplexed power amplifier, one switching unit is electrically connected between the output terminal of the auxiliary matching circuit and the input terminal of the inter-stage matching circuit electrically connected to the input terminal of the first-stage multiplexed power amplifier, one switching unit is electrically connected between the cascaded output port of the previous-stage multiplexed power amplifier and the input terminal of the inter-stage matching circuit electrically connected to the input terminal of the next-stage multiplexed power amplifier, and another switching unit is electrically connected between the cascaded output port of the last-stage multiplexed power amplifier and the input terminal of the output matching circuit.

[0023] Optionally, the RF power amplifier circuit further includes:

[0024] A power detection and control circuit is used to detect whether the power of the target radio frequency signal is less than a set power. If so, the bias circuit and the switching circuit are controlled to operate in the second gain mode; if not, the bias circuit and the switching circuit are controlled to operate in the first gain mode.

[0025] Optionally, the power detection and control circuit includes:

[0026] A power detection unit is used to acquire the target radio frequency signal output by the output matching circuit;

[0027] A detection unit, which is used to convert the target radio frequency signal acquired by the power detection unit into a low frequency signal;

[0028] A threshold comparison unit is used to compare whether the power of the low-frequency signal is less than the set power. If yes, a second enable signal is output; if no, a first enable signal is output.

[0029] The system includes a bias enable generation unit and a switch enable generation unit. The bias enable generation unit controls the bias circuit to operate in the first gain mode according to the first enable signal. The bias enable generation unit controls the bias circuit to operate in the second gain mode according to the second enable signal. The switch enable generation unit controls the switch circuit to operate in the first gain mode according to the first enable signal. The switch enable generation unit controls the switch circuit to operate in the second gain mode according to the second enable signal.

[0030] Based on the same inventive concept, this application also provides a radio frequency front-end chip, which includes the radio frequency power amplifier circuit described above.

[0031] Based on the same inventive concept, this application also provides a radio frequency front-end module, which includes the radio frequency front-end chip described above.

[0032] Compared with existing technologies, the technical solution provided in this application has at least the following advantages:

[0033] This application provides an RF power amplifier circuit, an RF front-end chip, and an RF front-end module. In a first gain mode, the bias circuit controls all transistors in all power amplifiers to conduct, and the switching circuit stops working. In a second gain mode, the bias circuit controls all transistors between the cascaded output ports and ground in all multiplexed power amplifiers to conduct, while the switching circuit controls the cascaded multiplexed power amplifiers and outputs the target RF signal through the output matching circuit. Thus, by controlling the operation of all transistors in all cascaded power amplifiers, a high-gain first gain mode is achieved, and by controlling the operation of some transistors in the multiplexed power amplifiers, a low-gain second gain mode is achieved. This enables multi-gain mode operation of the RF power amplifier circuit, avoiding deep fallback and ensuring high efficiency in different gain modes. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0035] Figure 1 A circuit diagram of a radio frequency power amplifier circuit provided in an embodiment of this application;

[0036] Figure 2A circuit diagram of another radio frequency power amplifier circuit provided in an embodiment of this application;

[0037] Figure 3 A circuit diagram of another radio frequency power amplifier circuit provided in the embodiments of this application;

[0038] Figure 4 A circuit diagram of another radio frequency power amplifier circuit provided in the embodiments of this application;

[0039] Figure 5 A circuit diagram of another radio frequency power amplifier circuit provided in the embodiments of this application;

[0040] Figure 6 A circuit diagram of another radio frequency power amplifier circuit provided in the embodiments of this application;

[0041] Figure 7 A circuit diagram of another radio frequency power amplifier circuit provided in the embodiments of this application;

[0042] Figure 8 A circuit diagram of another radio frequency power amplifier circuit provided in the embodiments of this application;

[0043] Figure 9 A circuit diagram of another radio frequency power amplifier circuit provided in the embodiments of this application;

[0044] Figure 10 A circuit diagram of another radio frequency power amplifier circuit provided in the embodiments of this application;

[0045] Figure 11 This is a circuit diagram of another radio frequency power amplifier circuit provided in an embodiment of this application.

[0046] Explanation of reference numerals in the attached figures:

[0047] 10 Power Amplifier; 101 First-Stage Power Amplifier; 102 Second-Stage Power Amplifier; 103 Third-Stage Power Amplifier; 20 Multiplexed Power Amplifier; 201 First-Stage Multiplexed Power Amplifier; 202 Second-Stage Multiplexed Power Amplifier; 31 Input Matching Circuit; 32 Inter-Stage Matching Circuit; 33 Output Matching Circuit; 40 Bias Circuit; 41 Bias Control Unit; 411 Bias Control Module; 42 Bias Power Supply Unit; 421 Bias Power Supply Module; 50 Auxiliary Matching Circuit; 60 Switching Circuit; 61 Switch Control Unit; 62 Switching Unit; 70 Power Detection Control Circuit; 71 Power Detection Unit; 72 Detection Unit; 73 Threshold Comparison Unit; 74 Bias Enable Generation Unit; 75 Switch Enable Generation Unit; 76 Filtering Unit; 77 DC Power Supply Bias Unit; Vcc Power Supply Voltage Terminal; GND Ground Terminal; RFin Input Radio Frequency Signal; Xout Cascaded Output Port; R Resistor; Qx Transistor; Qx1 First Transistor; Qx2 Second Transistor; Qx3 Third Transistor. Detailed Implementation

[0048] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0049] As described in the background section, the radio frequency (RF) front-end is a core component of modern wireless communication devices such as mobile phones, base stations, and routers. Its main function is to process and receive signals. RF front-end circuits typically include low-noise amplifiers (LNOA), power amplifiers, band switches, and filters. The LNOA and power amplifiers amplify the RF signal to a sufficiently high power to drive the antenna to radiate electromagnetic waves. The band switch and filter work together to control the switching of the RF signal between different frequency bands. Currently, when the power amplifier in an RF front-end achieves multi-gain mode operation, it is usually done by externally controlling the reduction of bias and supply voltage. However, for cascaded multi-stage power amplifiers, achieving a low-gain mode through external control of bias and supply voltage is difficult, and the efficiency obtained is only at the level of deep back-off. Furthermore, it is impossible to achieve multi-gain mode operation for multi-stage power amplifiers.

[0050] Based on this, the embodiments of this application provide an RF power amplifier circuit, an RF front-end chip, and an RF front-end module, which effectively solve the technical problems existing in the prior art. By controlling the operation of all transistors in all cascaded power amplifiers, a high-gain first gain mode is achieved, and by controlling the operation of some transistors in multiplexed power amplifiers, a low-gain second gain mode is achieved. This realizes the multi-gain mode operation of the RF power amplifier circuit and ensures that the RF power amplifier circuit has high efficiency in different gain modes.

[0051] To achieve the above objectives, the technical solutions provided in this application are as follows, in specific combination with... Figures 1 to 11 The technical solutions provided in the embodiments of this application will be described in detail.

[0052] Combination Figure 1 and Figure 2 As shown, Figure 1 This is a circuit diagram of an RF power amplifier circuit provided in an embodiment of this application. Figure 2 A circuit diagram of another radio frequency power amplifier circuit provided in this application embodiment. The radio frequency power amplifier circuit provided in this application embodiment includes:

[0053] At least two cascaded power amplifier stages 10, each power amplifier stage 10 including at least two transistors Qx connected in series between the power supply voltage terminal Vcc and the ground terminal GND; the input terminal of the first stage power amplifier stage 10 is connected to the input radio frequency signal RFin through an input matching circuit 31, and the output terminal of the previous stage power amplifier stage 10 is connected to the input terminal of the next stage power amplifier stage 10 through an inter-stage matching circuit 32; the output terminal of the last stage power amplifier stage 10 outputs the target radio frequency signal through an output matching circuit 33; starting from the second stage power amplifier stage 10, and along the cascading sequence of the power amplifier stages 10, all power amplifier stages 10 include at least one multiplexed power amplifier stage 20. The input matching circuit 31 is used to adjust the system impedance to the input impedance of the first stage power amplifier stage 10, the inter-stage matching circuit 32 is used to transform the input impedance of the next stage power amplifier stage 10 connected to it to the required impedance of the previous stage power amplifier stage 10, and the output matching circuit 33 is used to transform the system impedance to the optimal impedance of the last stage power amplifier stage 10.

[0054] A bias circuit 40 is electrically connected to the gate of the transistor Qx; the bias circuit 40 is used to control all transistors Qx in all power amplifiers 10 to be turned on in a first gain mode; and the bias circuit 40 is used to control all transistors Qx between the cascaded output port Xout and the ground terminal GND in all multiplexed power amplifiers 20 to be turned on in a second gain mode, wherein the cascaded output port Xout is the connection terminal of two pre-set adjacent series-connected transistors Qx in the multiplexed power amplifier 20; wherein the gain in the second gain mode is less than the gain in the first gain mode.

[0055] An auxiliary matching circuit 50 and a switching circuit 60 are provided. The auxiliary matching circuit 50 is used to connect the input RF signal RFin, and the switching circuit 60 is used to stop operating in the first gain mode. When the RF power amplifier circuit includes a single-stage multiplexed power amplifier 20, the switching circuit 60 is used to activate in the second gain mode, controlling the inter-stage matching circuit 32 electrically connected to the input terminal of the multiplexed power amplifier 20 to connect with the auxiliary matching circuit 50, and simultaneously controlling the cascaded output port Xout of the multiplexed power amplifier 20 to connect with the output matching circuit 33; or, in When the RF power amplifier circuit includes at least two stages of the multiplexed power amplifier 20, the switching circuit 60 is used to activate in the second gain mode, control the interstage matching circuit 32 electrically connected to the input terminal of the first stage multiplexed power amplifier 20 to be connected to the auxiliary matching circuit 50, control the cascaded output port Xout of the previous stage multiplexed power amplifier 20 to be connected to the interstage matching circuit 32 electrically connected to the input terminal of the next stage multiplexed power amplifier 20, and simultaneously control the cascaded output port Xout of the last stage multiplexed power amplifier 20 to be connected to the output matching circuit 33.

[0056] Understandably, in the first gain mode, the bias circuit 40 can control all transistors Qx in all power amplifiers 10 to be turned on, and the switching circuit 60 stops working at this time; and in the second gain mode, the bias circuit 40 can control all transistors Qx between the cascaded output port Xout and the ground terminal GND in all multiplexed power amplifiers 20 to be turned on, while the switching circuit 60 can control the cascaded multiplexed power amplifiers 20 and output the target RF signal through the output matching circuit 33. Thus, by controlling all transistors Qx in all cascaded power amplifiers 10 to work, a high-gain first gain mode is achieved, and by controlling some transistors Qx in multiplexed power amplifiers 20 to work, a low-gain second gain mode is achieved. This realizes multi-gain mode operation of the RF power amplifier circuit, avoids the RF power amplifier circuit operating in a deep fallback state, and ensures high efficiency of the RF power amplifier circuit in different gain modes.

[0057] The following describes the technical solution provided in this application embodiment in more detail, taking an RF power amplifier circuit including a cascaded three-stage power amplifier 10 as an example. That is, the RF power amplifier circuit provided in this application embodiment includes a cascaded first-stage power amplifier 101, a second-stage power amplifier 102, and a third-stage power amplifier 103. The input terminal of the input matching circuit 31 is connected to the input RF signal RFin, and the output terminal of the input matching circuit 31 is electrically connected to the input terminal of the first-stage power amplifier 101; the output terminal of the first-stage power amplifier 101 is electrically connected to the input terminal of an inter-stage matching circuit 32, and the output terminal of the inter-stage matching circuit 32 is electrically connected to the input terminal of the second-stage power amplifier 102; the output terminal of the second-stage power amplifier 102 is electrically connected to the input terminal of an inter-stage matching circuit 32, and the output terminal of the inter-stage matching circuit 32 is electrically connected to the input terminal of the third-stage power amplifier 103; the output terminal of the third-stage power amplifier 103 is electrically connected to the output matching circuit 33, and the output terminal of the output matching circuit 33 is used to output the amplified target RF signal. Continuing as... Figure 1As shown, the RF power amplifier circuit provided in this embodiment may include only one stage multiplexed power amplifier 20. For example, the third stage power amplifier 103 may be a multiplexed power amplifier 20. The input terminal of the multiplexed power amplifier 20 is electrically connected to the input terminal of the interstage matching circuit 32, which is electrically connected to the input terminal of the auxiliary matching circuit 50 through the switching circuit 60. The cascaded output port Xout of the multiplexed power amplifier 20 is electrically connected to the input terminal of the output matching circuit 33 through the switching circuit 60. In the first gain mode, the bias circuit 40 controls all transistors Qx of the first stage power amplifier 101, the second stage power amplifier 102, and the third stage power amplifier 103 to be turned on, while the switching circuit 60 stops working and disconnects the auxiliary matching circuit from the interstage matching circuit 32. At the same time, it disconnects the cascaded output port Xout of the multiplexed power amplifier 20 from the input terminal of the output matching circuit 33, thereby realizing a higher gain operating mode of the RF power amplifier circuit. In the second gain mode, the bias circuit 40 controls the first stage power amplifier 101 and the second stage power amplifier 50 to be turned on. In device 102, all transistors Qx are turned off, and the transistor Qx between the cascaded output port Xout of the multiplexed power amplifier 20 and the power supply voltage terminal Vcc is turned off. At the same time, the transistor Qx between the cascaded output port Xout of the multiplexed power amplifier 20 and the ground terminal GND is turned on. Meanwhile, the switching circuit 60 is started, connecting the auxiliary matching circuit 50 and the interstage matching circuit 32, and connecting the cascaded output port Xout of the multiplexed power amplifier 20 and the input terminal of the output matching circuit 33, thereby realizing the lower gain operating mode of the RF power amplifier circuit.

[0058] Figure 1 This diagram illustrates the circuit connection and corresponding operation of an RF power amplifier circuit, including a single-stage multiplexed power amplifier 20. The following section combines... Figure 2 The circuit connection and corresponding operation process of the RF power amplifier circuit, including the two-stage multiplexed power amplifier 20, are described. Continuing... Figure 2As shown, the RF power amplifier circuit provided in this embodiment includes a first-stage multiplexed power amplifier 201 and a second-stage multiplexed power amplifier 202, wherein the first-stage multiplexed power amplifier 201 is the second-stage power amplifier 102, and the second-stage multiplexed power amplifier 202 is the third-stage power amplifier 103. The input terminal of the first-stage multiplexed power amplifier 201 is electrically connected to the input terminal of the interstage matching circuit 32, which is electrically connected to the input terminal of the auxiliary matching circuit 50 through a switching circuit 60. The cascaded output port Xout of the first-stage multiplexed power amplifier 201 is electrically connected to the input terminal of the interstage matching circuit 32, which is electrically connected to the input terminal of the second-stage multiplexed power amplifier 202, through the switching circuit 60. The cascaded output port Xout of the second-stage multiplexed power amplifier 202 is electrically connected to the input terminal of the output matching circuit 33 through the switching circuit 60. In the first gain mode, the bias circuit 40 controls all transistors Qx in the first-stage power amplifier 101, the second-stage power amplifier 102, and the third-stage power amplifier 103 to be turned on, while the switching circuit 60 stops working and disconnects the auxiliary matching circuit from the inter-stage matching circuit 32, disconnects the cascaded output port Xout of the first-stage multiplexed power amplifier 201 from the input of the connected inter-stage matching circuit 32, and simultaneously disconnects the cascaded output port Xout of the second-stage multiplexed power amplifier 202 from the input of the output matching circuit 33, thereby achieving a higher gain operating mode for the RF power amplifier circuit. In the second gain mode, the bias circuit 40 controls all transistors Qx in the first-stage power amplifier 101 to be turned off, and controls the first-stage multiplexed power amplifier to be turned off. In amplifier 201, transistor Qx between the cascaded output port Xout of the first-stage multiplexed power amplifier 201 and the power supply voltage terminal Vcc is turned off. At the same time, transistor Qx between the cascaded output port Xout of the first-stage multiplexed power amplifier 201 and the ground terminal GND is turned on. Meanwhile, switching circuit 60 is activated, connecting auxiliary matching circuit 50 and interstage matching circuit 32, connecting the input terminal of interstage matching circuit 32 to the cascaded output port Xout of the first-stage multiplexed power amplifier 201, and connecting the cascaded output port Xout of the second-stage multiplexed power amplifier 202 to the input terminal of output matching circuit 33, thereby realizing the lower gain operating mode of the RF power amplifier circuit.

[0059] In some embodiments, the at least two transistors Qx are defined as first transistors Qx1 to Nth transistors, and the conduction types of first transistors Qx1 to Nth transistors are the same, which can all be N-type transistors or all be P-type transistors. Furthermore, the power amplifier 10 provided in this application embodiment includes a resistor R; the first end of the resistor R is electrically connected to the power supply voltage terminal Vcc, the second end of the resistor R is electrically connected to the first end of the first transistor Qx1 as the output terminal of the power amplifier 10, the second end of the i-th transistor is electrically connected to the first end of the (i+1)-th transistor, the second end of the N-th transistor is electrically connected to the ground terminal GBD, the gates of the first transistors Qx1 to the N-th transistors are all electrically connected to the bias circuit 40, and the gate of the N-th transistor is the input terminal of the power amplifier 10, where i is a positive integer less than N. In all the power amplifiers 10 provided in this application embodiment, the number of transistors Qx included in all power amplifiers 10 can be the same. Alternatively, in all the power amplifiers 10 provided in this application embodiment, the number of transistors Qx included in at least one power amplifier 10 can be different from the number of transistors Qx included in the other power amplifiers 10. like Figure 1 and 2 As shown, the first-stage power amplifier 101 provided in this embodiment may include two transistors Qx, namely a first transistor Qx1 and a second transistor Qx2. The first terminal of the first transistor Qx1 is electrically connected to the second terminal of the resistor R, forming the output terminal of the first-stage power amplifier 101, and the gate of the second transistor Qx2 is the input terminal of the first-stage power amplifier 101. Similarly, the second-stage power amplifier 102 and the third-stage power amplifier 103 provided in this embodiment may each include three transistors Qx, namely a first transistor Qx1, a second transistor Qx2, and a third transistor Qx3. The first terminal of the first transistor Qx1 is electrically connected to the second terminal of the resistor R, forming the output terminal of the second-stage power amplifier 102 (or the third-stage power amplifier 103), and the gate of the third transistor Qx3 is the input terminal of the second-stage power amplifier 102 (or the third-stage power amplifier 103). It should be noted that the power amplifier 10 provided in this embodiment may also include a greater number of transistors Qx, and this application does not impose specific limitations on this.

[0060] In some embodiments, when the RF power amplifier circuit provided in this application includes at least two stages of multiplexed power amplifiers 20, the positions of the cascaded output ports Xout of all multiplexed power amplifiers 20 can be the same, that is, the number of transistors Qx between the cascaded output port Xout and the ground terminal GND can be the same. Alternatively, when the RF power amplifier circuit provided in this application includes at least two stages of multiplexed power amplifiers 20, the position of the cascaded output port Xout of at least one multiplexed power amplifier 20 can be different from the positions of the cascaded output ports Xout of the other multiplexed power amplifiers 20, that is, the number of transistors Qx between the cascaded output port Xout of at least one multiplexed power amplifier 20 and the ground terminal GND can be different from the number of transistors Qx between the cascaded output port Xout of the other multiplexed power amplifiers 20 and the ground terminal GND. This application does not impose specific limitations on this, and specific design is required based on actual applications. Specifically, as shown below... Figure 2 As shown, the transistor Qx between the cascaded output port Xout of the first-stage multiplexed power amplifier 201 and the ground terminal GND can be two, that is, the connection between the second terminal of the first transistor Qx1 and the first terminal of the second transistor Qx2 is the cascaded output port Xout of the first-stage multiplexed power amplifier 201; while the transistor Qx between the cascaded output port Xout of the second-stage multiplexed power amplifier 202 and the ground terminal GND can be one, that is, the connection between the second terminal of the second transistor Qx2 and the first terminal of the third transistor Qx3 is the cascaded output port Xout of the second-stage multiplexed power amplifier 202. In the second gain mode, the first transistor Qx1 in the first-stage multiplexed power amplifier 201 is controlled to be turned off, while the second transistor Qx2 and the third transistor Qx3 are controlled to be turned on; and in the second-stage multiplexed power amplifier 202, the first transistor Qx1 and the second transistor Qx2 are controlled to be turned off, while the third transistor Qx3 is controlled to be turned on, thereby realizing the operation of the RF power amplifier circuit in a lower gain mode.

[0061] In some embodiments, the RF power amplifier circuit provided in this application includes at least two stages of the multiplexed power amplifier 20; wherein at least one stage of the power amplifier 10 is included between any two adjacent multiplexed power amplifiers 20; or, all the multiplexed power amplifiers 20 are power amplifiers 10 cascaded consecutively. That is, when the RF power amplifier circuit provided in this application includes a larger number of multiplexed power amplifiers 20, when selecting multiplexed power amplifiers 20, a multiplexed power amplifier 20 can be determined after a preset number of power amplifiers 10 intervals; or, a portion of the power amplifiers 10 cascaded consecutively can be selected as multiplexed power amplifiers 20, thereby not limiting the selection method of multiplexed power amplifiers 20, improving the application range of the RF power amplifier circuit, and enabling operation in more gain modes. Optionally, when the RF power amplifier circuit provided in the embodiments of this application includes a single-stage multiplexed power amplifier 20, the multiplexed power amplifier 20 can be the last stage power amplifier 10; or, when the RF power amplifier circuit provided in the embodiments of this application includes at least two stages of multiplexed power amplifiers 20, all multiplexed power amplifiers 20 can be the last few stages of power amplifiers 10 cascaded together, and this application does not impose specific limitations on this.

[0062] refer to Figure 3 The diagram shows a circuit diagram of another RF power amplifier circuit provided in this application embodiment. The bias circuit 40 provided in this application embodiment includes: a bias control unit 41, which outputs a first bias control signal in the first gain mode; and a bias control unit 41, which outputs a second bias control signal in the second gain mode. A bias power supply unit 42 is also included, which controls all transistors in all power amplifiers 10 to be turned on based on the first bias control signal; and the bias power supply unit 42 controls all transistors Qx between the cascaded output port Xout and the ground terminal GNG in all multiplexed power amplifiers 20 to be turned on based on the second bias control signal, and controls all transistors Qx between the cascaded output port Xout and the power supply voltage terminal Vcc in the multiplexed power amplifiers 20 to be turned off based on the second bias control signal, while simultaneously controlling transistors Qx in power amplifiers 10 that are not multiplexed power amplifiers 20 to be turned off based on the second bias control signal. If the transistor Qx provided in the embodiments of this application is an N-type transistor, the bias power supply unit 42 provides a high-level signal to control the transistor Qx to turn on and a low-level signal to control the transistor Qx to turn off; or, if the transistor Qx provided in the embodiments of this application is a P-type transistor, the bias power supply unit 42 provides a low-level signal to control the transistor Qx to turn on and a high-level signal to control the transistor Qx to turn off.

[0063] In some embodiments, the bias control unit 41 and the bias power supply unit 42 provided in this application can be integrated into a single circuit, thereby achieving control over all power amplifiers 10. Alternatively, the bias control unit 41 provided in this application can be integrated into a single circuit, while the bias power supply unit 42 can be decomposed into multiple independent circuits to control their respective connected power amplifiers 10. See details. Figure 4 The diagram shown is a circuit diagram of another RF power amplifier circuit provided in this application embodiment. The bias power supply unit 42 provided in this application embodiment includes: at least two bias power supply modules 421, each bias power supply module 421 being electrically connected to the gates of all transistors Qx in the power amplifier 10; the bias power supply module 421 is used to control all transistors Qx in the power amplifier 10 to be turned on based on the first bias control signal; and when the power amplifier 10 electrically connected to the bias power supply module 421 is the multiplexed power amplifier 20, the bias power supply... Module 421 is used to control all transistors Qx between the cascaded output port Xout and the ground terminal GND in the multiplexed power amplifier 20 to be turned on based on the second bias control signal, and to control all transistors Qx between the cascaded output port Xout and the power supply voltage terminal Vcc in the multiplexed power amplifier 20 to be turned off based on the second bias control signal; and when the power amplifier 10 electrically connected to the bias power supply module 421 is not the multiplexed power amplifier 20, the bias power supply module 421 controls the transistors Qx in the power amplifier 10 to be turned off based on the second bias control signal.

[0064] Furthermore, the bias control unit 41 provided in this embodiment can also be decomposed into multiple independent lines to cooperate with the bias power supply module 421 to control the power amplifiers 10 connected to each other. See details. Figure 5 The diagram shown is a circuit diagram of another RF power amplifier circuit provided in this application embodiment. The bias control unit 41 provided in this application embodiment includes: at least two bias control modules 411, one of the bias control modules 411 being electrically connected to a bias power supply module 421, the bias control module 411 being used to output the first bias control signal in the first gain mode; and the bias control module 411 being used to output the second bias control signal in the second gain mode.

[0065] refer to Figure 6 and Figure 7The diagram shown is a circuit diagram of another RF power amplifier circuit provided in an embodiment of this application. The switching circuit 60 provided in this embodiment includes: a switch control unit 61, which outputs a first switch control signal in a first gain mode; and a second switch control signal in a second gain mode. At least two switch units 62 are also included, which are used to control shutdown based on the first switch control signal, and to control turn-on based on the second switch control signal. Figure 6 As shown, when the RF power amplifier circuit includes the multiplexed power amplifier 20, a switching unit 62 is electrically connected between the output terminal of the auxiliary matching circuit 50 and the input terminal of the interstage matching circuit 32, which is electrically connected to the input terminal of the multiplexed power amplifier 20, and a switching unit 62 is electrically connected between the cascaded output port Xout of the multiplexed power amplifier 20 and the input terminal of the output matching circuit 33. Or as... Figure 7 As shown, when the RF power amplifier circuit includes at least two stages of the multiplexed power amplifier 20, a switching unit 62 is electrically connected between the output terminal of the auxiliary matching circuit 50 and the input terminal of the interstage matching circuit 32, which is electrically connected to the input terminal of the first-stage multiplexed power amplifier 20; a switching unit 62 is electrically connected between the cascaded output port Xout of the previous stage multiplexed power amplifier 20 and the input terminal of the interstage matching circuit 32, which is electrically connected to the input terminal of the next stage multiplexed power amplifier 20; and a switching unit 62 is electrically connected between the cascaded output port Xout of the last stage multiplexed power amplifier 20 and the input terminal of the output matching circuit 33. Continuing as... Figure 7 As shown, when the RF power amplifier circuit includes a first-stage multiplexed power amplifier 201 and a second-stage multiplexed power amplifier 202, the output terminal of the auxiliary matching circuit 50 is electrically connected to the input terminal of a switching unit 62. The output terminal of the switching unit 62 is electrically connected to the input terminal of the inter-stage matching circuit 32, which is electrically connected to the input terminal of the first-stage multiplexed power amplifier 201. A switching unit 62 is electrically connected between the cascaded output port Xout of the first-stage multiplexed power amplifier 201 and the input terminal of the inter-stage matching circuit 32, which is electrically connected to the input terminal of the second-stage multiplexed power amplifier 202. A switching unit 62 is also electrically connected between the cascaded output port Xout of the second-stage multiplexed power amplifier 202 and the input terminal of the output matching circuit 33. Thus, in conjunction with the first gain mode and the second gain mode, the switch control unit 61 controls the switching unit 62 to turn off or on, realizing the multi-gain mode operation of the RF power amplifier circuit. Optionally, the switching unit 62 provided in this embodiment can be implemented using a switching transistor or similar structure; this application does not impose specific limitations on this.

[0066] In some embodiments, the multi-gain mode switching of the RF power amplifier circuit provided in this application can be implemented through user control. Alternatively, the multi-gain mode switching of the RF power amplifier circuit can also be implemented by corresponding control based on the detected power of the target RF signal. See details. Figure 8 The diagram shows a circuit diagram of another RF power amplifier circuit provided in this application embodiment. The RF power amplifier circuit provided in this application embodiment further includes a power detection and control circuit 70. The power detection and control circuit 70 is used to detect whether the power of the target RF signal is less than a set power. If so, it controls the bias circuit 40 and the switching circuit 60 to operate in the second gain mode; if not, it controls the bias circuit 40 and the switching circuit 60 to operate in the first gain mode. In other words, when the power of the target RF signal output by the RF power amplifier circuit is less than a set power (e.g., 10dBm), the RF power amplifier circuit is controlled to operate in the second gain mode. This achieves multi-gain mode operation of the RF power amplifier circuit while avoiding the RF power amplifier circuit operating in a deep fallback state, ensuring high efficiency of the RF power amplifier circuit in different gain modes.

[0067] refer to Figure 9The diagram shown is a circuit diagram of another RF power amplifier circuit provided in this application embodiment. The power detection and control circuit 70 provided in this application embodiment includes: a power detection unit 71, used to acquire the target RF signal output by the output matching circuit 33; a detection unit 72, used to convert the target RF signal acquired by the power detection unit 71 into a low-frequency signal; a threshold comparison unit 73, used to compare whether the power of the low-frequency signal is less than a set power; if so, outputting a second enable signal; if not, outputting a first enable signal; and a bias circuit. The circuit includes an enable generation unit 74 and a switch enable generation unit 75. The bias enable generation unit 74 controls the bias circuit 40 to operate in the first gain mode according to the first enable signal, and the bias enable generation unit 74 controls the bias circuit 40 to operate in the second gain mode according to the second enable signal. The switch enable generation unit 75 controls the switch circuit 60 to operate in the first gain mode according to the first enable signal, and the switch enable generation unit 75 controls the switch circuit 60 to operate in the second gain mode according to the second enable signal. Furthermore, the power detection control circuit 70 also includes a filter unit 76 and a DC power supply bias unit 77. The filter unit 76 is electrically connected between the detection unit 72 and the threshold comparison unit 73, and is used to filter low-frequency signals before transmitting them to the threshold comparison unit 73 to improve detection accuracy. The DC power supply bias unit 77 is electrically connected to the detection unit 72 and is used to provide static operating bias power to the detection unit 72.

[0068] The above description uses a radio frequency power amplifier circuit including a three-stage power amplifier 10 as an example to illustrate the technical solution provided in the embodiments of this application. Furthermore, the radio frequency power amplifier circuit provided in the embodiments of this application may also include a greater number of power amplifiers 10, or only include a minimum of two-stage power amplifiers 10. See details... Figure 10The diagram shown is a circuit diagram of another RF power amplifier circuit provided in this application embodiment. The RF power amplifier circuit provided in this application embodiment may also include only two cascaded power amplifiers 10, that is, the RF power amplifier circuit includes a cascaded first-stage power amplifier 101 and a second-stage power amplifier 102. The input terminal of the input matching circuit 31 is connected to the input RF signal RFin, and the output terminal of the input matching circuit 31 is electrically connected to the input terminal of the first-stage power amplifier 101; the output terminal of the first-stage power amplifier 101 is electrically connected to the input terminal of an inter-stage matching circuit 32, and the output terminal of the inter-stage matching circuit 32 is electrically connected to the input terminal of the second-stage power amplifier 102; the output terminal of the second-stage power amplifier 102 is electrically connected to the output matching circuit 33, and the output terminal of the output matching circuit 33 is used to output the amplified target RF signal. Continuing as... Figure 10 As shown, the RF power amplifier circuit provided in this application embodiment includes only one stage multiplexed power amplifier 20, that is, the second stage power amplifier 102 is multiplexed power amplifier 20. The input terminal of the multiplexed power amplifier 20 is electrically connected to the input terminal of the interstage matching circuit 32, which is electrically connected to the input terminal of the auxiliary matching circuit 50 through the switching circuit 60. The cascaded output port Xout of the multiplexed power amplifier 20 is electrically connected to the input terminal of the output matching circuit 33 through the switching circuit 60. In the first gain mode, the bias circuit 40 controls all transistors Qx in the first-stage power amplifier 101 and the second-stage power amplifier 102 to be turned on, while the switching circuit 60 stops working and disconnects the auxiliary matching circuit 50 from the inter-stage matching circuit 32. At the same time, it disconnects the cascaded output port Xout of the multiplexed power amplifier 20 from the input terminal of the output matching circuit 33, thereby achieving a higher gain operating mode for the RF power amplifier circuit. In the second gain mode, the bias circuit 40 controls all transistors Qx in the first-stage power amplifier 101 to be turned off, controls the transistor Qx between the cascaded output port Xout of the multiplexed power amplifier 20 and the power supply voltage terminal Vcc to be turned off, and controls the transistor Qx between the cascaded output port Xout of the multiplexed power amplifier 20 and the ground terminal GND to be turned on. The switching circuit 60 starts working, connecting the auxiliary matching circuit 50 and the inter-stage matching circuit 32, and connecting the cascaded output port Xout of the multiplexed power amplifier 20 from the input terminal of the output matching circuit 33, thereby achieving a lower gain operating mode for the RF power amplifier circuit.

[0069] Further reference Figure 11 The diagram shown is a circuit schematic of another radio frequency power amplifier circuit provided in an embodiment of this application. Figure 10The illustrated RF power amplifier circuit includes a cascaded first-stage power amplifier 101 and a second-stage power amplifier 102, and also includes a power detection and control circuit 70. Similarly, the power detection and control circuit 70 includes: a power detection unit 71, which is used to acquire the target radio frequency signal output by the output matching circuit 33; a detection unit 72, which is used to convert the target radio frequency signal acquired by the power detection unit 71 into a low-frequency signal; a threshold comparison unit 73, which is used to compare whether the power of the low-frequency signal is less than the set power. If yes, it outputs a second enable signal; if no, it outputs a first enable signal; a bias enable generation unit 74 and a switch enable generation unit 75. The bias enable generation unit 74 is used to control the bias circuit 40 to operate in the first gain mode according to the first enable signal, and the bias enable generation unit 74 is used to control the bias circuit 40 to operate in the second gain mode according to the second enable signal. The switch enable generation unit 75 is used to control the switch circuit 60 to operate in the first gain mode according to the first enable signal, and the switch enable generation unit 75 is used to control the switch circuit 60 to operate in the second gain mode according to the second enable signal. In addition, the power detection and control circuit 70 also includes a filter unit 76 and a DC power supply bias unit 77. The filter unit 76 is electrically connected between the detector unit 72 and the threshold comparison unit 73. The filter unit 76 is used to filter the low-frequency signal and transmit it to the threshold comparison unit 73 to improve the detection accuracy. The DC power supply bias unit 77 is electrically connected to the detector unit 72. The DC power supply bias unit 77 is used to provide static working bias power to the detector unit 72.

[0070] Based on the same inventive concept, this application also provides a radio frequency front-end chip, which includes the radio frequency power amplifier circuit provided in any of the above embodiments.

[0071] Based on the same inventive concept, this application also provides a radio frequency front-end module, which includes the radio frequency front-end chip provided in any of the above embodiments.

[0072] In summary, this application provides an RF power amplifier circuit, an RF front-end chip, and an RF front-end module. In the first gain mode, the bias circuit can control all transistors in all power amplifiers to conduct, and the switching circuit stops working at this time. In the second gain mode, the bias circuit can control all transistors between the cascaded output ports and ground terminals in all multiplexed power amplifiers to conduct, while the switching circuit can control the cascaded multiplexed power amplifiers and output the target RF signal through the output matching circuit. Thus, by controlling the operation of all transistors in all cascaded power amplifiers, a high-gain first gain mode is achieved, and by controlling the operation of some transistors in the multiplexed power amplifiers, a low-gain second gain mode is achieved. This realizes multi-gain mode operation of the RF power amplifier circuit, avoids the RF power amplifier circuit operating in a deep fallback state, and ensures high efficiency of the RF power amplifier circuit in different gain modes.

[0073] In the description of the embodiments of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and other terms indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0074] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0075] In the embodiments of this application, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0076] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0077] In the embodiments of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0078] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A radio frequency power amplifier circuit, characterized in that, include: At least two cascaded power amplifiers, each power amplifier including at least two transistors connected in series between a power supply voltage terminal and a ground terminal; the input terminal of the first-stage power amplifier is connected to an input radio frequency signal via an input matching circuit, and the output terminal of the previous-stage power amplifier is connected to the input terminal of the next-stage power amplifier via an inter-stage matching circuit; the output terminal of the last-stage power amplifier outputs a target radio frequency signal via an output matching circuit; starting from the second-stage power amplifier and along the cascade sequence of the power amplifiers, all power amplifiers include at least one multiplexed power amplifier; A bias circuit is electrically connected to the gate of the transistor; the bias circuit is used to control all transistors in all power amplifiers to be turned on in a first gain mode; and the bias circuit is used to control all transistors between the cascaded output port and the ground terminal in all multiplexed power amplifiers to be turned on in a second gain mode, wherein the cascaded output port is the connection terminal of two pre-set adjacent transistors connected in series in the multiplexed power amplifier; wherein the gain in the second gain mode is less than the gain in the first gain mode; The RF power amplifier circuit includes an auxiliary matching circuit and a switching circuit. The auxiliary matching circuit is used to receive the input RF signal, and the switching circuit is used to stop operating in the first gain mode. When the RF power amplifier circuit includes one stage of the multiplexed power amplifier, the switching circuit is activated in the second gain mode, controlling the inter-stage matching circuit electrically connected to the input terminal of the multiplexed power amplifier to connect with the auxiliary matching circuit, and simultaneously controlling the cascaded output port of the multiplexed power amplifier to connect with the output matching circuit. Alternatively, when the RF power amplifier circuit includes at least two stages of the multiplexed power amplifier, the switching circuit is activated in the second gain mode, controlling the inter-stage matching circuit electrically connected to the input terminal of the first stage of the multiplexed power amplifier to connect with the auxiliary matching circuit, controlling the cascaded output port of the previous stage of the multiplexed power amplifier to connect with the inter-stage matching circuit electrically connected to the input terminal of the next stage of the multiplexed power amplifier, and simultaneously controlling the cascaded output port of the last stage of the multiplexed power amplifier to connect with the output matching circuit.

2. The radio frequency power amplifier circuit according to claim 1, characterized in that, The at least two transistors are defined as transistors 1 through N, and the power amplifier includes resistors; The first end of the resistor is electrically connected to the power supply voltage terminal, the second end of the resistor is electrically connected to the first end of the first transistor as the output terminal of the power amplifier, the second end of the i-th transistor is electrically connected to the first end of the (i+1)-th transistor, the second end of the N-th transistor is electrically connected to the ground terminal, the gates of the first transistor to the N-th transistor are all electrically connected to the bias circuit, and the gate of the N-th transistor is the input terminal of the power amplifier, where i is a positive integer less than N.

3. The radio frequency power amplifier circuit according to claim 1, characterized in that, The radio frequency power amplifier circuit includes at least two stages of the multiplexed power amplifier; Each pair of adjacent multiplexed power amplifiers includes at least one stage of the power amplifier; or, all of the multiplexed power amplifiers are power amplifiers cascaded in succession.

4. The radio frequency power amplifier circuit according to claim 1, characterized in that, The bias circuit includes: A bias control unit, wherein the bias control unit is configured to output a first bias control signal in a first gain mode; and the bias control unit is configured to output a second bias control signal in a second gain mode; A bias power supply unit is configured to control all transistors in all power amplifiers to be turned on based on a first bias control signal; and the bias power supply unit is configured to control all transistors between the cascaded output port and the ground terminal in all multiplexed power amplifiers to be turned on based on a second bias control signal.

5. The radio frequency power amplifier circuit according to claim 4, characterized in that, The bias power supply unit includes: At least two bias power supply modules are provided, one of which is electrically connected to the gates of all the transistors in the power amplifier; the bias power supply module is used to control all the transistors in the power amplifier to be turned on based on the first bias control signal; and when the power amplifier electrically connected to the bias power supply module is the multiplexed power amplifier, the bias power supply module is used to control all the transistors between the cascaded output port and the ground terminal in the multiplexed power amplifier to be turned on based on the second bias control signal.

6. The radio frequency power amplifier circuit according to claim 5, characterized in that, The bias control unit includes: At least two bias control modules are provided, one of which is electrically connected to a bias power supply module. The bias control module is configured to output a first bias control signal in the first gain mode and to output a second bias control signal in the second gain mode.

7. The radio frequency power amplifier circuit according to claim 1, characterized in that, The switching circuit includes: A switch control unit, wherein the switch control unit is configured to output a first switch control signal in a first gain mode; and the switch control unit is configured to output a second switch control signal in a second gain mode; At least two switching units are provided, wherein the switching units are configured to control shutdown based on the first switching control signal and to control turn-on based on the second switching control signal; wherein, when the RF power amplifier circuit includes a single-stage multiplexed power amplifier, one switching unit is electrically connected between the output terminal of the auxiliary matching circuit and the input terminal of the inter-stage matching circuit electrically connected to the input terminal of the multiplexed power amplifier, and another switching unit is electrically connected between the cascaded output port of the multiplexed power amplifier and the input terminal of the output matching circuit; or, when the RF power amplifier circuit includes at least two stages of the multiplexed power amplifier, one switching unit is electrically connected between the output terminal of the auxiliary matching circuit and the input terminal of the inter-stage matching circuit electrically connected to the input terminal of the first-stage multiplexed power amplifier, one switching unit is electrically connected between the cascaded output port of the previous-stage multiplexed power amplifier and the input terminal of the inter-stage matching circuit electrically connected to the input terminal of the next-stage multiplexed power amplifier, and another switching unit is electrically connected between the cascaded output port of the last-stage multiplexed power amplifier and the input terminal of the output matching circuit.

8. The radio frequency power amplifier circuit according to any one of claims 1-7, characterized in that, The radio frequency power amplifier circuit also includes: A power detection and control circuit is used to detect whether the power of the target radio frequency signal is less than a set power. If so, the bias circuit and the switching circuit are controlled to operate in the second gain mode; if not, the bias circuit and the switching circuit are controlled to operate in the first gain mode.

9. The radio frequency power amplifier circuit according to claim 8, characterized in that, The power detection and control circuit includes: A power detection unit is used to acquire the target radio frequency signal output by the output matching circuit; A detection unit, which is used to convert the target radio frequency signal acquired by the power detection unit into a low-frequency signal; A threshold comparison unit is used to compare whether the power of the low-frequency signal is less than the set power. If yes, a second enable signal is output; if no, a first enable signal is output. The system includes a bias enable generation unit and a switch enable generation unit. The bias enable generation unit controls the bias circuit to operate in the first gain mode according to the first enable signal. The bias enable generation unit controls the bias circuit to operate in the second gain mode according to the second enable signal. The switch enable generation unit controls the switch circuit to operate in the first gain mode according to the first enable signal. The switch enable generation unit controls the switch circuit to operate in the second gain mode according to the second enable signal.

10. A radio frequency front-end chip, characterized in that, The radio frequency front-end chip includes the radio frequency power amplifier circuit according to any one of claims 1-9.

11. A radio frequency front-end module, characterized in that, The radio frequency front-end module includes the radio frequency front-end chip as described in claim 10.

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