Delay-locked loop calibration circuit, control method thereof and electronic equipment

Abstract

The embodiment of the invention provides a delay phase-locked loop calibration circuit, a control method thereof and electronic equipment, and is applied to the technical field of integrated circuits, and the delay phase-locked loop calibration circuit comprises a phase discriminator, a first duty ratio calibration circuit, a charge pump, a low-pass filter, a delay unit module and a second duty ratio calibration circuit. According to the invention, the first duty ratio calibration circuit is used to automatically calibrate the phase error of the charge and discharge current of the charge pump caused by the deviation of the PVT, and the second duty ratio calibration circuit is used to automatically calibrate the phase error of the delay unit caused by the deviation of the PVT. Through the first duty ratio calibration circuit and the second duty ratio calibration circuit, the inherent phase error of the delay-locked loop can be reduced, and high-precision and high-quality clock output is realized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a delay phase-locked loop calibration circuit and its control method, as well as electronic equipment. Background Technology

[0002] In related technologies, the Delay-Locked Loop (DLL) is a widely used clock synchronization and regulation circuit in high-speed digital systems, playing a crucial role in many fields such as DDR memory interfaces, clock network distribution, and digital signal processing. Its core mechanism lies in dynamically adjusting the transmission delay of the clock signal using a voltage- or current-controlled delay line, ultimately achieving precise phase alignment between the output clock and the input reference clock. This characteristic enables the DLL to effectively eliminate clock skew, providing the system with a stable and low-jitter internal clock, ensuring the system's efficient and stable operation.

[0003] Ideally, a traditional phase-locked loop (DLL) circuit can achieve perfect synchronization between the input and output clocks through its internal negative feedback control loop. However, in the actual manufacturing and application of integrated circuits, the phase alignment accuracy of the DLL is severely affected by numerous non-ideal factors and variations in process, voltage, and temperature (PVT). For example, mismatches in charge pump charging and discharging currents and distortions in the duty cycle of the delay unit's output clock can lead to inherent phase errors between the DLL's output clock and the input reference clock, thus significantly impacting the application performance of the circuit system. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a delay phase-locked loop (PLL) calibration circuit and its control method, as well as an electronic device, designed to reduce the magnitude of the inherent phase error of the PLL.

[0005] In a first aspect, embodiments of this application provide a delay-locked loop calibration circuit, including: A phase detector is used to output a first signal and a second signal based on the input reference clock signal and feedback clock signal; A first duty cycle calibration circuit, connected to the phase detector, is used to output a third signal based on the duty cycle of the first signal. A charge pump is connected to the phase detector and the first duty cycle calibration circuit, respectively. The charge pump is used to charge and discharge according to the first signal and the second signal, and to obtain a fourth signal according to the third signal. A low-pass filter, connected to the charge pump, is used to filter the fourth signal to obtain the fifth signal; The delay unit module is connected to the low-pass filter; The second duty cycle calibration circuit is connected at one end to the delay unit module and at the other end to both the delay unit module and the phase detector, and is used to output a sixth signal according to the duty cycle of the feedback clock signal. The delay unit module is used to adjust the feedback clock signal according to the fifth signal and the sixth signal.

[0006] According to some embodiments of this application, the first duty cycle calibration circuit includes: The first integrator includes a first positive input terminal, a first negative input terminal, and a second output terminal; the first positive input terminal is connected to the power supply voltage; the first negative input terminal is connected to the phase detector and is used to input the first signal; the second output terminal is connected to the charge pump and is used to output a third signal.

[0007] According to some embodiments of this application, the first duty cycle calibration circuit further includes: A first resistor and a first capacitor are provided, with one end of the first resistor connected to the phase detector and the other end connected to the first negative input terminal; one end of the first capacitor is connected to the first negative input terminal and the other end is connected to the second output terminal.

[0008] According to some embodiments of this application, the second duty cycle calibration circuit includes: The second integrator includes a second positive input terminal, a second negative input terminal, and a third output terminal; the second positive input terminal is connected to the power supply voltage; the second negative input terminal is connected to the delay unit module and is used to input the feedback clock signal; the third output terminal is connected to the delay unit module and is used to output a sixth signal.

[0009] According to some embodiments of this application, the second duty cycle calibration circuit further includes: The second resistor and the second capacitor are connected, with one end of the second resistor connected to the delay unit module and the other end connected to the second negative input terminal; one end of the second capacitor is connected to the second negative input terminal and the other end is connected to the third output terminal.

[0010] According to some embodiments of this application, the charge pump includes: The system comprises a first input terminal, a second input terminal, a third input terminal, and a first output terminal. The first input terminal is used to input the first signal, the second input terminal is used to input the second signal, the third input terminal is used to input the third signal, and the first output terminal is used to output the fourth signal.

[0011] Secondly, embodiments of this application provide a control method for a delay-locked loop calibration circuit, applied to the delay-locked loop calibration circuit as described in the first aspect, the method comprising: The phase detector outputs a first signal and a second signal based on the input reference clock signal and the feedback clock signal. The third signal is output according to the duty cycle of the first signal through the first duty cycle calibration circuit; The charge pump performs charging and discharging based on the first and second signals, and obtains a fourth signal based on the third signal; The fourth signal is filtered by a low-pass filter to obtain the fifth signal; The sixth signal is output based on the duty cycle of the feedback clock signal through the second duty cycle calibration circuit. The feedback clock signal is adjusted according to the fifth signal and the sixth signal by the delay unit module.

[0012] According to some embodiments of this application, the step of outputting a third signal based on the duty cycle of the first signal includes: Integrate the first signal to obtain the first control voltage; When the duty cycle of the first signal is greater than the first preset threshold, the first control voltage is reduced based on the first preset adjustment coefficient to obtain the third signal; When the duty cycle of the first signal is equal to the first preset threshold, the first control voltage is determined to be the third signal; When the duty cycle of the first signal is less than the first preset threshold, the first control voltage is increased based on the second preset adjustment coefficient to obtain the third signal.

[0013] According to some embodiments of this application, the step of outputting a sixth signal based on the duty cycle of the feedback clock signal includes: Integrating the feedback clock signal yields the second control voltage; When the duty cycle of the feedback clock signal is greater than the second preset threshold, the second control voltage is reduced based on the third preset adjustment coefficient to obtain the sixth signal; When the duty cycle of the feedback clock signal is equal to the second preset threshold, the second control voltage is determined to be the sixth signal; When the duty cycle of the feedback clock signal is less than the second preset threshold, the second control voltage is increased based on the fourth preset adjustment coefficient to obtain the sixth signal.

[0014] Thirdly, embodiments of this application provide an electronic device including a delay phase-locked loop calibration circuit as described in the first aspect.

[0015] According to the technical solution of the embodiments of this application, at least the following beneficial effects are achieved: The embodiments of this application propose a delay phase-locked loop (PLL) calibration circuit and its control method, and an electronic device, which are applied in the field of integrated circuit technology. The delay PLL calibration circuit includes a phase detector, a first duty cycle calibration circuit, a charge pump, a low-pass filter, a delay unit module, and a second duty cycle calibration circuit. The phase detector is used to output a first signal and a second signal based on the input reference clock signal and the feedback clock signal. The first duty cycle calibration circuit is connected to the phase detector and is used to output a third signal based on the duty cycle of the first signal. The charge pump is connected to both the phase detector and the first duty cycle calibration circuit, and is used to charge and discharge based on the first and second signals, and to obtain a fourth signal based on the third signal. The low-pass filter is connected to the charge pump and is used to filter the fourth signal to obtain a fifth signal. The delay unit module is connected to the low-pass filter. The second duty cycle calibration circuit is connected at one end to the delay unit module and at the other end to both the delay unit module and the phase detector, and is used to output a sixth signal based on the duty cycle of the feedback clock signal. The delay unit module is used to adjust the feedback clock signal based on the fifth and sixth signals. Since this application can automatically calibrate the phase error caused by the deviation of the charge pump's charging and discharging current due to the PVT through the first duty cycle calibration circuit, and can automatically calibrate the phase error caused by the deviation of the delay unit due to the PVT through the second duty cycle calibration circuit, the magnitude of the inherent phase error of the delay phase-locked loop can be reduced through the first duty cycle calibration circuit and the second duty cycle calibration circuit, so as to achieve high-precision and high-quality clock output.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0017] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0018] Figure 1 This is a schematic diagram of the structure of a delay phase-locked loop calibration circuit provided in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of a phase detector provided in one embodiment of this application; Figure 3 This is a schematic diagram of the structure of a first duty cycle calibration circuit provided in one embodiment of this application; Figure 4 This is a schematic diagram of the structure of a charge pump provided in one embodiment of this application; Figure 5This is a schematic diagram of the structure of a delay unit module provided in one embodiment of this application; Figure 6 This is a schematic diagram of the structure of a second duty cycle calibration circuit provided in one embodiment of this application; Figure 7 This is a flowchart of a control method for a delay phase-locked loop calibration circuit provided in one embodiment of this application. Detailed Implementation

[0019] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0020] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0022] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0023] In some situations, the Delay-Locked Loop (DLL) is a widely used clock synchronization and regulation circuit in high-speed digital systems, playing a crucial role in many fields such as DDR memory interfaces, clock network distribution, and digital signal processing. Its core mechanism lies in dynamically adjusting the transmission delay of the clock signal using a voltage- or current-controlled delay line, ultimately achieving precise phase alignment between the output clock and the input reference clock. This characteristic enables the DLL to effectively eliminate clock skew, providing the system with a stable and low-jitter internal clock, ensuring the system's efficient and stable operation.

[0024] Ideally, a traditional phase-locked loop (DLL) circuit can achieve perfect synchronization between the input and output clocks through its internal negative feedback control loop. However, in the actual manufacturing and application of integrated circuits, the phase alignment accuracy of the DLL is severely affected by numerous non-ideal factors and variations in process, voltage, and temperature (PVT). For example, mismatches in charge pump charging and discharging currents and distortions in the duty cycle of the delay unit's output clock can lead to inherent phase errors between the DLL's output clock and the input reference clock, thus significantly impacting the application performance of the circuit system.

[0025] Based on the above, this application proposes a delay phase-locked loop calibration circuit and its control method and electronic device, aiming to reduce the magnitude of the inherent phase error of the delay phase-locked loop.

[0026] The various embodiments of the delay phase-locked loop calibration circuit of this application will be further described below with reference to the accompanying drawings.

[0027] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a delay phase-locked loop calibration circuit provided in one embodiment of this application.

[0028] In one embodiment, the delay phase-locked loop calibration circuit includes a phase detector PD, a first duty cycle calibration circuit DCC1, a charge pump CP, a low-pass filter LPF, a delay unit module, and a second duty cycle calibration circuit DCC2.

[0029] It is understood that the delay unit module includes multiple delay units. For example, the delay unit module includes four delay units, namely the first delay unit DLC1, the second delay unit DLC2, the third delay unit DLC3, and the fourth delay unit DLC4.

[0030] Understandably, the system comprises: a phase detector, used to output a first signal and a second signal based on the input reference clock signal and the feedback clock signal; a first duty cycle calibration circuit, connected to the phase detector, used to output a third signal based on the duty cycle of the first signal; a charge pump, connected to both the phase detector and the first duty cycle calibration circuit, used to charge and discharge based on the first and second signals, and to obtain a fourth signal based on the third signal; a low-pass filter, connected to the charge pump, used to filter the fourth signal to obtain a fifth signal; a delay unit module, connected to the low-pass filter; and a second duty cycle calibration circuit, one end connected to the delay unit module and the other end connected to both the delay unit module and the phase detector, used to output a sixth signal based on the duty cycle of the feedback clock signal; wherein, the delay unit module is used to adjust the feedback clock signal based on the fifth and sixth signals. Since this application can automatically calibrate the phase error caused by the deviation of the charge pump's charging and discharging current due to the PVT through the first duty cycle calibration circuit, and can automatically calibrate the phase error caused by the deviation of the delay unit due to the PVT through the second duty cycle calibration circuit, the magnitude of the inherent phase error of the delay phase-locked loop can be reduced through the first duty cycle calibration circuit and the second duty cycle calibration circuit, so as to achieve high-precision and high-quality clock output.

[0031] It is understood that the charge pump includes: a first input terminal, a second input terminal, a third input terminal, and a first output terminal. The first input terminal is used to input a first signal, the second input terminal is used to input a second signal, the third input terminal is used to input a third signal, and the first output terminal is used to output a fourth signal.

[0032] like Figure 2 As shown, Figure 2 This is a schematic diagram of the phase detector provided in one embodiment of this application.

[0033] Understandably, the phase detector uses an RS flip-flop phase detector structure. When the phase difference between the reference clock signal and the feedback clock signal is less than 180 degrees, the high-level width of the first signal is less than the high-level width of the second signal; when the phase difference between the reference clock signal and the feedback clock signal is greater than 180 degrees, the high-level width of the first signal is greater than the high-level width of the second signal; when the phase difference between the reference clock signal and the feedback clock signal is equal to 180 degrees, the high-level width of the first signal is equal to the high-level width of the second signal, and both are half a cycle.

[0034] For example, the first signal is the up signal, the second signal is the down signal, the reference clock signal is the ck_in signal, and the feedback clock signal is the ck_fb signal. When the phase difference between the ck_in signal and the ck_fb signal is less than 180 degrees, the high-level width of the up signal is less than the high-level width of the down signal. When the phase difference between the ck_in signal and the ck_fb signal is greater than 180 degrees, the high-level width of the up signal is greater than the high-level width of the down signal. When the phase difference between the ck_in signal and the ck_fb signal is equal to 180 degrees, the high-level width of the up signal is equal to the high-level width of the down signal, and both are half a cycle.

[0035] like Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a first duty cycle calibration circuit provided in one embodiment of this application.

[0036] It is understood that the first duty cycle calibration circuit includes: a first integrator 100, wherein the first integrator includes a first positive input terminal, a first negative input terminal, and a second output terminal; the first positive input terminal is connected to the power supply voltage; the first negative input terminal is connected to the phase detector and is used to input a first signal; and the second output terminal is connected to the charge pump and is used to output a third signal.

[0037] Understandably, the first integrator is used to output the third signal based on the duty cycle of the first signal.

[0038] For example, the first signal is integrated by a first integrator to obtain a first control voltage, and the magnitude of the first control voltage is adjusted according to the duty cycle of the first signal to obtain a third signal. For instance, when the duty cycle of the first signal is greater than a first preset threshold, the first control voltage is reduced based on a first preset adjustment coefficient to obtain the third signal; when the duty cycle of the first signal is equal to the first preset threshold, the first control voltage is determined to be the third signal; when the duty cycle of the first signal is less than the first preset threshold, the first control voltage is increased based on a second preset adjustment coefficient to obtain the third signal.

[0039] It is understood that the first preset threshold mentioned above can be 50%, and can be set according to actual needs. This application embodiment does not specifically limit it.

[0040] It is understood that the first preset adjustment coefficient and the second preset adjustment coefficient mentioned above can be greater than the second preset adjustment coefficient, equal to the second preset adjustment coefficient, or less than the second preset adjustment coefficient. The values ​​of the first preset adjustment coefficient and the second preset adjustment coefficient can be set according to actual needs, and the embodiments of this application do not impose specific limitations on them.

[0041] For example, the first signal is integrated by a first integrator to obtain a first control voltage, and the magnitude of the first control voltage is adjusted according to the duty cycle of the first signal to obtain a third signal. For instance, when the duty cycle of the first signal is greater than 50%, the first control voltage is reduced based on a first preset adjustment coefficient to obtain the third signal; when the duty cycle of the first signal is equal to 50%, the first control voltage is determined to be the third signal; when the duty cycle of the first signal is less than 50%, the first control voltage is increased based on a second preset adjustment coefficient to obtain the third signal.

[0042] It is understood that the first duty cycle calibration circuit also includes: a first resistor R1 and a first capacitor C1, one end of the first resistor is connected to the phase detector and the other end is connected to the first negative input terminal; one end of the first capacitor is connected to the first negative input terminal and the other end is connected to the second output terminal.

[0043] It is understandable that the first resistor and the first capacitor form an RC integrating circuit, which is used to integrate the first signal output by the phase detector and convert the duty cycle information of the first signal into the corresponding DC control voltage in order to calibrate the charge pump charging and discharging current.

[0044] like Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of a charge pump provided in one embodiment of this application.

[0045] It is understandable that, such as Figure 4 The control terminals of PMOS transistor M3 and NMOS transistor M2 are connected to the phase detector, respectively. The control terminals of PMOS transistor M7 and NMOS transistor M6 are connected to the first duty cycle calibration circuit. The output terminal of PMOS transistor M3 and the input terminal of NMOS transistor M2 are connected to the low-pass filter. The output terminal of PMOS transistor M7 and the input terminal of NMOS transistor M6 are connected to the low-pass filter.

[0046] like Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of a delay unit module provided in one embodiment of this application.

[0047] It is understandable that, such as Figure 5 The control terminals of PMOS transistors M2, M6, M12, M16, and M22 are connected to the low-pass filter, and the control terminals of NMOS transistors M7, M8, M17, and M18 are connected to one end of the second duty cycle calibration circuit. Figure 5 ck0 in the circuit is connected to the other end of the second duty cycle calibration circuit.

[0048] like Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of a second duty cycle calibration circuit provided in one embodiment of this application.

[0049] It is understood that the second duty cycle calibration circuit includes: a second integrator 200, wherein the second integrator includes a second positive input terminal, a second negative input terminal, and a third output terminal; the second positive input terminal is connected to the power supply voltage; the second negative input terminal is connected to the delay unit module and is used to input the feedback clock signal; the third output terminal is connected to the delay unit module and is used to output the sixth signal.

[0050] Understandably, the second integrator is used to output the sixth signal based on the duty cycle of the feedback clock signal.

[0051] For example, the feedback clock signal is integrated by a second integrator to obtain a second control voltage, and the magnitude of the second control voltage is adjusted according to the duty cycle of the feedback clock signal to obtain a sixth signal. For instance, when the duty cycle of the feedback clock signal is greater than a second preset threshold, the second control voltage is reduced based on a third preset adjustment coefficient to obtain the sixth signal; when the duty cycle of the feedback clock signal is equal to the second preset threshold, the second control voltage is determined to be the sixth signal; when the duty cycle of the feedback clock signal is less than the second preset threshold, the second control voltage is increased based on a fourth preset adjustment coefficient to obtain the sixth signal.

[0052] It is understood that the second preset threshold mentioned above can be 50%, and can be set according to actual needs. This application embodiment does not specifically limit it.

[0053] It is understood that the third preset adjustment coefficient and the fourth preset adjustment coefficient mentioned above can be greater than the fourth preset adjustment coefficient, equal to the fourth preset adjustment coefficient, or less than the fourth preset adjustment coefficient. The values ​​of the third preset adjustment coefficient and the fourth preset adjustment coefficient can be set according to actual needs, and the embodiments of this application do not impose specific limitations on them.

[0054] For example, the feedback clock signal is integrated by a second integrator to obtain a second control voltage, and the magnitude of the second control voltage is adjusted according to the duty cycle of the feedback clock signal to obtain a sixth signal. For instance, when the duty cycle of the feedback clock signal is greater than 50%, the second control voltage is reduced based on a third preset adjustment coefficient to obtain the sixth signal; when the duty cycle of the feedback clock signal is equal to 50%, the second control voltage is determined to be the sixth signal; when the duty cycle of the feedback clock signal is less than 50%, the second control voltage is increased based on a fourth preset adjustment coefficient to obtain the sixth signal.

[0055] It is understandable that the second duty cycle calibration circuit also includes: a second resistor R2 and a second capacitor C2, one end of the second resistor is connected to the delay unit module and the other end is connected to the second negative input terminal; one end of the second capacitor is connected to the second negative input terminal and the other end is connected to the third output terminal.

[0056] Understandably, the second resistor and the second capacitor form an RC integrator circuit, which is used to integrate the feedback clock signal output by the delay unit module, converting the duty cycle information of the feedback clock signal into a corresponding DC control voltage, so as to calibrate the duty cycle of the feedback clock signal.

[0057] Understandably, this application, through a first duty cycle calibration circuit and a second duty cycle calibration circuit, is able to resist the phase error caused by duty cycle distortion of the feedback clock signal ck_fb and the mismatch of the charge pump's charging and discharging current. First, the second duty cycle calibration circuit automatically calibrates the duty cycle of the feedback clock signal ck_fb to maintain a 50% duty cycle, thus eliminating the phase error caused by the feedback clock duty cycle distortion. The feedback clock signal is integrated by a second integrator to obtain a second control voltage vcont_dcc2. When the duty cycle of the feedback clock signal is greater than 50%, the second control voltage vcont_dcc2 is gradually decreased to obtain a sixth signal. The sixth signal and the fifth signal filtered by a low-pass filter are used to adjust the feedback clock signal, so that the duty cycle of the feedback clock signal output by the delay unit module gradually decreases. When the duty cycle of the feedback clock signal is less than 50%, the second control voltage vcont_dcc2 is gradually increased to gradually increase the duty cycle of the feedback clock signal. When the duty cycle of the feedback clock signal is equal to 50%, the second control voltage vcont_dcc2 remains constant, and the duty cycle remains unchanged at 50%.

[0058] The first duty cycle calibration circuit automatically calibrates the charge pump's charging and discharging current by detecting the high-level width of the up signal, ensuring the up signal maintains a 50% duty cycle (i.e., the high-level width is half a cycle). This eliminates the phase error caused by the PVT in the charge pump's charging and discharging currents. The up signal is integrated by the first integrator to obtain the first control voltage vcont_dcc1. When the duty cycle of the up signal is greater than 50%, the first control voltage vcont_dcc1 is gradually decreased to obtain the third signal. This third signal is used to calibrate the charge pump's charging and discharging current, causing the discharge current to gradually decrease and the charging current to gradually increase. The fifth signal vcont, the fourth signal (output voltage) of the charge pump, after passing through a low-pass filter, gradually increases. The delay of the delay unit module gradually decreases, the phase of the feedback clock signal gradually shifts forward, and the duty cycle of the up signal gradually decreases. When the duty cycle is less than 50%, the first control voltage vcont_dcc1 gradually decreases, causing the discharge current of the charge pump to gradually increase and the charging current to gradually decrease. The fifth signal vcont after the output voltage of the charge pump passes through the low-pass filter gradually decreases, the delay of the delay unit module gradually increases, the phase of the feedback clock signal gradually shifts backward, and the duty cycle of the up signal gradually increases. When the duty cycle of the up signal is equal to 50%, the control voltage vcont_dcc remains constant, the charging current and discharge current of the charge pump are equal, the fifth signal vcont remains constant, and the duty cycle of the up signal remains unchanged at 50%.

[0059] By working together with the first duty cycle calibration circuit and the second duty cycle calibration circuit, the phase error caused by non-ideal factors such as the mismatch of charge pump charging and discharging current and the distortion of the duty cycle output of the delay unit module can be effectively eliminated, thereby reducing the phase error and achieving high-precision and high-quality clock output.

[0060] Based on the hardware structure of the delay phase-locked loop calibration circuit in the above embodiments, the following presents various embodiments of the control method of the delay phase-locked loop calibration circuit of this application.

[0061] like Figure 7 As shown, Figure 7 This is a flowchart of a control method for a delay phase-locked loop calibration circuit provided in one embodiment of this application; the control method for the delay phase-locked loop calibration circuit may include, but is not limited to, steps S110, S120, S130, S140, S150 and S160.

[0062] Step S110: The phase detector outputs a first signal and a second signal based on the input reference clock signal and the feedback clock signal. Step S120: Output a third signal according to the duty cycle of the first signal through the first duty cycle calibration circuit; Step S130: Charge and discharge the device according to the first and second signals using a charge pump, and obtain the fourth signal according to the third signal; Step S140: Filter the fourth signal using a low-pass filter to obtain the fifth signal; Step S150: The sixth signal is output according to the duty cycle of the feedback clock signal through the second duty cycle calibration circuit. Step S160: Adjust the feedback clock signal according to the fifth and sixth signals through the delay unit module.

[0063] Understandably, the first signal is integrated by the first integrator to obtain the first control voltage. The magnitude of the first control voltage is then adjusted according to the duty cycle of the first signal to obtain the third signal. When the duty cycle of the first signal is greater than a first preset threshold, the first control voltage is reduced based on a first preset adjustment coefficient to obtain the third signal; when the duty cycle of the first signal is equal to the first preset threshold, the first control voltage is determined to be the third signal; when the duty cycle of the first signal is less than the first preset threshold, the first control voltage is increased based on a second preset adjustment coefficient to obtain the third signal.

[0064] It is understood that the first preset threshold mentioned above can be 50%, and can be set according to actual needs. This application embodiment does not specifically limit it.

[0065] It is understood that the first preset adjustment coefficient and the second preset adjustment coefficient mentioned above can be greater than the second preset adjustment coefficient, equal to the second preset adjustment coefficient, or less than the second preset adjustment coefficient. The values ​​of the first preset adjustment coefficient and the second preset adjustment coefficient can be set according to actual needs, and the embodiments of this application do not impose specific limitations on them.

[0066] For example, the first signal is integrated by a first integrator to obtain a first control voltage, and the magnitude of the first control voltage is adjusted according to the duty cycle of the first signal to obtain a third signal. For instance, when the duty cycle of the first signal is greater than 50%, the first control voltage is reduced based on a first preset adjustment coefficient to obtain the third signal; when the duty cycle of the first signal is equal to 50%, the first control voltage is determined to be the third signal; when the duty cycle of the first signal is less than 50%, the first control voltage is increased based on a second preset adjustment coefficient to obtain the third signal.

[0067] Understandably, the feedback clock signal is integrated by the second integrator to obtain the second control voltage. The magnitude of the second control voltage is then adjusted according to the duty cycle of the feedback clock signal to obtain the sixth signal. When the duty cycle of the feedback clock signal is greater than the second preset threshold, the second control voltage is decreased based on the third preset adjustment coefficient to obtain the sixth signal; when the duty cycle of the feedback clock signal is equal to the second preset threshold, the second control voltage is determined to be the sixth signal; when the duty cycle of the feedback clock signal is less than the second preset threshold, the second control voltage is increased based on the fourth preset adjustment coefficient to obtain the sixth signal.

[0068] It is understood that the second preset threshold mentioned above can be 50%, and can be set according to actual needs. This application embodiment does not specifically limit it.

[0069] It is understood that the third preset adjustment coefficient and the fourth preset adjustment coefficient mentioned above can be greater than the fourth preset adjustment coefficient, equal to the fourth preset adjustment coefficient, or less than the fourth preset adjustment coefficient. The values ​​of the third preset adjustment coefficient and the fourth preset adjustment coefficient can be set according to actual needs, and the embodiments of this application do not impose specific limitations on them.

[0070] For example, the feedback clock signal is integrated by a second integrator to obtain a second control voltage, and the magnitude of the second control voltage is adjusted according to the duty cycle of the feedback clock signal to obtain a sixth signal. For instance, when the duty cycle of the feedback clock signal is greater than 50%, the second control voltage is reduced based on a third preset adjustment coefficient to obtain the sixth signal; when the duty cycle of the feedback clock signal is equal to 50%, the second control voltage is determined to be the sixth signal; when the duty cycle of the feedback clock signal is less than 50%, the second control voltage is increased based on a fourth preset adjustment coefficient to obtain the sixth signal.

[0071] It is understood that this application automatically calibrates the phase error of the charge pump's charging and discharging current caused by the PVT deviation through the first duty cycle calibration circuit, and automatically calibrates the phase error of the delay unit caused by the PVT deviation through the second duty cycle calibration circuit. Therefore, the magnitude of the inherent phase error of the delay phase-locked loop can be reduced through the first duty cycle calibration circuit and the second duty cycle calibration circuit, so as to achieve high-precision and high-quality clock output.

[0072] Furthermore, one embodiment of this application also provides an electronic device that includes the delay phase-locked loop calibration circuit described above.

[0073] It is worth noting that since the electronic device of this application embodiment includes the delay phase-locked loop calibration circuit of the above embodiments, the specific implementation and technical effects of the electronic device of this application embodiment can refer to the specific implementation and technical effects of the delay phase-locked loop calibration circuit of any of the above embodiments.

[0074] The above provides a detailed description of the preferred embodiments of this application. However, this application is not limited to the above-described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A delay-locked loop calibration circuit, characterized in that, include: A phase detector is used to output a first signal and a second signal based on the input reference clock signal and feedback clock signal; A first duty cycle calibration circuit, connected to the phase detector, is used to output a third signal based on the duty cycle of the first signal. A charge pump is connected to the phase detector and the first duty cycle calibration circuit, respectively. The charge pump is used to charge and discharge according to the first signal and the second signal, and to obtain a fourth signal according to the third signal. A low-pass filter, connected to the charge pump, is used to filter the fourth signal to obtain the fifth signal; The delay unit module is connected to the low-pass filter; The second duty cycle calibration circuit is connected at one end to the delay unit module and at the other end to both the delay unit module and the phase detector, and is used to output a sixth signal according to the duty cycle of the feedback clock signal. The delay unit module is used to adjust the feedback clock signal according to the fifth signal and the sixth signal.

2. The delay-locked loop calibration circuit according to claim 1, characterized in that, The first duty cycle calibration circuit includes: The first integrator includes a first positive input terminal, a first negative input terminal, and a second output terminal; the first positive input terminal is connected to the power supply voltage; the first negative input terminal is connected to the phase detector and is used to input the first signal; the second output terminal is connected to the charge pump and is used to output a third signal.

3. The delay-locked loop calibration circuit according to claim 2, characterized in that, The first duty cycle calibration circuit further includes: A first resistor and a first capacitor are provided, with one end of the first resistor connected to the phase detector and the other end connected to the first negative input terminal; one end of the first capacitor is connected to the first negative input terminal and the other end is connected to the second output terminal.

4. The delay-locked loop calibration circuit according to claim 1, characterized in that, The second duty cycle calibration circuit includes: The second integrator includes a second positive input terminal, a second negative input terminal, and a third output terminal; the second positive input terminal is connected to the power supply voltage; the second negative input terminal is connected to the delay unit module and is used to input the feedback clock signal; the third output terminal is connected to the delay unit module and is used to output a sixth signal.

5. The delay-locked loop calibration circuit according to claim 4, characterized in that, The second duty cycle calibration circuit also includes: The second resistor and the second capacitor are connected, with one end of the second resistor connected to the delay unit module and the other end connected to the second negative input terminal; one end of the second capacitor is connected to the second negative input terminal and the other end is connected to the third output terminal.

6. The delay-locked loop calibration circuit according to claim 1, characterized in that, The charge pump includes: The system comprises a first input terminal, a second input terminal, a third input terminal, and a first output terminal. The first input terminal is used to input the first signal, the second input terminal is used to input the second signal, the third input terminal is used to input the third signal, and the first output terminal is used to output the fourth signal.

7. A control method for a delay phase-locked loop calibration circuit, characterized in that, The method, applied to the delay-locked loop calibration circuit as described in claim 1, comprises: The phase detector outputs a first signal and a second signal based on the input reference clock signal and the feedback clock signal. The third signal is output according to the duty cycle of the first signal through the first duty cycle calibration circuit; The charge pump performs charging and discharging based on the first and second signals, and obtains a fourth signal based on the third signal; The fourth signal is filtered by a low-pass filter to obtain the fifth signal; The sixth signal is output based on the duty cycle of the feedback clock signal through the second duty cycle calibration circuit. The feedback clock signal is adjusted according to the fifth signal and the sixth signal by the delay unit module.

8. The method according to claim 7, characterized in that, The step of outputting a third signal based on the duty cycle of the first signal includes: Integrate the first signal to obtain the first control voltage; When the duty cycle of the first signal is greater than the first preset threshold, the first control voltage is reduced based on the first preset adjustment coefficient to obtain the third signal; When the duty cycle of the first signal is equal to the first preset threshold, the first control voltage is determined to be the third signal; When the duty cycle of the first signal is less than the first preset threshold, the first control voltage is increased based on the second preset adjustment coefficient to obtain the third signal.

9. The method according to claim 7, characterized in that, The step of outputting the sixth signal based on the duty cycle of the feedback clock signal includes: Integrating the feedback clock signal yields the second control voltage; When the duty cycle of the feedback clock signal is greater than the second preset threshold, the second control voltage is reduced based on the third preset adjustment coefficient to obtain the sixth signal; When the duty cycle of the feedback clock signal is equal to the second preset threshold, the second control voltage is determined to be the sixth signal; When the duty cycle of the feedback clock signal is less than the second preset threshold, the second control voltage is increased based on the fourth preset adjustment coefficient to obtain the sixth signal.

10. An electronic device, characterized in that, Includes the delay phase-locked loop calibration circuit as described in any one of claims 1 to 6.

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