Multi-carrier channel extraction method

Abstract

The invention discloses a multi-carrier channel extraction method, which comprises the following steps of: sampling and quantifying an analog radio frequency signal to obtain a digital intermediate frequency signal; carrying out configurable digital down-conversion processing by utilizing a numerical control oscillator; carrying out decimation filtering processing of a configurable comb cascade integrator; performing half-band filtering and passband compensation processing; performing multi-channel parameter configuration control on each channel through a control system; farrow resampling and filtering processing is carried out; performing matched filtering processing; performing digital gain adjustment processing; and carrying out baseband signal switching routing processing. According to the invention, dynamic configuration of link parameters after program solidification is realized, and multi-channel independent parameter configuration is supported.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, and more specifically, to a method for multi-carrier channel extraction. Background Technology

[0002] In software radio receiver architecture, multicarrier channel extraction is a key step in front-end digital signal processing. Its function is to convert the high-frequency digital intermediate frequency signal after analog-to-digital conversion into a low-sampling-rate baseband signal suitable for subsequent processing through operations such as digital mixing, decimation filtering, resampling, and matched filtering.

[0003] In existing technologies, multi-carrier channel extraction methods typically employ fixed processing links developed for specific signal types. These links implement digital down-conversion, integer multiple decimation filtering, and matched filtering processes on hardware platforms such as field-programmable gate arrays. Parameters such as carrier frequency, decimation factor, and symbol rate are determined together during program setup.

[0004] However, the aforementioned existing technologies have the following drawbacks: parameters such as carrier frequency, decimation factor, and symbol rate in the signal processing link are locked after the program is solidified and cannot be adjusted at runtime; in multi-carrier application scenarios, the parameters corresponding to different channels and carriers are also locked after solidification, making it difficult for a single device to flexibly adapt to multiple communication standards and signal types; traditional integer multiple decimation methods cannot meet the sampling rate conversion requirements of signals with arbitrary symbol rates; each time a new communication standard or signal parameter is adapted, it needs to be redeveloped and solidified, increasing the lifecycle cost from R&D to deployment. These drawbacks restrict the flexibility and versatility of the system. Summary of the Invention

[0005] This invention provides a multi-carrier channel extraction method, which solves the technical problems existing in the multi-carrier channel extraction process in related technologies, such as inflexible parameter configuration, mutual coupling of processing links of each channel, insufficient out-of-band interference suppression, and poor passband flatness.

[0006] This invention discloses a multi-carrier channel extraction method, comprising the following steps: The analog radio frequency signal received by the antenna is input to an analog-to-digital converter after being filtered by an anti-aliasing low-pass filter. Sampling and quantization are performed according to a preset sampling rate to obtain a digital intermediate frequency (IF) signal. This IF signal is then transmitted to a field-programmable gate array (FPGA) chip via a high-speed serial interface. After physical layer deserialization, data link layer frame synchronization, and transport layer reassembly, a complex digital signal containing in-phase and quadrature components is obtained. A local carrier signal of a specified frequency is generated using a numerically controlled oscillator (CNC). The in-phase and quadrature components of the complex digital signal are multiplied and added with the cosine and sine values ​​of the local carrier signal, respectively, to obtain a spectrum-shifted baseband signal. The output frequency of the CNC oscillator is controlled by a frequency control word, which is written to the control system via a register interface and can be dynamically updated after the program is fixed. The baseband signal after spectrum shifting is filtered and downsampled using a comb-cascaded integrator to suppress out-of-band interference and reduce the data rate, resulting in a downsampled digital signal. The downsampling factor and number of stages of the comb-cascaded integrator filter are dynamically configured through the register interface of the control system. The downsampled digital signal is then subjected to half-band filtering to suppress residual sidelobe components and image components, while compensating for the passband roll-off introduced by the comb-cascaded integrator filter, resulting in a half-band filtered digital signal. The control system centrally manages the configurable parameters in each processing step. In multi-carrier scenarios, independent parameter configuration register groups are maintained for each channel and each carrier, ensuring that the parameter configurations of different channels and carriers do not affect each other, and the signal processing links of each channel operate independently according to the parameters in their respective registers.

[0007] Furthermore, the numerically controlled oscillator generates a local carrier signal using a phase accumulator combined with a lookup table. Utilizing the quadrant symmetry of the sine and cosine functions, the waveform data is compressed to a quarter-cycle interval and stored in a read-only memory. The phase accumulator increments by one frequency control word step in each clock cycle, and the high-order bits of the accumulation result are used as the address index of the read-only memory to read the sine and cosine values. The relationship between the frequency control word and the target output frequency is: the frequency control word equals the product of the target output frequency and the full-scale count value of the phase accumulator divided by the sampling rate. The phase accumulator has a bit width of 32 bits.

[0008] Furthermore, the comb-shaped cascaded integrator filter consists of multiple stages of cascaded integrators and multiple stages of cascaded combs. The integrator part achieves discrete integration accumulation by staggered addition after timing with a pipelined timing register. The data extraction part controls the retention of one data point every downsampling factor input sample through a timing logic enable signal. The comb filter part achieves this by subtracting the current value from the value of the sample delayed by the downsampling factor. The entire operation involves only addition, subtraction, and register shifting operations. After the comb-shaped cascaded integrator filter is completed, the digital signal expanded by the integration accumulation operation is truncated according to the actual effective bit range to extract 16 bits of effective data.

[0009] Furthermore, the half-band filter is a finite impulse response filter, whose frequency response satisfies the symmetry between the passband and stopband about half the Nyquist frequency and the sum of the gains at the corresponding frequencies is always 1. This symmetry makes nearly half of the coefficients in the filter's impulse response zero. The half-band filter is superimposed with an inverse sinc compensation characteristic, which boosts the high-frequency components in the passband and cancels out the passband roll-off caused by the comb cascade integrator filter, thereby improving the passband flatness.

[0010] Furthermore, the configurable parameters managed by the control system also include: a function bypass enable parameter, used to bypass a specified processing stage so that the signal is directly transmitted to the next stage without passing through the operation of that stage; an inversion spectrum enable parameter, used to mirror and flip the signal spectrum; and a gain control parameter, used to adjust the amplitude of the output signal. All of the above parameters can be dynamically configured after the program is fixed through the register interface. The control system adopts a parameterized register address mapping method. When a new channel is added, it is only necessary to expand the corresponding register address space and instantiate the new signal processing link in the field programmable gate array logic, without modifying the processing logic and control logic of the existing channel.

[0011] Furthermore, after the half-band filtering process, the method further includes: performing Farrow filtering on the half-band filtered digital signal to obtain a resampled digital signal; the filter coefficients of the Farrow filter are represented as a polynomial function of the fractional delay parameter, and the entire structure is composed of multiple finite impulse response sub-filters with fixed coefficients and a polynomial weighted summation. After the input signal passes through each sub-filter simultaneously, the output of each sub-filter is multiplied by the power weight of the corresponding fractional delay parameter and then summed to obtain the resampled output; the fractional delay parameter is dynamically configured by the control system through a register interface, and after the program is fixed, it can achieve arbitrary sampling rate conversion.

[0012] Furthermore, the Farrow filter adopts a third-order Lagrange structure, using four consecutive input samples and four sub-filters, each of which is a finite impulse response filter with a length of 4. In the field-programmable gate array chip, the coefficients of each sub-filter are quantized in a 16-bit fixed-point format, and the fractional coefficients are converted into integer representations with 65536 as the base. The delay data is then multiplied and added sequentially with the quantized filter coefficients. The output of each sub-filter is then multiplied by the powers of the fractional delay parameters, and finally the output signal is obtained through a shift and truncation operation.

[0013] Furthermore, after the Farrow filtering process, the method further includes: performing matched filtering on the resampled digital signal, wherein the matched filter is a finite impulse response filter, the impulse response of which is the time-reversed conjugate of the target signal waveform, performing finite impulse response convolution operations on the in-phase and quadrature components respectively, and making the output signal-to-noise ratio reach the theoretical upper limit at the sign decision time to obtain the matched filtered baseband signal; the coefficients of the matched filter are predetermined according to the pulse shaping waveform of the target signal, and different pulse shaping waveforms are adapted by loading different coefficient files.

[0014] Furthermore, after the matched filtering process, the system also includes gain adjustment and baseband signal switching routing: the gain adjustment process calculates the instantaneous power estimate based on the sum of the squares of the in-phase and quadrature components, and performs a left or right shift operation on the in-phase and quadrature component data based on the comparison between the power estimate and a preset power range, continuously adjusting until the signal power falls within the preset power range. The shift amount is configured by the control system through the register interface. The baseband signal switching routing process connects the baseband signals output from each channel to the baseband signal switching pool. The baseband signal switching pool maintains a routing mapping table. The control system configures and updates the routing mapping table through the register interface, routing the baseband signal of the specified channel to the corresponding subsequent processing interface to obtain the routed multi-channel baseband signal output.

[0015] This invention discloses a multi-carrier channel extraction system, comprising: a signal acquisition module for sampling and quantizing an analog radio frequency signal after anti-aliasing low-pass filtering, and transmitting it to a field-programmable gate array chip via a high-speed serial interface to complete physical layer deserialization, data link layer frame synchronization, and transport layer reassembly to obtain a complex digital signal; a digital down-conversion module for generating a local carrier signal using a numerically controlled oscillator, performing complex multiplication on the complex digital signal to obtain a spectrum-shifted baseband signal; a comb-cascaded integrator filtering module for performing comb-cascaded integrator filtering and downsampling on the spectrum-shifted baseband signal to obtain a downsampled digital signal; and a half-band filtering module for performing half-band filtering on the downsampled digital signal and superimposing inverse sinc compensation to obtain a half-band filtered digital signal. The parameter configuration control module centrally manages and dynamically configures the configurable parameters in each processing module through the register interface, maintaining an independent parameter configuration register group for each channel and each carrier. The Farrow resampling module performs Farrow filtering on the half-band filtered digital signal to achieve arbitrary sampling rate conversion. The matched filtering module performs matched filtering on the resampled digital signal to obtain the matched-filtered baseband signal. The gain adjustment module performs power detection and shift gain adjustment on the matched-filtered baseband signal to obtain the gain-adjusted baseband signal. The baseband signal switching and routing module connects the baseband signals of each channel to the baseband signal switching pool and routes the baseband signals of the specified channel to the corresponding downstream processing interface according to the routing mapping table.

[0016] This invention solves the technical problem of the inability to dynamically adjust link parameters after program fixation in traditional methods by centrally managing key parameters such as the frequency control word of the numerically controlled oscillator, the downsampling factor and the number of stages of the comb-cascaded integrator filter, and bringing them to the control system register interface. It achieves the technical effect of being able to update link parameters such as frequency, decimation factor, symbol rate, gain, inverse spectrum, and functional bypass through register write operations even after program fixation. By introducing a Farrow filter, it solves the technical problem that traditional integer decimation methods cannot adapt to signals with arbitrary symbol rates, achieving the technical effect of arbitrarily converting sampling rates by simply changing the fractional delay parameter while keeping the sub-filter coefficients fixed. By maintaining independent parameter configuration register groups for each channel and carrier, it achieves the technical effect of non-interference between parameter configurations of different channels and independent operation of each channel in multi-carrier scenarios. Through a baseband signal exchange pool, it achieves the technical effect of flexible routing of multi-channel baseband signals. Through parameterized register address mapping, it achieves the technical effect of not needing to modify the processing logic of existing channels when adding channels. Attached Figure Description

[0017] Figure 1This is a flowchart of the multi-carrier channel extraction method provided in the embodiments of the present invention; Figure 2 This is a sub-flowchart of the digital gain adjustment process in the multi-carrier channel extraction method provided in this embodiment of the invention; Figure 3 This is a signal flow diagram of the entire multi-carrier channel extraction system; Figure 4 This is a pin diagram of the AD9680 chip; Figure 5 This is a schematic diagram of the main functional components inside the AD9680 chip; Figure 6 This is the analog input conditioning circuit diagram for the AD9680; Figure 7 This is the amplitude-frequency response diagram of the CIC filter simulated in MATLAB; Figure 8 This is a pipelined implementation diagram of a CIC filter in an FPGA; Figure 9 This is a schematic diagram of the frequency response of a half-band filter. Detailed Implementation

[0018] In the architecture of a Software-Defined Radio (SDR) receiver, multicarrier channel extraction is a crucial step in the front-end digital signal processing. Its function is to convert the high-frequency digital intermediate frequency (IF) signal, after analog-to-digital conversion, into a low-sampling-rate baseband signal suitable for subsequent processing through operations such as digital mixing, decimation filtering, resampling, and matched filtering. The processing capability of multicarrier channel extraction directly determines the system's real-time processing performance for complex signals and spectra.

[0019] Traditional multi-carrier channel extraction methods are typically developed for specific signal types. Parameters such as carrier frequency, decimation factor, and symbol rate throughout the signal processing chain are fixed after program execution and cannot be adjusted. In multi-carrier applications, the parameters corresponding to different channels and carriers are also locked after execution, making it impossible for a single device to flexibly adapt to multiple communication standards and signal types. Furthermore, traditional methods have poor portability across different signal types and products. Each time a new communication standard or signal parameter is adapted, redevelopment and execution are required, increasing the lifecycle cost from R&D to deployment. As communication systems need to receive increasingly diverse and varied signals with varying parameters, the low portability and flexibility of traditional methods have become major factors restricting the applicability and versatility of systems.

[0020] Therefore, a multi-carrier channel extraction method is needed, see Figure 1 and Figure 2While ensuring the latency of digital signal processing, it enables flexible configuration of link parameters such as frequency, symbol rate, decimation factor, resampling rate, gain, inverse spectrum, and functional bypass after the program is solidified, and supports independent parameter configuration between different channels and carriers in multi-carrier scenarios.

[0021] According to an embodiment of this implementation, the hardware environment involved in this implementation includes: an analog-to-digital converter (ADC) chip, a field-programmable gate array (FPGA) chip, and corresponding analog front-end conditioning circuitry. In this embodiment, the analog-to-digital converter chip used is the AD9680 manufactured by Analog Devices (circuit diagram shown below). Figure 6 The main components include impedance matching, common-mode rejection (RXA / B / R121 / R138), single-ended to differential conversion and impedance transformation and isolation (T103 / T102) transformers, high-pass filtering and AC coupling (C108 / C187, C118 / C188), impedance matching and common-mode bias (R128 / R129 / R110 / R111), oscillation suppression and stabilization and compensation (C108 / C109 / C196 / C116 / C115). This analog-to-digital converter chip is a dual-channel, 14-bit, 1GSPS analog-to-digital converter with an integrated JESD204B high-speed serial interface. The field-programmable gate array (FPGA) chip used is the Xilinx XCVU13P-FHGB2104-2-I model, which has abundant logic resources, memory units, and interface resources to meet the resource requirements of systems under multi-carrier conditions. The analog-to-digital converter chip connects to the field-programmable gate array (FPGA) chip via the JESD204B interface. The FPGA chip serves as the main platform for digital signal processing, and its signal processing logic is developed using the Verilog hardware description language. The development environment is the Xilinx Vivado 2022.2 suite.

[0022] The signal flow of the entire multi-carrier channel extraction system is as follows: Figure 3 As shown, the signal flow of the entire multi-carrier channel extraction system is divided into three main data flow parts: the analog domain, the analog-to-digital converter (ADC), and the field-programmable gate array (FPGA) logic. The analog domain performs analog conditioning and anti-aliasing filtering. The ADC quantizes the analog signal into a digital signal and transmits it to the FPGA chip via a high-speed interface. The FPGA logic performs all digital signal processing steps, including digital down-conversion, decimation filtering, resampling, matched filtering, gain adjustment, and multi-channel signal routing. The chip pins and main internal functional components are shown below. Figure 4 and 5 As shown.

[0023] Step 1: Analog signal acquisition and digital conversion The analog radio frequency signal received by the antenna is filtered by an anti-aliasing low-pass filter and then input to an analog-to-digital converter (ADC). The analog signal is sampled and quantized according to a preset sampling rate to obtain a digital intermediate frequency (IF) signal. The ADC then transmits the quantized digital signal to a field-programmable gate array (FPGA) chip via a JESD204B high-speed serial interface. Inside the FPGA chip, the JESD204B interface sequentially processes the data through physical layer deserialization, data link layer frame synchronization, and transport layer reassembly before outputting the data as an enable signal and data stream, thus obtaining a complex digital signal containing in-phase and quadrature components. ,in The time index of the sampled sequence. It is an in-phase component. It is an orthogonal component (Quadrature).

[0024] It should be noted that the selection of the above sampling rate follows the Nyquist sampling theorem, i.e., the sampling frequency. satisfy ,in This represents the highest frequency component in the original signal. In this embodiment, the sampling rate is set to 250MHz, and the anti-aliasing filter is a low-pass filter with a cutoff frequency of 72MHz, leaving a margin while satisfying the sampling law.

[0025] It should be noted that the key parameter configurations for the JESD204B interface mentioned above include: number of converters. Converter resolution Total number of digits The number of samples sent per frame period by each converter Number of Lanes Used Number of bytes per frame Frame count of multiple frames The above parameters satisfy the following relationship: in The number of bytes per frame. For the number of converters, The number of samples sent per frame period for each converter. Total number of digits This refers to the number of lanes used. Furthermore, the line rate of the JESD204B physical layer is determined using the following formula: in Efficiency coefficients for JESD204B physical layer 10B / 8B encoding after removing overhead. The sampling rate is given. Substituting the above parameters, the line rate is 2.5Gbps. After configuring the JESD204B physical layer at the field-programmable gate array (FPGA) chip according to the above parameters, data transmission and reassembly from the physical layer to the data link layer and then to the transport layer can be completed.

[0026] In this embodiment, to perform impedance matching and signal conditioning on the input signal of the analog-to-digital converter, an analog input conditioning circuit is configured at the analog input terminal of the analog-to-digital converter. The analog input conditioning circuit includes the following components: an impedance matching and common-mode rejection network for matching the impedance of the preceding signal source and suppressing common-mode interference; a single-ended to differential transformer for converting the single-ended analog signal into a differential signal and performing impedance transformation and DC blocking; and a high-pass filter and AC coupling network, wherein the AC coupling capacitor and resistor constitute a high-pass filter with a cutoff frequency determined by... Confirmed, among which The resistance value is... The capacitance value is below the cutoff frequency. Low-frequency signals and noise are significantly attenuated; differential impedance matching and common-mode bias networks are used to provide a suitable DC bias level for the analog-to-digital converter; oscillation suppression and stabilization compensation networks are used to suppress parasitic oscillations that may occur in the conditioning link.

[0027] Step 2: Configurable digital downconversion processing Based on complex digital signals, a local carrier signal of a specified frequency is generated using a numerically controlled oscillator (NCO). The complex digital signal and the local carrier signal are then multiplied by a complex number to obtain the baseband signal after spectrum shifting.

[0028] Specifically, performing complex mixing operations on complex digital signals. The complex mixing operation is expanded into a form where the real and imaginary parts are calculated separately to obtain the in-phase and quadrature components after the shift: in For the target shift angular frequency, The in-phase component after mixing These are the quadrature components after mixing. The output of the numerically controlled oscillator provides the required components in the above equation. and value.

[0029] The numerically controlled oscillator generates the carrier signal using a phase accumulator combined with a lookup table. Utilizing the quadrant symmetry of the sine and cosine functions, waveform data spanning 360 degrees is compressed into a 90-degree interval. 4096 waveform sampling points are pre-stored in the read-only memory (ROM) of the field-programmable gate array (FPGA). The phase accumulator increments by one frequency control word in each clock cycle, and the high-order bits of the accumulation result are used as the address index for the ROM to retrieve and output the corresponding sine and cosine values.

[0030] To allow for flexible adjustment of the mixing frequency after the program is fixed, frequency control is achieved by configuring a frequency control word. Frequency control word With output frequency The relationship between them is: in For frequency control word, The sampling rate of the digital signal. The target output frequency is determined. The frequency control word is written to the control system via the register interface and can be dynamically updated even after the program is fixed, thereby controlling the frequency shift distance of the mixed signal in the spectrum. The in-phase and quadrature components are multiplied and added in four ways with the sine and cosine values ​​output by the numerically controlled oscillator according to the above expansion formula to obtain the baseband signal after complex mixing.

[0031] It should be noted that the phase accumulator described above has a bit width of 32 bits. The step precision of the frequency control word determines the resolution of the output frequency. The frequency resolution of the 32-bit phase accumulator at a sampling rate of 250MHz is approximately... .

[0032] Step 3: Configurable comb cascade integrator decimation filtering The baseband signal after spectrum shifting is filtered and downsampled using a cascaded integrator-Comb (CIC) to suppress out-of-band interference and reduce the data rate, thereby obtaining the downsampled digital signal.

[0033] Comb cascaded integrator filters are composed of Serial integrator and Composed of cascaded combs, the entire operation involves only addition, subtraction, and register shifting operations, requiring no multiplier resources. In a field-programmable gate array (FPGA) chip, it is implemented with the following structure: the integrator section achieves discrete integration accumulation through staggered addition using pipelined timing registers; the data decimation section is located between the integrator and the combs, controlled by a timing logic decimation enable signal, performing decimation at intervals... Each input sample retains one data point for output to the next stage; the comb filter section, after being processed by pipeline step-by-step, has its current value and delay... The subtraction operation is implemented for each sample value. All the above steps are processed in a pipelined manner to ensure regular timing and no additional delay under high-speed clock.

[0034] The complete transfer function of the comb cascade integrator filter is: in To reduce the sampling factor, This represents the number of stages in the comb-cascaded integrator filter. The aforementioned downsampling factor... The number of stages of a comb-cascaded integrator filter All parameters are brought out to the port and can be dynamically configured by the control system. After the program is fixed, they can be adjusted according to the requirements of signal bandwidth and channel spacing.

[0035] It should be noted that the above downsampling factor The value of has a direct impact on the frequency response characteristics of the comb cascaded integrator filter: As the value increases, the main lobe gain increases and the bandwidth narrows, while the side lobes become smaller and denser, thus enhancing the suppression of adjacent channel interference. The number of stages in a comb-cascaded integrator filter. As the amplitude increases, the transition band of the main lobe becomes steeper, and the attenuation of the side lobes is greater. It should be understood that the actual selection of parameters needs to be determined based on the bandwidth of the target signal and the interference from adjacent channels.

[0036] In this invention, a structure diagram of the combined filters is first constructed based on logical relationships, and then... Figure 8 As shown, an integrator is implemented using a pipelined timing register with staggered addition after timing. Data decimation is then achieved through timing logic timing. Finally, a comb filter is implemented using pipelined timing followed by subtraction. The filter stage number and decimation factor are routed to ports as adjustable parameters of the control system.

[0037] In this embodiment, after the comb cascade integrator completes the filtering process, the bit width of the digital signal expands from the initial 16 bits to a higher bit width due to the integration and accumulation operation. The expanded digital signal is then truncated according to the actual effective bit range to extract 16 bits of effective data, so as to control the data bit width of subsequent processing stages and avoid resource waste.

[0038] Figure 7The Cascaded Integrator-Comb (CIC) filter was visualized using MATLAB for verification. Different values ​​of the decimation factor R were compared. As the decimation factor increases, the main lobe gain becomes larger and narrower, while the side lobes become smaller and denser, thus better suppressing adjacent channel interference. Conversely, a larger filter order N results in a steeper main lobe and greater side lobe attenuation. Therefore, in this invention, the structure diagram of the combined filter was first constructed based on logical relationships, and then... Figure 5 As shown, an integrator is implemented using a pipelined timing register with staggered addition after timing. Data decimation is then achieved through timing logic timing. Finally, a comb filter is implemented using pipelined timing followed by subtraction. The filter stage number and decimation factor are routed to ports as adjustable parameters of the control system.

[0039] Step 4: Half-band filtering and passband compensation processing The downsampled digital signal is subjected to half-band filtering to suppress the sidelobe and image components remaining after the comb cascade integrator filter. At the same time, the passband roll-off introduced by the comb cascade integrator filter is compensated to obtain the half-band filtered digital signal.

[0040] A half-band filter (HB) is... A first-order finite impulse response (FIR) filter has a frequency response that satisfies the following symmetric properties: in This is the frequency response of a half-band filter. This refers to the digital angular frequency. The above characteristics are expressed in the digital frequency band. Internally, the passband and stopband are related to Symmetrical, and the sum of the gains at corresponding frequencies is always 1 ( Figure 9 This symmetry directly results in nearly half of the coefficients in the impulse response of the half-band filter being zero (sparse structure), which allows for effective suppression of sidelobes and image components using sparse coefficients even at low processing speeds.

[0041] Meanwhile, by superimposing an anti-sinc compensation characteristic in the half-band filter, the high-frequency components are moderately boosted in the passband, which cancels out the passband roll-off caused by the rapid drop in main lobe gain from low to high frequencies due to the comb cascade integrator filter, thus obtaining a filter output with improved passband flatness.

[0042] It should be noted that the above halfband filter is configured using a finite impulse response filter IP core provided by the field programmable gate array development tool. This finite impulse response filter IP core supports inverse sinc compensation settings and has been optimized to reduce the consumption of DSP48 resources, lookup tables (LUTs), and block random access memory (BRAM).

[0043] Step 5: Multi-channel parameter configuration control The control system centrally manages and dynamically configures the configurable parameters in each of the above processing steps, obtaining the independent parameter configuration status of each channel and each carrier. After the program is fixed, the control system writes and updates parameters such as the frequency control word of the numerically controlled oscillator, the downsampling factor of the comb cascade integrator filter, and the number of stages of the comb cascade integrator filter through the register interface, so that each parameter can be adjusted as needed during system operation without re-fixing the program.

[0044] In multi-carrier applications, the control system maintains an independent parameter configuration register set for each channel and each carrier. Parameters such as frequency, decimation factor, and symbol rate can be configured independently and do not affect each other. The control system receives configuration commands from external sources, parses them, and writes the corresponding parameter values ​​into the register of the target channel. The signal processing links of each channel operate independently according to the parameters in their respective registers.

[0045] It should be noted that the aforementioned control system is also responsible for the register initialization and configuration of the analog-to-digital converter chip, including sampling rate setting and JESD204B interface parameter configuration, and completes configuration communication with the analog-to-digital converter chip through the serial peripheral interface (SPI).

[0046] In this embodiment, the configurable parameters managed by the control system, in addition to the frequency control word, downsampling factor, and number of stages in the comb cascade integrator filter, also include the following parameters: functional bypass enable, used to bypass a certain processing stage when it is not needed, allowing the signal to be directly passed to the subsequent stage without going through the operation of that stage; inversion spectrum enable, used to mirror and invert the signal spectrum to adapt to different spectrum arrangement requirements; and gain control parameters, used to adjust the amplitude of the output signal. All of the above parameters can be dynamically configured after the program is fixed via the register interface.

[0047] In this embodiment of the application, in order to support on-demand expansion of channels, the control system adopts a parameterized register address mapping method. When a new channel is added, it is only necessary to expand the corresponding register address space in the control system and instantiate the new signal processing link in the field programmable gate array logic to complete the channel expansion without modifying the processing logic and control logic of the existing channel.

[0048] Step 6: Farrow resampling filtering In this embodiment of the application, in order to still be able to convert the sampling rate of the signal at any ratio after the program is solidified, so as to adapt to the signal requirements of different symbol rates, the following steps are also included on the basis of step 4: performing Farrow filtering on the digital signal after half-band filtering to obtain the resampled digital signal.

[0049] It should be understood that in traditional methods, fixed channel selection is usually achieved by selecting the sampling rate of the analog-to-digital converter chip and choosing an appropriate integer decimation factor in the subsequent stage. However, this method can only achieve sampling rate conversion at integer multiples and cannot meet the requirement of adapting to signals of arbitrary symbol rates after program execution. The Farrow filter, by representing the impulse response of the Farrow filter as a polynomial function of fractional delay parameters, can achieve arbitrary fractional delay and sampling rate conversion simply by changing the delay parameters with fixed sub-filter coefficients.

[0050] The filter coefficients of the Farrow filter Represented as fractional delay parameter of order polynomial: in This refers to the sample index of the Farrow filter. For the first Fixed coefficients of each sub-filter Let be the order of the polynomial. This is the fractional delay parameter, and its value range is... , This is the order index of the sub-filter. The range of values ​​is to The entire structure can be considered as A combination of a finite impulse response sub-filter with fixed coefficients and a polynomial weighted summation. The input signal... At the same time, through the coefficient is of Each sub-filter has a finite impulse response (FIR) sub-filter, and the output of each sub-filter is multiplied by the corresponding... The weights are then summed to obtain the resampled output: in The length of each sub-filter, This is the convolution index within the sub-filter. The range of values ​​is to .

[0051] This embodiment uses a third-order Lagrange Farrow filter with four consecutive input samples. , , , It has four sub-filters, each a finite impulse response filter of length 4. The polynomial order and coefficients of each sub-filter are as follows: Polynomial Order Corresponding weight and filter coefficients Polynomial order Corresponding weight and filter coefficients Polynomial order Corresponding weight and filter coefficients Polynomial order Corresponding weight and filter coefficients Substituting the above coefficients into the polynomial expansion, the output is: In a field-programmable gate array (FPGA) chip, the coefficients of each sub-filter are quantized in a 16-bit fixed-point format. Using 65536 as the base, the fractional coefficients are proportionally converted to integer representations. Then, the delay data is... arrive The outputs of each sub-filter are then multiplied and added sequentially with the quantized filter coefficients, and then multiplied and added to each sub-filter respectively. The powers of the integers are multiplied, and the output signal is obtained through a shift and truncation operation. Fractional delay parameter. The system can be dynamically configured through the register interface, thereby enabling arbitrary sampling rate conversion after the program is fixed, and adapting to signals with different symbol rates.

[0052] Step 7: Matched Filtering In this embodiment of the application, in order to suppress the image, aliasing and adjacent channel interference that remain after the pre-stage filtering, and to perform matched filtering on the inter-symbol interference and noise caused by the pulse shaping at the transmitter, thereby improving the signal-to-noise ratio of the output signal, the following steps are also included in addition to step 6 (or step 4 if step 6 is not performed): performing matched filtering on the digital signal to obtain the matched-filtered baseband signal.

[0053] A matched filter is a finite impulse response (FIR) filter, and its impulse response is the time-reversed conjugate of the target signal waveform. For a known baseband pulse waveform... ,exist Pick Within the interval, the received signal is ,in For the duration of the symbol, If the noise is zero-mean, then the impulse response of the matched filter is: That is, the conjugate of the transmitted signal is time-flipped and delayed to be aligned to the end of the symbol. The matched filter enables the output signal-to-noise ratio to reach its theoretical upper limit at the symbol decision time.

[0054] Finite impulse response convolution operations are performed on the in-phase and quadrature components respectively: in For the matched filter coefficients, For the order of the matched filter, For the coefficient index of the matched filter, The range of values ​​is to , and These are the in-phase and quadrature components of the input, respectively. and These represent the in-phase and quadrature components after matched filtering, respectively. The above operations are implemented using a multiply-accumulate unit and logic control. The matched filter coefficients are determined in advance based on the pulse shaping waveform of the target signal through simulation, and configured by loading the coefficients using the finite impulse response filter IP core provided by the field-programmable gate array development tool.

[0055] It should be noted that the matched filter coefficients mentioned above can be changed according to different target signal types. By loading different coefficient files, different pulse shaping waveforms can be adapted, further enhancing the system's adaptability to various signal types.

[0056] Step 8: Digital gain adjustment processing In this embodiment of the application, to prevent overflow or loss of quantization accuracy due to amplitude changes in the digital signal during multi-stage processing, and to maintain the amplitude of the output signal within a quantization range suitable for subsequent demodulation processing, in addition to step 7, the following step is further included: performing gain adjustment processing on the matched-filtered baseband signal to obtain the gain-adjusted baseband signal. The gain adjustment processing includes the following sub-steps: Step 801: Perform power detection on the baseband signal and determine the in-phase component. and orthogonal components Calculate instantaneous power The 16-bit in-phase and quadrature values ​​are converted into corresponding power quantization values ​​through complex multiplication operations to obtain the power estimate of the current signal.

[0057] Step 802: Based on the comparison between the power estimate and the preset power range, perform left or right shift operations on the in-phase and quadrature component data input after register pausing. When the power estimate is lower than the lower limit of the preset power range, perform a left shift operation to increase the signal amplitude; when the power estimate is higher than the upper limit of the preset power range, perform a right shift operation to decrease the signal amplitude; continue adjusting until the signal power falls within the preset power range to obtain the baseband signal after gain adjustment. The shift amount for gain adjustment is configured by the control system through the register interface.

[0058] Step 9: Baseband signal switching and routing processing In this embodiment, to achieve flexible signal routing between different channels in multi-channel application scenarios and meet the different channel configuration requirements, the following steps are also included: The baseband signals output from each channel after processing in the aforementioned steps are connected to a baseband signal switching pool. Based on the routing configuration instructions issued by the control system, the baseband signal switching pool performs rapid matching and switching operations on the baseband signals of each channel, routing the baseband signals of the specified channel to the corresponding subsequent processing interface to obtain the routed multi-channel baseband signal output.

[0059] It should be noted that the aforementioned baseband signal switching pool is a data switching module, and it maintains a routing mapping table internally. Each record in the routing mapping table contains a source channel identifier and a destination interface identifier. The control system configures and updates the routing mapping table through a register interface. When the baseband signal switching pool receives baseband signals from each channel, it forwards the data of the corresponding channel to the destination interface according to the mapping relationship in the routing mapping table.

[0060] The multi-carrier channel extraction method provided in this embodiment centrally manages the parameters of each key link in the signal processing chain by exporting them to the register interface of the control system. This allows parameters such as the frequency control word of the numerically controlled oscillator, the downsampling factor of the comb-cascaded integrator filter, and the number of stages of the comb-cascaded integrator filter to be dynamically updated via register write operations even after the program is fixed. Therefore, when it is necessary to adapt to different carrier frequencies or channel bandwidths, the control system only needs to modify the corresponding register parameter values ​​to complete the reconfiguration of the link, without recompiling and fixing the program, thus overcoming the limitation of traditional methods where parameters cannot be adjusted after being fixed.

[0061] Furthermore, the introduction of the Farrow filter allows the system to achieve arbitrary sampling rate conversion simply by changing the fractional delay parameter with fixed sub-filter coefficients, overcoming the limitation of traditional integer decimation methods that cannot adapt to signals with arbitrary symbol rates. The comb-cascaded integrator filter adopts a pipelined structure involving only addition, subtraction, and shift operations, saving field-programmable gate array (FPGA) chip multiplier resources while ensuring the regularity of high-speed processing timing, enabling the system to have flexible parameter configuration capabilities while ensuring processing latency.

[0062] In multi-carrier applications, the control system maintains an independent parameter configuration register set for each channel and each carrier, ensuring that parameter configurations between different channels do not interfere with each other. Each channel can independently configure parameters such as frequency, decimation factor, and symbol rate according to the type of signal it receives. The baseband signal switching pool further enables flexible signal routing between channels, allowing the mapping relationship between channels and physical channels to be dynamically adjusted. These features enable a single device to adapt to multiple communication standards and signal types through parameter configuration, reducing lifecycle costs from R&D to deployment. Simultaneously, the parameterized approach of on-demand channel expansion means that when the number of carriers increases, only the corresponding logic and register space needs to be expanded, without affecting the processing logic of existing channels, thus ensuring system scalability.

[0063] The embodiments of the present invention have been described above. However, the embodiments are not limited to the specific implementation methods described above. The specific implementation methods described above are merely illustrative and not restrictive. Those skilled in the art can make more equivalent embodiments under the guidance of the present embodiments, and all of them are within the protection scope of the present embodiments.

Claims

1. A multi-carrier channel extraction method, characterized in that, Includes the following steps: The analog radio frequency signal received by the antenna is input to the analog-to-digital converter after being filtered by an anti-aliasing low-pass filter. It is sampled and quantized according to a preset sampling rate to obtain a digital intermediate frequency signal. The signal is then transmitted to the field programmable gate array chip through a high-speed serial interface. After physical layer deserialization, data link layer frame synchronization and transport layer reassembly, a complex digital signal containing in-phase and quadrature components is obtained. A local carrier signal of a specified frequency is generated using a numerically controlled oscillator. The in-phase and quadrature components of the complex digital signal are multiplied and added with the cosine and sine values ​​of the local carrier signal, respectively, to obtain the baseband signal after frequency shifting. The output frequency of the numerically controlled oscillator is controlled by a frequency control word, which is written by the control system through a register interface and can be dynamically updated after the program is fixed. The baseband signal after spectrum shifting is filtered and downsampled by a comb-cascaded integrator to suppress out-of-band interference and reduce the data rate, thereby obtaining the downsampled digital signal. The downsampling factor and number of stages of the comb-cascaded integrator filter are dynamically configured through the register interface of the control system. The downsampled digital signal is subjected to half-band filtering to suppress residual sidelobe components and image components, while the passband roll-off introduced by the comb cascade integrator filter is compensated to obtain the half-band filtered digital signal. The control system centrally manages the configurable parameters in each processing step. In a multi-carrier scenario, an independent parameter configuration register group is maintained for each channel and each carrier, so that the parameter configurations of different channels and carriers do not affect each other, and the signal processing links of each channel operate independently according to the parameters in their respective registers.

2. The multi-carrier channel extraction method according to claim 1, characterized in that, The numerically controlled oscillator generates a local carrier signal using a phase accumulator combined with a lookup table. Utilizing the quadrant symmetry of the sine and cosine functions, the waveform data is compressed to a quarter-cycle interval and stored in a read-only memory. The phase accumulator increments by one frequency control word step per clock cycle. The high-order bits of the accumulation result are used as the address index of the read-only memory to read the sine and cosine values. The relationship between the frequency control word and the target output frequency is: the frequency control word equals the product of the target output frequency and the full-scale count value of the phase accumulator divided by the sampling rate. The phase accumulator has a bit width of 32 bits.

3. The multi-carrier channel extraction method according to claim 1, characterized in that, The comb-shaped cascaded integrator filter consists of multiple cascaded integrators and multiple cascaded combs. The integrator part achieves discrete integration accumulation by staggered addition after timing with a pipelined timing register. The data extraction part controls the retention of one data point every downsampling factor input sample through a timing logic enable signal. The comb filter part achieves this by subtracting the current value from the value of the sample delayed by the downsampling factor. The entire operation involves only addition, subtraction, and register shifting operations. After the comb-shaped cascaded integrator filter is completed, the digital signal expanded by the integration accumulation operation is truncated according to the actual effective bit range to extract 16 bits of effective data.

4. The multi-carrier channel extraction method according to claim 1, characterized in that, The half-band filter is a finite impulse response filter. Its frequency response satisfies the symmetry between the passband and stopband about half the Nyquist frequency, and the sum of the gains at the corresponding frequencies is always 1. This symmetry makes nearly half of the coefficients in the filter's impulse response zero. The half-band filter is superimposed with an inverse sinc compensation characteristic, which boosts the high-frequency components in the passband and cancels out the passband roll-off caused by the comb cascade integrator filter, thereby improving the passband flatness.

5. The multi-carrier channel extraction method according to claim 1, characterized in that, The configurable parameters managed by the control system also include: a function bypass enable parameter, used to bypass a specified processing stage so that the signal is directly transmitted to the next stage without passing through the operation of that stage; an inversion spectrum enable parameter, used to mirror and flip the signal spectrum; and a gain control parameter, used to adjust the amplitude of the output signal. All of the above parameters can be dynamically configured after the program is fixed through the register interface. The control system adopts a parameterized register address mapping method. When a new channel is added, it is only necessary to expand the corresponding register address space and instantiate the new signal processing link in the field programmable gate array logic, without modifying the processing logic and control logic of the existing channel.

6. The multi-carrier channel extraction method according to claim 1, characterized in that, Following the half-band filtering process, the method further includes: performing Farrow filtering on the half-band filtered digital signal to obtain a resampled digital signal; the filter coefficients of the Farrow filter are represented as polynomial functions of fractional delay parameters, and the entire structure is composed of multiple finite impulse response sub-filters with fixed coefficients and polynomial weighted summation. After the input signal passes through each sub-filter simultaneously, the output of each sub-filter is multiplied by the power weight of the corresponding fractional delay parameter and then summed to obtain the resampled output; the fractional delay parameter is dynamically configured by the control system through a register interface, and after the program is fixed, it can achieve arbitrary sampling rate conversion.

7. The multi-carrier channel extraction method according to claim 6, characterized in that, The Farrow filter employs a third-order Lagrange structure, using four consecutive input samples and four sub-filters, each of which is a finite impulse response filter with a length of 4. In the field-programmable gate array (FPGA) chip, the coefficients of each sub-filter are quantized in a 16-bit fixed-point format, and the fractional coefficients are converted to integer representations with a base of 65536. The delay data is then multiplied and added sequentially with the quantized filter coefficients. The output of each sub-filter is then multiplied by the powers of the fractional delay parameters, and finally, the output signal is obtained through a shift and truncation operation.

8. The multi-carrier channel extraction method according to claim 6, characterized in that, Following the Farrow filtering process, the method further includes: performing matched filtering on the resampled digital signal. The matched filter is a finite impulse response filter, whose impulse response is the time-reversed conjugate of the target signal waveform. Finite impulse response convolution operations are performed on the in-phase and quadrature components respectively, and the output signal-to-noise ratio reaches the theoretical upper limit at the sign decision time to obtain the matched filtered baseband signal. The coefficients of the matched filter are predetermined according to the pulse shaping waveform of the target signal, and different pulse shaping waveforms are adapted by loading different coefficient files.

9. The multi-carrier channel extraction method according to claim 8, characterized in that, Following the matched filtering process, the system further includes gain adjustment and baseband signal switching routing: the gain adjustment process calculates an instantaneous power estimate based on the sum of the squares of the in-phase and quadrature components, and performs a left or right shift operation on the in-phase and quadrature component data based on the comparison between the power estimate and a preset power range, continuously adjusting until the signal power falls within the preset power range. The shift amount is configured by the control system through the register interface. The baseband signal switching routing process connects the baseband signals output from each channel to the baseband signal switching pool. The baseband signal switching pool maintains a routing mapping table, and the control system configures and updates the routing mapping table through the register interface, routing the baseband signal of a specified channel to the corresponding subsequent processing interface to obtain the routed multi-channel baseband signal output.

10. A multi-carrier channel extraction system, used to execute the multi-carrier channel extraction method according to any one of claims 1 to 9, characterized in that, include: The signal acquisition module is used to sample and quantize the analog radio frequency signal after it is filtered by anti-aliasing low-pass filter, and then transmit it to the field programmable gate array chip through a high-speed serial interface to complete physical layer deserialization, data link layer frame synchronization and transport layer reassembly to obtain complex digital signals. The digital downconversion module is used to generate a local carrier signal using a numerically controlled oscillator, perform complex multiplication on a complex digital signal, and obtain the baseband signal after frequency shifting. The comb-cascaded integrator filter module is used to perform comb-cascaded integrator filtering and downsampling on the baseband signal after spectrum shifting to obtain the downsampled digital signal. The half-band filtering module is used to perform half-band filtering on the downsampled digital signal and superimpose inverse sinc compensation to obtain the half-band filtered digital signal. The parameter configuration control module is used to centrally manage and dynamically configure the configurable parameters in each processing module through the register interface, and maintains an independent parameter configuration register group for each channel and each carrier. The Farrow resampling module is used to perform Farrow filtering on the digital signal after half-band filtering, so as to achieve sampling rate conversion of any ratio. The matched filtering module is used to perform matched filtering on the resampled digital signal to obtain the matched filtered baseband signal. The gain adjustment module is used to perform power detection and shift gain adjustment on the matched-filtered baseband signal to obtain the gain-adjusted baseband signal. The baseband signal switching and routing module is used to connect the baseband signals of each channel to the baseband signal switching pool and route the baseband signals of a specified channel to the corresponding downstream processing interface according to the routing mapping table.

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