Printed circuit board

Abstract

The present disclosure relates to a printed circuit board comprising: a glass layer having an upper surface and a lower surface and a side surface connecting the upper surface and the lower surface; the through hole penetrates through the glass layer between the upper surface and the lower surface of the glass layer; and a metal via filling at least a portion of the through hole, in which at least one of the upper surface and the lower surface of the glass layer has a surface roughness greater than a surface roughness of the side surface of the glass layer, the surface roughness of at least one of the upper surface and the lower surface of the metal via hole is greater than the surface roughness of the side surface of the glass layer.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0162016, filed on November 14, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a printed circuit board. Background Technology

[0003] To meet the demands of high-performance and miniaturization strategies in the semiconductor industry, printed circuit boards (PCBs) require increasingly smaller and higher-density designs. For example, manufacturing high-end products such as server boards necessitates layered and large substrates. However, as the number of wiring layers and substrate size increase, the board may become prone to warping. To address this issue, the use of glass cores has been considered. However, due to the smooth surface of glass, adhesion to insulating materials may be low, potentially leading to glass damage and voids and delamination of the insulating material. Summary of the Invention

[0004] One aspect of this disclosure is to provide a printed circuit board that can improve the adhesion between the glass layer and the insulating material and reduce voids and delamination of the insulating material in a substrate structure including a glass layer on which metal vias are formed.

[0005] One of the various solutions disclosed herein is to form surface roughness by using a laser to perform a skiving operation on the surface of the glass layer and the exposed surface of the metal via.

[0006] For example, a printed circuit board may include: a glass layer having an upper surface and a lower surface and a side surface connecting the upper surface and the lower surface; a through-hole penetrating the glass layer between the upper surface and the lower surface; and a metal via filling at least a portion of the through-hole, wherein the surface roughness of at least one of the upper surface and the lower surface of the glass layer may be greater than the surface roughness of the side surface of the glass layer, and the surface roughness of at least one of the upper surface and the lower surface of the metal via may be greater than the surface roughness of the side surface of the glass layer.

[0007] For example, a printed circuit board may include: a glass layer having an upper surface and a lower surface and a side surface connecting the upper surface and the lower surface; a through-hole penetrating the glass layer between the upper surface and the lower surface; and a metal via filling at least a portion of the through-hole, wherein the average roughness Ra of the upper surface and the lower surface of the glass layer is greater than or equal to 0.1 μm and less than 10 μm, and the average roughness Ra of the upper surface and the lower surface of the metal via is greater than or equal to 0.1 μm and less than 10 μm.

[0008] For example, a printed circuit board may include: a glass layer having a top surface, a bottom surface, and a side surface connecting the top surface and the bottom surface, wherein the surface roughness of the top surface and / or the bottom surface is greater than the surface roughness of the side surface; a through-hole penetrating the glass layer between the top surface and the bottom surface; and a metal via at least partially filling the through-hole, wherein, in a cross-sectional view, the top surface of the metal via protrudes above the top surface of the glass layer by a distance greater than the surface roughness of the top surface of the glass layer.

[0009] One of the various effects of this disclosure is to provide a printed circuit board that can improve the adhesion of the glass layer to the insulating material and reduce voids and delamination of the insulating material in a substrate structure including a glass layer in which metal vias are formed. Attached Figure Description

[0010] The above and other aspects, features and advantages of this disclosure will be more clearly understood through the following specific embodiments in conjunction with the accompanying drawings, in which: Figure 1 It is a block diagram that schematically illustrates an example of an electronic device system; Figure 2 This is a schematic cross-sectional view illustrating an example of a printed circuit board; Figure 3 This shows a top-view image obtained by capturing the surface of a glass layer with metal vias formed thereon using an electron microscope; and Figure 4 It was captured using an electron microscope along... Figure 3 The image shows a portion of the cross-section of the surface of the glass layer with metal vias formed on it, taken by line A-A'. Detailed Implementation

[0011] The present disclosure will be described below with reference to the accompanying drawings. In the drawings, the shape and size of the elements may be exaggerated or reduced for clarity of description.

[0012] Figure 1 This is a block diagram schematically illustrating an example of an electronic device system.

[0013] Reference Figure 1 Electronic device 1000 houses motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to motherboard 1010. These components are also connected to other electronic components described below via various signal lines 1090.

[0014] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these and may also include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with each other. Chip-related components 1020 may be in the form of a package including the aforementioned chips.

[0015] Network-related components 1030 may include components compatible with or operating under protocols such as: Wi-Fi (such as the IEEE 802.11 series), WiMAX (such as the IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, GSM+, EDGE+, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, and 5G protocols, as well as any other wireless or wired standards or protocols specified after the aforementioned protocols. However, network-related component 1030 is not limited to this, and may also include components compatible with or operating according to multiple other wireless or wired standards or protocols. Furthermore, network-related component 1030 may be combined with the aforementioned chip-related component 1020.

[0016] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these and may also include passive components in the form of chip modules for various other purposes. Furthermore, other components 1040 may be combined with each other in conjunction with chip-related components 1020 and / or network-related components 1030.

[0017] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, other electronic components are not limited to these and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), optical disc (CD) drives, digital versatile disc (DVD) drives, etc. In addition, depending on the type of electronic device 1000, it may also include other electronic components for various purposes.

[0018] Electronic device 1000 can be a smartphone, personal digital assistant, digital video camera, digital camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, or automotive component. However, electronic device 1000 is not limited to these, and can also be any other electronic device capable of processing data.

[0019] Figure 2 This is a schematic cross-sectional view illustrating an example of a printed circuit board.

[0020] Reference Figure 2The printed circuit board 100 according to an example embodiment may include: a glass layer 111 having an upper surface S1 and a lower surface S2 and a side surface S3 connecting the upper surface S1 and the lower surface S2; a through-hole V penetrating the glass layer 111 between the upper surface S1 and the lower surface S2; and a metal via 131 filling at least a portion of the through-hole V. In this case, the upper surface S1 and / or the lower surface S2 of the glass layer 111 may have a specific surface roughness. Additionally, the upper surface and / or the lower surface of the metal via 131 may also have a specific surface roughness. For example, the surface roughness of the upper surface S1 and / or the lower surface S2 of the glass layer 111 may be greater than the surface roughness of the side surface S3 of the glass layer 111, and the surface roughness of the upper surface and / or the lower surface of the metal via 131 may be greater than the surface roughness of the side surface S3 of the glass layer 111. For example, the upper surface S1 and / or lower surface S2 of the glass layer 111 and the upper surface and / or lower surface of the metal via 131 can be laser-scraped as described below. Therefore, the average roughness Ra of the upper surface S1 and / or lower surface S2 of the glass layer 111 and the upper surface and / or lower surface of the metal via 131 can be greater than or equal to about 0.1 μm and less than about 10 μm, or greater than or equal to about 0.1 μm and less than or equal to about 2 μm. On the other hand, the side surface of the glass layer 111 may not be treated in this way, and the average roughness Ra of the side surface of the glass layer 111 can be greater than or equal to 0.001 μm and less than 0.1 μm.

[0021] In this manner, the printed circuit board 100 according to the example embodiment may substantially comprise a glass layer 111. Furthermore, the metal via 131 may be formed on the glass layer 111 in a padless manner (i.e., without individual pads or solder pads), thereby facilitating the implementation of microcircuits on the insulating material 112 described below, improving fabrication capabilities, and enabling warpage control using a low coefficient of thermal expansion. Additionally, in the printed circuit board 100 according to the example embodiment, the upper and / or lower surfaces of the glass layer 111 may have specific surface roughness, and the upper and / or lower surfaces of the metal via 131 exposed from the glass layer 111 may also have specific surface roughness. Therefore, the adhesion between the glass layer 111 and the metal via 131 and the insulating material 112 described below can be improved, thus reducing problems such as damage to the glass layer 111 and voids and delamination of the insulating material 112. Furthermore, the adhesion between the metal via 131 and the first connection via 132 and the second connection via 133 described below can also be improved, thus further improving reliability.

[0022] The surface roughness of the upper surface S1 and / or lower surface S2 of the glass layer 111 and the upper surface and / or lower surface of the metal via 131 can be formed by performing a scraping operation using a laser. Both ultraviolet and infrared lasers can be used as the laser. The surface roughness can be formed in two mutually perpendicular directions on a plane, and can be formed in only one direction if desired. The size of the surface roughness can be adjusted according to the laser source or the amount of energy. The surface roughness can be selectively formed in desired areas and can be formed over a large area. In this case, the surface roughness of the upper surface of the glass layer 111 can be formed to be greater than the surface roughness of the upper surface of the metal via 131, and the surface roughness of the lower surface of the glass layer 111 can be formed to be greater than the surface roughness of the lower surface of the metal via 131, but this disclosure is not necessarily limited to this. Additionally, the surface roughness of the upper surface and / or lower surface of the glass layer 111 can be formed to be greater than the surface roughness of the upper surface and / or lower surface of the metal via 131.

[0023] Reference Figure 2 The printed circuit board 100 according to the example embodiment may further include: an insulating material 112 covering at least a portion of the upper surface S1 and lower surface S2 of the glass layer 111 and the upper surface and lower surface of the metal via 131; a first wiring layer 121 disposed on the upper surface of the insulating material 112; a first connection via 132 penetrating at least a portion of the upper side of the insulating material 112 and directly connecting a portion of the first wiring layer 121 to the upper surface of the metal via 131; a second wiring layer 122 disposed on the lower surface of the insulating material 112; and a second connection via 133 penetrating at least a portion of the lower side of the insulating material 112 and directly connecting a portion of the second wiring layer 122 to the lower surface of the metal via 131. The insulating material 112 can protect the glass layer 111 and the metal via 131. Furthermore, the first wiring layer 121 and the second wiring layer 122 can be formed on the insulating material 112 instead of on the glass layer 111, thereby improving the reliability of the first wiring layer 121 and the second wiring layer 122 by improving adhesion, etc., and enabling more diverse designs. Additionally, the first connection via 132 and the second connection via 133 can be directly connected to the metal via 131 without pads or solder pads, thereby allowing for a thinner overall substrate thickness and a shorter signal transmission path.

[0024] The surface roughness of the upper surface S1 and / or lower surface S2 of the glass layer 111 may be greater than the surface roughness of the upper surface and / or lower surface of the insulating material 112, and the surface roughness of the upper surface and / or lower surface of the metal via 131 may be greater than the surface roughness of the upper surface and / or lower surface of the insulating material 112. For example, the upper surface S1 and / or lower surface S2 of the glass layer 111 and the upper surface and / or lower surface of the metal via 131 may be laser-scraped as described above, such that the average roughness Ra of each surface may be greater than or equal to about 0.1 μm and less than about 10 μm, or greater than or equal to about 0.1 μm and less than or equal to about 2 μm. On the other hand, in the case where the insulating material 112 may include an Ajinomoto deposited film (ABF), the surface roughness (e.g., average roughness Ra) of each of the above surfaces may be about 400 nm to 800 nm.

[0025] Reference Figure 2 The printed circuit board 100 according to the example may also include a frame 105 having a through-hole H. A glass layer 111 may be at least partially disposed within the through-hole H. An insulating material 112 may cover at least a portion of each of the upper and lower surfaces of the frame 105. The insulating material 112 may fill at least a portion of the space between the frame 105 and the glass layer 111 within the through-hole H. If desired, at least a portion of the space between the frame 105 and the glass layer 111 within the through-hole H may also be filled using a separate filler. The frame 105 may comprise a material with excellent rigidity. The frame 105 may be used as a fixture during processing, thus allowing processing to be performed at the panel level via the frame 105. Additionally, the frame 105 may be retained in the final unit after splitting, which may further facilitate warpage control.

[0026] Reference Figure 2 The printed circuit board 100 according to the example embodiment may further include: a plurality of first stacked insulating layers 141 disposed on the upper surface of the insulating material 112; a plurality of first stacked wiring layers 142 disposed on or within the plurality of first stacked insulating layers 141; and a plurality of first stacked via layers 143 disposed within the plurality of first stacked insulating layers 141 and respectively connected to at least one of the plurality of first stacked wiring layers 142. For example, the stacked layers may be formed on the upper side of the glass layer 111. For example, the printed circuit board 100 may include the glass layer 111 as a core layer, may have stacked layers formed on at least one side of the core layer, and may be used as a packaging substrate, an interposer substrate, etc.

[0027] Reference Figure 2The printed circuit board 100 according to the example embodiment may further include: a plurality of second stacked insulating layers 151 disposed on the lower surface of the insulating material 112; a plurality of second stacked wiring layers 152 disposed on or within the plurality of second stacked insulating layers 151; and a plurality of second stacked via layers 153 disposed within the plurality of second stacked insulating layers 151 and respectively connected to at least one of the plurality of second stacked wiring layers 152. For example, the printed circuit board 100 may include a glass layer 111 as a core layer, may have stacked layers formed on both sides of the core layer, and may be used as a packaging substrate, an interposer substrate, etc.

[0028] Reference Figure 2 The printed circuit board 100 according to the example embodiment may further include a first passivation layer 161 and / or a second passivation layer 162. The first passivation layer 161 is disposed on the uppermost first stacked insulating layer 141 among a plurality of first stacked insulating layers 141, covering a portion of the uppermost first stacked wiring layer 142 among a plurality of first stacked wiring layers 142, and has a first opening that exposes another portion of the uppermost first stacked wiring layer 142 among a plurality of first stacked wiring layers 142. The second passivation layer 162 is disposed on the lowermost second stacked insulating layer 151 among a plurality of second stacked insulating layers 151, covering a portion of the lowermost second stacked wiring layer 152 among a plurality of second stacked wiring layers 152, and has a second opening that exposes another portion of the lowermost second stacked wiring layer 152 among a plurality of second stacked wiring layers 152. Therefore, the internal structure of the printed circuit board 100 can be protected more easily.

[0029] In the following text, reference will be made to Figure 2 The components of the printed circuit board 100 according to the example embodiment are described in more detail.

[0030] Frame 105 may include an organic insulating material. The organic insulating material may include thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or materials prepared by impregnating a thermosetting or thermoplastic resin together with inorganic and / or organic fillers into a core material (such as glass fiber, e.g., a glass fabric, for example, glass cloth). For example, the organic insulating material may include copper-clad laminate (CCL) or unclad CCL, but this disclosure is not limited thereto, and may also include other organic or inorganic materials with excellent rigidity. A through-pass H may extend through frame 105 between its upper and lower surfaces. The through-pass H may continuously surround the side surface S3 of glass layer 111.

[0031] Glass layer 111 may comprise glass as an amorphous solid. The glass may include, for example, pure silica (approximately 100% SiO2), soda-lime glass, borosilicate glass, and aluminosilicate glass. However, this disclosure is not limited thereto, and alternative glass materials (e.g., fluorine glass, phosphate glass, chalcogenide glass, etc.) may also be used as materials for forming glass layer 111. Furthermore, other additives may be included to form glass with specific physical properties. Such additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda ash), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of these and other elements. Glass layer 111 may differ from organic insulating materials (such as copper-clad laminates (CCL), prepregs (PPG), etc.) that include glass fibers (e.g., glass fabrics such as glass cloth). Glass layer 111 may be in the form of, for example, a glass plate. A through-hole V may penetrate glass layer 111 between its upper and lower surfaces. Depending on the shape of the glass layer 111, the number of side surfaces S3 can be one or more. For example, when the glass layer 111 has a generally rectangular shape in a plane, multiple side surfaces S3 can be provided, such as four side surfaces S3, but this disclosure is not limited thereto. When the glass layer 111 has a generally elliptical shape in a plane, the number of side surfaces S3 can be one, but this disclosure is not limited thereto.

[0032] The insulating material 112 may include an organic insulating material. The organic insulating material may include thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or materials prepared by impregnating a thermosetting or thermoplastic resin together with inorganic and / or organic fillers into a core material (such as glass fiber, e.g., a glass fabric, for example, glass cloth). For example, the organic insulating material may include prepreg (PPG), Ajinomoto laminate (ABF), and photosensitive dielectric (PID), but this disclosure is not limited thereto. The insulating material 112 may be formed using multiple layers. In this case, the multiple layers may be integral without boundaries, or the boundaries between the layers may be identifiable. Additionally, the multiple layers may include substantially the same insulating material, or may include different insulating materials.

[0033] Each of the first wiring layer 121 and the second wiring layer 122 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the first wiring layer 121 and the second wiring layer 122 may include a seed layer formed by electroless plating (e.g., electroless copper plating) and may include a patterned plating layer formed based on the seed layer by electrolytic plating (e.g., electrolytic copper plating). Each of the first wiring layer 121 and the second wiring layer 122 may perform various functions according to the design. For example, the first wiring layer 121 and the second wiring layer 122 may include signal patterns, power patterns, and ground patterns. Each pattern may have various shapes such as lines, traces, planes, pads, and mats.

[0034] Metal via 131 may include a metal. This metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, metal via 131 may include a titanium and copper layer formed by sputtering (i.e., sputtered titanium and sputtered copper) as a seed layer, and may include a patterned plating based on the titanium and copper layers formed by electrolytic plating (e.g., electrolytic copper). Metal via 131 may perform various functions depending on the design. For example, metal via 131 may include through-vias for signal transmission, through-vias for power transmission, and through-vias for grounding transmission. Metal via 131 may include filled vias in which the through-holes are filled with metal. Metal via 131 may have a cylindrical shape, but may also have an hourglass shape. Multiple metal vias 131 may exist.

[0035] Each of the first connection via 132 and the second connection via 133 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the first connection via 132 and the second connection via 133 may include a seed layer formed by electroless plating (e.g., electroless copper plating) and may include a patterned plating layer formed based on the seed layer by electrolytic plating (e.g., electrolytic copper plating). Each of the first connection via 132 and the second connection via 133 may perform various functions according to design. For example, the first connection via 132 and the second connection via 133 may include connection vias for signal transmission, connection vias for power transmission, and connection vias for grounding transmission. Each of the first connection via 132 and the second connection via 133 may include a filled via in which the via is filled with metal, but may also include a conformal via in which metal is disposed along the wall surface of the via. The first connecting via 132 and the second connecting via 133 may have a shape that gradually tapers in opposite directions. Each of the first connecting via 132 and the second connecting via 133 may be provided in multiples.

[0036] Each of the plurality of first stacked insulating layers 141 and the plurality of second stacked insulating layers 151 may include an organic insulating material. The organic insulating material may include a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by impregnating a thermosetting or thermoplastic resin together with inorganic and / or organic fillers into a core material (such as glass fiber (e.g., glass fabric, exemplified by glass cloth)). For example, the organic insulating material may be a prepreg (PPG), an ajinomoto laminate (ABF), a photosensitive dielectric (PID), etc., but this disclosure is not limited thereto. Each of the plurality of first stacked insulating layers 141 and the plurality of second stacked insulating layers 151 may be formed using multiple layers. In this case, the multiple layers may be integral without boundaries, or the boundaries between the layers may be identifiable. Furthermore, each of the multiple layers may include substantially the same insulating material, but may also include different insulating materials. The plurality of first stacked insulating layers 141 and the plurality of second stacked insulating layers 151 may have the same number of layers, but this disclosure is not limited thereto, and the plurality of first stacked insulating layers 141 may have a relatively larger number of layers.

[0037] Each of the plurality of first stacked wiring layers 142 and the plurality of second stacked wiring layers 152 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the plurality of first stacked wiring layers 142 and the plurality of second stacked wiring layers 152 may include a seed layer formed by electroless plating (e.g., electroless copper plating) and may include a patterned plating layer formed based on the seed layer by electrolytic plating (e.g., electrolytic copper plating). Each of the plurality of first stacked wiring layers 142 and the plurality of second stacked wiring layers 152 may perform various functions according to the design. For example, the plurality of first stacked wiring layers 142 and the plurality of second stacked wiring layers 152 may include signal patterns, power patterns, and ground patterns. Each pattern may have various shapes such as lines, traces, planes, pads, and so on. The plurality of first stacked wiring layers 142 and the plurality of second stacked wiring layers 152 may have the same number of layers, but the plurality of first stacked wiring layers 142 may also have a relatively larger number of layers.

[0038] Each of the first via layer 143 and the second via layer 153 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the first via layer 143 and the second via layer 153 may include a seed layer formed by electroless plating (e.g., electroless copper plating) and may include a patterned plating layer formed based on the seed layer by electrolytic plating (e.g., electrolytic copper plating). Each of the first via layer 143 and the second via layer 153 may perform various functions according to design. For example, the first via layer 143 and the second via layer 153 may include connection vias for signal transmission, connection vias for power transmission, and connection vias for grounding transmission. Each of the plurality of first via layers 143 and the plurality of second via layers 153 may include a filled via in which the via is filled with metal, but may also include a conformal via in which metal is disposed along the wall surface of the via. Each of the plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may include a plurality of connection vias. The connection vias included in each of the plurality of first stacked via layers 143 may have a shape that tapers gradually in the opposite direction to the connection vias included in each of the plurality of second stacked via layers 153. The plurality of first stacked via layers 143 and the plurality of second stacked via layers 153 may have the same number of layers, but the plurality of first stacked via layers 143 may also have a relatively larger number of layers.

[0039] Each of the first passivation layer 161 and the second passivation layer 162 may include an organic insulating material. The organic insulating material may include a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by impregnating a thermosetting or thermoplastic resin together with inorganic and / or organic fillers into a core material (such as glass fiber (e.g., glass fabric, exemplified by glass cloth)). For example, the organic insulating material may be an ajinomoto film (ABF), a photosensitive dielectric (PID), a solder resist (SR), etc., but this disclosure is not limited thereto. Each of the first passivation layer 161 and the second passivation layer 162 may be formed using multiple layers. Each of the first passivation layer 161 and the second passivation layer 162 may have multiple openings, and the pattern exposed through each opening may be of the solder resist-defined (SMD) type and / or the non-solder resist-defined (NSMD) type, but this disclosure is not limited thereto.

[0040] Figure 3 This shows a top-view image obtained by capturing the surface of a glass layer with metal vias formed thereon using an electron microscope.

[0041] Figure 4 It was captured using an electron microscope along... Figure 3 The image shows a portion of the cross-section of the surface of the glass layer with metal vias formed on it, taken by line A-A'.

[0042] Reference Figure 3 and Figure 4The surfaces of the glass layer and the metal via can have specific surface roughness. For example, as described above, the surfaces of the glass layer and the metal via can be formed by laser scraping. In this case, the upper surface of the glass layer and the upper surface of the metal via can have a height difference greater than or equal to 10 μm and less than 100 μm, greater than or equal to 30 μm and less than 90 μm, or greater than or equal to 50 μm and less than 80 μm. For example, during the scraping process, a portion of the upper surface of the glass layer can be removed more than another portion, resulting in a significant height difference exceeding the range of surface roughness (e.g., the aforementioned surface roughness Ra). The height difference between a portion and another portion of the upper surface of the glass layer can exceed the range of the average roughness Ra of the upper surface of the glass layer. In addition, the metal via can have a pad-free structure, and the upper surface of the metal via can protrude more than at least a portion of the upper surface of the glass layer. For example, a structure can be implemented in which the glass layer around the metal via is removed during the scraping process, causing the metal via to protrude. For example, the upper surface of the metal via may protrude beyond at least a portion of the upper surface of the glass layer by the following distances: greater than or equal to 10 μm and less than 100 μm, greater than or equal to 30 μm and less than 90 μm, or greater than or equal to 50 μm and less than 80 μm. The above can be applied not only to the upper surface of the glass layer and the upper surface of the metal via, but also to the lower surface of the glass layer and the lower surface of the metal via. The electron microscope may be a scanning electron microscope (SEM) or a transmission electron microscope (TEM). These techniques can be applied to the printed circuit board 100 according to the above example.

[0043] In this disclosure, the term "cover" can include covering a portion or the entirety of something, and can also include direct and indirect coverage. Furthermore, the term "fill" can include not only complete filling but also partial filling and general filling. For example, the term "fill" can include the presence of some pores or gaps. Additionally, the term "surround" can include not only complete surrounding but also partial surrounding and general surrounding. Furthermore, the term "expose" can include not only complete exposure but also partial exposure, and "expose" can mean that a feature is exposed from the corresponding component that encloses it.

[0044] In this disclosure, in cross-section, "located in a cavity, cavity, through portion, or through hole" can include not only the case where the object is completely located in the cavity, cavity, through portion, or through hole, but also the case where the object protrudes upward or downward. For example, when an object is located in a cavity, cavity, through portion, or through hole on a plane, it can be determined in a broader sense that the object is located in a cavity, cavity, through portion, or through hole.

[0045] In this disclosure, "basically" can be a concept that includes process errors, positional deviations, and measurement errors that may occur during the manufacturing process. For example, substantially the same direction can include not only exactly the same direction, but also substantially the same direction. Furthermore, substantially coplanar can include not only completely coplanar cases, but also substantially coplanar cases. Furthermore, substantially having a specific shape can include not only completely having that shape, but also substantially having that shape. Furthermore, substantially the same insulating material can mean not only completely identical insulating materials, but also cases comprising the same type of insulating material. Therefore, the composition of the insulating materials can be substantially the same, but their specific composition ratios can be slightly different.

[0046] In this disclosure, "section" can mean the shape when an object is cut vertically, or the shape when the object is viewed from a side view. Furthermore, "plane" can mean the shape when an object is cut horizontally, or the shape when the object is viewed from a top or bottom view.

[0047] In this disclosure, for convenience, the term "lower" in "lower side," "lower part," and "lower surface" refers to the downward direction relative to the cross-section of the figures, and the term "upper side," "upper part," and "upper surface" refers to the direction opposite to the downward direction. However, this is defined for ease of explanation, and the scope of the claims is not particularly limited by the description of this direction, and the concepts of upper / lower may be changed at any time.

[0048] In this disclosure, the term "connection" includes not only direct connections but also indirect connections such as those via adhesive layers. Additionally, the term "electrical connection" includes both physical and non-physical connections. Furthermore, expressions such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the claims, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component.

[0049] In this disclosure, thickness, width, length, depth, linewidth, gap, pitch, separation distance, surface roughness, etc., can be measured using a scanning electron microscope, optical microscope, or similar method based on a cross-section of a polished or cut printed circuit board. The cross-section can be vertical or horizontal, and each value can be measured based on the desired cross-section. For example, the width of the upper and / or lower portion of a via can be measured in a cross-section cut along the central axis of the via. In this case, when these values ​​are not constant, they can be determined as the average of values ​​measured at five arbitrary points.

[0050] The term "example embodiment" as used in this disclosure does not imply the same example embodiment, but is provided to explain different features. However, the example embodiments presented above do not preclude implementation in combination with features of other example embodiments. For example, unless there is a description contrary to or contradicting the matters in other example embodiments, even if matters described in a particular example embodiment are not described in other example embodiments, they may be understood as descriptions relating to other example embodiments.

[0051] The terminology used in this disclosure is for the purpose of describing exemplary embodiments only and is not intended to limit the disclosure. In this context, unless they are explicitly stated otherwise in the context, the singular meaning includes the plural meaning.

[0052] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: A glass layer having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface; A through hole penetrates the glass layer between the upper and lower surfaces of the glass layer; as well as Metal via, filling at least a portion of the through hole. Wherein, the surface roughness of at least one of the upper surface and the lower surface of the glass layer is greater than the surface roughness of the side surface of the glass layer, and the surface roughness of at least one of the upper surface and the lower surface of the metal via is greater than the surface roughness of the side surface of the glass layer.

2. The printed circuit board according to claim 1, in, The surface roughness of each of the upper and lower surfaces of the glass layer is greater than the surface roughness of the side surface of the glass layer, and the surface roughness of each of the upper and lower surfaces of the metal via is greater than the surface roughness of the side surface of the glass layer.

3. The printed circuit board according to claim 2, in, The surface roughness of the upper surface of the glass layer is greater than the surface roughness of the upper surface of the metal via, and The surface roughness of the lower surface of the glass layer is greater than the surface roughness of the lower surface of the metal via.

4. The printed circuit board according to claim 2, in, The average roughness Ra of the upper and / or lower surfaces of the glass layer is greater than or equal to 0.1 μm and less than 10 μm, and the average roughness Ra of the upper and / or lower surfaces of the metal via is greater than or equal to 0.1 μm and less than 10 μm.

5. The printed circuit board according to claim 2, in, The average roughness Ra of the side surface of the glass layer is in the range of greater than or equal to 0.001 μm and less than 0.1 μm.

6. The printed circuit board according to claim 1, further comprising: An insulating material covering at least a portion of each of the upper and lower surfaces of the glass layer and the upper and lower surfaces of the metal via; A first wiring layer is disposed on the upper surface of the insulating material; A first connection via penetrates at least a portion of the upper side of the insulating material and directly connects a portion of the first wiring layer to the upper surface of the metal via; A second wiring layer is disposed on the lower surface of the insulating material; as well as The second connection via penetrates at least a portion of the underside of the insulating material and directly connects a portion of the second wiring layer to the underside of the metal via.

7. The printed circuit board according to claim 6, in, The surface roughness of each of the upper and lower surfaces of the glass layer is greater than the surface roughness of each of the upper and lower surfaces of the insulating material, and the surface roughness of each of the upper and lower surfaces of the metal via is greater than the surface roughness of each of the upper and lower surfaces of the insulating material.

8. The printed circuit board according to claim 6, further comprising: The frame has a through section. Wherein, the glass layer is at least partially disposed within the through portion, and The insulating material covers at least a portion of each of the upper and lower surfaces of the frame and fills at least a portion of the space between the frame and the glass layer within the through-hole.

9. The printed circuit board according to claim 6, further comprising: Multiple first stacked insulating layers are disposed on the upper surface of the insulating material; Multiple first stacked wiring layers are respectively disposed on or within the multiple first stacked insulating layers; as well as A plurality of first stacked via layers are respectively disposed within the plurality of first stacked insulating layers and respectively connected to at least one of the plurality of first stacked wiring layers.

10. The printed circuit board according to claim 9, further comprising: Multiple second stacked insulating layers are disposed on the lower surface of the insulating material; Multiple second stacked wiring layers are respectively disposed on or within the multiple second stacked insulating layers; as well as A plurality of second stacked via layers are respectively disposed within the plurality of second stacked insulating layers and respectively connected to at least one of the plurality of second stacked wiring layers.

11. A printed circuit board, comprising: A glass layer having an upper surface and a lower surface, and a side surface connecting the upper surface and the lower surface; A through hole penetrates the glass layer between the upper and lower surfaces of the glass layer; as well as Metal via, filling at least a portion of the through hole. Wherein, the average roughness Ra of the upper surface and / or the lower surface of the glass layer is in the range of greater than or equal to 0.1 μm and less than 10 μm, and the average roughness Ra of the upper surface and / or the lower surface of the metal via is in the range of greater than or equal to 0.1 μm and less than 10 μm.

12. The printed circuit board according to claim 11, in, The average roughness Ra of the upper and / or lower surfaces of the glass layer is in the range of 0.1 μm to 2 μm, and the average roughness Ra of the upper and / or lower surfaces of the metal via is in the range of 0.1 μm to 2 μm.

13. The printed circuit board according to claim 11, in, The height difference between a portion of the upper surface of the glass layer and another portion of the upper surface of the glass layer exceeds the range of the average roughness Ra of the upper surface of the glass layer.

14. The printed circuit board according to claim 11, in, The metal via has a padless structure.

15. The printed circuit board according to claim 14, in, The upper surface of the metal via protrudes more than at least a portion of the upper surface of the glass layer.

16. The printed circuit board of claim 11, further comprising: An insulating material covering at least a portion of each of the upper and lower surfaces of the glass layer and the upper and lower surfaces of the metal via; A first wiring layer is disposed on the upper surface of the insulating material; A first connection via penetrates at least a portion of the upper side of the insulating material and directly connects a portion of the first wiring layer to the upper surface of the metal via; A second wiring layer is disposed on the lower surface of the insulating material; as well as The second connection via penetrates at least a portion of the underside of the insulating material and directly connects a portion of the second wiring layer to the underside of the metal via.

17. The printed circuit board of claim 16, further comprising: The frame has a through section. Wherein, the glass layer is at least partially disposed within the through portion, and The insulating material covers at least a portion of each of the upper and lower surfaces of the frame and fills at least a portion of the space between the frame and the glass layer within the through-hole.

18. A printed circuit board, comprising: A glass layer having a top surface, a bottom surface, and a side surface connecting the top surface and the bottom surface, wherein the surface roughness of the top surface and / or the bottom surface is greater than the surface roughness of the side surface; A through-hole extends through the glass layer between the top surface and the bottom surface; as well as Metal vias, at least partially filling the through-hole. In the cross-sectional view, the distance by which the top surface of the metal via protrudes above the top surface of the glass layer is greater than the surface roughness of the top surface of the glass layer.

19. The printed circuit board according to claim 18, wherein, The surface roughness of the top and / or bottom surface of the metal via is greater than the surface roughness of the side surface of the glass layer and less than the surface roughness of the top and / or bottom surface of the glass layer.

20. The printed circuit board according to claim 18, wherein, In the cross-sectional view, the distance between the top surface of the metal via and the top surface of the glass layer is greater than or equal to 10 μm and less than 100 μm.

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