Component carrier and method for manufacturing same

Abstract

A component carrier (100) comprising: a stack (102) comprising at least one electrically insulating layer structure (104) and at least one electrically conductive layer structure (106); the at least one electrically conductive layer structure (106) comprises at least one trace (108) embedded in the at least one electrically insulating layer structure (104); the at least one trace (108) comprises, in cross section, two side walls (110) inclined inwardly starting from an outer surface (112), and wherein the embedded trace (108) is exposed relative to the at least one electrically insulating layer structure (104); wherein the at least one trace (108) comprises, in cross section, two sharp edges (114) at the outer surface (112) and at least one rounded edge (116) at opposite ends. A method of manufacturing a component carrier (100) is also provided.

Description

Cross-reference to related applications

[0001] This application claims the benefit of European Patent Application No. 24 212 663.9, filed on 13 November 2024, the disclosure of which is incorporated herein by reference. Technical Field

[0002] This application relates to a component carrier and a method for manufacturing the component carrier. Background Technology

[0003] Against the backdrop of the increasing functionality of products equipped with component carriers containing one or more components, the growing miniaturization of such components, and the increasing number of components or component carriers to be connected to component carriers (such as printed circuit boards), increasingly robust array-like components or packages with several components are being adopted. These components or packages have multiple contacts or connections with increasingly smaller spacing between them. In particular, component carriers should be mechanically robust and electrically reliable so that they can operate even under harsh conditions.

[0004] Traditional methods for forming component carriers remain challenging. Summary of the Invention

[0005] It may be necessary to develop a compact and reliable component carrier.

[0006] According to an exemplary embodiment of the present invention, a component carrier is provided, the component carrier comprising: a stack, the stack including at least one electrically insulating layer structure and at least one electrically conductive layer structure; the at least one electrically conductive layer structure including at least one trace embedded in the at least one electrically insulating layer structure; the at least one trace including two sidewalls inclined inward from an outer surface in a cross section (particularly in a cross section perpendicular to the stack thickness direction), wherein the embedded trace is exposed relative to the at least one electrically insulating layer structure; wherein the at least one trace including two sharp edges located at the outer surface and at least one rounded edge located at opposite ends in a cross section.

[0007] According to another exemplary embodiment of the present invention, a method for manufacturing a component carrier is provided, wherein the method includes: forming a stack comprising at least one electrically insulating layer structure and at least one electrically conductive layer structure; forming the at least one electrically conductive layer structure to have at least one trace embedded in the at least one electrically insulating layer structure; configuring the at least one trace such that the at least one trace includes two sidewalls inclined inward from an outer surface in a cross section (particularly in a cross section perpendicular to the stack thickness direction), wherein the embedded trace is exposed relative to the at least one electrically insulating layer structure; and configuring the at least one trace such that the at least one trace includes two sharp edges located at the outer surface and at least one rounded edge located at opposite ends in a cross section.

[0008] In the context of this application, the term "component carrier" may specifically refer to any support structure capable of housing one or more components thereon and / or therein to provide mechanical support and / or electrical and / or thermal connections. In other words, a component carrier can be configured as a mechanical and / or electronic and / or thermal carrier for a component. A component carrier may include laminated stacks, such as laminated layered stacks. Specifically, a component carrier may be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. A component carrier may also be a hybrid board combining the above-described different types of component carriers.

[0009] In the context of this application, the term "stack" may specifically refer to a planar or flat sheet-like body. For example, a stack can be a layered stack, particularly a laminated layered stack or laminate. Such a laminate can be formed by joining multiple layers together by applying mechanical pressure and / or heat. Preferably, the multiple layers are aligned parallel to each other. The stack may include at least one electrically conductive structure and at least one electrically insulating structure.

[0010] In the context of this application, the term "layer structure" may specifically refer to a continuous layer, a patterned layer, or a plurality of discontinuous islands in a common plane, and the layer structure may perform the functions of electrical conduction and / or electrical insulation.

[0011] In the context of this application, the term "trace" may specifically refer to an elongated element of a horizontal conductive layer structure. For example, such an elongated element may be straight, curved, and / or angled. An example of a horizontal trace element is wiring in a horizontal plane. Traces in a conductive layer structure may extend in a horizontal plane. The length of a trace may be at least five times the height and / or width of the trace.

[0012] In the context of this application, the term "sidewall sloping inward from the outer surface, wherein the embedded trace is exposed relative to at least one electrically insulating layer structure" can specifically mean that the opposite sidewall of the trace tapers inward directly from the outer surface, with no vertical section at the outer surface. In particular, the width of the trace may decrease along the thickness of the stack.

[0013] In the context of this application, the term "sharp edge at the exposed outer surface of an embedded trace relative to at least one electrically insulating layer structure" can specifically refer to a discontinuity between the horizontal outer surface of the trace and its corresponding sloping sidewall. In a cross-sectional view, this discontinuity can exist on opposite sides of the trace. For example, in a cross-sectional view, a sharp edge can be seen through the corner between two adjacent dividing lines, one relating to the sloping sidewall and the other to the outer surface. The outer surface can have a horizontal appearance in the cross-sectional view. For example, the angle between the two dividing lines can be an acute angle inside the trace.

[0014] In the context of this application, the term "rounded edge at the end opposite to the exposed outer surface of the embedded trace relative to at least one electrically insulating layer structure" can specifically refer to a curved, continuous end region opposite to a sharp edge. One or more rounded edges may be concave and have no sharp edges.

[0015] In the context of this application, the term "main surface of a body" may specifically refer to one or more of the largest, generally flat surface areas of a body (e.g., a stacked component). Typically, for example, a generally cuboid may have two opposite main surfaces, taking the form of two horizontal surface areas on the top and bottom of the body. Thus, the main surfaces may differ from the sidewalls of the body.

[0016] According to an exemplary embodiment, a component carrier (e.g., a printed circuit board or integrated circuit substrate) includes (preferably laminated) layered stacks having one or more electrically conductive traces embedded in an electrically insulating layer structure of the layered stack. When viewed in a cross-section cut along a vertical plane, the two sidewalls of the trace slope inward directly from the outer surface of the trace, exposing the trace relative to the electrically insulating layer structure in which it is embedded. In the cross-sectional view and at the aforementioned outer surface, the trace has two sharp edges, which are opposite to one or more rounded edges at the ends of the trace opposite to the outer surface. A trace with this geometry can be a fingerprint of the manufacturing process, wherein grooves or recesses can be formed in the electrically insulating layer structure accommodating the trace by laser blasting while the laser scans along the trajectory of the trace. The fingerprint of such laser-formed grooves or recesses can be a rounded profile at the vertical ends of the grooves or recesses, connected by two sidewalls sloping inward (particularly toward the closed bottom of the grooves or recesses). Then, such trenches or recesses can be filled with an electrically conductive material (e.g., copper), for example, by plating. Specifically, several traces that can be formed side-by-side in an electrically insulating layer structure can be simultaneously filled with an electrically conductive material, intentionally in an overfill and overlapping manner, and then the excess or overlapping electrically conductive material is removed to separate the traces, thereby completing the formation of one or more traces. The fingerprint of removing excess or overlapping electrically conductive material to separate the traces can be two sharp edges on the exposed side of the main surface of the corresponding electrically insulating layer structure, because the corresponding removal is along the planar direction (especially by milling, peeling, etc.). This trace manufacturing method and the corresponding trace shape can produce excellent performance in fine line structures because extremely small line spacing ratios can be created in this way. Adjacent traces that are close to each other (especially very close) can be formed first without much consideration for the resulting overlap and / or bridging of the filling conductive structure. The traces can then be separated by a removal step, which is also configured to precisely define the vertical thickness of the trace, the resulting horizontal width, and the corresponding distance between two adjacent traces. This can be achieved by setting the height of the plane removal relative to the bottom end of the trace and / or the distance from the main surface opposite to the corresponding side of the corresponding electrical insulation layer structure that forms the trench. Therefore, these traces may contribute to the ongoing trend of miniaturization of component carrier features.

[0017] Detailed description of exemplary embodiments The following describes further exemplary embodiments of the component carrier and method.

[0018] In embodiments, the ratio between the maximum horizontal width and vertical thickness of at least one trace is in the range of 0.05 to 3, particularly in the range of 0.1 to 1. Specifically, the ratio between the maximum horizontal width and vertical thickness of at least one trace is less than 1. Therefore, traces can be formed with an aspect ratio greater than one or two or more. Greater design flexibility can be achieved by using relevant manufacturing methods, especially for traces with a width less than 5 μm. The above figure may refer to a section perpendicular to the plane direction of the trace at the portion of the section intersecting with the trace.

[0019] In this embodiment, at least one rounded edge is continuously integrated into the two sloping sidewalls. In particular, because the manufacturing method implies the formation of (adjacent) recesses or grooves, discontinuities between the trace and the electrical insulating layer structure can be avoided, except for sharp edges at the interface with the out-of-plane surface. For example, the rounded edge may define a tangential transition with the corresponding sloping sidewall. No edge may be formed at the transition between the rounded edge and the sloping sidewall. Because discontinuities can be avoided, signal transmission (e.g., electrical) can be enhanced and / or signal loss can be avoided.

[0020] In one embodiment, at least a portion of the inclined sidewall extends in a generally straight manner. This generally straight portion may be inclined rather than vertical. This inclined sidewall can attach better to the adjacent electrical insulation layer structure because the inclination of the inclined sidewall expands the surface area of ​​the trace compared to a sidewall extending along the stack thickness direction.

[0021] In some embodiments, the inclined sidewalls have an irregular shape that follows a dominant direction, particularly a straight direction. For example, this irregular shape can be achieved using reinforcing beads or fibers (e.g., glass spheres or fibers) that can be included in the electrically insulating layer structure embedded in the corresponding trace. Alternatively, reinforcing materials that do not contain glass, such as alumina, magnesium oxide, etc., can also be used. When forming the laser trench, the interface between the trench and the electrically insulating layer structure can include corrugations formed at least partially by reinforcing particles that were not removed or not completely removed by laser processing.

[0022] In this embodiment, the maximum horizontal width of the at least one trace is in the range of 0.5 μm to 4 μm, particularly in the range of 1.5 μm and 2.5 μm. Advantageously, the manufacturing architecture and the corresponding trace configuration can be fully compatible with desired fine-line structure requirements. Specifically, the trace pitch ratio L / S can be no greater than 4 μm / 4 μm, preferably no greater than 3 μm / 3 μm.

[0023] As described, the width of the trace can be less than 4 μm, and can be defined as a "small trace" or "small trench". Alternatively, the range can be from 4 μm to 20 μm, and can be defined as a "wide trench" or "wide trace". Therefore, traces constructed as wide trenches are also feasible. In particular, larger embedded traces can be used when the design of the electrically conductive layer structure (e.g., copper traces) can be more flexible (e.g., on the periphery of a component carrier) or when the traces should carry a larger current or dissipate more heat. For example, such wide traces can be created using multiple laser blasts. In a cross-sectional view, this can be seen as Figure 10 The wavy bottom portion of the trace at the bottom dashed line can have a significantly lower oscillation amplitude than the trace 108 shown there. In the example, the small trace can be very close to the wide trace. When a wide trace is present, the trace spacing ratio L / S can be larger than previously mentioned, for example, exceeding 10 μm / 10 μm, such as 20 μm / 20 μm or greater.

[0024] In this embodiment, at least one trace in the cross-section has a diameter of 1 μm. 2 and 25 μm 2 The trace area within the range, especially at 6 μm 2 and 18 μm 2 The area of ​​the trace within the range. Therefore, it is possible to produce tiny traces with precisely defined geometric characteristics, which cover only a very small area. Due to the specific shape imparted during the formation of the recess, especially the specific shape imparted when the recess is formed by a laser beam, the traces formed with the aforementioned "small trace" range produce a suitable cross-sectional area as described above.

[0025] In an embodiment, the sidewalls of the at least one trace are inclined at an angle ranging from 1° to 30° relative to the stack thickness direction, starting from the outer surface, particularly from 5° to 15°. In any case, the sidewalls can extend in a non-vertical manner starting from the outer surface. This can be achieved by creating shapes through trenching, particularly by creating shapes through a laser beam, providing the advantage of ensuring reliable signal transmission and mechanical bonding of the trace to the stack.

[0026] In an embodiment, the roughness Ra of the sidewalls of the at least one trace is different from (e.g., greater than) the roughness Ra of the outer surface of the at least one trace. In the context of this application, the term "roughness" may specifically refer to the average height Ra of the centerline of a surface. Ra is the arithmetic mean of all distances from the centerline to the profile. For example, the measurement or determination of roughness Ra as mentioned in the context of this application can be performed according to DIN EN ISO 4287:2010 (industry standard). These different roughness values ​​may be the result of manufacturing processes during which the sidewalls are defined by laser processing, while the outer surface can be defined by planarization processes (e.g., chemical mechanical polishing (CMP)). More generally, the outer surface can be defined by any removal process, such as etching or grinding, particularly chemical mechanical polishing.

[0027] In an embodiment, the roughness Ra of the outer surface of at least one trace differs from the roughness Ra of the main surface of the at least one electrical insulating layer structure (particularly where the main surface of the trace is exposed). These different roughness values ​​may be a result of different trace materials and different materials of the embedded electrical insulating layer structure. While the electrical insulating layer structure may include reinforcing particles, such as glass beads, which may be exposed to increase surface roughness, the trace may be a metallic (particularly copper) material, and the trace may have a smoother surface.

[0028] In one embodiment, the component carrier includes a plurality of traces arranged side-by-side in at least one electrically insulating layer structure. Advantageously, the plurality of traces can be formed in a common simultaneous process. For example, multiple trenches can be formed side-by-side in the same electrically insulating layer structure by laser processing. Subsequently, the traces can be filled with metal using common plating processes. Thereafter, common removal processes, such as planarization processes (e.g., CMP), can be performed to remove excess metal material, thereby separating the individual traces from each other.

[0029] In this implementation, different traces within the traces have different maximum horizontal widths, and / or different traces have different inclination angles of their sidewalls at the outer surface, and / or different traces have different vertical thicknesses. In particular, adjacent traces may have one or more of these differences. This difference can be generated by individually adjusting the laser processing characteristics of the different traces and / or by different local interactions between the laser and the material to be removed, for example, due to different distributions of filler in the material, especially when the trench is formed by a single laser channel. Therefore, even though the traces have different maximum horizontal widths, different inclination angles of their outer surface sidewalls, and / or different vertical thicknesses, the traces can have reliable mechanical integration and / or electronic signal transmission. Furthermore, the corresponding traces can be easily formed using the same manufacturing process, which can shorten the overall manufacturing time of the component carrier.

[0030] In an implementation, at least one trace is configured as a signal trace, a power trace, or a ground trace. A signal trace may be a trace configured and connected to conduct electrical (e.g., high-frequency) or optical signals during operation of the component carrier. A power trace may be a trace configured and connected to supply power to at least one consumer of the component carrier during operation. A ground trace may be a trace connected to a ground potential or a quality potential, or more generally, a trace connected to a reference potential. This can offer the advantage that multiple traces can be manufactured using the same manufacturing method, where each trace may have different application purposes, thereby simplifying the manufacturing process.

[0031] In an embodiment, the minimum distance from at least one rounded edge of the at least one trace to the main surface of the electrically insulating layer structure opposite to the outer surface is at least 0.8 times (preferably a value in the range of 0.8 to 1.5) the maximum horizontal width of the at least one trace and / or at least 0.8 times the vertical thickness of the at least one trace. Other dimensions are also possible. This may provide the advantage of ensuring reliable electrical signal transmission and the variable extension dimensions of the corresponding traces.

[0032] For example, at least one trace ( Figure 1 (of) at least one rounded edge or ( Figure 23 The minimum distance between the flat portion and the main surface of the electrically insulating layer structure opposite to the outer surface can be at least 1 μm. Preferably, the minimum distance can be in the range of 1 μm to 5 μm. This ensures that short circuits caused by electric arcing will not occur.

[0033] In this implementation, the two embedded traces are offset from each other in a planar view. This offset can be relative to the corresponding geometric dimensions of the different traces, offset according to the arrangement direction of the multiple traces, and / or offset perpendicular to the arrangement direction of the multiple traces, etc. Corresponding manufacturing methods can produce traces that may be offset from each other by a distance of less than 2 μm, particularly less than 800 nm. However, this offset may have a minimal impact on the signal transmission behavior of the traces, thereby ensuring a reliable component carrier in terms of signal quality.

[0034] In this embodiment, two adjacent embedding traces are spaced apart from each other by a center-to-center distance less than 15 μm, particularly less than 5 μm. Therefore, very high integration density can be achieved by applying the manufacturing concept according to the exemplary embodiment. For example, a component carrier may include a center-to-center distance between two adjacent embedding traces in the range of 2 μm to 10 μm, preferably in the range of 3 μm to 6 μm. Alternatively or alternatively, a component carrier may include a center-to-center distance between two adjacent embedding traces in the range of 15 μm to 45 μm (particularly in the case of wide embedding traces).

[0035] In an embodiment, the component carrier includes two components disposed within and / or on the stack, wherein at least one trace is configured to connect the two components. In the context of this application, the term "component" may specifically refer to a device or component, such as one that performs an electronic task. For example, the component may be an electronic component. Such an electronic component may be an active component, such as a semiconductor chip containing semiconductor material, particularly as a primary or base material. For example, the semiconductor material may be a type IV semiconductor, such as silicon or germanium, or a type III-V semiconductor material, such as gallium arsenide. In particular, the semiconductor component may be a semiconductor chip, such as a bare wafer or a molded wafer. At least one integrated circuit element may be monolithically integrated in such a semiconductor chip. However, the component may also be a passive component. Advantageously, one or more traces manufactured as described herein can be used to connect two such surface-mount electronic components arranged side-by-side. Thus, the trace can accomplish, or facilitate, the electrical connection of two such surface-mount electronic components in a simple and compact manner.

[0036] In one embodiment, at least one electrically insulating layer structure with at least one trace embedded does not contain reinforcing fibers. For example, at least one electrically insulating layer structure with at least one trace embedded includes reinforcing beads or no reinforcing particles. When grooves or recesses are formed in an electrically insulating layer structure comprising, for example, glass fibers by laser processing, the laser-cut ends of the reinforcing fibers may extend into the recesses or grooves, potentially significantly increasing the roughness at the interface. This can be problematic, for example, for high-frequency applications where the recesses or grooves are filled with metal. To keep the roughness within reasonable limits, the electrically insulating layer structure can be achieved without reinforcing fibers. In one embodiment, reinforcing beads or spheres can be used instead of reinforcing fibers. This can provide an electrically insulating layer structure with good mechanical stability while avoiding excessive roughness due to the laser-cut reinforcing fibers extending into the laser-cut recesses or grooves. In yet another embodiment, the electrically insulating layer structure may contain no reinforcing particles at all. For example, the electrically insulating layer structure may include a resin such as epoxy resin and optional reinforcing particles, such as beads, which may be made of glass, for example.

[0037] In one embodiment, the stack comprises multiple electrically insulating layer structures, wherein different traces are embedded within different electrically insulating layer structures. Therefore, the process of stacking the layer structures and forming metallic traces within them through laser processing, plating, and planarization can be repeated any number of times until the intended stack is completed. This reduces the overall thickness of the stack because different traces are embedded into correspondingly different electrically insulating layer structures.

[0038] In this embodiment, the different electrically insulating layer structures in the plurality of electrically insulating layer structures are stacked one on top of the other. Therefore, the trace manufacturing architecture according to the exemplary embodiment is compatible with any number of layers.

[0039] In this implementation, different traces embedded in different electrical insulating layer structures within multiple electrical insulating layer structures are electrically coupled to each other. Specifically, a stacked electrical insulating layer structure with embedded overlapping traces possessing the aforementioned characteristics can be formed, and these overlapping traces can be electrically coupled to each other directly or indirectly (e.g., through metal pads, metal pillars, etc. between the traces). This can enhance the local density of the conductive layer structure material, thus enabling the creation of complex designs of vertically interconnected conductive layer structures when multiple electrical insulating layer structures are stacked one on top of the other.

[0040] In one embodiment, the at least one trace has a turning point located between the inclined sidewall and the at least one rounded edge, wherein the curvature of the interface between the at least one trace and the at least one electrical insulating layer structure changes from a right-hand curve to a left-hand curve, particularly at the turning point. In another embodiment, the at least one trace has a turning point located between the inclined sidewall and the sharp edge, wherein the curvature of the interface between the at least one trace and the at least one electrical insulating layer structure (particularly along the thickness direction) changes from the turning point toward the sharp edge. Advantageously, a continuous and smooth transition between the concave and convex curved sections of the trace can be achieved through a specific recess-forming step, particularly by a laser beam. Additionally or alternatively, due to this particular shape of the at least one trace, electronic signals can be transmitted in a way that reduces loss, as the electronic signals are guided through the convex and / or concave sections.

[0041] In an embodiment, the ratio between the horizontal distance from one of the sharp edges to the inflection point and the horizontal distance between the inflection points at the opposite sidewalls is in the range of 0.1 to 0.7, particularly in the range of 0.1 to 0.3. This design can be achieved by forming traces based on laser-generated trenches, then overcoating the trenches, followed by planarization, particularly by chemical mechanical polishing. Additionally or alternatively, this specific shape of the traces can ensure that the traces can transmit power and / or signals.

[0042] In one embodiment, the at least one rounded edge is a common rounded edge of the two sidewalls. This configuration is as follows: Figure 1 As shown. In another embodiment, the at least one rounded edge comprises two rounded edges, for example, the two rounded edges are connected to each other by a flat portion between the two rounded edges. Such a configuration is as follows. Figure 23 As shown. Depending on the processing parameters, particularly during the laser processing used to create the groove, the base for forming the trace obtained after metal filling can be one or another configuration. In one example, for a specific application, such as for electronic signal transmission, a trace having a shape including a common rounded edge for both sidewalls may be preferred. In another example, for a specific application, such as for electronic power transmission, a trace having a shape including two common rounded edges for both sidewalls may be preferred.

[0043] In an embodiment, the method includes forming a first portion of the at least one trace by seed layer deposition. For example, such a seed layer can be formed by chemical plating or sputtering of a metallic material such as copper. Seed layer deposition typically refers to the preparation of a seed layer using chemical processes (so-called chemical processes) and / or physical processes (e.g., physical vapor deposition, particularly sputtering). The presence of a seed layer lining the trench in an electrically insulating layer structure simplifies the subsequent thickening of the metal filler by electroplating.

[0044] In one embodiment, the method includes forming a second portion of the at least one trace by current plating on the first portion. For electroplating or current plating, a pre-formed seed layer lining the inner surface of the trench in the electrically insulating layer structure may be advantageous. The electroplating process can be performed in one or more subsequent electroplating stages until the trench is completely filled with metallic material, and excess metallic material connects adjacent traces into overlapping areas. When the excess material in the overlapping areas is subsequently removed, planarization of the metallic structure is preferably performed, which allows the individual traces to be separated and achieves the aforementioned characteristic geometric trace design with excellent adhesion to the embedded dielectric material.

[0045] In one embodiment, the method includes forming at least two recesses in the at least one electrically insulating layer structure, filling the at least two recesses and the overlapping region between the at least two recesses with an electrically conductive material, and then removing excess portion of the electrically conductive material in the overlapping region to separate the remaining electrically conductive material, thereby obtaining at least two separated traces. In particular, the resulting overlapping region may extend vertically beyond the corresponding main surface of the at least one electrically insulating layer structure. For example, due to the presence of more copper plating in the traces, pits or shallow recesses may exist in the overlapping region, such as... Figure 12 As shown. Preferably, the removal of the excess portion of the electrically conductive material in the overlapping region includes partially removing material from the at least one electrically insulating layer structure, and more preferably reducing the thickness of the at least one electrically insulating layer structure. Due to this process, a planarized surface can be obtained, which is partially formed by the electrically insulating layer structure and partially by embedded traces.

[0046] In one embodiment, the method includes forming at least one recess in the at least one electrically insulating layer structure using a laser beam, and (preferably subsequently) filling the at least one recess with an electrically conductive material to form the at least one trace. For example, a single laser shot may be sufficient to form a recess or trench. In other embodiments, multiple laser shots may be performed. The laser processing may involve a UV (ultraviolet) laser or a laser operating in the visible light range. The laser source may emit a continuous laser beam or may be a pulsed laser source. The pulsed laser may be a picosecond laser, a femtosecond laser, or a nanosecond laser. Preferably, the method includes forming a pulsed laser beam having laser pulses with a duration and / or time distance of no more than 1 ps.

[0047] In one embodiment, the method includes forming at least one recess by moving along the main surface of the at least one electrically insulating layer structure along the trajectory of at least one trace to be formed using only one laser irradiation (or multiple laser irradiations). In one embodiment, the electrically insulating layer structure or panel can remain spatially fixed while the laser source scans the surface. In another embodiment, the electrically insulating layer structure or panel can move to perform the scanning while the laser source remains spatially fixed. This can offer the advantage of simplifying the manufacturing process of embedding traces and / or embedding trenches, thereby accelerating the manufacturing process of component carriers.

[0048] In an embodiment, the component carrier comprises a stack of at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a laminate of one or more electrically insulating layer structures and one or more electrically conductive layer structures, particularly a laminate formed by applying mechanical pressure and / or heat. The stack can provide a plate-like component carrier, which can provide a large mounting surface for other components and is very thin and compact.

[0049] In one embodiment, the component carrier is shaped as a plate. This facilitates a compact design, where the component carrier provides a large base for mounting components. In particular, bare wafers for electronic components, for example, can be surface-mounted onto thin plates such as printed circuit boards.

[0050] In one embodiment, the component carrier is configured as one of a printed circuit board, a substrate (particularly an IC substrate), and an interposer.

[0051] In the context of this application, the term "printed circuit board" (PCB) can specifically refer to a board-shaped component carrier formed by laminating several electrically conductive layer structures with several electrically insulating layer structures, for example, by applying pressure and / or by providing heat. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may include resin and / or glass fiber, i.e., so-called prepreg or FR4 material. Various electrically conductive layer structures can be interconnected in the desired manner by forming vias or any other through-hole connections through holes formed through the laminate (e.g., by laser drilling or mechanical drilling) and partially or completely filled with an electrically conductive material (particularly copper). Filled vias either connect the entire stack (through-hole connections extending through several layers or the entire stack) or connect at least two electrically conductive layers, referred to as vias. Similarly, optical interconnects can be formed through the various layers of the stack to receive electro-optical circuit boards (EOCBs). Printed circuit boards are typically configured to house one or more components on one surface or two opposite surfaces of a board-shaped printed circuit board. Components can be soldered to their respective main surfaces. The dielectric of the PCB can be composed of resin and reinforcing fibers (such as glass fiber).

[0052] In the context of this application, the term "substrate" can specifically refer to a small component carrier, particularly an IC substrate. Compared to a PCB, an IC substrate can be a relatively small component carrier capable of mounting one or more components and can act as a connection medium between one or more chips and another PCB. For example, an IC substrate can have substantially the same dimensions as the components (particularly electronic components) to be mounted thereon (e.g., in the case of a chip-scale package (CSP)). More specifically, an IC substrate can be understood as a carrier for electrical connections or electrical networks, and a component carrier equivalent to a printed circuit board (PCB), but with a much higher density of laterally arranged connectors and / or vertically arranged connectors. For example, lateral connectors are conductive paths, while vertical connectors can be, for example, drilled holes. These lateral and / or vertical connectors can be specifically arranged within the IC substrate and can be used to provide electrical, thermal, and / or mechanical connections for accommodating or not accommodating components (such as bare wafers), particularly IC chips, to printed circuit boards or intermediate printed circuit boards. In the context of this application, "substrate" particularly facilitates electrical connections and / or heat dissipation and / or provides mechanical strength. Therefore, in the context of this application, the term "substrate" is specifically used as a synonym for "IC substrate." It must be noted that the term "substrate" should not be confused with the term "substrate" in the context of wafers, where it is generally used to refer to the substrate material used in wafer fabrication as a base material for constructing devices or circuits and forming a foundational layer supporting the electronic or photonic structures integrated into the wafer. This is not the meaning of "substrate" in the context of this application.

[0053] The substrate or interlayer may include or consist of the following: at least one layer of glass, silicon (Si) and / or photo-imageable or dry-etchable organic material, such as epoxy-based stacked materials (e.g., epoxy-based stacked films) or polymer compounds (which may or may not include photosensitive molecules and / or thermosensitive molecules), such as polyimide or polybenzoxazole.

[0054] In embodiments, the at least one electrically insulating layer structure comprises at least one of the following: resins or polymers such as epoxy resins, cyanate ester resins, benzocyclobutene resins, melamine derivatives, polybenzo[a]methyl methacrylate (PBO), bismaleimide-triazine resins, polyphenylene derivatives (e.g., based on polyphenylene ether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymers (LCP), polytetrafluoroethylene (PTFE), bisbenzocyclobutene (BCB), and / or combinations thereof. Reinforcing structures, such as meshes, fibers, spheres, or other types of filler particles, made of glass (multilayer glass), may also be used to form composite materials. The semi-cured resin combined with a reinforcing agent (e.g., fibers impregnated with the aforementioned resins) is called a prepreg. These prepregs are typically named for their properties, such as FR4 or FR5, describing their flame-retardant characteristics. While prepregs, particularly FR4, are generally preferred for rigid PCBs, other materials may also be used, particularly epoxy-based stacking materials (e.g., stacked films) or photo-imageable dielectric materials. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate resins may be preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low, very low, or ultra-low DK materials can be used as electrical insulation structures in component carriers.

[0055] In embodiments, the at least one electrically conductive layer structure comprises at least one of copper, aluminum, nickel, silver, gold, palladium, tungsten, titanium, and magnesium. While copper is generally preferred, other materials or their coated versions may also be used, particularly those coated with superconducting materials or conductive polymers, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT).

[0056] The at least one component may be selected from at least one of the following: non-conductive inlays, conductive inlays (e.g., metallic inlays, preferably including copper or aluminum), heat transfer units (e.g., heat pipes), light guiding elements (e.g., optical waveguides or optical conductor connectors), electronic components, or combinations thereof. For example, the inlay may be a metal block with or without an insulating material coating (IMS inlay), which can be surface-mounted to facilitate heat dissipation. Suitable materials are defined by their thermal conductivity, which should be at least 2 W / mK. Such materials are typically based on, but not limited to, metals, metal oxides, and / or ceramics, such as copper, alumina (Al₂O₃), or aluminum nitride (AlN). Other geometries with increased surface area are also frequently used to increase heat exchange capacity. In addition, components can be active electronic components (implemented with at least one pn junction), passive electronic components such as resistors, inductors or capacitors, electronic chips, storage devices (such as DRAM or other data memories), filters, integrated circuits (such as field-programmable gate arrays (FPGAs), programmable array logic (PALs), general-purpose array logic (GALs), and complex programmable logic devices (CPLDs)), signal processing components, and power management components (such as field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, and junction field-effect transistors (JFETs). These components, including insulated-gate field-effect transistors (IGFETs), are based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), and / or any other suitable inorganic compound; optoelectronic interface elements; light-emitting diodes; optocouplers; voltage converters (e.g., DC / DC converters or AC / DC converters); encryption components; transmitters and / or receivers; electromechanical transmitters; sensors; actuators; microelectromechanical systems (MEMS); microprocessors; capacitors; resistors; inductors; batteries; switches; cameras; antennas; logic chips; and energy harvesting units. However, other components can be surface-mounted onto component carriers. For example, magnetic elements can be used as components. Such magnetic elements can be permanent magnets (e.g., ferromagnetic, antiferromagnetic, multiferroic, or ferrimagnetic elements, such as ferrite cores) or paramagnetic elements. However, the component can also be an IC substrate, interposer, or other component carrier, such as a board-in-board configuration. This component can be surface-mounted onto a component carrier. In addition, other components may be used as components, especially those that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment.

[0057] In one embodiment, the component carrier is a laminated component carrier. In such an embodiment, the component carrier is a multi-layered composite structure that is stacked and connected together by applying pressure and / or heat.

[0058] After processing the inner layer structure of the component carrier, one or more additional electrically insulating and / or electrically conductive layer structures can be used to symmetrically or asymmetrically cover (especially by lamination) one main surface or two opposite main surfaces of the processed layer structure. In other words, stacking can continue until the desired number of layers is obtained.

[0059] After the stacked components of the electrical insulation layer structure and the electrical conductivity layer structure are formed, the obtained layer structure or component carrier can be surface treated.

[0060] In particular, regarding surface treatment, electrically insulating solder resist can be applied to one or two opposing main surfaces of a layered stack or component carrier. For example, such a solder resist can be formed over the entire main surface, and the solder resist layer can then be patterned to expose one or more electrically conductive surface portions used to electrically couple the component carrier to an electronic periphery. Maintaining the surface portions of the component carrier covered by solder resist effectively prevents oxidation or corrosion, especially on copper-containing surfaces.

[0061] In terms of surface treatment, the exposed electrically conductive surface portions of the component carrier can also be selectively surface-treated. This surface-treated portion can be an electrically conductive covering material on the exposed electrically conductive layer structure (e.g., pads, conductive traces, etc., particularly including or composed of copper) on the surface of the component carrier. If this exposed electrically conductive layer structure is not protected, the exposed electrically conductive component carrier material (especially copper) may oxidize, thereby reducing the reliability of the component carrier. The surface-treated portion can then be formed, for example, as an interface between the surface-mount component and the component carrier. The surface-treated portion functions to protect the exposed electrically conductive layer structure (especially copper circuitry) and enables the connection process with one or more components, such as by soldering. Examples of suitable materials for the surface-treated portion include organic solderable corrosion inhibitors (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), gold (especially hard gold), electroless tin, nickel-gold, nickel-palladium, etc. Attached Figure Description

[0062] The above and other aspects of the invention will become apparent from the examples of embodiments described below, and will be illustrated with reference to these examples of embodiments.

[0063] Figure 1 A cross-sectional view of the traces of a component carrier according to an exemplary embodiment of the present invention is shown.

[0064] Figure 2 A cross-sectional view of a component carrier according to another exemplary embodiment of the present invention is shown.

[0065] Figure 3 A cross-sectional view of a component carrier according to yet another exemplary embodiment of the present invention is shown.

[0066] Figures 4 to 8 An exemplary embodiment of the present invention is shown in the execution of the action against Figure 3 The cross-sectional view of the structure obtained during the manufacturing process of the component carrier shown.

[0067] Figure 9 A cross-sectional image of the traces of a component carrier according to an exemplary embodiment of the present invention is shown.

[0068] Figure 10 A cross-sectional view of a preform of a component carrier trace according to an exemplary embodiment of the present invention is shown.

[0069] Figure 11 Three-dimensional views, cross-sectional views, and plan views of the traces and grooves of a component carrier according to an exemplary embodiment of the present invention are shown.

[0070] Figure 12 and Figure 13 A cross-sectional image of a preform of a component carrier trace according to an exemplary embodiment of the present invention is shown.

[0071] Figure 14 A cross-sectional view of the traces of a component carrier according to an exemplary embodiment of the present invention is shown.

[0072] Figures 15 to 19 A cross-sectional view of the traces of a component carrier according to an exemplary embodiment of the present invention is shown.

[0073] Figure 20 and Figure 21 A cross-sectional image of the trace or preform of the trace of a component carrier according to an exemplary embodiment of the present invention is shown.

[0074] Figure 22 A cross-sectional view of a preform of a component carrier with two traces according to an exemplary embodiment of the present invention is shown.

[0075] Figure 23 A cross-sectional view of the traces of a component carrier according to another exemplary embodiment of the present invention is shown. Detailed Implementation

[0076] The illustrations in the accompanying drawings are schematic. In different drawings, similar or identical elements are given the same reference numerals.

[0077] Before describing the exemplary embodiments in further detail with reference to the accompanying drawings, some basic considerations on which the exemplary embodiments of the present invention are based will be summarized.

[0078] Traditionally, in PCB technology, conductive lines and traces are manufactured using subtractive processes involving etching or additive processes. Both manufacturing concepts involve creating traces on top of previously applied dielectric layers.

[0079] However, traditional additive manufacturing processes require etching the seed layer after plating, which presents several challenges. Firstly, etching is an isotropic process, meaning all features are uniformly etched from all sides, removing not only the bottom seed layer but also the copper material from the sidewalls. This introduces problematic etching factors. Secondly, a traditional drawback is that in many cases, the etching process can create undercuts, resulting in small notches at the bottom of the trace where the seed layer meets the underlying dielectric. These notches can undesirably affect adhesion and mechanical reliability.

[0080] According to an exemplary embodiment, a component carrier (such as an IC substrate or PCB) is provided with a stack of interconnected layer structures, the stack including metal traces embedded in (rather than formed on) an electrically insulating layer structure of the stack, the electrically insulating layer structure being, for example, a resin sheet containing optional reinforcing particles. In a cross-sectional view, at the portion where the trace extends beyond the embedded electrically insulating layer structure, two opposing sidewalls of the trace may be obliquely or inclined inwardly on the outer trace surface. On the same outer surface, two sharp edges of the trace—each edge assigned to one of the opposing sidewalls—may be positioned on a vertical side opposite to (or opposite to) the rounded edges at or near the inner end or tip of the trace. These structural properties of the trace can be obtained by forming a recess in the electrically insulating layer structure through a single laser irradiation of a moving laser beam, the laser beam scanning along the main surface of at least one electrically insulating layer structure according to the extension trajectory of the currently formed trace. After the laser-based trace trajectory is defined, the recesses can be partially or completely filled with an electrically conductive material, such as metal (preferably copper), which can be applied by chemical plating followed by electroplating. Advantageously, the trace manufacturing process can fill multiple juxtaposed trace recesses with an electrically conductive material (e.g., metal), wherein preforms of adjacent traces can be interconnected by excess electrically conductive material in overlapping areas. Subsequently, the spaces can be separated by removing excess electrically conductive material, particularly metal, extending vertically (especially vertically) beyond the trace to be formed, leaving traces with the aforementioned shape. Advantageously, traces formed by this manufacturing process and possessing the aforementioned geometry may be highly suitable for fine-line structure applications requiring high integration density and small line-to-space ratios. Thus, compact component carriers with complex electronic functions can be provided according to exemplary embodiments.

[0081] The formation of the embedded traces can allow for at least some of the oversights of the aforementioned and / or other conventional disadvantages. In particular, the formation of embedded traces can facilitate the desired miniaturization of component carrier features, allow for increased functionality of the component carrier, be compatible with higher integration densities, and be particularly compatible with the formation of smaller features. Advantageously, the line space ratio (L / S) of the component carrier (e.g., PCB or IC substrate) can be advantageously reduced. In particular, embedded trench techniques for forming embedded traces in a substrate or the like can allow for the formation of fine-line structures with a line pitch ratio (L / S) of less than 3 μm. More specifically, this can be achieved by forming the desired overlap between preforms of different traces before removing at least a portion of the overlapping metal material.

[0082] Specifically, exemplary embodiments of the present invention can provide a manufacturing architecture that forms (preferably electrical) conductive traces or lines for a component carrier (such as a PCB or IC substrate) by irradiating a trench or recess with a laser (e.g., using an excimer laser), then plating an electrically conductive trace material, particularly a metallic trace material, in the trench or recess, and performing surface planarization. Thus, (particularly electrical and / or thermal) conductive traces can be embedded in the dielectric material of an electrically insulating layer structure, rather than forming metallic traces on top of the electrically insulating layer structure. During the formation of the trace structure with the desired linear and spatial properties, intentional overlaps may form between preforms of adjacent traces. By removing the overlapping portions of the electrically conductive (e.g., electroplated) plating structure to separate the different traces from each other, highly reliable and miniature traces with very small structural dimensions can be created. By using the intended overlaps to form (particularly electrical and / or thermal) conductive traces embedded in the dielectric material, the adhesion of the electrically conductive material (particularly copper) to the embedded electrically insulating layer structure (particularly resin, optionally including reinforcing particles) can be improved. From a descriptive perspective, better adhesion between the copper trace and the dielectric material can be achieved because, in a cross-sectional view, three sides of the metal trace can adhere to the electrically insulating material, rather than just one side as in conventional methods. Furthermore, according to the exemplary embodiment, seed layer etching may not be required, meaning no interfering undercuts of the trace are produced. Therefore, a smaller L / S value (preferably below 3 μm) can be achieved. In addition, fewer processing stages may be sufficient to fabricate the trace, especially compared to additive lithography. This can reduce manufacturing workload. Moreover, the planarization over-metal removal process, such as chemical mechanical polishing (CMP), can improve the flatness of the stack. This can potentially bring advantageous properties in terms of surface morphology.

[0083] In addition to the advantages associated with miniaturization of the manufactured component carrier, fan-out panel-level package (FO-PLP) devices can be manufactured using the manufacturing architecture according to the exemplary embodiments. Furthermore, ultra-high density fan-out devices and high-performance computing (HPC) devices are also possible.

[0084] Due to the underlying laser process that forms the corresponding grooves and recesses, the fabricated traces can possess characteristic shapes. In particular, characteristic taper portions can be obtained due to the basic Gaussian beam shape. Furthermore, the formation of the desired metallic overlap followed by a surface planarization and material removal process can influence the final shape of the traces.

[0085] According to an exemplary embodiment of the present invention, a component carrier is provided, the component carrier including a stack, the stack including at least one electrically insulating layer structure and at least one electrically conductive layer structure, the at least one electrically conductive layer structure including at least one trace embedded in the at least one electrically insulating layer structure, the at least one trace including a cross section composed of two sidewalls inclined away from the surface exposing the embedded trace, and the two sidewalls being configured to define two sharp edges on the exposed side and a rounded edge at opposite ends.

[0086] In particular, the maximum horizontal width divided by the vertical thickness of the trace can be between 0.05 and 3 (this may correspond to a small trace). For example, rounded edges smoothly merge into two sloping sidewalls. For example, rounded edges define a tangential transition with the corresponding sloping sidewalls. In an embodiment, the transition between the rounded edges and the sloping sidewalls does not create an edge. For example, the sloping sidewalls have (e.g., generally) a straight direction. Alternatively, the sloping sidewalls can have a curved shape. In an embodiment, the sloping sidewalls have an irregular shape along a straight direction (which may be inclined relative to the stacking direction). Alternatively, the sloping sidewalls can have an irregular shape along a curved direction. For example, the maximum horizontal width of the trace is between 0.5 μm and 4 μm, particularly between 1 μm and 3.5 μm. Alternatively, the range can be from 4 μm to 20 μm (which may correspond to a wide trace). In an embodiment, the cross-sectional area of ​​the trace is 1 μm. 2 Up to 25 μm 2 Between, especially at 4 μm 2 Up to 22 μm 2Between. For example, the sidewalls of the trace are inclined at a value between 1° and 30°, particularly between 3° and 20°, relative to the stack thickness direction. For example, the roughness Ra of the sidewalls differs from the roughness Ra of the surface exposed or horizontally extending from the trace. For example, the roughness Ra of the surface exposed or horizontally extending from the trace differs from the roughness Ra of the main surface of at least one electrically insulating layer structure. In particular, traces can be formed by seed layer deposition. In embodiments, several traces can be formed side by side. The traces can have different widths, sidewall inclinations, and trace thicknesses (e.g., a trace can consist of vias (where the length and width may be approximately equal, but the thickness may be significantly different)). For example, these traces can be embodied as signal traces. In particular, the minimum distance from the rounded portion of the trace to the main surface of the electrically insulating layer opposite to the surface exposing the trace can be at least 0.8 times the maximum width or thickness of the trace. For example, two embedded traces are offset from each other in the planar direction. Additionally or alternatively, two embedded traces can be aligned with each other in the planar direction. In one embodiment, the two embedded traces are spaced apart by a distance less than 10 μm, particularly less than 1.5 μm (when considering center-to-center distance). However, the distance between wide traces may be greater. For example, at least one trace may be configured to connect two components disposed in and / or on the component carrier. For example, the electrical insulation layer of the embedded trace has no reinforcing fibers. For example, it is foreseeable that several layer structures constituting a stack may be provided, in which at least two embedded traces may be provided for each corresponding insulation layer structure. In one embodiment, the component carrier further includes an additional electrical insulation layer structure having at least one additional electrically conductive trace embedded or located on the traced layer. In one embodiment, the traces of the additional layer are interconnected with each other.

[0087] According to an exemplary embodiment, the conductive traces of the component carrier can be embedded in the dielectric layer material of the PCB or IC substrate, rather than creating traces on top of the dielectric material. This may improve the adhesion of the trace's metallic material (especially copper) to the dielectric material. It can also create fine lines with a line pitch ratio (L / S) of less than, for example, 3 μm. However, wide traces can have a line pitch ratio (L / S) greater than 20 μm.

[0088] To achieve the above, below, and / or other advantages, the traces can be manufactured according to the following method: First, a dielectric layer (e.g., a resin sheet, such as a pure resin sheet or a resin sheet containing reinforcing particles, such as glass beads or glass fibers, or a photoimageable dielectric) can be laminated onto a stack. Subsequently, trenches can be formed in the dielectric material, with intentional overlap between adjacent trenches. This can be achieved, for example, by forming trenches in the resin sheet using an excimer laser and cleaning it, or by exposing and developing the photoimageable dielectric. In optional subsequent processes, an adhesion promoter can be applied. A metal seed layer plating process, such as chemical plating of copper or other metals, can then be performed. In subsequent processing stages, the metal pattern may be overplated, for example, by electroplating copper or other metals. The excess metal material can then be removed, for example, by performing chemical mechanical polishing (CMP). Advantageously, seed layer etching is not required in this manufacturing process compared to conventional additive trace formation processes. This may result in a reduction in manufacturing effort for the exemplary embodiments.

[0089] The exemplary embodiments of the present invention can have the following advantages: In particular, excellent adhesion can be achieved between the traces (e.g., made of copper) and the dielectric material of the embedded electrical insulating layer structure, because adhesion or bonding effects can be achieved on multiple sides compared to only one side in conventional methods. Advantageously, according to the exemplary embodiments, no seed layer etching is required, thus avoiding undercutting of the traces. Therefore, according to the exemplary embodiments, very small line space ratios L / S can also be created, for example, less than 3 μm. Compared to additive lithography, the manufacturing process according to the exemplary embodiments can involve fewer processing stages, which can further reduce manufacturing workload. Furthermore, improved flatness of the stacked parts can be achieved by performing planarization processes, such as chemical mechanical polishing, to adjust the surface morphology.

[0090] Figure 1 A cross-sectional view of the trace 108 of a component carrier 100 according to an exemplary embodiment of the present invention is shown. For example, component carrier 100 ( Figure 1 (Only a small portion of the component carrier 100 is shown in the image) can be a printed circuit board (PCB) or an integrated circuit (IC) substrate. For example, the trace 108 shown can be configured as a signal trace, power trace, or ground trace within the functional framework of the component carrier 100.

[0091] The illustrated component carrier 100 includes a laminated layered stack 102, which includes one or more electrically insulating layer structures 104 (including 104') and one or more electrically conductive layer structures 106. The layers 104, 106 can be interconnected by lamination, i.e., by applying increased temperature and / or pressure. The electrically insulating layer structure 104 may include resin, particularly epoxy resin, and may include optional reinforcing particles, such as glass beads. More generally, the electrically insulating layer structure 104 may include prepreg sheets, resin sheets, photoimageable dielectric sheets, solder resists or adhesives, and / or glass plates or glass cores. The electrically conductive layer structure 106 may be configured as copper-filled laser vias, patterned metal layers, such as copper foil, and / or deposited copper material. The electrically conductive layer structure 106 can perform various functions, such as vertical transmission of signals and / or electrical energy via vertical through-connections, such as copper pillars or stacked copper-filled laser vias. In addition, the electrical conduction layer structure 106 may include horizontal lines or traces 108 that transmit electrical signals and / or power in a horizontal plane.

[0092] In the following reference Figure 1 The description will focus on the electrically conductive layer structure 106 configured as horizontal traces 108, which is preferably made of copper and embedded in an electrically insulating layer structure 104, which may preferably be, for example, a resin sheet formed on an epoxy resin base. Of course, other materials are also possible.

[0093] Figure 1 The electrically conductive layer structure 106 shown is implemented as a horizontal metal trace 108, which is embedded in a resin-based horizontal layer in the form of an embedded electrically insulating layer structure 104. The horizontal trace 108 extends in an elongated manner perpendicular to... Figure 1 An elliptical wiring structure on a paper plane (not shown). As will be referenced below... Figures 3 to 8 A more detailed description of the trace manufacturing process, Figure 1 The copper trace 108 shown in the cross-sectional view has a characteristic appearance, which will be described below. For example... Figure 1As shown in the cross-section, the trace 108 includes two laterally opposing sidewalls 110 that form the sidewalls of the trace 108. As illustrated, the sidewalls 110 slope inwards from the outer surface 112 of the trace 108, which is aligned with the main surface 199 of the electrically insulating layer structure 104 into which the trace 108 is embedded. Therefore, at the upper outer main surface 199 of the electrically insulating layer structure 104, which is formed at the same vertical height as the upper outer surface 112 of the trace 108, the copper trace 108 begins to slope inwards towards the interior of the electrically insulating layer structure 104, rather than extending only vertically. As shown, the embedded trace 108 is exposed at the outer surface 112 relative to the embedded electrically insulating layer structure 104. This geometric feature of the copper trace 108 is a fingerprint of the copper trace 108 manufacturing process. More specifically, the shape mentioned refers to a fingerprint formed by a laser process performed to create trenches, which are then filled with metal overlapping at least one other trench, and excess metal is removed to separate the metal-filled trenches, forming individual traces 108, as shown. Figure 1 As shown.

[0094] Refer again Figure 1 The cross-section of the trace 108 shown reveals two sharp edges 114 at the interface between the outer surface 112 and the inclined sidewall 110, and a common rounded edge 116 at the opposite end or tip relative to the outer surface 112. More specifically, each of the sharp edges 114 is formed at a corresponding interface between the outer surface 112 and the corresponding sidewall 110. Figure 1 As shown, an acute interior angle α is formed in the trace at the discontinuity between the outer surface 112 and the corresponding sidewall 110. Figure 1 The interior angles of the acute angles on the left and right sides of the trace can be different (e.g., due to the limited precision of the laser process). Unlike forming acute angles, the common rounded edge 116 at the bottom end of the metal trace 108 forms a curved, continuous structure, and constitutes a structure according to... Figure 1 The lower end of the (at least approximately) axially symmetrical section of trace 108. For example... Figure 1 As shown, a single common rounded edge 116 is continuously fused into two inclined sidewalls 110.

[0095] Refer again Figure 1 The trace 108 has a turning point 128 located between the inclined sidewall 110 and the common rounded edge 116. The curvature of the boundary wall or interface 118 between the metal trace 108 and the electrical insulating layer structure 104 varies between a right-hand bend and a left-hand bend at the turning point 128.

[0096] Preferably, the ratio between the maximum horizontal width D of the trace 108 at the outer surface 112 and the vertical thickness L of the metal trace 108 from the outer surface 112 to the common rounded edge 116 can be in the range of 0.1 to 0.5. For example, the maximum horizontal width D of the copper trace 108 can be in the range of 1.5 μm to 2.5 μm. In the cross-section shown, the copper trace 108 has a trace area portion A, which is preferably 6 μm. 2 Up to 18 μm 2 Within the range. Although a section of the inclined sidewall 110 is based on Figure 1 It extends in a generally straight manner, but other segments of the inclined sidewall 110 may be curved accordingly in a concave or convex form. As shown, the sidewall 110 of the copper trace 108 is inclined at an angle β relative to the vertical stacking thickness direction 138 from the outer surface 112, and the angle β is preferably in the range of 5° to 15°. Figure 1 The tilt angle β on the left and right sides can be different (e.g., due to the limited precision of the laser process). In other words, the angle β between the vertical stacking thickness direction 138 and the tangent on the outer surface of the trace 108 can be within the stated angle range. Both the acute trace interior angle α and the tilt angle β can have the same corner point in the form of a sharp edge 114. Also... Figure 1 As shown, the minimum vertical distance F from the rounded edge 116 of trace 108 to the main surface 198 of the adjacent electrically insulating layer structure 104' opposite to the outer surface 112 can be 0.8 times the maximum horizontal width D of trace 108, and / or the minimum vertical distance F can be at least 0.8 times the vertical thickness L of trace 108. Alternatively, the minimum vertical distance F from the rounded edge 116 of trace 108 to the main surface 198 of the adjacent electrically insulating layer structure 104' opposite to the outer surface 112 can be at least 0.6 times the maximum horizontal width D of trace 108, and / or the minimum vertical distance F can be at least 0.6 times the vertical thickness L of trace 108. The ratio between the horizontal distance B from the corresponding sharp edge 114 to the turning point 128 and the horizontal distance C between the turning points 128 at the opposite sidewall 110 can preferably be in the range of 0.1 to 0.3. Alternatively, the ratio between the horizontal distance B from the corresponding sharp edge 114 to the turning point 128 and the horizontal distance C between the turning point 128 at the opposite sidewall 110 can preferably be less than 0.45.

[0097] Furthermore, the roughness Ra of the sidewall 110 of the trace 108 may differ from the roughness Ra of the outer surface 112 of the trace 108. In particular, the roughness Ra of the sidewall 110 of the trace 108 may be greater than the roughness Ra of the outer surface 112 of the trace 108. This may be a result of the manufacturing process during which the sidewall 110 of the trace 108 may be defined by a laser process (particularly by an excimer laser process), while the planar outer surface 112 may be defined by a planarization process (particularly CMP). Additionally, the roughness Ra of the outer surface 112 of the trace 108 may differ from (e.g., be less than) the roughness Ra of the connecting portion of the main surface 199 of the embedded electrical insulating layer structure 104, wherein the outer surface 112 and the main surface 199 may be at the same vertical level and aligned with each other.

[0098] Preferably, the electrically insulating layer structure 104 embedded therein in the trace 108 may not contain reinforcing glass fibers. For example, the trace 108 may include reinforcing glass beads or reinforcing beads 124, such as... Figure 1 As shown in detail 160, the absence of glass fibers ensures that trace 108 can provide relatively smooth walls. This can be advantageous, especially for high-frequency references when high-frequency signals propagate along trace 108. With relatively smooth walls, trace 108 promotes low signal distortion by suppressing signal loss, according to the so-called skin effect, where current flows at high frequencies only along or at least primarily along a thin skin at the outer surface of trace 108. For this purpose, detail 160 indicates that the electrically insulating layer structure 104 into which trace 108 is embedded includes, for example, spherical reinforcing beads 124. Alternatively, the electrically insulating layer structure 104 may be completely free of reinforcing particles, for example, it may be a pure resin sheet, optionally with additives. Optionally, the spherical reinforcing beads 124 may be in direct contact with trace 108, particularly with the sidewalls 110 of trace 108. This can result in better adhesion between trace 108 and the electrically insulating layer structure 104.

[0099] Although not shown, the stacked component 102 may also include a plurality of vertically stacked electrical insulating layer structures 104, wherein different traces 108 are embedded in different electrical insulating layer structures of the plurality of electrical insulating layer structures 104. The different traces 108 embedded in the different electrical insulating layer structures of the plurality of electrical insulating layer structures 104 can be electrically coupled to each other, for example, through vertically penetrating metal connections (such as copper pillars or copper vias). Figure 1 Not shown in the image.

[0100] Figure 2 A cross-sectional view of a component carrier 100 according to another exemplary embodiment of the present invention is shown.

[0101] according to Figure 2The component carrier 100 includes a laminated layered stack 102, which includes an electrically insulating layer structure 104 and an electrically conductive layer structure 106. The electrically conductive layer structure 106 includes an embedded trench 162, which may be completely filled with metal, particularly copper. The trench 162 can be electrically coupled to the ends 164 of two surface-mounted electronic components 120, 122. For example, the electronic components 120, 122 may be semiconductor wafers. The metal ends 164 of the electronic components 120, 122 can be electrically coupled to the embedded trench 162 via an electrically conductive connection medium (not shown) between the metal ends 164 and the embedded trench 162, such as solder, sintering material, and / or electrically conductive adhesive. As shown, the electronic components 120, 122 can be electrically coupled or connected via the ends 164 and the trench 162. Alternatively, two components 120, 122 disposed on the stack 102 may be electrically coupled to each other via one or more traces 108, wherein the one or more traces 108 may be arranged, for example, according to Figure 1 or Figure 23 The construction is shown. This allows for a compact design of the component carrier 100. Figure 2 The diagram also shows the ends 164 of components 120, 122 further connected in the surface portion of the stack 102 by an additional electrically conductive layer structure 106.

[0102] End 164 can be the connection end of corresponding components 120, 122. Reference numeral 162 can indicate an embedded groove. Components 120, 122 can be connected by one or more embedded grooves 162 at different vertical levels.

[0103] The corresponding components 120, 122 can be embedded in the trace 108 and the connecting portion below (e.g., through corresponding through holes, vias, etc., not shown, or through the trace 108 itself, such as...). Figure 3 The left trace 108 shown connects to other (especially the lower) conductive layer structures.

[0104] Figure 3 A cross-sectional view of a component carrier 100 according to yet another exemplary embodiment of the present invention is shown.

[0105] exist Figure 3In one embodiment, the component carrier 100 has a laminated layered stack 102, which includes a plurality of stacked electrical insulating layer structures 104. Each electrical insulating layer structure 104 has an electrically conductive layer structure 106 embedded within it, and / or the electrical insulating layer structure 104 has electrically conductive layer structures 106 disposed between and / or within the electrical insulating layer structures 104. In the uppermost electrical insulating layer structure 104, a plurality of metal traces 108 are embedded side-by-side. It should be noted that the cross-sectional shape of the metal traces 108 is only schematically shown. Figure 3 In China (and correspondingly in Figures 4 to 8 (in the middle), and when obtained from a real manufacturing process, the cross-sectional shape of the metal trace 108 can have, for example, Figure 1 or Figure 23 The appearance shown.

[0106] As shown, Figure 3 All traces 108 extend from the upper main surface 199 of the uppermost electrical insulating layer structure 104 for embedding, such that the outer surface 112 of the traces 108 is aligned with the upper main surface 199 of the electrical insulating layer structure 104 and is at the same vertical level. However, different traces 108 may have different maximum horizontal widths D, different tilt angles β of the sidewalls 110 at the outer surface 112, different vertical thicknesses L, etc. (see reference). Figure 1 For example, these different geometries of the different traces 108 can be adjusted by varying the processing parameters during the formation of the grooves for the base of the traces 108 by laser processing. The different embedded traces 108 can also be misaligned in a plan view. Alternatively, the different embedded traces 108 can be aligned. (See also...) Figure 3 Two adjacent embedded traces 108 can be configured to be spaced apart from each other by a center-to-center distance T. For example, the center-to-center distance T can be less than 5 μm.

[0107] like Figure 3 The document also indicates that each trace in trace 108 may consist of a first portion 130 and a second portion 132. The first portion 130 serves as a liner for a trench formed as the base for manufacturing the metal trace 108. The second portion 132 lies on the first portion 130 and fills the main portion of the trench with an electrically conductive material, particularly a metallic material such as copper. For example, after forming the trench, the first portion 130 may be applied as a seed layer by chemical plating, and then the second portion 132 may be formed on the first portion 130 by electroplating. The trace 108 may be in contact with the electrically conductive layer structure on its bottom side. Figure 3(The left-side groove in the image). Furthermore, trace 108 can have an elongated shape (unlike a standard laser via).

[0108] Figures 4 to 8 An exemplary embodiment of the present invention is shown in the execution of the action against Figure 3 A cross-sectional view of the structure obtained during the manufacturing process of the component carrier 100 shown.

[0109] refer to Figure 4 The diagram shows a flat, layered stack 102, which consists of alternating sequences of electrically insulating layer structures 104 and electrically conductive layer structures 106. The stack 102 can be formed by lamination, i.e., by applying increased temperature and / or increased mechanical pressure.

[0110] More specifically, the stack 102 can be formed, for example, as a substrate, such as a copper-clad laminate (CCL) having a full copper layer or a structured copper layer on both sides of the dielectric core. The dielectric layer can be applied to one side of the copper-clad laminate. For example, such a dielectric layer or the uppermost electrically insulating layer structure 104 can be realized as a resin sheet, a non-photographic imaging stacking material composed of organic materials and nanoscale inorganic fillers, etc.

[0111] refer to Figure 5 Multiple trenches or recesses 134 can be formed in the uppermost electrically insulating layer structure 104 using a laser beam (not shown). More specifically, each trench-shaped recess 134 can be formed by a single laser irradiation, provided by a laser source that moves along the main surface 199 of the uppermost electrically insulating layer structure 104 according to the trajectory of the corresponding trace 108 to be formed. Figure 5 As shown, different trenches (extending to) Figure 5 In the plane of the paper (not shown), the recess 134 may have different or the same cross-sectional area, width, and depth. These different parameters can be adjusted by changing the laser processing parameters used to form the corresponding recess 134 in different ways.

[0112] More specifically, trenches and vias can be formed in the dielectric layer using a laser source (which can have any suitable wavelength, such as an excimer laser emitting a 305 nm wavelength laser). This can be achieved in any desired design combination, such as one or two laser steps using, for example, a direct laser or an excimer laser mask. The laser processing can form the basis for the desired overlap of linear and spatial structures, see reference. Figure 8 .

[0113] refer to Figure 6 ,according to Figure 5The resulting structure can undergo a cleaning process, such as for removing laser residue. Optionally, an adhesion-promoting layer 168 may also be formed in the recess 134.

[0114] Therefore, the laser-treated substrate can then be cleaned, for example, by a wet or dry cleaning process, to remove laser residue.

[0115] refer to Figure 7 Then, a first portion 130 of the metal trace 108 can be formed by seed layer deposition in the trench or recess 134. The first portion 130 may be a thin copper layer that lays a liner on the exposed surface portions of the layer structures 104, 106 located in the trench or recess 134 and on the main surface 199.

[0116] Therefore, the copper seed layer can be applied as the first part 130, for example by chemical plating or PVD (physical vapor deposition), especially by sputtering or chemical vapor deposition.

[0117] refer to Figure 8 The second portion 132 of the trace 108 can be formed on the first portion 130 by electroplating with an additional metallic material. Therefore, each trench or recess 134 can be completely filled with a bulk electrically conductive material, such as copper, to form the trace 108. However, each of the trenches or recesses 134 may be overfilled or excessively filled with metal. This overfilling may result in the formation of a metal overlap region 136 on the trench or recess 134 and between adjacent trenches or recesses. The second portion 130 and the overlap region 136 can be formed by electroplating or electroplating and can include a metal such as copper. Therefore, it is possible to obtain... Figure 8 The structure is shown. For this purpose, trench and via structures can be filled with copper overplating (e.g., electrolytic copper). For example, also in Figure 8 In the process, because more copper is plated in the traces, pits or shallow depressions may exist in the overlapping areas, such as... Figure 12 As shown.

[0118] In order to be based on Figure 8 The structure shown is obtained according to Figure 3 The component carrier 100 can also remove excess portions of the electrically conductive material in the overlapping region 136, thereby separating the remaining electrically conductive material to obtain individual traces 108. For this purpose, planarization processes, such as CMP (chemical mechanical polishing), can be applied to remove excess copper and dielectric material from the top surface. Through planarization, the metal of structures 130, 132, and 136 and the dielectric material of the electrically insulating layer structure 104 can be removed.

[0119] Therefore, the electrically conductive layer structure 106 has a metal trace 108 embedded in the surface portion of the uppermost electrically insulating layer structure 104, such as... Figure 3 As shown. Now, referring to... Figure 1 or Figure 23 Each of the traces 108 can be formed such that: the trace 108 includes two sidewalls 110 that slope inward from the outer surface 112 in cross-section, and each embedded trace 108 is exposed relative to the uppermost electrical insulating layer structure 104. Furthermore, each of the traces 108 can be configured such that the trace includes two sharp edges 114 located at the outer surface 112 and one or two rounded edges 116 at two opposite ends in cross-section. As described above, these features in... Figures 3 to 8 It is not visible in the schematic diagram.

[0120] Subsequently, from the dielectric application to the completion of the formation of the trace 108 for the next layer, the process can be repeatedly referenced. Figures 3 to 8 The process described. This can continue until the required stacking is complete.

[0121] Figure 9 A cross-sectional image of the trace 108 of a component carrier 100 according to an exemplary embodiment of the present invention is shown. Figure 9 As shown, according to an exemplary embodiment, a trace 108 with a very small horizontal width in the range of 3 μm to 4 μm can be obtained by a manufacturing process.

[0122] Figure 10 A cross-sectional view of a preform of the trace 108 of a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0123] More specifically, Figure 10 The diagram shows multiple traces 108 that remain integrally connected, wherein the interconnection of the traces 108 is completed by overlapping regions 136, as referenced above. Figure 8 As stated above. Based on Figure 10 The structure shown can be planarized using processes such as CMP to remove material from the overlapping regions 136 and the surface material of the uppermost electrical insulating layer structure 104, thereby separating the individual trenches 108 and forming the structure as shown in the reference above. Figure 1 The geometry of the aforementioned trace.

[0124] Figure 10 Several feature dimensions are indicated in the text.

[0125] Figure 11A three-dimensional view 200, a cross-sectional view 202, and a plan view 204 are shown of a trace 108 and a (copper-filled) embedding trench 162 of a component carrier 100 according to an exemplary embodiment of the present invention. The trace 108 and the embedding trench 162 may be made of an electrically conductive material and may be interconnected. The trace 108 may extend vertically, while the embedding trench 162 may extend horizontally. Figure 11 Plan view 204 shows a wide groove 162 with reference numeral 206 and a narrow or small groove 162 with reference numeral 208. When the groove 162 is formed and a laser is applied to the same location for a longer period of time, a connection with the underlying layer can be formed. Therefore, lateral protrusions 210 in the corresponding groove 162 can be seen in plan view 204. Due to the laser process, the vertical connection in the form of the trace 108 can have a tapered shape.

[0126] Figure 12 and Figure 13 A cross-sectional image of a preform of the trace 108 of a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0127] refer to Figure 12 This shows an overview of several still integrally connected traces 108 of the preform of the component carrier 100, where the connection is completed by overlapping areas 136. Figure 12 In this embodiment, because more copper is plated in the traces, pits or shallow recesses exist in the overlapping areas. Therefore, pits may be generated because more copper is plated in the recesses rather than in the remaining areas.

[0128] refer to Figure 13 This shows a further enlarged view.

[0129] Figure 14 A cross-sectional view of the trace 108 of a component carrier 100 according to an exemplary embodiment of the present invention is shown. Compared with other cross-sectional views (xz views) showing the width of the trace 108, in Figure 14 In the diagram, the cross-sectional view is a yz view. The xz and yz views are shown below. Figure 13 and Figure 14 As shown. Therefore, the length of an embedded trench 162 (especially copper-filled) is as follows Figure 14 As shown. The vertical depth can be adjusted by changing the laser parameters. Compared to the right side, the left side of trench 162 is deeper, so the copper filling trench 162 has a larger cross-section. On the right side, the trench depth is not as deep. In this way, the geometry of the copper trench 162 can be changed and adjusted very easily. Figure 14 A trench 162 is shown embedded in the electrical insulation layer structure 104 before the removal of the overlapping region 136.

[0130] Figures 15 to 19 A cross-sectional view of the trace 108 of a component carrier 100 according to an exemplary embodiment of the present invention is shown. Figures 15 to 19 The geometry of trace 108 is shown only schematically. In practice, trace 108 can have, for example, the geometry of trace 108. Figure 1 or Figure 23 The geometry shown.

[0131] refer to Figure 15 The diagram shows vertically stacked traces 108, which may also be connected to pads 170. Such pads 170 or traces 108 may also be inserted into cavities 172 formed within the layered stack 102. Preferably, the cavities 172 are created using a laser process similar to that used to create trenches (e.g., the wide trenches described above). However, the trenches are not completely filled with copper. In this example, the copper traces, created, for example, by an additive process (e.g., modified semi-additive processing, mSAP), are entirely within the cavities 172.

[0132] refer to Figure 16 Vertically stacked traces 108 can be provided together with side-by-side traces 108. Figure 16 A stack 102 is shown having two vertically stacked electrical insulating layer structures 104. In one electrical insulating layer structure 104, an embedded trace 108 may be located in the bottom layer. The top electrical insulating layer structure 104 may be attached to an electrical conductive layer structure 106, in which case the electrical conductive layer structure 106 is a copper pad, exposed on a main surface of the stack 102 and / or protruding outward from the stack 102. Optionally, the copper pad and the embedded trace 108 may be connected via vertical interconnects.

[0133] refer to Figure 17 The two traces 108 are vertically stacked. The stack 102 includes two electrically insulating layer structures 104 stacked vertically. The two electrically insulating layer structures 104 may include embedded traces 108. In one option, the traces 108 may be vertically aligned with each other (left side). In another option, the traces 108 in each layer may be laterally shifted (right side). This provides the possibility of considering the impedance of the traces 108 during the design of the stack 102, thereby optimizing the position of the embedded traces 108 with low loss through crosstalk.

[0134] refer to Figure 18The trace 108 according to the exemplary embodiment can be combined with a pad 174 formed on top of the electrically insulating layer structure 104. The stack 102 includes an electrically insulating layer structure 104 having an electrically conductive layer structure 106 internally therein, the electrically conductive layer structure 106 being created by an additive process (e.g., mSAP, the bottom electrically conductive layer structure shown as reference numeral 174 in the figures) on the bottom side of the electrically insulating layer structure 104. Within the same electrically insulating layer structure 104, the embedded trace 108 can be located on the opposite top side. Both the trace 108 and the trench are located within the layer structure 104. In one option, the trace 108 and the electrically conductive layer structure 174 can be vertically aligned (left trace 108). In another option, the trace and trench can be laterally displaced (right trace 108). In this example, the trace 108 can have a different function compared to the electrically conductive layer structure 174. Trace 108 can have a grounding function, and conductive layer structure 174 can have a signaling function. Alternatively, conductive layer structure 174 can have a power function, and trace 108 can have a signaling function. This may have the advantage of having a higher copper density within an electrically insulating layer structure 104 (which has two functions internally).

[0135] refer to Figure 19 The diagram illustrates exemplary dimensions of traces 108 and their mutual distances according to an exemplary embodiment. From... Figure 19 It can be seen that a very small line space L / S ratio can be obtained, for example, no more than 4 μm or less.

[0136] Figure 20 A cross-sectional image of the trace 108 of the component carrier 100 or a preform of the trace 108 according to an exemplary embodiment of the present invention is shown. (Reference) Figure 20 The left side shows a preform of the component carrier 100 with traces 108, which are still integrally connected by overlapping regions 136. The vertical line 176 in this image represents a vertical height achievable by planarization processes (e.g., chemical mechanical polishing) to remove metal and dielectric material from the top region of the layered stack 102, thereby obtaining... Figure 20 The single trace 108 shown on the right.

[0137] refer to Figure 21 This shows a practical example of the stack 102 manufactured before the overlapping region 136 is removed and thus before the individual traces 108 are separated. Figure 21 A three-dimensional image is shown. Figure 21 In the image, we can see the seed layer before the trench is completely filled with an electrically conductive material; in this example, it is a sputtered metal layer.

[0138] Figure 22A cross-sectional view of a preform of two traces 108 of a component carrier 100 according to an exemplary embodiment of the present invention is shown. The material can be removed by chemical mechanical polishing. Figure 22 The upper surface portion of the stacked parts 102 is used to separate the individual traces 108.

[0139] Figure 23 A cross-sectional view of the trace 108 of a component carrier 100 according to another exemplary embodiment of the present invention is shown. Specifically, Figure 23 Implementation methods and basis Figure 1 The difference in the implementation method is that, according to Figure 23 Two rounded edges 116 are provided, and these rounded edges 116 are interconnected by a flat portion 150. Therefore, according to Figure 23 It has two rounded edges 116, instead of... Figure 1 A common rounded edge 116 is shown. The shape of the trace 108 having one or two rounded edges 116 can be adjusted by setting manufacturing parameters accordingly, such as parameters for the laser process for defining the trench and the plating process for filling the trench with a metallic material.

[0140] It should be noted that the term "comprising" does not exclude other elements or steps, and "a" or "the" does not exclude a plural. Furthermore, elements described in connection with different embodiments may be combined.

[0141] It should also be noted that the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

[0142] The present invention is not limited to the preferred embodiments shown in the figures and described above. On the contrary, even in fundamentally different embodiments, it is possible to use the illustrated solutions and various variations based on the principles of the present invention.

Claims

1. A component carrier (100), the component carrier (100) comprising: The stack (102) includes at least one electrically insulating layer structure (104) and at least one electrically conductive layer structure (106). The at least one electrically conductive layer structure (106) includes at least one trace (108) embedded in the at least one electrically insulating layer structure (104). The at least one trace (108) includes two sidewalls (110) in the cross section that slope inward from the outer surface (112), wherein the embedded trace (108) is exposed relative to the at least one electrical insulating layer structure (104); The at least one trace (108) includes, in cross section, two sharp edges (114) located at the outer surface (112) and at least one rounded edge (116) located at the opposite end portion.

2. The component carrier (100) according to claim 1, wherein, The ratio between the maximum horizontal width (D) and the vertical thickness (L) of the at least one trace (108) is in the range of 0.05 to 1, for example, the ratio between the maximum horizontal width (D) and the vertical thickness (L) of the at least one trace (108) is in the range of 0.1 to 0.

5.

3. The component carrier (100) according to claim 1, wherein, The at least one rounded edge (116) is continuously fused into the two inclined sidewalls (110).

4. The component carrier (100) according to claim 1, wherein, At least a portion of the sloping sidewall (110) extends in a generally straight manner.

5. The component carrier (100) according to claim 1, wherein, The maximum horizontal width (D) of the at least one trace (108) is in the range of 0.5 μm to 4 μm, for example, the maximum horizontal width (D) of the at least one trace (108) is in the range of 1.5 μm to 2.5 μm.

6. The component carrier (100) according to claim 1, wherein, The at least one trace (108) has a cross-section with a diameter of 3 μm. 2 Up to 25 μm 2 The trace area portion (A) within the range, for example, the at least one trace (108) has a cross-section with a diameter of 6 μm. 2 Up to 18 μm 2 The area of ​​the trace within the range (A).

7. The component carrier (100) according to claim 1, wherein, The sidewall (110) of the at least one trace (108) is inclined at an angle (β) between 1° and 30° relative to the stacking thickness direction (138) starting from the outer surface (112). In particular, the sidewall (110) of the at least one trace (108) is inclined at an angle (β) between 5° and 15° relative to the stacking thickness direction (138) starting from the outer surface (112).

8. The component carrier (100) according to claim 1, wherein, The roughness Ra of the sidewall (110) of the at least one trace (108) is different from the roughness Ra of the outer surface (112) of the at least one trace (108).

9. The component carrier (100) according to claim 1, wherein, The roughness Ra of the outer surface (112) of the at least one trace (108) is different from the roughness Ra of the main surface of the at least one electrical insulating layer structure (104).

10. The component carrier (100) according to claim 1, wherein, The component carrier (100) includes a plurality of traces (108) arranged side by side in the at least one electrical insulating layer structure (104).

11. The component carrier (100) according to claim 10, wherein, Different traces in the traces (108) have different maximum horizontal widths (D), different traces in the traces (108) have different tilt angles (β) of the sidewall (110) at the outer surface (112), and / or, different traces in the traces (108) have different vertical thicknesses (L).

12. The component carrier (100) according to claim 1, wherein, The minimum distance (F) between at least one rounded edge (116) of the at least one trace (108) and the main surface of the electrical insulating layer structure (104') opposite to the outer surface (112) is at least 0.8 times the maximum horizontal width (D) of the at least one trace (108) and / or at least 0.8 times the vertical thickness (L) of the at least one trace (108).

13. The component carrier (100) according to claim 1, wherein, The two embedded traces (108) are offset from each other when viewed along the plan view.

14. The component carrier (100) according to claim 1, wherein, Two adjacent embedded traces (108) are configured to be spaced apart from each other by a center-to-center distance (T), wherein the center-to-center distance (T) is less than 15 μm, for example, the center-to-center distance (T) is less than 5 μm.

15. The component carrier (100) according to claim 1, the component carrier (100) comprising two components (120, 122) disposed in and / or on the stack (102), wherein at least two traces (108) are configured to bridge the two components (120, 122).

16. The component carrier (100) according to claim 1, wherein, The at least one electrically insulating layer structure (104) in which the at least one trace (108) is embedded does not contain reinforcing fibers.

17. The component carrier (100) according to claim 1, wherein, The at least one electrical insulating layer structure (104) embedded with the at least one trace (108) includes reinforcing beads (124) or does not contain reinforcing particles.

18. The component carrier (100) according to claim 1, wherein, The stack (102) includes a plurality of electrically insulating layer structures (104), wherein different traces (108) are embedded in different electrically insulating layer structures in the plurality of electrically insulating layer structures (104).

19. The component carrier (100) according to claim 18, wherein, The different traces (108) embedded in the different electrical insulation layer structures (104) are electrically coupled to each other.

20. The component carrier (100) according to claim 1, wherein, The at least one trace (108) has a turning point (128) located between the inclined sidewall (110) and the at least one rounded edge (116), wherein the bend of the interface (118) between the at least one trace (108) and the at least one electrical insulating layer structure (104) changes from a right bend to a left bend.

21. The component carrier (100) according to claim 1, wherein, The at least one trace (108) has a turning point (128) located between the inclined sidewall (110) and the sharp edge (114), wherein the curvature of the interface (118) between the at least one trace (108) and the at least one electrical insulating layer structure (104) changes from the turning point (128) toward the sharp edge (114).

22. The component carrier (100) according to claim 20, wherein, The ratio between the horizontal distance (B) from one of the sharp edges (114) to the turning point (128) and the horizontal distance (C) from the turning point (128) at the opposite two sidewalls (110) is in the range of 0.1 to 0.

7. For example, the ratio between the horizontal distance (B) from one of the sharp edges (114) to the turning point (128) and the horizontal distance (C) from the turning point (128) at the opposite two sidewalls (110) is in the range of 0.1 to 0.

3.

23. A method for manufacturing a component carrier (100), wherein, The method includes: A stack (102) is formed, the stack (102) including at least one electrically insulating layer structure (104) and at least one electrically conductive layer structure (106). The at least one electrically conductive layer structure (106) is formed with at least one trace (108) embedded in the at least one electrically insulating layer structure (104). The at least one trace (108) is configured such that the at least one trace (108) includes two sidewalls (110) in cross-section that slope inward from the outer surface (112), wherein the embedded trace (108) is exposed relative to the at least one electrically insulating layer structure (104); and The at least one trace (108) is configured such that the at least one trace (108) includes, in cross section, two sharp edges (114) located at the outer surface (112) and at least one rounded edge (116) located at the opposite end portion.

24. The method according to claim 23, wherein, The method includes forming a first portion (130) of the at least one trace (108) by seed layer deposition or sputter deposition.

25. The method according to claim 23, wherein, The method includes: At least two recesses (134) are formed in the at least one electrically insulating layer structure (104). The at least two recesses (134) and the overlapping area (136) between the at least two recesses (134) are filled with an electrically conductive material; and The excess portion of the electrically conductive material in the overlapping region (136) is then removed, thereby separating the remaining electrically conductive material to obtain at least two separate traces (108).

26. The method according to claim 23, wherein, The method includes: At least one recess (134) is formed in the at least one electrically insulating layer structure (104) by a laser beam; and The at least one recess (134) is filled with an electrically conductive material to form the at least one trace (108).

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