Ultrathin copper foil, ultrathin copper foil with carrier, and method for manufacturing printed circuit board

Abstract

The invention provides an ultra-thin copper foil, an ultra-thin copper foil with a carrier, and a method for manufacturing a printed circuit board. An ultra-thin copper foil which can form highly micronized wiring lines having a line / pitch (L / S) of 10 [mu] m or less / 10 [mu] m or less on both sides in different patterns, and thus can be used as an inexpensive and easy-to-process better substitute for a silicon interposer and a glass interposer. The ultra-thin copper foil is provided with a first ultra-thin copper layer, an etching barrier layer and a second ultra-thin copper layer in this order, and the arithmetic average roughness Ra of both surfaces of the ultra-thin copper foil is 20 nm or less.

Description

[0001] This application is a divisional application of the application filed on October 18, 2018, with application number 201880049861.5, entitled "Ultra-thin Copper Foil and Ultra-thin Copper Foil with Carrier, and Method for Manufacturing Printed Circuit Board". Technical Field

[0002] This invention relates to ultra-thin copper foil and ultra-thin copper foil with a carrier, as well as a method for manufacturing printed circuit boards. Background Technology

[0003] With the miniaturization and increasing functionality of portable electronic devices in recent years, there is a growing demand for further miniaturization (fine pitch) of wiring patterns on printed circuit boards (PCBs). To meet these requirements, copper foil used in PCB manufacturing needs to be thinner and have lower surface roughness than ever before. For example, Patent Document 1 (Japanese Patent Application Publication No. 2005-76091) discloses a method for manufacturing an ultra-thin copper foil with a carrier, which includes sequentially stacking a release layer and an ultra-thin copper foil on the smooth surface of a carrier copper foil with an average surface roughness Rz reduced to 0.01 to 2.0 μm. The method also discloses the implementation of high-density ultra-fine wiring (fine patterning) through this ultra-thin copper foil with a carrier to obtain a multilayer PCB.

[0004] Furthermore, to further reduce the thickness and surface roughness of the ultrathin copper layer in a carrier-supported ultrathin copper foil, it has recently been proposed to form the ultrathin copper layer using vapor phase methods such as sputtering. For example, Patent Document 2 (International Publication No. 2017 / 150283) discloses a carrier-supported copper foil comprising a carrier, a release layer, an anti-reflective layer, and an ultrathin copper layer in sequence, and describes the formation of the release layer, anti-reflective layer, and ultrathin copper layer by sputtering. Patent Document 3 (International Publication No. 2017 / 150284) discloses a carrier-supported copper foil comprising a carrier, an intermediate layer (e.g., a bonding metal layer and a release aid layer), a release layer, and an ultrathin copper layer, and describes the formation of the intermediate layer, release layer, and ultrathin copper layer by sputtering. In both Patent Documents 2 and 3, each layer is formed by sputtering on a carrier (e.g., a glass carrier), thereby achieving an extremely low arithmetic mean roughness Ra of 1.0–100 nm on the outer surface of the ultrathin copper layer.

[0005] However, in the formation of multilayer wiring circuits accompanied by etching, it is known to provide an etch barrier layer on the metal layer to prevent the insulating film from being exposed to the etching solution. For example, Patent Document 4 (Japanese Patent Application Publication No. 2009-88572) discloses a multilayer metal plate having a wiring film forming metal layer (e.g., a copper foil with a thickness of 12 μm), an etch barrier layer (e.g., a Ni layer with a thickness of 1 μm), and a bump forming metal layer (e.g., a copper foil with a thickness of 80 μm) in sequence, and points out that the etch barrier layer can prevent the wiring film forming metal film from being etched during selective etching of the bump forming metal layer.

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2005-76091

[0009] Patent Document 2: International Publication No. 2017 / 150283

[0010] Patent Document 3: International Publication No. 2017 / 150284

[0011] Patent Document 4: Japanese Patent Application Publication No. 2009-88572 Summary of the Invention

[0012] In recent years, a packaging technology called 2.5D mounting has been developed to achieve high density and high speed in semiconductor components. In this 2.5D mounting, a silicon interposer serves as an intermediate substrate between the IC (integrated circuit) chip and the packaging substrate, and IC chips with different terminal pitches are bonded to the packaging substrate via this silicon interposer. That is, in 2.5D mounting, the silicon interposer functions as a redistribution substrate. Specifically, the upper and lower electrodes of the silicon interposer are electrically connected through through-silicon vias (TSVs) formed on the silicon interposer. Furthermore, the upper part of the silicon interposer becomes a high-density wiring layer, connecting the uppermost electrode of the silicon interposer and the IC chip via microbumps, and the silicon interposer and the packaging substrate are connected by bumps, thereby enabling bonding of the IC chip and the packaging substrate. In addition, because the silicon interposer has good processability and low hygroscopicity and low coefficient of thermal expansion (CTE), highly reliable and highly miniaturized wiring patterns that are difficult to achieve in conventional resin substrates can be formed. On the other hand, from the perspective of physical and electrical properties, a technology has also been developed to use a glass interlayer instead of a silicon interlayer.

[0013] However, besides the high cost of the substrates themselves, silicon and glass interposers also require very expensive processing techniques for forming through-glass electrodes (TGVs). Therefore, rewiring techniques using silicon or glass interposers are only used in certain fields, such as high-performance computing, where high manufacturing costs are permissible. Thus, a cheaper and easier-to-process material to replace silicon and glass interposers is desired. In this regard, conventional copper foils, as shown in Patent Documents 1-4, are designed to form circuits only on one side and are not suitable for forming different wiring patterns on both sides, as with silicon and glass interposers.

[0014] The inventors have now discovered that by constructing an ultrathin copper foil as a three-layer structure consisting of a first ultrathin copper layer, an etch barrier layer, and a second ultrathin copper layer, and setting the arithmetic mean roughness Ra on both sides to below 20 nm, highly miniaturized wiring with line / spacing (L / S) of below 10 μm / below 10 μm can be formed on both sides with different patterns. Therefore, an ultrathin copper foil can be provided that can be used as a cheaper and easier-to-process alternative to silicon interposers and glass interposers.

[0015] Therefore, the object of the present invention is to provide an extremely thin copper foil that can form highly miniaturized wiring with line / spacing (L / S) of less than 10 μm on both sides in different patterns, thus serving as a cheaper and easier-to-process alternative to silicon and glass interposers.

[0016] According to one aspect of the present invention, an ultrathin copper foil is provided, which is an ultrathin copper foil having a first ultrathin copper layer, an etch barrier layer and a second ultrathin copper layer in sequence, wherein the arithmetic mean roughness Ra of both sides of the ultrathin copper foil is less than 20 nm.

[0017] According to another aspect of the present invention, an extremely thin copper foil with a carrier is provided, comprising:

[0018] The carrier is made of glass or ceramic;

[0019] A close-fitting metal layer disposed on the carrier is composed of at least one metal selected from the group consisting of Ti, Cr, Mo, Mn, W and Ni;

[0020] A release layer, disposed on the bonded metal layer, is composed of a carbon layer; and,

[0021] The ultrathin copper foil is disposed on the release layer in such a way that the second ultrathin copper layer is in contact with the release layer.

[0022] According to another aspect of the present invention, a method for manufacturing a printed circuit board is provided, comprising:

[0023] The process of preparing the ultrathin copper foil with a carrier;

[0024] The process of processing the first extremely thin copper layer to form the first circuit;

[0025] The process of sealing the first circuit with insulating resin;

[0026] The process of peeling the carrier together with the adhesive metal layer and the release layer to expose the second ultrathin copper layer;

[0027] The process of processing the second thin copper layer, and then processing the etch barrier layer to form the second circuit; and,

[0028] The process of sealing the second circuit with insulating resin. Attached Figure Description

[0029] Figure 1 A schematic cross-sectional view illustrating one aspect of the ultrathin copper foil of the present invention.

[0030] Figure 2 A schematic cross-sectional view illustrating one aspect of the carrier-supported ultrathin copper foil of the present invention.

[0031] Figure 3 This is a process flow diagram illustrating the manufacturing method of the printed circuit board of the present invention, showing the first half of the process (processes (a) to (c)).

[0032] Figure 4 This is a process flow diagram illustrating the manufacturing method of the printed circuit board of the present invention, showing the latter half of the process (processes (d) to (f)).

[0033] Figure 5 This is a schematic diagram used to illustrate the baseline and peak area in a Raman spectrum.

[0034] Figure 6 The image shows the Raman spectrum B of the peel layer side surface of an extremely thin copper foil when the carrier and the metal layer are peeled off together, and the Raman spectrum A of the peel layer side surface of the carrier with the metal layer peeled off. Detailed Implementation

[0035] Extremely thin copper foil

[0036] The ultrathin copper foil of the present invention is schematically shown in Figure 1 .like Figure 1 As shown, the ultrathin copper foil 10 of the present invention sequentially comprises a first ultrathin copper layer 12, an etch barrier layer 14, and a second ultrathin copper layer 16. Furthermore, the arithmetic mean roughness Ra of both sides of the ultrathin copper foil 10 is 20 nm or less. Thus, by constructing the ultrathin copper foil 10 as a three-layer structure consisting of the first ultrathin copper layer 12, the etch barrier layer 14, and the second ultrathin copper layer 16, and setting the arithmetic mean roughness Ra of both sides to 20 nm or less, highly miniaturized wiring with a line / spacing (L / S) of 10 μm or less / 10 μm or less can be formed on both sides with different patterns. Therefore, an ultrathin copper foil that is inexpensive and easy to process can be provided as a superior alternative to silicon interposers and glass interposers. That is, by using the ultrathin copper foil 10 of the present invention, as... Figure 3 and Figure 4As shown, by processing a first ultrathin copper layer 12 of an ultrathin copper foil 10 to form a first circuit 13, and then processing a second ultrathin copper layer 16 and an etch barrier layer 14 to form a second circuit 17, wiring with different patterns can be formed on both sides. This is because the etch barrier layer 14, located between the first ultrathin copper layer 12 and the second ultrathin copper layer 16, prevents the etchant from eroding the second ultrathin copper layer 16 on the opposite side when the first ultrathin copper layer 12 is etched to form the first circuit 13, and prevents the etchant from eroding the first circuit 13 on the opposite side when the second ultrathin copper layer 16 is etched to form the second circuit 17. In addition, by making the arithmetic mean roughness Ra of both sides of the ultrathin copper foil 10 less than 20 nm, the formability of microcircuits can be improved, and highly miniaturized wiring patterns with line / pitch (L / S) of less than 10 μm / less, which can only be achieved by silicon interposers or glass interposers, can be formed. Furthermore, since the ultrathin copper foil 10 is mainly composed of copper layers, it is much cheaper and easier to process than silicon and glass interlayers, which are expensive, hard and difficult to process, making it an extremely suitable alternative to them.

[0037] The first ultrathin copper layer 12 and the second ultrathin copper layer 16 are both layers composed of copper. The copper constituting the first ultrathin copper layer 12 and the second ultrathin copper layer 16 may contain unavoidable impurities originating from the raw material composition, film formation process, etc. The first ultrathin copper layer 12 and the second ultrathin copper layer 16 can be manufactured by any method, for example, they can be copper layers formed by wet film formation methods such as electroless copper plating and copper electroplating, physical vapor deposition methods such as sputtering and vacuum evaporation, chemical vapor deposition, or combinations thereof. From the viewpoint of easily addressing the fine pitch caused by ultrathinness, the ultrathin copper layer is particularly preferred to be a copper layer formed by vapor deposition methods such as sputtering and vacuum evaporation, and most preferably a copper layer manufactured by sputtering. In addition, the ultrathin copper layer is preferably a copper layer without roughening, but as long as it does not hinder the formation of wiring patterns during printed circuit board manufacturing, it can also be a copper layer that has been pre-roughened or has undergone secondary roughening through soft etching, cleaning, or oxidation-reduction treatment. The thicknesses of the first ultrathin copper layer 12 and the second ultrathin copper layer 16 are preferably 0.05 to 1.0 μm, more preferably 0.10 to 0.8 μm, further preferably 0.15 to 0.6 μm, particularly preferably 0.2 to 0.5 μm, and most preferably 0.25 to 0.35 μm. By setting these thicknesses, it is more suitable to form highly refined wiring patterns with a line / pitch (L / S) of 10 μm or less. Furthermore, from the viewpoint of in-plane uniformity of film thickness and productivity in sheet or roll form, ultrathin copper layers with thicknesses within such a range are preferably manufactured by sputtering.

[0038] The etch barrier layer 14 is a layer that is more difficult to etch by the copper flash etchant compared to the first ultrathin copper layer 12 and the second ultrathin copper layer 16. That is, the etch barrier layer 14 is characterized by its lower etch rate than that of copper. This etch rate is determined as follows: during the copper etching process, a foil sample made of the same material as the etch barrier layer 14 and a copper foil sample serving as a reference sample are treated for the same amount of time, the weight loss of the two samples is measured, and the thickness is calculated based on the density of each metal. Here, the copper flash etchant can be a known liquid capable of dissolving copper through a redox reaction. Examples of copper flash etchants include aqueous solutions of sodium persulfate, potassium persulfate, and sulfuric acid / hydrogen peroxide. Furthermore, the etching temperature can be appropriately set within the range of 25–70°C.

[0039] Therefore, the etching barrier layer 14 is preferably made of a metal or alloy that is more difficult to be etched by the copper flash etchant compared to the first ultrathin copper layer 12 and the second ultrathin copper layer 16. Preferred examples of the metal or alloy constituting the etching barrier layer 14, from the viewpoint of ensuring adhesion to the first ultrathin copper layer 12 and the second ultrathin copper layer 16, include Al, Nb, Zr, Cr, W, Ta, Co, Ti, Ag, Ni, Mo, and combinations thereof; more preferably, Cr, Ta, Ti, Ni, Mo, and combinations thereof; further preferably, Cr, Ti, Mo, and combinations thereof; and most preferably, Ti, Mo, and combinations thereof. These elements have the property of not dissolving in the copper flash etchant, resulting in excellent chemical resistance to the copper flash etchant. The thickness of the etch barrier layer 14 is preferably 0.05 to 1.0 μm, more preferably 0.08 to 0.8 μm, even more preferably 0.10 to 0.6 μm, particularly preferably 0.12 to 0.45 μm, and most preferably 0.15 to 0.35 μm. By setting this thickness, the requirement for extremely thin copper foil can be met, and the erosion of the second extremely thin copper layer 16 during the etching of the first extremely thin copper layer 12, and the erosion of the first circuit 13 during the etching of the second extremely thin copper layer 16, can be more effectively prevented. Furthermore, from the viewpoint of in-plane uniformity of film thickness and productivity in sheet or roll form, an etch barrier layer of this thickness is preferably manufactured by sputtering.

[0040] The preferred thickness of the ultrathin copper foil 10 is 0.15–3.0 μm, more preferably 0.28–2.4 μm, further preferably 0.4–1.8 μm, particularly preferably 0.52–1.45 μm, and most preferably 0.65–1.05 μm. It should be noted that as long as the ultrathin copper foil 10 sequentially comprises the first ultrathin copper layer 12, the etching barrier layer 14, and the second ultrathin copper layer 16, it may contain other layers besides these three layers, provided that the original function of the ultrathin copper foil 10 is not impaired.

[0041] The arithmetic mean roughness Ra of both sides of the ultrathin copper foil 10 (i.e., the surface of the first ultrathin copper layer 12 away from the etch barrier layer 14 and the surface of the second ultrathin copper layer 16 away from the etch barrier layer 14) as measured according to JIS B 0601-2001 is 20 nm or less, preferably 0.1 to 20 nm, more preferably 0.25 to 18 nm, further preferably 0.5 to 15 nm, particularly preferably 1.0 to 13 nm, and most preferably 2.0 to 10 nm. Thus, the smaller the arithmetic mean roughness, the more suitable it is for forming highly refined wiring patterns with a line / pitch (L / S) of 10 μm or less (e.g., 10 μm / 10 μm to 2 μm / 2 μm) in printed circuit boards manufactured using the ultrathin copper foil 10. The lower limit of the arithmetic mean roughness Ra is not particularly limited and can be zero, but considering the efficiency of the planarization process of the carrier 22 described later, a target of 0.1 nm can be taken as the lower limit value. Since the Ra of the carrier 22 is reflected on the Ra of both sides of the ultrathin copper foil 10, the Ra of both sides of the ultrathin copper foil 10 can be controlled by adjusting the planarization process of the carrier 22.

[0042] The first ultrathin copper layer 12, the etch barrier layer 14, and the second ultrathin copper layer 16 are all preferably sputtered films, i.e., films formed by sputtering. By using sputtering to form all layers of the first ultrathin copper layer 12, the etch barrier layer 14, and the second ultrathin copper layer 16, manufacturing efficiency is significantly improved. Furthermore, since sputtering generally uses high-purity targets to form films in a vacuum, a clean state with very few impurities can be formed on both sides of the ultrathin copper foil 10. As a result, good adhesion between the photoresist and the ultrathin copper foil 10 can be ensured during circuit formation. In addition, when manufactured in the form of an ultrathin copper foil with a carrier, since each layer inherits the high flatness of the carrier made of glass or ceramic, it is easier to achieve a high flatness with an arithmetic mean roughness Ra of less than 20 nm on both sides of the ultrathin copper foil 10. As a result, it is possible to form micro-circuits with a line / spacing (L / S) of less than 10 μm / 10 μm using photoresist with higher precision.

[0043] Extremely thin copper foil with carrier

[0044] The ultrathin copper foil of the present invention is provided in the form of an ultrathin copper foil with a carrier, which is preferred in terms of improving processability and making the manufacture of printed circuit boards (especially the circuit formation on both sides of the ultrathin copper foil) easier. Figure 2 The diagram schematically illustrates a preferred embodiment of the carrier-supported ultrathin copper foil of the present invention. Figure 2The ultrathin copper foil 20 with a carrier shown comprises, in sequence, a carrier 22, a bonding metal layer 24, a release layer 26, and the aforementioned ultrathin copper foil 10. The carrier 22 is made of glass or ceramic. The bonding metal layer 24 is a layer composed of at least one metal selected from the group consisting of Ti, Cr, Mo, Mn, W, and Ni, and is disposed on the carrier 22. The release layer 26 is a carbon layer disposed on the bonding metal layer 24. The ultrathin copper foil 10 is disposed on the release layer 26 in such a way that the second ultrathin copper layer 16 contacts the release layer 26. Ideally, the aforementioned layers can be sequentially provided in a manner that is symmetrical on both sides of the carrier 22. The ultrathin copper foil 20 with a carrier is not particularly limited in its layer configuration, except for the aforementioned ultrathin copper foil 10, carrier 22, bonding metal layer 24, and release layer 26, as long as a known layer structure is used.

[0045] The carrier 22 is made of glass or ceramic. Furthermore, the carrier 22 can be in the form of a sheet, film, or plate. Alternatively, the carrier 22 can be a carrier laminated from these sheets, films, and plates. For example, the carrier 22 is preferably a carrier capable of functioning as a rigid support, such as a glass plate or ceramic plate. Preferred examples of ceramics constituting the carrier 22 include alumina, zirconium oxide, silicon nitride, aluminum nitride, and various other fine ceramics. From the viewpoint of preventing warping of the extremely thin copper foil 20 with the carrier during heating processes, a material with a coefficient of thermal expansion (CTE) of less than 25 ppm / K (typically 1.0 to 23 ppm / K) is more preferred. Examples of such materials include the ceramics and glass described above. Furthermore, from the viewpoint of processability and ensuring flatness during chip mounting, the Vickers hardness of the carrier 22 is preferably 100 HV or higher, more preferably 150 to 2500 HV. As a material satisfying the above characteristics, the carrier 22 is particularly preferably made of glass, such as a glass plate or glass sheet. When glass is used as the carrier 22, it offers advantages such as being lightweight, having a low coefficient of thermal expansion, high insulation, rigidity, and a flat surface, thus enabling extremely smooth surfaces on both sides of the ultrathin copper foil 10. Furthermore, when the carrier 22 is glass, it offers the following advantages: surface flatness (coplanarity) favorable for forming microcircuits; resistance to chemical reagents during descaling and various plating processes in printed circuit board manufacturing; and the ability to use chemical separation methods when peeling the carrier from the ultrathin copper foil. Preferred examples of the glass constituting the carrier 22 include quartz glass, borosilicate glass, alkali-free glass, soda-lime glass, aluminosilicate glass, and combinations thereof, with alkali-free glass, soda-lime glass, and combinations thereof being more preferred, and alkali-free glass being particularly preferred. Alkali-free glass is a glass that is substantially free of alkali metals, primarily composed of alkaline earth metal oxides such as silicon dioxide, aluminum oxide, boron oxide, calcium oxide, and barium oxide, and thus contains boric acid. The alkali-free glass exhibits a low and stable coefficient of thermal expansion of 3 to 5 ppm / K over a wide temperature range of 0°C to 350°C, thus minimizing glass warpage during heating processes. The thickness of the carrier 22 is preferably 100 to 2000 μm, more preferably 300 to 1800 μm, and even more preferably 400 to 1100 μm. Thicknesses within this range ensure adequate strength without hindering processing, enabling the thinning of printed circuit boards and reducing warpage during electronic component mounting.

[0046] The surface of the adhesive metal layer 24 side of the carrier 22 preferably has an arithmetic mean roughness Ra of 0.1 to 15 nm as measured according to JIS B 0601-2001, more preferably 0.5 to 12 nm, further preferably 1.0 to 10 nm, particularly preferably 1.5 to 7.5 nm, and most preferably 2.0 to 5.0 nm. Thus, the smaller the arithmetic mean roughness, the lower the arithmetic mean roughness Ra can be achieved on both sides of the ultrathin copper foil 10. Therefore, it is suitable to form wiring patterns with highly refined line / spacing (L / S) of less than 10 μm / 10 μm (e.g., 10 μm / 10 μm to 2 μm / 2 μm) in printed circuit boards manufactured using the ultrathin copper foil 10 or the ultrathin copper foil 20 with a carrier. The lower limit of the arithmetic mean roughness Ra is not particularly limited and can be zero, but 0.1 nm can be considered as a target lower limit value when considering the efficiency of planarization processing.

[0047] The bonding metal layer 24 is a layer located between the carrier 22 and the release layer 26, which helps ensure the adhesion between the carrier 22 and the release layer 26. It is a layer composed of at least one metal selected from the group consisting of Ti, Cr, Mo, Mn, W, and Ni, and can be a pure metal or an alloy. The metal constituting the bonding metal layer 24 may contain unavoidable impurities originating from the raw material composition, film formation process, etc. Furthermore, although there are no particular limitations, the presence of oxygen introduced from the atmosphere is permissible when the bonding metal layer 24 is exposed to the atmosphere after film formation. The bonding metal layer 24 is preferably a layer formed by a vapor phase method such as sputtering. A layer formed by magnetron sputtering of a metal target is particularly preferred in terms of improving the uniformity of film thickness distribution. The thickness of the bonding metal layer 24 is preferably 5–500 nm, more preferably 10–300 nm, further preferably 18–200 nm, and particularly preferably 20–100 nm. This thickness was determined by analyzing the cross-section of the layer using a transmission electron microscope with an energy-dispersive X-ray spectroscopy analyzer (TEM-EDX).

[0048] The release layer 26 is a layer that enables the carrier 22 (which has a tightly bonded metal layer 24) to be peeled off. Considering ease of peeling and film formation, it is preferably composed of a carbon layer. The carbon layer is preferably a layer mainly formed of carbon or hydrocarbons, and more preferably formed of amorphous carbon as a hard carbon film. In this case, the carbon concentration of the release layer 26 (i.e., the carbon layer), as measured by XPS, is preferably 60 atomic% or more, more preferably 70 atomic% or more, more preferably 80 atomic% or more, and particularly preferably 85 atomic% or more. There is no particular upper limit to the carbon concentration; it can be 100 atomic%, but in practice it is 98 atomic% or less. The release layer 26 (carbon layer) may contain unavoidable impurities (e.g., oxygen, carbon, hydrogen, etc., originating from the surrounding environment such as the atmosphere). Furthermore, due to the film formation method of the second extremely thin copper layer 16, metal atoms (especially Cu) may be incorporated into the release layer 26 (carbon layer). The carbon exhibits low interdiffusion and reactivity with the carrier, preventing the formation of metallic bonds between the copper foil layer and the bonding interface caused by high-temperature heating, even under pressing processes at temperatures exceeding 300°C. This ensures easy removal of the carrier. From the perspectives of suppressing excessive impurities in the amorphous carbon and ensuring continuous production of the aforementioned bonded metal layer 24, it is preferable that the release layer 26 is also formed by a vapor phase method such as sputtering. The thickness of the release layer 26 is preferably 1–20 nm, more preferably 1–10 nm. This thickness is measured by analyzing the layer cross-section using a transmission electron microscope with energy-dispersive X-ray spectroscopy (TEM-EDX).

[0049] When the carrier 22 is peeled off together with the adhesive metal layer 24, the residual proportion of the release layer 26 on the surface of the ultrathin copper foil 10 on the release layer 26 side is preferably 50% or less, more preferably 30% or less, and even more preferably 15% or less, relative to the residual amount of the release layer 26 on the surface of the carrier 22 with the adhesive metal layer 24 after peeling. This ensures good adhesion between the photoresist and the surface of the ultrathin copper foil 10 during circuit formation, enabling the formation of fine circuits with a line / spacing (L / S) of 10 μm or less / 10 μm or less using photoresist with higher precision. The lower limit of the residual proportion of the release layer 26 on the surface of the ultrathin copper foil 10 on the release layer 26 side is not particularly limited; it can be 0% (i.e., no release layer 26 remains on the surface of the ultrathin copper foil 10 on the release layer 26 side), but in practice it is 1% or more. The residual amount or proportion of the release layer 26 can be determined by Raman spectroscopy, preferably using a Raman spectrophotometer under the following conditions. It should be noted that, from the viewpoint of removing peaks or noise originating from components other than the release layer 26, it is preferable to use a Raman spectrophotometer to measure the surface of the sealed metal layer 24 in the laminated sample of the separately fabricated carrier 22 / sealed metal layer 24 (in the state where the release layer 26 and the layer thereon are not formed), and the surface of the second extremely thin copper layer 16 in the laminated sample of the separately fabricated carrier 22 / sealed metal layer 24 / release layer 26 / second extremely thin copper layer 16 (in the state where the etch barrier layer 14 and the layer thereon are not formed), and subtract the obtained Raman spectra as background as needed.

[0050] <Measurement Conditions>

[0051] - Measuring apparatus: NRS-5200 laser Raman spectrophotometer (manufactured by Nippon Spectrophotometer Co., Ltd.)

[0052] - Excitation wavelength: 532.29nm

[0053] - Raster: 600 Lines / mm

[0054] - Slit width: 200×1000μm

[0055] - Aperture: 4000 μm in diameter

[0056] - Objective lens: MPLFLN 100x

[0057] - Exposure time: 60 seconds

[0058] Specifically, in Raman spectra, carbon typically appears at 1500–1600 cm⁻¹. -1There is a peak present, so it can be said that the peak originates from the release layer 26. Therefore, by comparing the Raman spectra of the release layer 26 side surface of the carrier 22 with the bonded metal layer 24 and the release layer 26 side surface of the ultrathin copper foil 10, the peak present at 1500-1600 cm⁻¹ can be identified. -1 The residual proportion of the exfoliated layer 26 can be determined by calculating the peak area (peak intensity area) of the peaks between 1500 and 1600 cm⁻¹. Here, "exists in the 1500–1600 cm⁻¹" range. -1 The peak area between peaks" Figure 5 As illustrated schematically, unless otherwise specified, it refers to 1000cm. -1 and 1800cm -1 The intensity of the Raman spectrum at a given location is connected by a straight line as a baseline, and the values ​​at this baseline and those at 1500–1600 cm⁻¹ are used to determine the baseline. -1 The area of ​​the region enclosed by the peak profiles drawn from the peaks between them. Figure 6 Raman spectra A of the release layer 26 side surface of the carrier 22 with the adhesive metal layer 24 after it is peeled off together with the carrier 22 are shown; and Raman spectra B of the release layer 26 side surface of the ultrathin copper foil 10 are shown. Figure 6 B in A As the baseline of spectrum A, B B This is the baseline of spectrum B. For example... Figure 6 As shown, the Raman spectra A of the side surface of the peeling layer 26 of the carrier 22 with the sealed metal layer 24 that has been peeled off are calculated, and the presence of the Raman spectra in the 1500-1600 cm⁻¹ region is obtained. -1 The peak between (P) A The peak area A A Raman spectra B of the side surface of the release layer 26 of the ultrathin copper foil 10, and the presence of [a substance] in the 1500–1600 cm⁻¹ region. -1 The peak between (P) B The peak area A B By calculating the peak area A B Relative to peak area A A percentage [(A)] B / A A [100%] can be used to determine the residual percentage of the peeling layer 26 on the surface of the extremely thin copper foil 10 when the carrier 22 is peeled off together with the adhesive metal layer 24.

[0059] The first ultrathin copper layer 12, the etch barrier layer 14, the second ultrathin copper layer 16, the release layer 26, and the bonding metal layer 24 are all preferably sputtered films, i.e., films formed by sputtering. By using sputtering to form all layers of the first ultrathin copper layer 12, the etch barrier layer 14, the second ultrathin copper layer 16, the release layer 26, and the bonding metal layer 24, manufacturing efficiency is significantly improved. Furthermore, since sputtering generally uses high-purity targets to form films in a vacuum, a clean state with very few impurities can be formed on both sides of the ultrathin copper foil 10. As a result, good adhesion between the photoresist and the ultrathin copper foil 10 can be ensured during circuit formation. In addition, since each layer inherits the high flatness of the carrier 22 made of glass or ceramic, it is easier to achieve high flatness with an arithmetic mean roughness Ra of less than 20 nm on both sides of the ultrathin copper foil 10. As a result, it is possible to form fine circuits with line / spacing (L / S) of less than 10 μm using photoresist with higher precision.

[0060] Method for manufacturing extremely thin copper foil with carrier

[0061] The ultrathin copper foil 20 with a carrier can be manufactured as follows: A carrier 22 is prepared, and a bonding metal layer 24, a release layer 26, a second ultrathin copper layer 16, an etch barrier layer 14, and a first ultrathin copper layer 12 are formed on the carrier 22. From the viewpoint of easily handling fine-pitch variations based on ultrathinness, the formation of each layer—bonding metal layer 24, release layer 26, second ultrathin copper layer 16, etch barrier layer 14, and first ultrathin copper layer 12—is preferably performed by a vapor phase method. Examples of vapor phase methods include sputtering, vacuum evaporation, and ion plating. Sputtering is most preferred from the perspectives of controlling film thickness over a wide range (0.05 nm to 5000 nm) and ensuring film thickness uniformity over a wider area or region. In particular, by using sputtering to form all layers—bonding metal layer 24, release layer 26, second ultrathin copper layer 16, etch barrier layer 14, and first ultrathin copper layer 12—manufacturing efficiency is significantly improved. Furthermore, since sputtering typically uses high-purity targets to form films in a vacuum, a clean state with minimal impurities can be achieved on both sides of the ultrathin copper foil 10. As a result, good adhesion between the photoresist and the ultrathin copper foil 10 can be ensured during circuit formation. Additionally, since each layer inherits the high flatness of the glass or ceramic carrier 22, it is easier to achieve high flatness with an arithmetic mean roughness Ra of less than 20 nm on both sides of the ultrathin copper foil 10. Consequently, it is possible to form microcircuits with a line / spacing (L / S) of less than 10 μm using photoresist with higher precision.

[0062] There are no particular limitations to vapor phase film formation as long as it is performed using a known vapor phase film formation apparatus under known conditions. For example, when using sputtering, the sputtering method can be any known method such as magnetron sputtering, bipolar sputtering, or opposed target sputtering. From the perspective of fast film formation speed and high productivity, magnetron sputtering is preferred. Sputtering can be performed under either DC (direct current) or RF (high frequency) power supply. In addition, although plate-shaped targets with widely known target shapes can also be used, from the viewpoint of target utilization efficiency, it is desirable to use cylindrical targets. Hereinafter, the film formation of each layer of the bonding metal layer 24, the release layer 26, the second ultrathin copper layer 16, the etch barrier layer 14, and the first ultrathin copper layer 12 using vapor phase method (preferably sputtering) will be described.

[0063] From the perspective of improving the uniformity of film thickness distribution, the deposition of the dense metal layer 24 using a gas-phase method is preferably performed by magnetron sputtering in a non-oxidizing atmosphere using a target material composed of at least one metal selected from the group consisting of Ti, Cr, Mo, Mn, W, and Ni. The purity of the target material is preferably 99.9% or higher. As the gas used in sputtering, a non-reactive gas such as argon is preferred. The argon flow rate is not particularly limited as long as it is appropriately determined according to the sputtering chamber size and film deposition conditions. Furthermore, from the viewpoint of avoiding abnormal discharges or poor plasma irradiation and continuously performing film deposition, the pressure during film deposition is preferably in the range of 0.1 to 20 Pa. This pressure range can be set by adjusting the film deposition power and argon flow rate according to the device structure, capacity, vacuum pump exhaust capacity, and rated capacity of the film deposition power supply. Additionally, considering the uniformity of film thickness and productivity, the sputtering power can be 0.05 to 10.0 W / cm² per unit area of ​​the target material. 2 Set appropriately within the specified range.

[0064] The carbon layer, serving as the release layer 26, is deposited using a vapor phase method (preferably sputtering) preferably with a carbon target in an inactive atmosphere such as argon. The carbon target is preferably made of graphite, but may contain unavoidable impurities (e.g., oxygen and carbon from the surrounding environment). The purity of the carbon target is preferably 99.99% or higher, more preferably 99.999% or higher. Furthermore, from the viewpoint of avoiding operational malfunctions such as abnormal discharges or poor plasma irradiation and ensuring continuous film deposition, the pressure during film deposition is preferably in the range of 0.1 to 2.0 Pa. This pressure range can be set by adjusting the film deposition power and argon flow rate according to the apparatus structure, capacity, vacuum pump exhaust capacity, and rated capacity of the film deposition power supply. Additionally, considering film thickness uniformity and productivity, the sputtering power can be 0.05 to 10.0 W / cm² per unit area of ​​the target material. 2 Set appropriately within the specified range.

[0065] The deposition of the second thin copper layer 16 using a vapor phase method (preferably sputtering) is preferably performed using a copper target under an inactive atmosphere such as argon. The copper target is preferably made of metallic copper, but may contain unavoidable impurities. The purity of the copper target is preferably 99.9% or higher, more preferably 99.99%, and even more preferably 99.999% or higher. To prevent temperature rise during vapor phase deposition of the second thin copper layer 16, a cooling mechanism for the stage can be provided during sputtering. Furthermore, from the viewpoint of stable deposition without abnormal discharges or poor plasma irradiation, the deposition pressure is preferably in the range of 0.1 to 2.0 Pa. This pressure range can be set by adjusting the deposition power and argon flow rate according to the apparatus structure, capacity, vacuum pump exhaust capacity, and rated capacity of the deposition power supply. Additionally, considering film thickness uniformity and productivity, the sputtering power can be 0.05 to 10.0 W / cm² per unit area of ​​the target material. 2 Set appropriately within the specified range.

[0066] The etching barrier layer 14 is preferably formed using a target material composed of at least one selected from the group consisting of Cr, W, Ta, Co, Ti, Ag, Ni, and Mo, and is formed by magnetron sputtering. The purity of the target material is preferably 99.9% or higher. The deposition of the etching barrier layer 14 using magnetron sputtering is particularly preferably performed under an atmosphere of inactive gas such as argon at a pressure of 0.1–20 Pa. The sputtering pressure is more preferably 0.2–15 Pa, and even more preferably 0.3–10 Pa. It should be noted that the above pressure range can be controlled by adjusting the film deposition power and argon flow rate according to the apparatus structure, capacity, vacuum pump exhaust capacity, and rated capacity of the film deposition power supply. The argon flow rate is not particularly limited as long as it is appropriately determined based on the sputtering chamber size and film deposition conditions. Furthermore, considering the film thickness uniformity and productivity, the sputtering power can be 1.0–15.0 W / cm² per unit area of ​​the target material. 2 The temperature should be set appropriately within a certain range. Furthermore, from the perspective of easily obtaining stable film properties (e.g., film resistance, crystal size), it is preferable to maintain a constant carrier temperature during film formation. The carrier temperature during film formation is preferably adjusted within the range of 25–300°C, more preferably 40–200°C, and even more preferably within the range of 50–150°C.

[0067] The deposition of the first ultrathin copper layer 12 using a vapor phase method (preferably sputtering) is the same as that of the second ultrathin copper layer 16, preferably using a copper target in an inactive atmosphere such as argon. Therefore, the various conditions described for the deposition of the second ultrathin copper layer 16 are directly applied to the deposition of the first ultrathin copper layer 12.

[0068] Laminate for printed circuit board

[0069] The ultra-thin copper foil with a carrier of the present invention can be provided in the form of a laminate for printed circuit boards. That is, according to a preferred embodiment of the present invention, a laminate for printed circuit boards having the above-mentioned ultra-thin copper foil with a carrier is provided. As a form of laminate for printed circuit boards, the following two forms can be cited. (i) The first form of the laminate for printed circuit boards is the form of the ultra-thin copper foil with a carrier itself. That is, including: the form of the ultra-thin copper foil 10 with a carrier having a bonding metal layer 24 / release layer 26 / second ultra-thin copper layer 16 / etch barrier layer 14 / first ultra-thin copper layer 12 sequentially stacked on at least one side of the carrier 22; and the form of having a bonding metal layer 24 / release layer 26 / second ultra-thin copper layer 16 / etch barrier layer 14 / first ultra-thin copper layer 12 sequentially stacked on both sides of the carrier. In any case, this form is valid when the carrier itself is rigid and can function as a support, for example when the carrier 22 is a glass plate, ceramic plate, etc. For example, when glass is used as the carrier 22, it has advantages such as being lightweight, having a low coefficient of thermal expansion, being rigid, and having a flat surface, thus enabling both sides of the ultrathin copper foil 10 to be extremely smooth. (ii) The second form of the laminate for printed circuit boards is a form in which an adhesive layer is provided on the side of the carrier 22 opposite to the bonding metal layer 24 (i.e., the outer surface of the carrier 22). In this case, examples of adhesive layers include resin layers, fiber-reinforced prepregs (such as glass), etc. For example, a layer structure of first ultrathin copper layer 12 / etch barrier layer 14 / second ultrathin copper layer 16 / release layer 26 / bonding metal layer 24 / carrier 22 / adhesive layer (not shown) / carrier 22 / bonding metal layer 24 / release layer 26 / second ultrathin copper layer 16 / etch barrier layer 14 / first ultrathin copper layer 12 may also be used.

[0070] Method for manufacturing printed circuit board

[0071] Printed circuit boards can be manufactured using the carrier-supported ultrathin copper foil of the present invention. A preferred method for manufacturing the printed circuit board is described below. This method includes the following steps: (1) a preparation step of the carrier-supported ultrathin copper foil; (2) a formation step of a first circuit; (3) a sealing step of the first circuit; (4) a carrier peeling step; (5) a formation step of a second circuit; and (6) a sealing step of the second circuit. A schematic diagram of the method for manufacturing a printed circuit board including these steps is shown below. Figure 3 and 4 .

[0072] (1) Preparation process of ultra-thin copper foil with carrier

[0073] Prepare an extremely thin copper foil 20 with a carrier as a support (refer to...) Figure 3(a) As described above, the ultra-thin copper foil 20 with a carrier can be prepared in the form of a laminate for a printed circuit board. That is, as described above, it can be provided in the form of the ultra-thin copper foil with a carrier itself, or it can be prepared in the form of having an adhesive layer on the side of the carrier 22 opposite to the adhesive metal layer 24 (the outer surface of the carrier 22) (for example, a layer configuration of first ultra-thin copper layer 12 / etch barrier layer 14 / second ultra-thin copper layer 16 / release layer 26 / adhesive metal layer 24 / carrier 22 / adhesive layer / carrier 22 / adhesive metal layer 24 / release layer 26 / second ultra-thin copper layer 16 / etch barrier layer 14 / first ultra-thin copper layer 12).

[0074] (2) Formation process of the first circuit

[0075] The first ultrathin copper layer 12 is processed to form the first circuit 13 in a prescribed pattern (see reference). Figure 3 (b)). The formation of the first circuit 13 is not particularly limited as long as it is carried out by a known method, but it is preferred to be carried out as shown in (2a) to (2d) below.

[0076] (2a) Formation process of photoresist layer

[0077] A photoresist layer is formed in a prescribed pattern on the surface of the first ultrathin copper layer 12. The photoresist is preferably a photosensitive film, such as a photosensitive dry film. The photoresist layer can be given a prescribed wiring pattern by exposure and development.

[0078] (2b) The process of forming the electroplated copper layer

[0079] An electroplated copper layer is formed on the exposed surface of the first ultrathin copper layer 12 (i.e., the portion not covered by the photoresist layer). There are no particular limitations on the electroplating method as long as it is performed by a known method.

[0080] (2c) Stripping process of photoresist layer

[0081] Next, the photoresist layer is stripped off. As a result, the electroplated copper layer remains in the form of a wiring pattern, and the portion of the first ultrathin copper layer 12 where no wiring pattern is formed is exposed.

[0082] (2d) Copper flash etching process

[0083] The first circuit 13 is formed by removing unwanted portions of the first ultrathin copper layer 12 through copper flash etching, thereby exposing the etch barrier layer 14. From the perspective of avoiding over-etching of the electroplated copper layer and reliably etching out the exposed first ultrathin copper layer 12, it is preferable to use a sulfuric acid / hydrogen peroxide mixture or a liquid containing at least one of sodium persulfate and potassium persulfate as the copper flash etching solution. In this way, the electroplated copper layer / first ultrathin copper layer 12 remains in a wiring pattern, and the etch barrier layer in the unpatterned portions remains undissolved by the copper flash etching solution and is exposed to the surface. At this time, at least one metal selected from Cr, W, Ta, Co, Ti, Ag, Ni, and Mo constituting the etch barrier layer 14 has the property of being insoluble in the copper flash etching solution, thus exhibiting excellent chemical resistance to the copper flash etching solution. That is, the etch barrier layer 14 remains exposed and is not removed by copper flash etching, thereby preventing the second ultrathin copper layer 16 on the opposite side from being etched by the etching solution.

[0084] (3) Sealing process of the first circuit

[0085] Seal the first circuit 13 with insulating resin 28 (see reference). Figure 3 (c) It should be noted that sealing with insulating resin can be performed using known methods.

[0086] (4) Carrier peeling process

[0087] The carrier 22, along with the adhesive metal layer 24 and the release layer 26, is peeled off from the laminate sealed with insulating resin 28 in the first circuit 13, thereby exposing the second thin copper layer 16 (see reference). Figure 4 (d)). Physical separation, chemical separation, etc., can be used as the peeling method, but physical separation is preferred. Physical separation involves peeling the carrier 22 and the like from the laminate using hands, clamps, machinery, etc. In this case, the carrier-bearing ultrathin copper foil 20 of the present invention has a tightly bonded metal layer 24, which provides excellent stability to the mechanical peel strength of the carrier 22. As a result, the carrier 22 can be easily peeled off together with the tightly bonded metal layer 24 and the peeling layer 26. This is believed to be because, compared to the adhesion between the carrier 22 and the peeling layer 26 ensured by the presence of the tightly bonded metal layer 24, the adhesion between the peeling layer 26 and the second ultrathin copper layer 16 is stable and reduced.

[0088] (5) Formation process of the second circuit

[0089] The second thin copper layer 16 is fabricated, followed by the etching barrier layer 14, to form the second circuit 17 (see reference). Figure 4(e) At this point, the laminate no longer has a carrier 22, and it does not originally have a rigid silicon interlayer or glass interlayer as in the prior art. However, the laminate itself, sealed by the insulating resin 28 through the first circuit 13 (as if the laminate were a resin substrate), can ensure the required rigidity. Therefore, it has the advantage of being able to stably maintain the flat shape of the laminate while forming the second circuit 17 (especially microcircuit formation) and mounting the IC chip 30 as described later. Furthermore, the stable maintenance of the flat shape of the laminate not only allows for the high-precision formation of microcircuits, but also makes it less likely to damage the formed microcircuits during the mounting of the IC chip 30, thus contributing to improved product yield.

[0090] The processing of the second thin copper layer 16 used to form the second circuit 17 can be carried out according to the first circuit formation process described in (2) above.

[0091] The etching barrier layer 14 used to form the second circuit 17 is preferably processed by flash etching to remove unwanted portions (typically exposed portions) of the etching barrier layer 14. In this way, the etching barrier layer 14 can be flash-etched to form the same pattern as the second ultrathin copper layer 16 that has already undergone wiring. This flash etching, for example, as illustrated in Table 1 below, is preferably performed using an appropriate etchant selected based on the constituent elements of the etching barrier layer 14. Table 1 shows representative etchants, but is not limited to these; the type or concentration of acid or ammonium salt, temperature, etc., can be appropriately varied according to the conditions described in Table 1.

[0092] [Table 1]

[0093] Table 1

[0094] By using such an etchant, the etch barrier layer 14 can be selectively flash-etched. Therefore, only unwanted portions of the etch barrier layer 14 can be selectively removed without eroding the first circuit 13 and the second circuit 17 (which are made of copper). That is, as the etchant for flash-etching at least one of the constituent materials of the etch barrier layer 14 selected from the group consisting of Cr, W, Ta, Co, Ti, Ag, Ni, and Mo, a highly selective etchant can be used. As a result, the dissolution of the copper constituting the first circuit 13 and the second circuit 17 by the etchant can be suppressed or avoided.

[0095] The formation process of the second circuit 17 preferably further includes a process of mounting the IC chip 30 (see reference). Figure 4(e)). It should be noted that in this specification, IC (integrated circuit) broadly includes CPU (central processing unit), DSP (digital signal processor), memory, PMIC (power management IC), RFIC (high-frequency integrated circuit, such as GPS (global positioning system)), and various other ICs. The mounting site of IC chip 30 can be either the first circuit 13 or the second circuit 17, but it is preferred to mount it on the first circuit 13. When IC chip 30 is mounted on the first circuit 13, it is preferable to mount IC chip 30 on the surface of the first circuit 13 exposed by etching away the second ultrathin copper layer 16 and the etch barrier layer 14. Examples of IC chip mounting methods include flip chip mounting and chip bonding. Flip chip mounting is a method of bonding the mounting pads of IC chip 30 to the first circuit 13 or the second circuit 17. Columnar electrodes (pillars), solder bumps, etc., can be formed on the mounting pads, or NCF (non-conductive resin film) can be attached as a sealing resin film to the surface of the first circuit 13 or the second circuit 17 before mounting. Film, etc. Bonding is preferably performed using low-melting-point metals such as solder, but anisotropic conductive films can also be used. The chip bonding method involves bonding the IC chip 30 to the side opposite to the mounting pad surface of the first circuit 13 or the second circuit 17. In this bonding, a paste or film as a resin composition containing a thermosetting resin and a thermally conductive inorganic filler is preferably used.

[0096] (6) Sealing process of the second circuit

[0097] The second circuit 17, formed by processing the second thin copper layer 16, is sealed with insulating resin 28 to obtain a printed circuit board 32 (see reference). Figure 4 (f)). Sealing using insulating resin 28 can be performed based on known methods.

[0098] like Figure 4 The printed circuit board 32 shown in (f) can be processed on its outer layers using various processes. For example, a solder resist layer can be formed on the surface of the first circuit 13 and / or the second circuit 17 of the printed circuit board 32, and surface treatments such as Ni-Au plating and OSP treatment (Organic Solderability Preservative) can be performed to create the outer layer pads. Furthermore, pillar-shaped supports can be provided on the outer layer pads. In any case, well-known processes commonly used in printed circuit boards can be appropriately added, without particular limitation.

Claims

1. An ultrathin copper foil with a carrier, comprising: The carrier is made of glass; A tightly bonded metal layer, disposed on the carrier, is composed of Ti; A release layer, which is disposed on the adhesive metal layer in direct contact, is composed of a carbon layer; and, An ultra-thin copper foil is disposed on the release layer in such a manner that a second ultra-thin copper layer contacts the release layer. The ultrathin copper foil sequentially comprises a first ultrathin copper layer, an etching barrier layer, and a second ultrathin copper layer. The arithmetic mean roughness Ra of both sides of the ultrathin copper foil is below 20 nm, the thickness of the ultrathin copper foil is 0.15–3.0 μm, the thickness of the first ultrathin copper layer and the second ultrathin copper layer is 0.05–1.0 μm respectively, and the thickness of the etching barrier layer is 0.05–1.0 μm. The residual proportion of the peeling layer on the surface of the ultrathin copper foil on the peeling layer side, as determined by Raman spectroscopy, when the carrier and the adhesive metal layer are peeled off together, is less than 50% relative to the residual amount of the peeling layer on the surface of the carrier with the adhesive metal layer that has been peeled off.

2. The ultrathin copper foil with a carrier according to claim 1, wherein, The residual percentage of the release layer on the surface of the ultrathin copper foil on the release layer side is less than 30%.

3. The ultra-thin copper foil with a carrier according to claim 1 or 2, wherein, The etch barrier layer is composed of at least one element selected from the group consisting of Al, Nb, Zr, Cr, W, Ta, Co, Ti, Ag, Ni, and Mo.

4. The ultra-thin copper foil with a carrier according to claim 1 or 2, wherein, The arithmetic mean roughness Ra of both sides of the ultrathin copper foil is 0.1 to 20 nm.

5. The ultrathin copper foil with a carrier according to claim 1 or 2, wherein, The first ultrathin copper layer, the etch barrier layer, and the second ultrathin copper layer are all sputtered films.

6. The ultrathin copper foil with a carrier according to claim 1 or 2, wherein, The thickness of the dense metal layer is 5–500 nm.

7. The ultrathin copper foil with a carrier according to claim 1 or 2, wherein, The thickness of the release layer is 1–20 nm.

8. The ultrathin copper foil with a carrier according to claim 1 or 2, wherein, The first ultrathin copper layer, the etching barrier layer, the second ultrathin copper layer, the release layer, and the bonding metal layer are all sputtered films.

9. A method for manufacturing a printed circuit board, comprising: The process of preparing the ultrathin copper foil with a carrier as described in any one of claims 1 to 8; The process of processing the first extremely thin copper layer to form the first circuit; The process of sealing the first circuit with insulating resin; The process of peeling the carrier together with the adhesive metal layer and the release layer to expose the second ultrathin copper layer; The process of processing the second thin copper layer, and then processing the etch barrier layer to form the second circuit; and, The process of sealing the second circuit with insulating resin.

10. The manufacturing method according to claim 9, wherein, The process of forming the second circuit further includes the process of installing an IC chip.

Images