RRAM memory device structure and preparation method thereof

Abstract

The invention provides an RRAM memory device structure and a preparation method thereof, and the method comprises the steps: providing a connection layer, forming a conductive through hole with a preset surface curvature in the connection layer, and correspondingly arranging a storage unit on the conductive through hole, thereby enabling the storage unit to be matched with a lower concave surface of the conductive through hole in a forming process, and forming a concave region. According to the RRAM memory device structure provided by the invention, after a programming signal is applied, an electric field correspondingly generated by the RRAM memory device structure gathers in the internal concave area of the memory unit and guides an electric field line to gather towards the curvature center of the concave area, so that the formation probability of a conductive filament in a preset interval in the memory unit is improved; and the purpose of controlling and improving the uniformity and reliability of the electrical performance of the RRAM device is achieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing process technology, and in particular to an RRAM memory device structure and its fabrication method. Background Technology

[0002] Resistive Random Access Memory Reactive RAM (Reactive RAM) devices store data through the formation and breakage of conductive filaments within a resistive switching layer. However, the randomness of the filament growth location leads to instability in device performance. Ideally, the conductive filaments should form in a homogeneous region within the resistive switching layer. In practice, however, filaments readily form in sidewall regions susceptible to etching damage. These regions exhibit unstable interface states and are easily affected by external environmental interference, resulting in significant fluctuations in switching parameters, durability, and data retention capabilities in devices based on this principle.

[0003] Therefore, how to effectively control the growth position of conductive filaments to avoid unstable edge regions, thereby improving the uniformity and reliability of the electrical performance of RRAM devices, has become a key technical problem that needs to be solved in this field. Summary of the Invention

[0004] This application aims to at least partially address one of the technical problems in the related art.

[0005] To achieve the above objectives, a first aspect of this application provides an RRAM memory device structure, comprising:

[0006] The connection layer includes at least one conductive via; At least one storage cell is disposed on the connection layer and corresponds one-to-one with the conductive via; The surface of the conductive via near the storage cell is configured as a concave surface with a preset curvature. The storage cell is disposed on the conductive via and forms a recessed area that is adapted to the concave surface.

[0007] Optionally, the storage unit includes: The first electrode is disposed on the connecting layer and covers the concave surface corresponding to the conductive via. A resistive switching layer is disposed on the first electrode; The second electrode is disposed on the resistive switching layer; The resistive switching layer includes a recessed portion that is recessed towards the side close to the first electrode, and a horizontally extending portion that surrounds the periphery of the recessed portion, wherein the recessed portion is located within the recessed region.

[0008] Optionally, the storage unit further includes an oxygen barrier layer and / or an oxygen storage layer, wherein the oxygen barrier layer is disposed on the resistive switching layer and the oxygen storage layer is disposed on the oxygen barrier layer.

[0009] Optionally, the thickness of the resistive switching layer ranges from 10 Å to 2000 Å, the thickness of the oxygen barrier layer ranges from 10 Å to 500 Å, and the thickness of the oxygen storage layer ranges from 10 Å to 2000 Å.

[0010] Optionally, the storage unit includes the oxygen barrier layer and the oxygen storage layer stacked sequentially on the resistive switching layer; wherein the vertical projection of the oxygen storage layer in the stacking direction of the storage unit is located within the vertical projection plane of the resistive switching layer and the oxygen barrier layer, and the projected area is smaller than the projected area of ​​the resistive switching layer and the oxygen barrier layer.

[0011] Optionally, the storage unit further includes a first sidewall isolation layer disposed on the sidewall of the oxygen storage layer and a second sidewall isolation layer disposed on the sidewall of the second electrode; wherein the first sidewall isolation layer covers the exposed sidewall surface of the oxygen storage layer, and the second sidewall isolation layer covers the exposed sidewall surface of the second electrode.

[0012] Optionally, the thickness of the first sidewall isolation layer and the second sidewall isolation layer ranges from 1 Å to 500 Å.

[0013] Optionally, the first electrode includes at least a first bottom electrode layer, and the second electrode includes at least a first top electrode layer; wherein the thickness of the first bottom electrode layer ranges from 10 Å to 1500 Å, and the thickness of the first top electrode layer ranges from 10 Å to 2000 Å.

[0014] Optionally, the first electrode further includes a second bottom electrode layer, the thickness of which ranges from 10 Å to 200 Å.

[0015] Optionally, the second electrode further includes a second top electrode layer, the thickness of which ranges from 10 Å to 1000 Å.

[0016] Optionally, the thickness of the conductive via is in the range of 150 Å to 2000 Å, and the maximum depth of the concave surface is not greater than the thickness of the conductive via.

[0017] Optionally, the connection layer includes a first dielectric layer and at least one first through-hole penetrating the first dielectric layer, wherein the conductive through-holes are disposed one-to-one in the first through-holes and fill the first through-holes.

[0018] Optionally, the connection layer is further provided with a first isolation layer, which covers the exposed surface of the connection layer near the storage cell and extends vertically upward to cover the sidewall of the storage cell.

[0019] Optionally, it also includes: The first interconnect includes a first metal layer disposed on the side close to the memory cell, and the conductive via is disposed on the first metal layer at the end away from the memory cell, electrically connecting the first electrode to the first interconnect. The second interconnect includes a second metal layer disposed on the side near the memory cell, and the second metal layer is disposed on the second electrode, electrically connecting the second electrode to the second interconnect.

[0020] Optionally, the storage cell is further provided with a hard barrier layer, which is disposed on the second electrode and includes a second through hole that exposes a portion of the second electrode. The second metal layer is disposed on the second through hole and contacts the second electrode exposed by the second through hole to form an electrical connection.

[0021] To achieve the above objectives, a second aspect of this application provides a method for fabricating an RRAM memory device structure, comprising: Provide first-hand interconnection; A connection layer is formed on the first interconnect, the connection layer including at least one conductive via, and the surface of the conductive via away from the first interconnect is a concave surface with a preset curvature. A storage stack layer is formed on the connection layer; The memory stack layer is patterned and etched to form at least one memory cell, each memory cell corresponding to one of the conductive vias and adapted to the concave surface to form a recessed area; A first isolation layer is formed on the sidewall of the storage cell and on the connection layer between adjacent storage cells; A first filling layer is formed on the first isolation layer between adjacent storage cells; A second interconnect is formed on the storage unit.

[0022] Optionally, the step of forming a connection layer on the first interconnect includes: A first dielectric layer is formed on the first interconnect; At least one first via is etched on the first dielectric layer, and the first via exposes a portion of the first metal layer of the first interconnect. Deposit metallic material into the first through hole to fully fill the first through hole; The metal material deposited in the first through hole is surface-polished to form the conductive through hole with the concave surface.

[0023] Optionally, the step of forming a storage stack layer on the conductive via includes: A first electrode material layer is formed on the conductive via; A resistive switching material layer is formed on the first electrode; A second electrode material layer is formed on the resistive switching material layer.

[0024] Optionally, after the step of forming a resistive switching material layer on the first electrode, the method further includes: An oxygen barrier material layer is formed on the resistive switching material layer; and, An oxygen storage material layer is formed on the oxygen barrier material layer; The second electrode material layer is formed on the oxygen storage material layer.

[0025] Optionally, after the step of forming a second electrode material layer on the resistive switching material layer, the method further includes: A barrier material layer is formed on the second electrode material layer; and, The barrier material layer is patterned and etched to form a window on the barrier material layer that exposes a portion of the second electrode material layer; The location where the window is formed corresponds one-to-one with the location where the conductive via is formed.

[0026] Optionally, after the step of patterning and etching the memory stack layer to form at least one memory cell, the method further includes: The sidewalls of the oxygen storage layer, formed by patterned etching of the oxygen storage material layer, are subjected to high-temperature oxidation to form a first sidewall isolation layer on the sidewalls of the oxygen storage layer; and, The sidewalls of the second electrode, formed by patterning and etching the second electrode material layer, are subjected to high-temperature oxidation to form a second sidewall isolation layer on the sidewalls of the second electrode.

[0027] Optionally, the step of forming a first filling layer on the first isolation layer between adjacent memory cells includes: A first filling material layer is deposited in the first isolation layer between adjacent memory cells to form a first filling material layer; and, The first isolation layer and the first filling material layer located above the memory cell are selectively etched away using an etch rollback process.

[0028] Optionally, the first electrode material layer or the second electrode material layer is composed of one or more conductive metal materials selected from Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, and W. Or, from TiO x TaO x HfO x ZrO x AlO x WO x NiO x It is composed of one or more metal oxides; Alternatively, it may be composed of a mixture of one or more metal nitrides selected from TiN, TaN, and AlN; Alternatively, it can be composed of one or more metal nitrides selected from TiON, TaON, and AlON.

[0029] Optionally, the resistive switching material layer is composed of one or more of the following: HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, WO3, HfSiO, HfTaO, HfZrO, and HfAlO.

[0030] Optionally, the oxygen barrier material layer is composed of one or more metal oxides selected from HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, HfSiO, HfTaO, HfZrO, and HfAlO. Alternatively, it may be composed of a mixture of one or more metal nitrides selected from TiN, TaN, and AlN; Alternatively, it can be composed of one or more metal nitrides selected from TiON, TaON, and AlON.

[0031] Optionally, the oxygen storage layer is composed of one or more conductive metal materials selected from Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, and W; Or, from TiO x TaO x HfO x ZrO x AlO x WO x NiO x It is composed of one or more metal oxides; Alternatively, it may be composed of a mixture of one or more metal nitrides selected from TiN, TaN, and AlN; Alternatively, it can be composed of one or more metal nitrides selected from TiON, TaON, and AlON.

[0032] The RRAM memory device structure and its fabrication method provided in this application have at least the following beneficial effects: This application provides an RRAM memory device structure and its fabrication method. By providing a connection layer and forming conductive vias with a predetermined surface curvature within the connection layer, and by correspondingly placing memory cells on the conductive vias, the memory cells can be adapted to the concave surface of the conductive vias during the formation process to form a recessed region. Therefore, after a programming signal is applied, the corresponding electric field generated by the RRAM memory device structure will accumulate in the recessed region inside the memory cell, guiding the electric field lines to converge towards the center of curvature of the recessed region. This increases the probability of forming conductive filaments within the predetermined region of the memory cell, achieving the goal of controlling and improving the uniformity and reliability of the electrical performance of the RRAM device.

[0033] Meanwhile, this application significantly improves the performance of RRAM devices by using a multi-component oxide mixture to construct the resistive switching layer and introducing a structural design in which the oxygen barrier layer and the oxygen storage layer work synergistically. Specifically, the oxygen barrier layer effectively suppresses oxygen ion leakage, while the oxygen storage layer dynamically adjusts the oxygen vacancy distribution. Together, they enhance the controllability and stability of the formation and breakage of conductive filaments in the resistive switching layer. The device exhibits a significantly expanded high- and low-resistivity window and a cycle life exceeding 10... 6 Furthermore, it features faster switching speeds and lower operating power consumption, meeting the application requirements of high-density, low-power memories.

[0034] Furthermore, this application constructs a multi-layered composite oxygen barrier around the critical structure (memory cell) of the device by setting a first sidewall isolation layer, a second sidewall isolation layer, and the first isolation layer. This structure effectively blocks the penetration and diffusion of oxygen and moisture from the external environment, thereby inhibiting the oxidation of the electrode material and the degradation of the electrical properties of the resistive switching layer. This synergistic protection mechanism significantly improves the long-term stability and reliability of the device under harsh environments such as high temperature and high humidity, expanding its application potential in a wider range of industrial and consumer electronics scenarios.

[0035] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0036] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figures 1-7 This is a cross-sectional structural schematic diagram illustrating the fabrication process of an RRAM memory device structure according to an embodiment of this application.

[0037] Figure 8 This is a schematic flowchart illustrating the fabrication method of an RRAM memory device structure according to an embodiment of this application.

[0038] 110 Connector layer; 111 First dielectric layer; 112 Conductive via; 113 First via; 200 Storage cell; 210 First electrode; 211 First bottom electrode layer; 212 Second bottom electrode layer; 220 Resistive switching layer; 230 Oxygen barrier layer; 240 Oxygen storage layer; 250 Second electrode; 251 First top electrode layer; 252 Second top electrode layer; 261 First sidewall isolation layer; 262 Second sidewall isolation layer; 310 Hard barrier layer; 320 First isolation layer; 330 First filler layer; 340 Second filler layer; 200' Storage stack layer; 210' First electrode material layer; 220' Resistance switching material layer; 230' Oxygen barrier material layer; 240' Oxygen storage material layer; 250' Second electrode material layer. Detailed Implementation

[0039] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0040] Resistive Random Access Memory Access memory (RRAM) devices store information based on the principle that their resistive switching layer forms or breaks conductive filaments under the action of an electric field. They have the potential to be simple in structure, fast in read and write speed and highly miniaturizable, and are one of the important candidates for the next generation of non-volatile memory technology.

[0041] RRAM devices typically consist of a bottom electrode, a top electrode, and a switching functional layer, such as a resistive switching layer, located between the bottom and top electrodes. Initially, an RRAM device exhibits high resistance, also known as a high-resistance state (HRS). Applying a programming signal (voltage or current) to the bottom and top electrodes causes oxygen ions to migrate through the resistive switching layer under the influence of an electric field, forming a through-wire conductive filament, thus bringing the device into a low-resistance state (LRS). This process, starting from the initial high-resistance state, is called the shaping process; starting from the reset high-resistance state, it is called the setting process. Applying a reset signal causes oxygen ions to migrate back to the resistive switching layer, breaking the conductive filament and restoring the device to the high-resistance state. This allows RRAM devices to reversibly switch between high and low resistance states via a programming signal. In cross-array circuits, the programming signal can be applied to the target RRAM device through a gating device (such as a transistor). Therefore, RRAM device arrays can also be integrated into CMOS circuits to achieve high-density storage and / or in-memory computing applications.

[0042] However, existing RRAM devices generally suffer from unstable conductivity characteristics. The root cause lies in the inherent randomness of the conductive filament formation process. Theoretically, the most ideal formation of conductive filaments is in a uniform location within the resistive switching layer (such as its central region), which helps achieve stable and consistent resistive switching characteristics. However, in actual manufacturing and operation, conductive filaments are prone to non-ideal formation at the edges or sidewalls of the resistive switching layer. These areas are easily damaged during device etching and other fabrication processes, leading to increased material defects and unstable interface states. Consequently, the conductive filaments formed here are structurally fragile and their behavior difficult to control. Furthermore, conductive filaments located at the device edges are more susceptible to penetration and interference from the external environment (such as oxygen atoms), and their resistance state is more prone to drift or failure during cyclic operation or hold-up. These factors collectively cause significant fluctuations in key parameters of RRAM devices based on sidewall conductivity, such as switching voltage, high-to-low resistance ratio, durability, and hold-up characteristics, severely restricting their mass production applications and reliability improvements.

[0043] To address the aforementioned issues, this application provides an RRAM memory device structure and its fabrication method. By providing conductive vias with a predetermined surface curvature R within the interconnect layer, and correspondingly placing memory cells on the conductive vias, the memory cells can adapt to the concave surface of the conductive vias during formation, forming a recessed region. Consequently, after a programming signal is applied, the electric field generated by the RRAM memory device structure will accumulate in the recessed region within the memory cell, guiding electric field lines towards the center of the curvature R of the recessed region. This increases the probability of conductive filaments forming within the predetermined region of the memory cell, achieving the goal of controlling and improving the uniformity and reliability of the RRAM device's electrical performance.

[0044] Based on its first aspect, an RRAM memory device structure is provided, such as Figure 7 As shown, the structure includes a connection layer 110 and at least one storage cell 200. The connection layer 110 includes at least one conductive via 112. The surface of each conductive via 112 near the storage cell 200 is configured as a concave surface with a preset curvature R. The storage cell 200 is disposed on the conductive via 112 of the connection layer 110 and corresponds one-to-one with the conductive via 112. Furthermore, the storage cell 200 also forms a recessed area adapted to the concave surface of the conductive via 112.

[0045] In some embodiments, such as Figure 7 As shown, the connection layer 110 may include a first dielectric layer 111 and at least one first through-hole 113 penetrating the first dielectric layer 111. Conductive through-holes 112 are disposed one-to-one in the first through-holes 113 and fill the first through-holes 113 to electrically connect the storage cell 200 to the lower circuit.

[0046] The first dielectric layer 111 is composed of one or more of the following materials, including but not limited to SiO2, NDC (nitrogen-doped silicon carbide), and PEOX (plasma-enhanced silicon oxide), which can be flexibly adjusted according to the location of the storage unit 200 disposed thereon.

[0047] For example, the first dielectric layer 111 may be a combination of NDC (nitrogen-doped silicon carbide) and PEOX (plasma-enhanced silicon oxide). The portion in contact with the lower circuit layer uses NDC material to enhance the diffusion ability of Cu, while the portion in contact with the memory cell 200 uses PEOX material to improve the interfacial adhesion between the first dielectric layer 111 and the memory cell 200. This balances insulation performance with compatibility with subsequent processes, solves the problem of single function and poor adaptability of existing insulating layers, and provides a stable substrate for the fabrication of conductive vias 112.

[0048] For example, the thickness of the first dielectric layer 111 ranges from 150 Å to 2000 Å.

[0049] The conductive via 112 is composed of one or more low-resistance conductive materials, including but not limited to elemental metals, metal nitrides, and metal oxides. Specifically, it can be selected and matched according to the characteristics of the electrode material in contact with the storage cell 200 to improve interface conductivity and bonding strength while strictly controlling the contact resistance below 5Ω. This ensures reliable electrical connection between the conductive via 112 and the storage cell 200, solving the problems of high contact resistance and poor stability in existing conductive vias 112.

[0050] For example, the elemental metals constituting the conductive via 112 include one or more conductive metal materials such as Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, and W; the metal nitrides constituting the conductive via 112 include one or more of TiN, TaN, and AlN; and the metal oxynitrides constituting the conductive via 112 include one or more of TiON, TaON, and AlON.

[0051] For example, the thickness of the conductive via 112 ranges from 150 Å to 2000 Å. Furthermore, the maximum depth of the recessed surface where the conductive via 112 contacts the memory cell 200 should not exceed the thickness of the conductive via 112, so as to ensure the stable formation of the recessed area inside the memory cell 200 while ensuring the contact characteristics between the memory cell 200 and the conductive via 112.

[0052] It should be noted that the memory cell 200 of the RRAM memory device structure is typically fabricated in the first metal layer (M). n ) and the second metal layer (M) n+1 Between ), where Mn M represents a metallization layer located at the bottom of memory cell 200 and close to memory cell 200. n+1 It is located at the top of storage cell 200, and is also located in the first level of metallization layer of storage cell 200. Where, n≥1.

[0053] The lower-level circuitry carrying the first connection layer 110 typically refers to the first interconnect, which in turn includes the M circuitry located near the memory cell 200. n The end of the conductive via 112 furthest from the storage cell 200 is connected to M. n This enables the electrical connection between the storage unit 200 and the first interconnect structure.

[0054] Similarly, the storage unit 200 should also include a second interconnect, which in turn includes M arranged on the side closest to the storage unit 200. n+1 The top end of storage cell 200 near the second interconnect is connected to M n+1 The connection is made so as to realize the electrical connection between the storage cell 200 and the second interconnection structure.

[0055] Thus, the RRAM memory device structure can be fabricated during the fabrication of the first and second interconnects, thereby achieving compatibility between RRAM devices and CMOS.

[0056] For example, each first interconnect or second interconnect can provide an electrical connection between a transistor and one or more other semiconductor devices, which refer to one or more other transistors, or one or more other RRAM devices, etc. Multiple RRAM memory device structures can be shared on the first interconnect and connected to the same M... n To achieve electrical connection, the second interconnect is shared across multiple RRAM memory device structures, and utilizes the M of the second interconnect. n+1 Multiple RRAM memory device structures are electrically connected. Programming signals can then be applied to both ends of the RRAM memory device structure via a first interconnect and a second interconnect, thereby enabling reversible electrical switching between a high-resistance state and a low-resistance state for the array of multiple RRAM memory device structures.

[0057] In some embodiments, the storage unit 200 includes a first electrode 210, a resistive switching layer 220, and a second electrode 250 sequentially stacked on the connection layer 110. The first electrode 210 and the second electrode 250 serve as the two poles of the storage unit 200, respectively handling electrical signal input and output, providing the conductive electrode basis for the intermediate resistive switching layer 220. The resistive switching layer 220, as the core functional layer for data storage and retrieval in the storage unit 200, can undergo a reversible resistance change under the action of an applied programming signal, thereby enabling the storage unit 200 to perform data writing, erasing, and reading.

[0058] A resistive switching layer 220 is formed between the first electrode 210 and the second electrode 250. It completes the formation and breakage of conductive filaments in response to externally input programming signals, thereby realizing reversible switching between high and low resistance states. Since the memory cell 200 also includes a recessed region adapted to the concave surface of the conductive via 112, the resistive switching layer 220 includes a recessed portion recessed towards the side close to the first electrode 210, and a horizontal extension portion surrounding the periphery of the recessed portion.

[0059] The recessed portion is configured to be recessed towards the side closer to the first electrode 210, so that the resistive switching layer 220 can form a directional constraint on the migration of oxygen ions and the aggregation of oxygen vacancies driven by the programming signal. This allows the growth and melting process of the conductive filaments to be limited within a preset position range corresponding to the recessed portion, avoiding the problem of random formation and breakage of conductive filaments in traditional planar resistive switching layers 220, and effectively improving the consistency and repeatability of high and low resistance state switching of the memory cell 200.

[0060] Meanwhile, the horizontal extension surrounding the recessed portion can also provide stable structural support for the recessed portion, ensuring the structural integrity and stability of the entire resistive switching layer 220, and maintaining the effective contact area between the resistive switching layer 220 and the upper and lower electrodes. This ensures stable transmission of the switching signal between the first electrode 210, the resistive switching layer 220, and the second electrode 250, providing a reliable electrical basis for the precise control of the position range of the conductive filament in the recessed portion.

[0061] Furthermore, the storage unit 200 also includes an oxygen barrier layer 230, which is disposed between the resistive switching layer 220 and the second electrode 250. This oxygen barrier layer 230 can effectively suppress the migration and loss of oxygen ions in the resistive switching layer 220 towards the second electrode 250, and avoid the imbalance of oxygen vacancy concentration in the resistive switching layer 220 due to abnormal migration of oxygen ions, thereby preventing abnormal growth, melting or displacement of the conductive filament.

[0062] In addition, the oxygen barrier layer 230 can reduce the interface degradation between the resistive switching layer 220 and the second electrode 250 caused by oxygen ion migration, and maintain the long-term stability of the oxygen vacancy concentration in the resistive switching layer 220. This not only further improves the consistency and repeatability of high and low resistance state switching, but also effectively extends the cycle life and storage reliability of the storage unit 200, laying a solid foundation for the resistive switching storage performance of the entire storage unit 200 from the perspective of ion regulation.

[0063] Furthermore, the storage unit 200 also includes an oxygen storage layer 240, which is disposed between the oxygen barrier layer 230 and the second electrode 250. The oxygen storage layer 240 can realize dynamic replenishment and precise control of oxygen ions, and works synergistically with the oxygen barrier layer 230 to further improve the oxygen ion control system of the storage unit 200. Combined with the structured design of the resistive switching layer 220, it fundamentally ensures the long-term stability of the oxygen vacancy concentration in the resistive switching layer 220, and significantly improves the long-term performance and operational reliability of the resistive switching of the storage unit 200.

[0064] In the stacking direction of the storage cell 200, the vertical projection of the oxygen storage layer 240 is located within the vertical projection plane of the resistive switching layer 220 and the oxygen barrier layer 230, and the projected area is smaller than the projected area of ​​the resistive switching layer 220 and the oxygen barrier layer 230. For example, the projected range is slightly larger than the recess of the resistive switching layer 220, so that the oxygen ions released by the oxygen storage layer 240 can be directionally focused on the recess of the resistive switching layer 220, avoiding the random diffusion of oxygen ions in the resistive switching layer 220, realizing the precise replenishment of oxygen vacancies, and keeping the oxygen vacancy concentration in the recess at the optimal range for the formation and breakage of conductive filaments, further improving the controllability of the evolution of conductive filaments and the consistency of high and low resistance state switching.

[0065] For example, the thickness of the resistive switching layer 220 ranges from 10 Å to 2000 Å, the thickness of the oxygen barrier layer 230 ranges from 10 Å to 500 Å, and the thickness of the oxygen storage layer 240 ranges from 10 Å to 2000 Å.

[0066] For example, the resistive switching layer 220 is composed of one or more of oxide materials such as HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, WO3, HfSiO, HfTaO, HfZrO, and HfAlO.

[0067] The oxygen barrier layer 230 is composed of one or more of the following metal oxides: HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, HfSiO, HfTaO, HfZrO, and HfAlO; or, it is composed of one or more of the following metal nitrides: TiN, TaN, and AlN; or, it is composed of one or more of the following metal nitrides: TiON, TaON, and AlON.

[0068] The oxygen storage layer 240 is composed of one or more conductive metallic materials selected from Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, and W; or, it is composed of TiO2. x TaO x HfO x ZrO x AlO x WO x NiO xIt is composed of one or more of the following metal oxides; or, one or more of the following metal nitrides; or, one or more of the following metal nitrides: TiON, TaON, AlON, etc.

[0069] It should be noted that the specific curvature R range of the concave surface that causes the recess or recessed area to form is not specifically limited above, and can be flexibly configured according to the thickness range of each stacked layer in the memory cell 200. Conversely, in other embodiments, the curvature R of the concave surface of the conductive via 112 is 0, that is, the surface of the conductive via 112 near the first electrode 210 is a horizontal plane, so that the memory cell 200 has no adapted recessed area. The interaction between the resistive switching layer 220, the oxygen barrier layer 230, and the oxygen storage layer 240 can also limit the location range of the conductive filaments to a certain extent, improving the reliability of the RRAM memory device structure.

[0070] Furthermore, the oxygen barrier layer 230 and oxygen storage layer 240 materials in the above examples are merely illustrative and should not be construed as limiting the scope of this application. For instance, in other examples, the oxygen barrier layer 230 can also employ a fluorinated graphene material system with a higher oxygen diffusion barrier energy barrier instead of traditional oxide or nitride barrier materials. Its advantage lies in its ability to more effectively impede the migration of oxygen ions / oxygen atoms, exhibiting significantly superior oxygen barrier performance compared to common oxide / nitride stacks or composite structures. The oxygen storage layer 240 can also employ a rare earth oxide material system (such as CeO2, Y2O3, etc.) instead of traditional transition metal oxides. Its advantage lies in the higher oxygen storage capacity and superior oxygen ion migration kinetics of rare earth oxides, enabling more efficient controllable storage and release of oxygen ions. This allows for dynamic adjustment of the oxygen vacancy concentration and distribution in the resistive switching layer 220, improving the controllability and stability of the resistive switching operation.

[0071] The first electrode 210 is formed as the bottom electrode on the interconnect layer 110 and contacts the conductive via 112 to achieve electrical connection with the first interconnect. The second electrode 250 is formed as the top electrode on the resistive switching layer 220 (or oxygen barrier layer 230 or oxygen storage layer 240) and is electrically connected to the second interconnect.

[0072] The first electrode 210 and the second electrode 250 are composed of one or more low-resistance conductive materials, including but not limited to elemental metals, metal nitrides, and metal oxynitrides. Specifically, they can be matched and selected based on the characteristics of the resistive switching layer 220 in contact with them to improve interfacial conductivity and regulate oxygen ion migration.

[0073] For example, the first electrode 210 includes at least a first bottom electrode layer 211, and the second electrode 250 includes at least a first top electrode. The first bottom electrode layer 211 is formed on the connecting layer 110 and has a thickness ranging from 10 Å to 1500 Å. The first top electrode is formed on the resistive switching layer 220 and has a thickness ranging from 10 Å to 2000 Å.

[0074] For example, the first bottom electrode layer 211 and the first top electrode layer 251 may be made of the same or different materials. Specifically, they may be composed of one or more conductive metal materials such as Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, and W; or, they may be composed of TiO2. x TaO x HfO x ZrO x AlO x WO x IrO x NiO x It consists of one or more of the following metal oxide materials: TiN, TaN, AlN, etc.; or TiON, TaON, AlON, etc.

[0075] For example, the first electrode 210 further includes a second bottom electrode layer 212. The second bottom electrode layer 212 is formed between the first bottom electrode layer 211 and the resistive switching layer 220, and has a thickness ranging from 10 Å to 200 Å, which can improve the oxidation resistance and resistive switching stability of the first electrode 210 to a certain extent.

[0076] The second electrode 250 also includes a second top electrode layer 252. The second top electrode layer 252 is formed on the first top electrode layer 251, with a thickness ranging from 10 Å to 200 Å. It can be compatible to some extent with the subsequently formed barrier layer and improves the etching capability of the second electrode 250, thereby facilitating the etching of the M interconnect with the second electrode. n+1 Electrical connections form a stable connection window, providing stable support.

[0077] For example, the second top electrode layer 252 is composed of one or more metal nitride materials such as TiN, TaN, and AlN.

[0078] In some embodiments, the storage unit 200 further includes a first sidewall isolation layer 261 disposed on the sidewall of the oxygen storage layer 240 and a second sidewall isolation layer 262 disposed on the sidewall of the second electrode 250. The first sidewall isolation layer 261 covers the exposed sidewall surface of the oxygen storage layer 240, and the second sidewall isolation layer 262 covers the exposed sidewall surface of the second electrode 250.

[0079] The first sidewall isolation layer 261 completely covers the exposed sidewall surface of the oxygen storage layer 240. On the one hand, it provides physical protection for the oxygen storage layer 240, preventing its sidewall from being eroded by the environment or damaged by the process during device fabrication or operation, maintaining the structural integrity of the oxygen storage layer 240, and ensuring the stability of its oxygen ion storage and directional release. On the other hand, it can achieve electrical isolation, preventing unnecessary electrical contact between the sidewall of the oxygen storage layer 240 and the surrounding device structure, avoiding the generation of stray currents, and blocking the path of abnormal loss of oxygen ions from the sidewall of the oxygen storage layer 240 or doping by external impurities. This ensures that the oxygen ions of the oxygen storage layer 240 are only directionally released along the stacking direction to the oxygen barrier layer 230 and the resistive switching layer 220, ensuring the targeted and accurate storage and replenishment of oxygen ions.

[0080] The second sidewall isolation layer 262 fully covers the exposed sidewall surface of the second electrode 250, which can also prevent leakage and electrical crosstalk between the sidewall of the second electrode 250 and other structures, ensuring the electrical transmission stability of the second electrode 250 as the signal output electrode of the storage unit 200, preventing stray currents from interfering with the formation and breakage process of the conductive filaments in the resistive switching layer 220, and ensuring the accuracy of resistive state switching; at the same time, it can also prevent oxidation and wear of the sidewall of the second electrode 250 from causing the conductivity to decay, and maintain the long-term stable conductivity of the second electrode 250.

[0081] For example, the thickness of the first sidewall isolation layer 261 and the second sidewall isolation layer 262 in the horizontal direction ranges from 1 Å to 500 Å.

[0082] For example, the first sidewall isolation layer 261 and the second sidewall isolation layer 262 may be made of the same or different materials; specifically, they may be made of TiO2. x TaO x HfO x ZrO x AlO x WO x NiO x It consists of one or more of the following metal oxide materials: TiN, TaN, AlN, etc.; or TiON, TaON, AlON, etc.

[0083] In some embodiments, the memory cell 200 is further provided with a hard barrier layer 310. The hard barrier layer 310 is disposed on the second electrode 250 and includes a second through-hole exposing a portion of the second electrode 250, and a second interconnect M n+1 The second through hole is filled and contacts the second electrode 250 to form an electrical connection with the storage cell 200.

[0084] For example, the hard barrier layer 310 may specifically be composed of one or more of SiON, Si3N4, PEOX (plasma-enhanced silicon oxide), TiN, etc.

[0085] For example, the thickness of the hard barrier layer 310 ranges from 10 Å to 8000 Å.

[0086] In some embodiments, a first isolation layer 320 is further provided on the connection layer 110 between adjacent storage cells 200. The first isolation layer 320 covers the exposed surface of the connection layer 110 between adjacent storage cells 200 and extends vertically upward along the sidewall of the storage cell 200, covering the sidewall of the storage cell 200 and the hard barrier layer 310.

[0087] The first isolation layer 320 is disposed on the connection layer 110 between adjacent storage cells 200. It not only covers the exposed surface of the connection layer 110 between storage cells 200, but also extends vertically upward along the sidewall of the storage cell 200 and fully covers the sidewall. This achieves electrical isolation and physical protection between adjacent storage cells 200. It blocks electrical crosstalk formed between adjacent cells through the connection layer 110 and the sidewall, ensuring that each cell works independently, while also protecting the connection layer 110 and the sidewall of the storage cell 200 from damage and maintaining structural integrity. At the same time, it forms a synergistic protection with the sidewall isolation layer inside the storage cell 200, without intruding into functional areas or affecting the normal operation of a single storage cell 200, further adapting to the integrated layout requirements of the storage cell 200 array.

[0088] For example, the first insulating layer 320 may specifically be composed of oxides such as HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, etc., or SiN. x The composition may include one or more of nitrides, TEOS (tetraethylsilane), and other oxygen-dispersing materials; or, SiO2 may be used. x / AlO x The composite layer of materials is designed to balance oxygen barrier properties with structural flexibility, and can also reduce cracking caused by process stress.

[0089] For example, the thickness of the first isolation layer 320 ranges from 10 Å to 500 Å.

[0090] Furthermore, a first filling layer 330 and a second filling layer 340 are also provided on the first isolation layer 320 between adjacent storage cells 200.

[0091] The first filling layer 330 is used to fill the gap between adjacent storage cells 200 to ensure that there are no obvious holes. It is especially suitable for storage cells 200 with a high aspect ratio, thereby achieving isolation between storage cells 200 and surface flattening.

[0092] For example, the first filling layer 330 may be composed of one or more of TEOS (tetraethylsilane) or OSG (organic silica glass); or, porous SiO2 with a lower dielectric constant and better signal crosstalk suppression effect may be used.

[0093] The second filler layer 340 is formed on the first filler layer 330 to fill the gap between the second interconnect and the first filler layer 330, thereby realizing the second metal layer M. n+1 Insulation and isolation from the underlying structure effectively reduce M n+1 Inter-signal crosstalk, working in conjunction with the first filler layer 330 to ensure consistency of subsequent processes.

[0094] For example, the second filler layer 340 may specifically be composed of OSG (organic silica glass).

[0095] According to a second aspect of this application, a method for fabricating an RRAM memory device structure is also provided, such as... Figures 1-8 As shown, the method includes the following steps: Step S1, providing the first interconnection.

[0096] The first interconnect refers to a connection substrate on which connection circuitry has been embedded, enabling electrical connection between a transistor and one or more other semiconductor devices, and multiple transistors or other semiconductor devices can be connected to the same M on the first interconnect. n Electrical connections are achieved. Since these semiconductor devices are all existing technologies, and the fabrication methods are commonly used in this field, they will not be elaborated upon here.

[0097] Step S2: A connection layer 110 is formed on the first interconnect. The connection layer 110 includes at least one conductive via 112. The surface of the conductive via 112 away from the first interconnect is a concave surface with a preset curvature R.

[0098] like Figure 1 and Figure 2 As shown, in the step of forming the interconnect layer 110, a first dielectric layer 111 can first be deposited on the first interconnect using a PECVD process, such as a stack composed of NDC (nitrogen-doped silicon carbide) and PEOX (plasma-enhanced silicon oxide), wherein PEOX (plasma-enhanced silicon oxide) is deposited on NDC (nitrogen-doped silicon carbide).

[0099] Then, a patterned etching process is used, for example, photolithography is used to form a first via 113 penetrating the first dielectric layer 111, and each first via 113 exposes the M on the first interconnect. n Part of the surface.

[0100] Next, a CVD / PVD process is used to deposit a metal material into the first through-hole 113 to form a metal material layer, such as TiN and TaN, filling the first through-hole 113.

[0101] Finally, the surface of the metal material layer is ground to create a concave surface with a certain curvature R, thereby forming a conductive via 112.

[0102] Step S3: A storage stack layer 200' is formed on the connection layer 110.

[0103] like Figure 3 As shown, the step of forming the storage stack layer 200' includes using a deposition process to sequentially stack a first electrode material layer 210', a resistive switching material layer 220', and a second electrode material layer 250' on the interconnect layer 110. Alternatively, the first electrode material layer 210', the resistive switching material layer 220', the oxygen barrier material layer 230', the oxygen storage material layer 240', and the second electrode material layer 250' can be sequentially stacked on the interconnect layer 110.

[0104] The storage stack layer 200' can be formed by deposition using PVD, CVD, sputtering deposition, ALD and / or any other suitable deposition techniques and combinations thereof.

[0105] Step S4: Pattern the storage stack layer 200' to form at least one storage cell 200. Each storage cell 200 corresponds to a conductive via 112 and is adapted to the concave surface to form a recessed area.

[0106] like Figure 4 As shown, before the step of patterning and etching the memory stack layer 200', a hard barrier material layer, such as a hard barrier material layer composed of Si3N4, is first formed on the memory stack layer 200' using a PECVD process.

[0107] Then, as Figure 5 As shown, the hard barrier material layer and the storage stack layer 200' below it are selectively etched using wet, dry or plasma etching methods until the portion of the first dielectric layer 111 between adjacent conductive vias 112 is exposed, thereby forming a plurality of storage cells 200 with a preset spacing in the horizontal direction, and a hard barrier layer 310 on the storage cells 200, and each storage cell 200 and each conductive via 112 are in one-to-one correspondence.

[0108] Furthermore, after the step of forming a hard barrier material layer on the storage stack layer 200', it should also include patterning etching using the hard barrier material layer formed on the storage stack layer 200', and the etching pattern of the patterned etching corresponds to the position of the conductive via 112, so as to form a second via on the hard barrier material layer that exposes part of the electrode surface of the storage cell 200.

[0109] The step of forming a second via on the hard barrier material layer by etching can be performed before or after the step of patterning etching of the memory stack layer 200' to form at least one memory cell 200. This application does not specifically limit this step.

[0110] Furthermore, after the step of patterning and etching the storage stack layer 200' to form at least one storage cell 200, the method further includes high-temperature oxidation of the sidewalls of the oxygen storage layer 240 formed after patterning and etching the oxygen storage material layer 240' to form a first sidewall isolation layer 261 on the sidewalls of the oxygen storage layer 240; and high-temperature oxidation of the sidewalls of the second electrode 250 formed after patterning and etching the second electrode material layer 250' to form a second sidewall isolation layer 262 on the sidewalls of the second electrode 250.

[0111] S5, a first isolation layer 320 is formed on the sidewall of the storage cell 200 and on the connection layer 110 between adjacent storage cells 200.

[0112] like Figure 6 As shown, the step of forming the first isolation layer 320 may include using an ALD process to deposit TEOS (tetraethylsilane) material on the surface of the etched interconnect layer 110, as well as on the sidewalls of the memory cell 200 and the hard barrier layer 310, and to cover the sidewalls of the memory cell 200 to block external oxygen atoms from entering the memory cell 200 and to prevent sidewall film oxidation and interface failure, thereby enhancing the overall structural stability of the device and avoiding damage to the device caused by subsequent filling and polishing processes.

[0113] S6, a first filling layer 330 is formed on the first isolation layer 320 between adjacent storage cells 200.

[0114] like Figure 7 As shown, the steps for forming the first filling layer 330 firstly include depositing TEOS (tetraethylsilane) material or OSG (organic silica glass) material on the first isolation layer 320 between adjacent memory cells 200 using a PECVD process to form a first filling material layer. Then, an etching process is used to selectively etch and remove the portion of the first isolation layer and the first filling material layer that is higher than the memory cell 200 to form the first filling layer 330 with a surface height not higher than the memory cell 200.

[0115] S7 forms a second interconnect on the storage unit 200.

[0116] like Figure 7 As shown, the second interconnect refers to a connection substrate containing pre-embedded connection circuitry that can electrically connect a transistor to one or more other semiconductor devices, and multiple transistors or other semiconductor devices can be connected to the same M on the second interconnect. n+1 Electrical connections are achieved. Since these semiconductor devices are all existing technologies, and the fabrication methods are commonly used in this field, they will not be elaborated upon here.

[0117] Among them, the second interconnection of M n+1 Formed within the second through hole and filled to allow the M of the second interconnection to... n+1 It can make contact with the second electrode 250 exposed by the second through hole to form an electrical connection.

[0118] Among them, in the formation of the second interconnection M n+1 Following this step, the process further includes depositing OSG (organic silica glass) material onto the first filling layer 330 between adjacent memory cells 200 using a PECVD process to form a second filling layer 340, thereby completing the M on adjacent memory cells 200. n+1 The basic isolation between devices and the further filling of gaps between devices provide a flat substrate for the subsequent deposition of the second interconnect and the functional layers on it.

[0119] It should be noted that for details in the second aspect of the RRAM memory device structure fabrication method that are omitted above, please refer to the RRAM memory device structure in the first aspect, and they will not be repeated here.

[0120] In summary, this application provides an RRAM memory device structure and its fabrication method. By providing a connection layer 110 and forming conductive vias 112 with a preset surface curvature within the connection layer 110, and by correspondingly placing memory cells 200 on the conductive vias 112, the memory cells 200 can adapt to the concave surface of the conductive vias 112 during the formation process, forming a recessed region. Therefore, after a programming signal is applied, the electric field generated by the RRAM memory device structure will accumulate in the recessed region inside the memory cell 200, guiding the electric field lines to converge towards the center of curvature of the recessed region. This increases the probability of conductive filaments forming within the preset region of the memory cell 200, achieving the goal of controlling and improving the uniformity and reliability of the electrical performance of the RRAM device.

[0121] Meanwhile, this application significantly improves the performance of the RRAM device by using a multi-component oxide mixture to construct the resistive switching layer 220 and introducing a structural design in which the oxygen barrier layer 230 and the oxygen storage layer 240 work synergistically. Specifically, the oxygen barrier layer 230 effectively suppresses oxygen ion leakage, and the oxygen storage layer 240 can dynamically adjust the oxygen vacancy distribution. Together, they enhance the controllability and stability of the formation and breakage of conductive filaments in the resistive switching layer 220. The device exhibits a significantly expanded high- and low-resistivity window and a cycle life exceeding 10... 6 Furthermore, it features faster switching speeds and lower operating power consumption, meeting the application requirements of high-density, low-power memories.

[0122] Furthermore, this application constructs a multi-layered composite oxygen barrier around the critical structure of the device (memory cell 200) by setting a first sidewall isolation layer 261, a second sidewall isolation layer 262, and a first isolation layer 320. This structure effectively blocks the penetration and diffusion of oxygen and moisture from the external environment, thereby inhibiting the oxidation of the electrode material and the degradation of the electrical properties of the resistive switching layer 220. This synergistic protection mechanism significantly improves the long-term stability and reliability of the device under harsh environments such as high temperature and high humidity, expanding its application potential in a wider range of industrial and consumer electronics scenarios.

[0123] In the foregoing descriptions of the embodiments, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0124] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

Claims

1. An RRAM storage device structure, characterized in that, include: The connection layer includes at least one conductive via; At least one storage cell is disposed on the connection layer and corresponds one-to-one with the conductive via; The surface of the conductive via near the storage cell is configured as a concave surface with a preset curvature. The storage cell is disposed on the conductive via and forms a recessed area that is adapted to the concave surface.

2. The structure according to claim 1, characterized in that, The storage unit includes: The first electrode is disposed on the connecting layer and covers the concave surface corresponding to the conductive via. A resistive switching layer is disposed on the first electrode; The second electrode is disposed on the resistive switching layer; The resistive switching layer includes a recessed portion that is recessed towards the side close to the first electrode, and a horizontally extending portion that surrounds the periphery of the recessed portion, wherein the recessed portion is located within the recessed region.

3. The structure according to claim 2, characterized in that, The storage unit further includes an oxygen barrier layer and / or an oxygen storage layer, wherein the oxygen barrier layer is disposed on the resistive switching layer and the oxygen storage layer is disposed on the oxygen barrier layer.

4. The structure according to claim 3, characterized in that, The thickness of the resistive switching layer ranges from 10 Å to 2000 Å, the thickness of the oxygen barrier layer ranges from 10 Å to 500 Å, and the thickness of the oxygen storage layer ranges from 10 Å to 2000 Å.

5. The structure according to claim 3, characterized in that, The storage unit includes an oxygen barrier layer and an oxygen storage layer stacked sequentially on the resistive switching layer; wherein, the vertical projection of the oxygen storage layer in the stacking direction of the storage unit is located within the vertical projection plane of the resistive switching layer and the oxygen barrier layer, and the projected area is smaller than the projected area of ​​the resistive switching layer and the oxygen barrier layer.

6. The structure according to claim 5, characterized in that, The storage unit further includes a first sidewall isolation layer disposed on the sidewall of the oxygen storage layer and a second sidewall isolation layer disposed on the sidewall of the second electrode; wherein the first sidewall isolation layer covers the exposed sidewall surface of the oxygen storage layer, and the second sidewall isolation layer covers the exposed sidewall surface of the second electrode.

7. The structure according to claim 6, characterized in that, The thickness of the first sidewall isolation layer and the second sidewall isolation layer ranges from 1 Å to 500 Å.

8. The structure according to claim 2, characterized in that, The first electrode includes at least a first bottom electrode layer, and the second electrode includes at least a first top electrode layer; wherein the thickness of the first bottom electrode layer ranges from 10 Å to 1500 Å, and the thickness of the first top electrode layer ranges from 10 Å to 2000 Å.

9. The structure according to claim 8, characterized in that, The first electrode further includes a second bottom electrode layer, the thickness of which ranges from 10 Å to 200 Å.

10. The structure according to claim 8, characterized in that, The second electrode also includes a second top electrode layer, the thickness of which ranges from 10 Å to 1000 Å.

11. The structure according to claim 1, characterized in that, The thickness of the conductive via ranges from 150 Å to 2000 Å, and the maximum depth of the concave surface is not greater than the thickness of the conductive via.

12. The structure according to claim 1, characterized in that, The connection layer includes a first dielectric layer and at least one first through hole penetrating the first dielectric layer. The conductive through holes are disposed one-to-one in the first through holes and fill the first through holes.

13. The structure according to claim 1, characterized in that, The connection layer is further provided with a first isolation layer, which covers the exposed surface of the connection layer near the storage unit and extends vertically upward to cover the side wall of the storage unit.

14. The structure according to claim 2, characterized in that, Also includes: The first interconnect includes a first metal layer disposed on the side close to the memory cell, and the conductive via is disposed on the first metal layer at the end away from the memory cell, electrically connecting the first electrode to the first interconnect. The second interconnect includes a second metal layer disposed on the side near the memory cell, and the second metal layer is disposed on the second electrode, electrically connecting the second electrode to the second interconnect.

15. The structure according to claim 14, characterized in that, The storage unit is further provided with a hard barrier layer, which is disposed on the second electrode and includes a second through hole that exposes part of the second electrode. The second metal layer is disposed on the second through hole and contacts the second electrode exposed by the second through hole to form an electrical connection.

16. A method for fabricating an RRAM memory device structure, characterized in that, include: Provide first-hand interconnection; A connection layer is formed on the first interconnect, the connection layer including at least one conductive via, and the surface of the conductive via away from the first interconnect is a concave surface with a preset curvature. A storage stack layer is formed on the connection layer; The memory stack layer is patterned and etched to form at least one memory cell, each memory cell corresponding to one of the conductive vias and adapted to the concave surface to form a recessed area; A first isolation layer is formed on the sidewall of the storage cell and on the connection layer between adjacent storage cells; A first filling layer is formed on the first isolation layer between adjacent storage cells; A second interconnect is formed on the storage unit.

17. The method according to claim 16, characterized in that, The step of forming a connection layer on the first interconnect includes: A first dielectric layer is formed on the first interconnect; At least one first via is etched on the first dielectric layer, and the first via exposes a portion of the first metal layer of the first interconnect. Deposit metallic material into the first through hole to fully fill the first through hole; The metal material deposited in the first through hole is surface-polished to form the conductive through hole with the concave surface.

18. The method according to claim 16, characterized in that, The step of forming a storage stack layer on the conductive via includes: A first electrode material layer is formed on the conductive via; A resistive switching material layer is formed on the first electrode; A second electrode material layer is formed on the resistive switching material layer.

19. The method according to claim 18, characterized in that, After the step of forming a resistive switching material layer on the first electrode, the method further includes: An oxygen barrier material layer is formed on the resistive switching material layer; and, An oxygen storage material layer is formed on the oxygen barrier material layer; The second electrode material layer is formed on the oxygen storage material layer.

20. The method according to claim 18, characterized in that, After the step of forming the second electrode material layer on the resistive switching material layer, the method further includes: A barrier material layer is formed on the second electrode material layer; and, The barrier material layer is patterned and etched to form a window on the barrier material layer that exposes a portion of the second electrode material layer; The location where the window is formed corresponds one-to-one with the location where the conductive via is formed.

21. The method according to claim 19, characterized in that, After the step of patterning and etching the memory stack layer to form at least one memory cell, the method further includes: The sidewalls of the oxygen storage layer, formed by patterned etching of the oxygen storage material layer, are subjected to high-temperature oxidation to form a first sidewall isolation layer on the sidewalls of the oxygen storage layer; and, The sidewalls of the second electrode, formed by patterning and etching the second electrode material layer, are subjected to high-temperature oxidation to form a second sidewall isolation layer on the sidewalls of the second electrode.

22. The method according to claim 20, characterized in that, The step of forming a first filling layer on the first isolation layer between adjacent memory cells includes: A first filling material layer is formed on the first isolation layer deposited between adjacent memory cells; and, The first isolation layer and the first filling material layer located above the memory cell are selectively etched away using an etch rollback process.

23. The method according to claim 18, characterized in that, The first electrode material layer or the second electrode material layer is composed of one or more conductive metal materials selected from Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, and W. Or, from TiO x TaO x HfO x ZrO x AlO x WO x NiO x It is composed of one or more metal oxides; Alternatively, it may be composed of a mixture of one or more metal nitrides selected from TiN, TaN, and AlN; Alternatively, it can be composed of one or more metal nitrides selected from TiON, TaON, and AlON.

24. The method according to claim 19, characterized in that, The resistive switching material layer is composed of one or more of the following: HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, WO3, HfSiO, HfTaO, HfZrO, and HfAlO.

25. The method according to claim 19, characterized in that, The oxygen barrier material layer is composed of one or more metal oxides selected from HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, HfSiO, HfTaO, HfZrO, and HfAlO. Alternatively, it may be composed of a mixture of one or more metal nitrides selected from TiN, TaN, and AlN; Alternatively, it can be composed of one or more metal nitrides selected from TiON, TaON, and AlON.

26. The method according to claim 19, characterized in that, The oxygen storage layer is composed of one or more conductive metallic materials selected from Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, and W. Or, from TiO x TaO x HfO x ZrO x AlO x WO x NiO x It is composed of one or more metal oxides; Alternatively, it may be composed of a mixture of one or more metal nitrides selected from TiN, TaN, and AlN; Alternatively, it can be composed of one or more metal nitrides selected from TiON, TaON, and AlON.

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