A SiC packaging structure based on flip chip
By using a flip-chip and copper sintered layer packaging structure, the thermoelectric separation and contact resistance problems of SiC devices are solved, achieving efficient heat dissipation and high integration, thereby improving the reliability and lifespan of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- JIANGSU XINGAN TECH CO LTD
- Filing Date
- 2025-05-27
- Publication Date
- 2026-07-03
Smart Images
Figure CN224460555U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of silicon carbide technology, and in particular to a SiC packaging structure based on chip flip-chip. Background Technology
[0002] With the rapid development of third-generation semiconductor materials (such as SiC and GaN), their advantages in high power density, high frequency, and high efficiency have led to their widespread application in renewable energy fields such as wind power, photovoltaics, and energy storage. However, existing packaging technologies still face many challenges when applied to high-power-density SiC devices. First, the traditional sandwich packaging structure fails to achieve effective thermoelectric separation, resulting in a significant temperature difference between the device junction and case, leading to a substantial heat concentration effect that impacts device reliability and lifespan. Second, to reduce operating temperature and improve load capacity, existing technologies typically employ a multi-tube parallel structure. However, due to the large variability in device parameters, the failure rate is high when tubes are connected in parallel, resulting in poor reliability. Furthermore, existing packaging often relies on physically increasing electrode creepage distances to meet insulation requirements in high-voltage insulation designs. This not only occupies a large packaging space but also limits the miniaturization and high integration of devices. Simultaneously, traditional packaging processes use ohmic contacts, resulting in high contact resistance, further limiting the improvement of current carrying capacity. Finally, existing packaging structures also exhibit significant thermal stress and thermal yielding effects, further exacerbating device performance degradation and failure risks. Therefore, to address the above issues, a novel packaging process is urgently needed to optimize the heat dissipation performance, interconnect reliability, and high-voltage insulation capability of SiC devices, thereby meeting the requirements of high power density applications. Utility Model Content
[0003] The present invention aims to provide a SiC packaging structure based on chip flip-chip to overcome the shortcomings of the prior art. The technical problem to be solved by the present invention is achieved through the following technical solution.
[0004] A SiC packaging structure based on flip-chip bonding includes a heat sink and a SiC substrate disposed on the heat sink. The SiC substrate has a bottom copper electrode formed on its surface, and the bottom copper electrode is connected to the SiC substrate via a bonding layer. Multiple chips connected in parallel are disposed on the bottom copper electrode, and a top copper electrode is connected to the top of the multiple parallel chips. Both the bottom copper electrode and the multiple parallel chips, as well as the top copper electrode and the multiple parallel chips, are connected via copper sintering layers.
[0005] Furthermore, the bonding layer is at least one metallic material selected from titanium, nickel, or silver, or a multilayer structure formed by a combination thereof.
[0006] Furthermore, the thickness of the copper sintered layer is 5 micrometers to 20 micrometers.
[0007] Furthermore, the thicknesses of the top copper electrode and the bottom copper electrode are 20 micrometers to 100 micrometers, respectively.
[0008] This invention achieves the following technical effects: First, by using a flip-chip approach instead of traditional aluminum wires, copper wires, or copper CLIP (Copper Local Interconnect Process) for electrode interconnection, it effectively reduces contact resistance, improves current carrying capacity, and meets the needs of high power density applications. Second, by optimizing the package structure design and extending the electrodes to both sides or the top, it not only avoids the traditional method of increasing creepage distance to meet high-voltage insulation, but also significantly reduces the package size, improving the miniaturization and high integration level of the device. Furthermore, by forming a metal bonding layer on the SiC substrate surface through ion-plated copper technology, it further reduces contact resistance and improves the stability and reliability of electrical connections. Finally, the package structure adopts a three-dimensional heat dissipation design, achieving thermoelectric separation, effectively reducing heat concentration effects, improving the heat dissipation performance of the device, thereby extending the device's lifespan and ensuring its reliable operation in high-power, high-frequency scenarios. Attached Figure Description
[0009] Figure 1 This is a schematic diagram of the packaging structure of this utility model.
[0010] Figure 2 This is a comparison of the thermal resistance simulation results of the packaging structure of this utility model and the traditional packaging structure.
[0011] Figure 3 This is a comparison of the current and channel temperature simulation results of the packaging structure of this utility model and the traditional packaging structure. Detailed Implementation
[0012] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0013] This embodiment provides a SiC packaging structure based on chip flip-chip, such as Figure 1 As shown, its core feature lies in achieving efficient electrical connection and heat dissipation performance through optimized packaging design. The packaging structure includes a heat sink 1, a SiC substrate 2, a bottom copper electrode 3, multiple parallel chips 5, and a top copper electrode 6.
[0014] The heat sink 1 is made of a metal or ceramic material with high thermal conductivity, preferably a copper-aluminum composite material or aluminum nitride ceramic material, with a thermal conductivity higher than 200 W / (m·K). The surface of the heat sink 1 is smoothed to ensure close contact with the SiC substrate 2, thereby reducing interfacial thermal resistance. The heat sink 1 is fixedly connected to the SiC substrate 2 by thermally conductive silicone grease or soldering material, thus forming an efficient heat conduction path.
[0015] The SiC substrate 2 is made of high-quality silicon carbide material, which has excellent electrical insulation and thermal conductivity. A bottom copper electrode is formed on the surface of the SiC substrate 2 using an ion-plating copper process. The thickness of the copper electrode is controlled within the range of 10-50 micrometers to ensure a balance between conductivity and heat dissipation. The bottom copper electrode 3 is connected to the SiC substrate 1 through a metal bonding layer, specifically using metal materials such as titanium or nickel as an intermediate layer to form a strong chemical bond, thereby significantly reducing contact resistance and improving long-term reliability.
[0016] Multiple parallel SiC chips 5 are distributed on the bottom copper electrode 3, and these chips are mounted in a flip-chip configuration. The flip-chip bonding is achieved through a copper sintering process, with a copper sintering layer thickness of 5-20 micrometers. This copper sintering layer possesses high thermal conductivity and high mechanical strength, enabling it to maintain stable electrical and thermal performance under high power conditions. The top of the multiple parallel chips is connected to a top copper electrode 6 via a copper sintering layer 4. The top copper electrode 6 is designed to be 20-100 micrometers thick, capable of withstanding high current density operating conditions.
[0017] The top copper electrode 6 and the bottom copper electrode 3 are led out to both sides of the package structure, forming a double-sided lead design. This design not only effectively meets the high-voltage insulation requirements but also avoids the traditional method of achieving insulation by increasing the creepage distance, thus significantly reducing the package size. In addition, the double-sided lead design simplifies circuit connections and greatly improves the integration level of the package structure.
[0018] In terms of heat dissipation, the packaging structure adopts a three-dimensional heat dissipation design, which uses a multi-path heat dissipation method through the heat sink, bottom copper electrode, and top copper electrode to quickly dissipate the heat generated during chip operation. The thermoelectric separation design avoids the concentrated accumulation of heat in the electrical path, thereby effectively reducing the heat concentration effect and improving the overall heat dissipation performance.
[0019] The packaging structure of this invention optimizes the contact resistance between the chip and the PCB. According to the formula R= ρ Calculated using *L / A (ρ is the material resistivity, L is the conductor length, and A is the conductor cross-sectional area), the contact resistance is 1 / 3 of that of traditional products, and the overcurrent capacity is increased by 3 times. Figure 2The comparison of thermal resistance simulation results between the packaging structure of this utility model and the traditional packaging structure under the same power density conditions shows that the thermal resistance of the packaging structure of this utility model is significantly reduced. Figure 3 The simulation results of current and channel temperature of the packaging structure of this utility model are compared with those of the traditional packaging structure. It can be seen that the current and channel temperature are significantly reduced.
[0020] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
Claims
1. A flip-chip-based SiC packaging structure comprising a heat sink, and a SiC substrate disposed on the heat sink, characterized in that, A bottom copper electrode is formed on the surface of the SiC substrate, and the bottom copper electrode is connected to the SiC substrate through a bonding layer; a plurality of chips are disposed on the bottom copper electrode and connected in parallel, and the top of the plurality of parallel chips is connected to a top copper electrode; the bottom copper electrode and the plurality of parallel chips, as well as the top copper electrode and the plurality of parallel chips, are connected through a copper sintering layer.
2. The flip-chip-based SiC packaging structure of claim 1, wherein, The bonding layer is at least one metallic material selected from titanium, nickel, or silver, or a multilayer structure formed by a combination of these materials.
3. The SiC packaging structure based on chip flip-chip as described in claim 1, characterized in that, The thickness of the copper sintered layer is 5 micrometers to 20 micrometers.
4. The flip-chip-based SiC packaging structure of claim 1, wherein, The thicknesses of the top copper electrode and the bottom copper electrode are 20 micrometers to 100 micrometers, respectively.