Photovoltaic cell, preparation method thereof, photovoltaic module and photovoltaic system

Abstract

The invention discloses a photovoltaic cell piece and a preparation method thereof, a photovoltaic module and a photovoltaic system, and the preparation method of the photovoltaic cell piece comprises the steps: forming a first diffusion layer and a first doped oxide layer on the front surface of a silicon substrate after surface texturing; performing laser scribing and slotting on the front surface of the silicon substrate by using laser, and removing the first doped oxide layer in a preset slotting region; removing the first doped oxide layer plated around the back surface of the silicon substrate; removing and texturing the first diffusion layer in the preset slotting region; sequentially growing a dielectric layer and a second diffusion layer on the back surface of the silicon substrate; removing the second doped oxide layer and the first doped oxide layer on the silicon substrate; depositing a first passivation layer on the front surface of the silicon substrate, and forming a second passivation layer on the back surface of the silicon substrate; and carrying out electrode printing and sintering on the silicon substrate to obtain the photovoltaic cell. The color consistency of the front surface of the photovoltaic cell prepared by the method is good, and the appearance requirement of a photovoltaic module is met.

Description

Technical Field

[0001] This application relates to the field of photovoltaic cell manufacturing technology, and in particular to a photovoltaic cell and its preparation method, a photovoltaic module and a photovoltaic system. Background Technology

[0002] Photovoltaic cell slicing is one of the core processes in the manufacturing of high-efficiency photovoltaic modules. It involves cutting a standard photovoltaic cell into multiple smaller cells and combining them with encapsulation technologies such as shingled, half-cell, and multi-busbar (MBB) to significantly improve module power and conversion efficiency, while reducing the risk of hot spots and improving crack resistance.

[0003] However, during the process of cutting photovoltaic cells into whole sheets, the PN junction in the cutting area can be damaged, leading to the formation of recombination centers and reducing the luminous efficiency of the cells to some extent. Therefore, the current practice is to remove the PN junction at a predetermined cutting position on the photovoltaic cell, essentially creating a safety "insulating trench" at the PN junction. This is followed by conventional processes such as passivation layer coating and screen printing. After the cell is completed, it is cut along the predetermined trench line. Since the PN junction has been eliminated, no potential difference is generated, thus virtually eliminating the risk of hot spot effects. Cutting damage is also significantly reduced, typically increasing power by 1-3W. However, during the passivation layer coating process in this marked area, there can be a color difference in the passivation layer deposition between the marked area and the non-marked area. This results in a mismatch between the structural layer color in the cutting area and the color of the other non-cut areas. When such cells are assembled into a photovoltaic module, the entire module will exhibit a mottled color appearance, failing to meet the aesthetic requirements of the photovoltaic module. Summary of the Invention

[0004] The purpose of this invention is to provide a photovoltaic cell and its preparation method, a photovoltaic module and a photovoltaic system, which ensures the color consistency of the cell film layer of the photovoltaic module.

[0005] To address the aforementioned technical problems, in a first aspect, a photovoltaic cell is provided, comprising: a silicon substrate; a first diffusion layer disposed on the front side of the silicon substrate in a non-preset slotted area; and a first passivation layer covering N preset slotted areas on the front side of the silicon substrate and the first diffusion layer; wherein the first passivation layer has the same thickness covering the preset slotted areas and the first diffusion layer; the preset slotted areas are regions with PN junctions removed and having a textured surface structure, and N is greater than or equal to 1;

[0006] On the back side of the silicon substrate, a dielectric layer, a second diffusion layer, and a second passivation layer are sequentially stacked in a direction away from the silicon substrate.

[0007] A first electrode is disposed on the front side of the silicon substrate and a second electrode is disposed on the back side; in the thickness direction of the silicon substrate, the first electrode extends through the first passivation layer to the first diffusion layer, and the second electrode extends through the second passivation layer to the second diffusion layer.

[0008] In this application, the photovoltaic cells have the same thickness of the first passivation layer formed in the preset slotted area and the non-preset slotted area for dividing and forming the slab cells, thereby ensuring the consistency of the front color of the photovoltaic cells and ensuring that the slab cells obtained by slab division can meet the appearance requirements of photovoltaic modules.

[0009] In some embodiments, the first passivation layer is any one or more layers of silicon nitride, silicon oxynitride, and silicon oxide.

[0010] The second passivation layer is any one or more layers of silicon nitride, silicon oxynitride, and silicon oxide.

[0011] In some embodiments, the thickness of the first passivation layer is 60 nm to 90 nm and the refractive index is 1.8 to 2.2; the thickness of the second passivation layer is 100 nm to 150 nm and the refractive index is 2.0 to 2.4.

[0012] Secondly, a method for preparing a photovoltaic cell includes:

[0013] After texturing the front side of the silicon substrate, a first diffusion layer and a first doped oxide layer are formed;

[0014] Laser processing is performed on a predetermined groove area on the front side of the silicon substrate to remove the first doped oxide layer in the predetermined groove area;

[0015] Remove the first doped oxide layer and the first diffusion layer that were deposited around the back side of the silicon substrate;

[0016] The first diffusion layer in the preset slotted area is removed and texturized;

[0017] A dielectric layer and a second diffusion layer are sequentially grown on the back side of the silicon substrate;

[0018] Remove the second doped oxide layer, the second diffusion layer and the first doped oxide layer in the non-preset trench area on the front side of the silicon substrate, and remove the second doped oxide layer on the back side of the silicon substrate;

[0019] A first passivation layer is deposited on the front side of the silicon substrate, and a second passivation layer is deposited on the back side of the silicon substrate.

[0020] Electrode printing and sintering are performed on the silicon substrate to obtain a photovoltaic cell; wherein the front side of the photovoltaic cell has N preset slotted areas for removing PN junctions, where N is greater than or equal to 1.

[0021] In this application, during the fabrication of a whole photovoltaic cell, before depositing the passivation layer on the front side, the first diffusion layer and the first doped oxide layer of the pre-defined trench area on the front side are removed, and the pre-defined trench area is also textured. This ensures that the surfaces of both the pre-defined trench area and the non-pre-defined trench area on the front side of the silicon substrate are textured during the deposition of the first passivation layer. This guarantees that the pre-defined trench area and the non-pre-defined trench area have consistent surface shapes, and that the thickness of the first passivation layer is consistent, avoiding color inconsistencies caused by different thicknesses of the first passivation layer on the front side of the photovoltaic cell. Therefore, the photovoltaic cell fabrication method of this application can ensure color consistency across the entire front side of the cell, meeting the appearance requirements of photovoltaic modules.

[0022] In some embodiments, laser processing is performed on a predetermined trench area on the front side of the silicon substrate to remove the first doped oxide layer in the predetermined trench area, including:

[0023] Laser picosecond laser is used to scribing the first doped oxide layer in the preset groove area; wherein the groove width of the first doped oxide layer removed by etching is 240um-600um.

[0024] In some embodiments, removing the first doped oxide layer and the first diffusion layer around the back side of the silicon substrate includes:

[0025] The first doped oxide layer and the first diffusion layer deposited around the back side of the silicon substrate are removed and polished.

[0026] The back side of the silicon substrate is purged with ozone to form a silicon oxide layer;

[0027] A water film layer covering the silicon oxide layer is formed on the back side of the silicon substrate.

[0028] In some embodiments, removing and texturing the first diffusion layer in the preset slotted area includes:

[0029] The first diffusion layer of the preset grooved area is removed in a chain and texturized by using KOH solution and texturizing additives; wherein the texturizing additives include polyβ-amino acids, polydimethyldiallylammonium chloride, chitosan, polyethylene glycol and glycerol polyoxypropylene polyoxyethylene ether.

[0030] In some embodiments, a first passivation layer is deposited on the front side of the silicon substrate, and a second passivation layer is deposited on the back side of the silicon substrate, comprising:

[0031] A first passivation layer is formed on the front side of the silicon substrate using plasma chemical vapor deposition;

[0032] A second passivation layer is formed on the back side of the silicon substrate using plasma chemical vapor deposition.

[0033] Thirdly, a photovoltaic module includes a front glass, a front encapsulant layer, a cell string layer, a back encapsulant layer, and a backsheet structure stacked sequentially.

[0034] The battery string layer is formed by connecting segmented battery cells in series and parallel, and the segmented battery cells are formed by cutting and slicing the photovoltaic battery cells described above.

[0035] The slab cells used in the photovoltaic modules of this application have good color consistency on the front side, thereby ensuring that the entire photovoltaic module has a good appearance and meets the appearance requirements of photovoltaic modules.

[0036] Fourthly, a photovoltaic system is provided, including the aforementioned photovoltaic modules. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A schematic flowchart illustrating the method for preparing a photovoltaic cell according to an embodiment of this application;

[0039] Figure 2 This is a partial cross-sectional structural diagram of a photovoltaic cell provided in an embodiment of this application;

[0040] Figure 3 A schematic diagram of a photovoltaic module provided in an embodiment of this application;

[0041] Figure 4 This is a schematic diagram of a photovoltaic system provided in an embodiment of this application;

[0042] The accompanying drawings are not drawn to scale.

[0043] Reference numerals in the figures: 1 is silicon substrate, 2 is first diffusion layer, 3 is first passivation layer, 31 is first aluminum oxide layer, 4 is dielectric layer, 5 is second diffusion layer, 6 is second passivation layer, 61 is second aluminum oxide layer, 7 is first electrode, and 8 is second electrode. Detailed Implementation

[0044] The descriptions of specific structures or functions implemented according to the concept of this application disclosed in this specification are merely illustrative examples for explaining embodiments based on the concept of this application. Those skilled in the art will understand that embodiments based on the concept of this application can have various variations and forms, and are not limited to the embodiments described in this specification, but also include various modifications, equivalents, or substitutions made within the scope of the purpose, concept, and technology of this application.

[0045] Research by our technical personnel has revealed that in the traditional Topcon battery manufacturing process, after photovoltaic cells are sliced ​​into sectional cells, inconsistencies in the light and dark colors of the front surface of these sectional cells are prone to occur. Ultimately, this results in photovoltaic modules assembled from these sectional cells failing to meet application requirements in terms of appearance. The root cause of this color inconsistency lies in the fact that during the photovoltaic cell manufacturing process, the PN junction needs to be removed from the pre-defined slotted areas on the front surface of the photovoltaic cell. Then, a passivation layer is formed on the pre-defined slotted areas and the non-pre-defined slotted areas on the front surface of the photovoltaic cell. The difference in the thickness of the passivation layer between the pre-defined slotted areas and the non-pre-defined slotted areas leads to color inconsistencies, resulting in different front surface colors for the sectional cells.

[0046] Based on this, the core of the present invention is to provide a photovoltaic cell and its preparation method, a photovoltaic module and a photovoltaic system, which can effectively ensure the consistency of the surface color of the photovoltaic cell and meet the appearance requirements of the photovoltaic module.

[0047] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] like Figure 1 and Figure 2 As shown, Figure 1 This is a schematic flowchart illustrating the method for preparing photovoltaic cells according to an embodiment of this application. Figure 2 This is a partial cross-sectional structural diagram of a photovoltaic cell provided in an embodiment of this application. The fabrication method of the photovoltaic cell in this application will be described in detail below with reference to specific embodiments.

[0049] In one optional embodiment of this application, the method for preparing the photovoltaic cell may include:

[0050] S11: A first diffusion layer and a first doped oxide layer are formed on the front side of the textured silicon substrate; wherein the first diffusion layer is a boron diffusion layer and the first doped oxide layer is a BSG layer.

[0051] In this embodiment, the silicon substrate 1 is an N-type silicon wafer substrate; a first diffusion layer 2 can be formed on the front side of the silicon substrate 1 by thermal diffusion. In this embodiment, the sheet resistance of the first diffusion layer 2 is 180Ω / sq~600Ω / sq, forming a P+ emitter.

[0052] The first doped oxide layer covering the first diffusion layer 2 is a product generated during the formation of the first diffusion layer 2.

[0053] S12: Use a laser to scribing the pre-defined groove area on the front side of the silicon substrate to remove the first doped oxide layer in the pre-defined groove area.

[0054] In this embodiment, the preset slotted area refers to the area where the cutting line is located after the entire solar cell has been fabricated and needs to be cut into at least two wafers. The non-preset slotted area refers to all areas on the front side of the silicon substrate 1 except for the area where the wafer cutting line is located; this will not be described again later.

[0055] This step aims to remove the first diffusion layer 2 of the preset slotted area, but the first doped oxide layer covering the first diffusion layer 2 is equivalent to a protective layer; therefore, it is necessary to first remove the first doped oxide layer of the preset slotted area to prepare for the subsequent removal of the first diffusion layer 2 of the preset slotted area.

[0056] Optionally, a picosecond green laser with a power of 28W-40W can be used to laser scribing the first doped oxide layer in the preset trench area; wherein the trench width of the first doped oxide layer removed by etching is 240um-600um.

[0057] It should be noted that the first doped oxide layer covering the first diffusion layer 2 has a hard and brittle structure, thus it can be removed by laser grooving in the predetermined grooving area. In practical applications, a picosecond green laser with a power of 28W-40W can be used to laser scribing the first doped oxide layer in the predetermined grooving area. The laser spot width for etching away the first doped oxide layer can be 240um-600um, thereby forming a linear groove with a grooving width of 240um-600um. After removing the first doped oxide layer in the predetermined grooving area by laser grooving, the first diffusion layer 2 in the predetermined grooving area can be further removed by etching.

[0058] S13: Remove the first doped oxide layer and the first diffusion layer from the back side of the silicon substrate.

[0059] It is understandable that the first doped oxide layer is the BSG layer, and the first diffusion layer is the boron diffusion layer.

[0060] During the formation of the first diffusion layer 2 on the front side of the silicon substrate 1, a certain amount of first doped oxide layer and first diffusion layer will inevitably be generated on the edge area of ​​the back side of the silicon substrate 1. Therefore, after the first doped oxide layer in the preset trench area is removed, the first doped oxide layer and the first diffusion layer on the back side of the silicon substrate 1 need to be removed in order to prepare for the subsequent deposition of the passivation layer on the back side.

[0061] Optionally, the first doped oxide layer and the first diffusion layer on the back side of the silicon substrate 1 can be removed by a chain-like process.

[0062] Further optionally, the process of removing the first doped oxide layer and the first diffusion layer can include:

[0063] S131: The first doped oxide layer and the first diffusion layer on the back side of the silicon substrate are removed and polished in a chain-like manner.

[0064] S132: Ozone purging is performed on the back side of the silicon substrate to form a silicon oxide layer;

[0065] S133: A water film layer covering a silicon oxide layer is formed on the back side of a silicon substrate.

[0066] In this embodiment, hydrofluoric acid solution and polishing alkaline solution can be used as etching solutions to remove the first doped oxide layer and the first diffusion layer on the back side of the silicon substrate 1 using a chain etching process. Specifically, a 50%-60% HF solution can be used to chain-remove the first doped oxide layer on the back side of the silicon substrate 1. Subsequently, a 1%-4% NaOH solution and a 0.5%-2% polishing additive are used for chain polishing to remove the first diffusion layer, followed by chain washing and drying. This process not only removes the first doped oxide layer and the first diffusion layer but also polishes the back side of the silicon substrate 1, resulting in a smooth polished surface. Furthermore, a flipper can be used to turn the front side of the silicon substrate 1 with the first diffusion layer 2 facing down. An ozone generator is used to purge the polished surface on the back side of the silicon substrate 1 with ozone, forming a silicon oxide layer to block subsequent alkaline etching. After purging, a water film is applied for protection before the substrate enters the chain etching equipment to etch and remove the first diffusion layer 2 in the preset trench area on the front side of the silicon substrate 1 and to texturize it.

[0067] S14: Remove the first diffusion layer in the preset slotted area and perform texturing.

[0068] It is understandable that the first diffusion layer 2 in the preset slotted area is removed, that is, the emitter PN junction structure of the preset slotted area is removed, and finally a textured surface is formed.

[0069] Optionally, a chain can be used to remove and texturize the first diffusion layer 2 of the preset slotted area.

[0070] In order to avoid mutual interference between the removal of the first diffusion layer 2 in the pre-set trench area on the front side of the silicon substrate 1 and the removal of the first doped oxide layer and the first diffusion layer on the back side, in this embodiment, a chain etching device can be used to first etch and remove the first doped oxide layer on the back side, and then the chain etching device can be used to chain remove the first diffusion layer 2 in the pre-set trench area on the front side.

[0071] S15: A dielectric layer and a second diffusion layer are sequentially formed on the back side of the silicon substrate; wherein the dielectric layer is a tunneling oxide layer and the second diffusion layer is a phosphorus diffusion layer.

[0072] In practical applications, a SiO2 thin film layer can be grown on the back side of the silicon substrate 1 as a dielectric layer 4. During operation, photogenerated carriers can penetrate the dielectric layer 4 to form electrical conduction. The thickness of the dielectric layer 4 is between 0.5 nm and 2 nm. The growth method of the SiO2 thin film layer can be any one of the following: high-temperature thermal oxidation, nitric acid oxidation, ozone oxidation, or CVD deposition.

[0073] After the dielectric layer 4 is formed, a second diffusion layer 5 can be deposited on the surface of the dielectric layer 4. The thickness of the second diffusion layer 5 can be from 80 nm to 300 nm. The second diffusion layer 5 can be deposited by LPCVD, PECVD, PEALD and PVD. Specifically, intrinsic polysilicon can be deposited first, and then phosphorus diffusion or ion implantation doping can be performed. Alternatively, in-situ doping (in-situ doping requires annealing) can be used to finally form the second diffusion layer 5.

[0074] S16: Remove the second doped oxide layer, the second diffusion layer and the first doped oxide layer in the non-preset trench area from the front side of the silicon substrate, and remove the second doped oxide layer from the back side of the silicon substrate, wherein the second doped oxide layer is a PSG layer.

[0075] During the fabrication of the second diffusion layer 5 on the back side of the silicon substrate 1, a second doped oxide layer will also be coated on the surface of the second diffusion layer 5. Furthermore, a second doped oxide layer and a second diffusion layer may also be deposited around the front side of the silicon substrate 1. Therefore, the second doped oxide layer and the second diffusion layer can be removed by first using chain etching or other methods to deposit around the edge area of ​​the front side of the silicon substrate 1, and then the first doped oxide layer on the non-preset trench area on the front side of the silicon substrate 1 and the second doped oxide layer on the back side can be removed by using trench etching or other methods.

[0076] The etching process may include:

[0077] S161: The second doped oxide layer on the front side of the silicon substrate is removed by chaining with a 10-12% HF solution.

[0078] S162: Chain polishing is performed using 1%-2% NaOH and 0.5%-1% polishing additives to remove the second diffusion layer around the front side of the silicon substrate, followed by chain spray washing and drying.

[0079] S163: Enter the cleaning tank containing 1%-1.5% NaOH and 2%-4% hydrogen peroxide solution for the first cleaning to remove additive residues.

[0080] S164: The second doped oxide layer on the back side of the silicon substrate and the first doped oxide layer in the non-preset trench area on the front side are removed by immersing the substrate in an acid pickling tank containing 10%-15% HF solution.

[0081] In order to ensure that the second doped oxide layer on the back side of the silicon substrate 1 and the first doped oxide layer in the non-preset trench area on the front side are fully etched and removed, the acid solution used in the acid washing process must be a high-concentration acid with a concentration greater than 10%.

[0082] S165: Enter a cleaning tank containing 1%-1.5% NaOH and 2%-4% H2O2 for a second cleaning.

[0083] Hydrogen peroxide is used to clean surface dirt and neutralize acid.

[0084] S166: The solution is introduced into a tank containing 0.5%-1.5% HCl and 1%-2% HF to remove residual metal ions and attached impurities.

[0085] S167: Enter the drying tank and use the high temperature of 80℃-90℃ and hot air inside the tank to dry the silicon substrate.

[0086] Each of the aforementioned tanks has a water tank at the front and back to clean the silicon substrate 1 from the residual cleaning solution left in the previous tank.

[0087] Obviously, in this step, when removing the first doped oxide layer in the non-preset slotted area, the non-preset slotted area will eventually form a textured surface.

[0088] S17: Deposit a first passivation layer on the front side of the silicon substrate and a second passivation layer on the back side of the silicon substrate.

[0089] In this embodiment, the first passivation layer 3 and the second passivation layer 6 can both be formed using various different processes to form different types of passivation layers.

[0090] Optionally, the first passivation layer 3 may be one or more layers of silicon nitride, silicon oxynitride, or silicon oxide.

[0091] The second passivation layer 6 can be one or more layers of silicon nitride, silicon oxynitride, or silicon oxide.

[0092] Further optionally, in step S17 above, the process of forming the first passivation layer 3 and the second passivation layer 6 may include:

[0093] S171: A first passivation layer is formed on the front side of a silicon substrate using plasma chemical vapor deposition;

[0094] S172: A second passivation layer is formed on the back side of a silicon substrate using plasma chemical vapor deposition.

[0095] The thickness of the first passivation layer 3 can be 60nm to 90nm, and the refractive index can be 1.8 to 2.2; the thickness of the second passivation layer 6 can be 100nm to 150nm, and the refractive index can be 2.0 to 2.4.

[0096] Further, optionally, after step S16 and before step S17, the following may also be included:

[0097] A first aluminum oxide layer 31 is deposited on the front side of the silicon substrate 1, and a second aluminum oxide layer 61 is deposited on the back side.

[0098] In other words, in this embodiment, before forming the first passivation layer 3 and the second passivation layer 6, aluminum oxide layers are first formed on both the front and back sides of the silicon substrate 1. Specifically, a 4nm-8nm first aluminum oxide layer 31 and a 4nm-8nm second aluminum oxide layer 61 can be formed simultaneously on the front and back sides of the silicon substrate 1 by atomic layer deposition.

[0099] It should be noted that in this embodiment, the first alumina layer 31 and the second alumina layer 61 can be films grown on the front and back sides of the silicon substrate 1 before depositing the first passivation layer 3 and the second passivation layer 6, respectively, in order to better deposit the first passivation layer 3 and the second passivation layer 6.

[0100] Furthermore, as mentioned above, both the first passivation layer 3 and the second passivation layer 6 can be multi-layer structures. Therefore, the first alumina layer 31 can also be regarded as part of the first passivation layer 3, and the second alumina layer 61 can be regarded as part of the second passivation layer 6. That is, the first alumina layer 31 and the second alumina layer 61 belong to the first layer structure in the multi-layer structure of the first passivation layer 3 and the second passivation layer 6, respectively.

[0101] Based on this, in another optional embodiment of this application, the process of forming the first passivation layer 3 and the second passivation layer 6 in step S17 may include:

[0102] S1701: A first aluminum oxide layer of 4nm-8nm and a second aluminum oxide layer of 4nm-8nm are simultaneously formed on the front and back sides of a silicon substrate by atomic layer deposition.

[0103] S1702: A first silicon nitride layer covering a first aluminum oxide layer is formed on the front side of a silicon substrate using plasma chemical vapor deposition.

[0104] S1703: A second silicon nitride layer covering the first aluminum oxide layer is formed on the back side of a silicon substrate using plasma chemical vapor deposition.

[0105] As described above, in this embodiment, a textured surface is formed in the preset slotted area while the first diffusion layer 2 is removed. Similarly, a textured surface is formed after the first doped oxide layer is removed from the non-preset slotted area on the front side of the silicon substrate 1. After the aluminum oxide layer is deposited simultaneously on the front and back sides of the silicon substrate 1, the preset slotted area and the non-preset slotted area can still maintain a textured surface with the same shape. That is, during the passivation process of the first passivation layer 3 on the front side of the silicon substrate 1, the entire front surface of the silicon substrate 1 is textured. This ensures that the thickness of the first passivation layer 3 deposited in all areas of the front surface is consistent, thereby ensuring that the front color of the entire solar cell is consistent.

[0106] S18: Electrode printing and sintering are performed on the silicon substrate to obtain a photovoltaic cell; wherein, the front side of the photovoltaic cell has N preset slotted areas for removing PN junctions, where N is greater than or equal to 1.

[0107] In this embodiment, the photovoltaic cell is a whole cell. The thickness of the first passivation layer 3 formed on the front side of the whole cell is uniform, so the color is also relatively uniform. When the photovoltaic cell is cut into pieces along the preset slotted area, the front side of the obtained N+1 pieces of the pieced cell also has good color consistency.

[0108] Based on the above discussion, in this embodiment, the process of removing the first diffusion layer 2 of the preset trench area on the front side of the silicon substrate 1 and removing the first doped oxide layer around the back side are carried out in two parts. In the current conventional process of removing the first diffusion layer 2 of the preset trench area on the front side of the silicon substrate 1 and the first doped oxide layer around the back side, as well as the first diffusion layer around the back side, are mostly completed simultaneously using a trench etching method. This results in the preset trench area on the front side forming a polished surface after the first diffusion layer 2 is applied. In the subsequent preparation of the passivation layer on the front side, the non-preset trench area on the front side is a textured surface. This leads to different thicknesses of the first passivation layer 3 deposited in the preset trench area and the non-preset trench area due to the different surface shapes (the first passivation layer 3 deposited on the polished surface will be thicker and lighter in color), which in turn leads to the problem of inconsistent color on the front side of the solar cell.

[0109] In summary, during the fabrication of the entire photovoltaic cell in this application, before depositing the passivation layer on the front side, the first diffusion layer and the first doped oxide layer in the pre-defined trench area on the front side are removed, and the pre-defined trench area is also textured. This ensures that the surfaces of both the pre-defined trench area and the non-pre-defined trench area on the front side of the silicon substrate have a textured surface when the first passivation layer is deposited. This avoids the problem of inconsistent thickness of the first passivation layer due to the inconsistent surface shape of the pre-defined trench area and the non-pre-defined trench area, which would lead to inconsistent colors. Therefore, the photovoltaic cell fabrication method of this application can ensure the color consistency of the entire front side of the cell, meeting the appearance requirements of photovoltaic modules.

[0110] In another optional embodiment of this application, the method for preparing the photovoltaic cell may include:

[0111] S21: A first diffusion layer and a first doped oxide layer are formed on the front side of the textured silicon substrate.

[0112] S22: Use a laser to scribing the pre-defined groove area on the front side of the silicon substrate to remove the first doped oxide layer in the pre-defined groove area.

[0113] S23: Remove the first doped oxide layer and the first diffusion layer from the back side of the silicon substrate.

[0114] S24: The first diffusion layer in the preset grooved area is removed in a chain and then texturized using a KOH solution with a concentration of 3%-15% and a texturing additive with a mass concentration of 0.1%-2%.

[0115] The texturing additives include 0.2%–2.0% polyβ-amino acids, 0.5%–10% polydimethyldiallylammonium chloride, 0.1%–0.5% chitosan, 0.1%–0.5% polyethylene glycol, and 0.1%–2.0% glycerol polyoxypropylene polyoxyethylene ether, with the remainder being water.

[0116] It should be noted that, since the pre-grooved area of ​​the laser scribing has a small proportion on the front side of the silicon substrate, the requirements for texturing are higher, and the use of chain-type sheeting is more challenging to achieve uniformity of the texturing surface. It is necessary to develop texturing additives with better adsorption and longer molecular chains to facilitate the formation of a pyramidal texturing surface with uniform size and good morphology in a smaller area.

[0117] The texturing additive described in this embodiment can be used for chain texturing of monocrystalline silicon wafers in a pre-defined grooved area. The mass ratio of the texturing additive to the alkaline solution is 0.1–5:100, and the alkaline solution is an aqueous solution of an inorganic alkali. For example, the alkaline solution can be a 2wt%–10wt% aqueous solution of sodium hydroxide or potassium hydroxide; the texturing temperature is 70℃–95℃, and the texturing time is 2 min–5 min. Ultimately, the texturing surface reflectivity of the pre-defined grooved area is maintained at 9%–12%, which is basically equivalent to the texturing surface reflectivity of other non-pre-defined grooved areas on the front side of the silicon substrate.

[0118] In this embodiment, the texturing additives, such as polyβ-amino acids, polydimethyldiallylammonium chloride, and chitosan, have polar amino groups and hydrophobic vinyl groups, exhibiting excellent adsorption properties. Furthermore, the amino groups in the molecules possess high activity, enabling them to combine with different groups and form stable nucleation centers on the surface of the pre-defined grooved area. Additionally, polyethylene glycol and other additives have long molecular chains. The synergistic effect of these additives achieves excellent texturing results. Moreover, due to the rapid chain-type texturing reaction and the generation of significant heat during the reaction, texturing poses a significant challenge to the morphology, uniformity, and consistency of the texturing pyramid structure during the fabrication process. By employing long-chain polyether additives, which have low surface tension and whose long chains effectively adsorb and protect the initially formed nucleation centers, the texturing surface of the pre-defined grooved area becomes uniform and free of bubble marks after texturing.

[0119] In addition, in this embodiment, after etching and removing the first diffusion layer 2 of the preset trench area using 3%-15% KOH solution and 0.1%-2% texturing additive, the final etched surface is the textured surface. That is to say, in this embodiment, a specific etching method is used for the first diffusion layer 2 of the preset trench area, so that texturing of the preset trench area can be achieved at the same time as etching. After texturing is completed, the silicon substrate 1 is then subjected to RCA cleaning and drying in sequence. RCA cleaning includes first entering a 1%-1.5% H2O2 + 2%-4% NaOH solution tank to clean and remove additive residues, and then entering a 0.5%-1.5% HCl + 1%-2% HF solution tank to remove residual metal ions. Each of the aforementioned tanks has a water tank before and after it to clean the silicon substrate 1 of the residual solution in the previous tank.

[0120] S25: A dielectric layer and a second diffusion layer are sequentially grown on the back side of the silicon substrate.

[0121] S26: Remove the second doped oxide layer, the second diffusion layer and the first doped oxide layer in the non-preset trench area from the front side of the silicon substrate, and remove the second doped oxide layer from the back side of the silicon substrate.

[0122] S27: A first aluminum oxide layer is deposited on the front side of the silicon substrate, and a second aluminum oxide layer is deposited on the back side.

[0123] S28: A first passivation layer covering a first aluminum oxide layer is deposited on the front side of the silicon substrate, and a second passivation layer covering a second aluminum oxide layer is deposited on the back side of the silicon substrate.

[0124] S29: Electrode printing and sintering are performed on the silicon substrate to obtain a photovoltaic cell; wherein, the front side of the photovoltaic cell has N preset slotted areas for removing PN junctions, and N is greater than or equal to 1.

[0125] like Figure 2 As shown, this application also provides an embodiment of a photovoltaic cell, which is prepared by the photovoltaic cell preparation method described above.

[0126] In one specific embodiment of this application, the photovoltaic cell includes:

[0127] Silicon substrate 1;

[0128] A first diffusion layer 2 is disposed on the non-pre-defined trench area on the front side of the silicon substrate 1;

[0129] A pre-defined trench area and a first passivation layer 3 covering the front side of the silicon substrate 1 and the first diffusion layer 2; wherein, the first passivation layer 3 has the same thickness covering the pre-defined trench area and the first diffusion layer; the pre-defined trench area is a region with a PN junction removed and a textured surface structure, where N is greater than or equal to 1;

[0130] On the back side of the silicon substrate 1, a dielectric layer 4, a second diffusion layer 5, and a second passivation layer 6 are stacked sequentially in a direction away from the silicon substrate 1.

[0131] A first electrode 7 is disposed on the front side of the silicon substrate 1 and a second electrode 8 is disposed on the back side; in the thickness direction of the silicon substrate 1, the first electrode 7 extends through the first passivation layer 3 to the first diffusion layer 2, and the second electrode 8 extends through the second passivation layer 6 to the second diffusion layer 5.

[0132] In this embodiment, the first diffusion layer 2 is a boron diffusion layer, the second diffusion layer 5 is a phosphorus diffusion layer, and the dielectric layer 4 is a tunneling oxide layer; in addition, the silicon substrate 1 can be an N-type substrate.

[0133] Optionally, a first alumina layer 31 is further disposed between the first diffusion layer 2 and the first passivation layer 3; and a second alumina layer 61 is further disposed between the second diffusion layer 5 and the second passivation layer 6.

[0134] Further optionally, the first passivation layer 3 is one or more layers selected from silicon nitride, silicon oxynitride, and silicon oxide.

[0135] The second passivation layer 6 is one or more layers of silicon nitride, silicon oxynitride, and silicon oxide.

[0136] In addition, in this embodiment, the thickness of the first passivation layer 3 is 60nm to 90nm and the refractive index is 1.8 to 2.2; the thickness of the second passivation layer 6 is 100nm to 150nm and the refractive index is 2.0 to 2.4.

[0137] Alternatively, the photovoltaic cell can be a TOPCon photovoltaic cell.

[0138] The following three examples (Examples 1 to 3) illustrate the preparation method and measurement process of photovoltaic cells, and provide comparison results with comparative examples.

[0139] Example 1:

[0140] 1) The manufacturing process of photovoltaic cells:

[0141] a) A first diffusion layer and a first doped oxide layer are formed on the front side of a textured silicon substrate;

[0142] b) A picosecond green laser with a power of 38W is used to laser scribing the first doped oxide layer in the preset groove area. The groove width of the first doped oxide layer removed by etching is 500um.

[0143] c) Removal of the first doped oxide layer and the first diffusion layer on the back side of the silicon substrate: The first doped oxide layer on the back side of the silicon substrate 1 is removed by chaining with a 60% HF solution. Then, the first diffusion layer is removed by chaining polishing with 2% NaOH and 1.5% polishing additive. Further, the side of the silicon substrate 1 with the first diffusion layer 2 is turned down using a flipper. An ozone generator is used to purge the polished surface on the back side of the silicon substrate 1 with ozone to form a silicon oxide layer to block subsequent alkaline etching. After purging, a water film is applied for protection.

[0144] d) Removing and texturing the first diffusion layer in the pre-set grooved area: The first diffusion layer in the pre-set grooved area is removed and texturized in a chain using a 3% KOH solution and a 0.1% texturing additive, followed by chain-linked spray washing and drying; wherein, the texturing additive includes 0.2% polyβ-amino acid, 0.5% polydimethyldiallyl ammonium chloride, 0.1% chitosan, 0.1% polyethylene glycol, and 0.1% glycerol polyoxypropylene polyoxyethylene ether;

[0145] e) RCA cleaning and drying of silicon substrates: RCA cleaning includes first entering a 1% NaOH + 2% H2O2 solution tank to remove additive residues, and then entering a 0.5% HCl + 1% HF solution tank to remove residual metal ions. Each of the aforementioned tanks has a water tank before and after it, and the silicon substrate is cleaned by passing through the solution remaining in the previous tank; then it enters a drying tank to dry the silicon wafer using a high temperature of 90°C and hot air.

[0146] f) A 0.8 nm dielectric layer and a 115 nm second diffusion layer are sequentially formed on the back side of the silicon substrate;

[0147] g) Removal of the second doped oxide layer, the second diffusion layer, and the first doped oxide layer in the non-preset trench area on the front side of the silicon substrate, and removal of the second doped oxide layer on the back side of the silicon substrate. This process includes: first, chain-removal of the second doped oxide layer on the front side of the silicon substrate in a 10% HF solution; then, chain-polishing removal of the second diffusion layer on the front side of the silicon substrate in 2% NaOH and 0.5% polishing additive; followed by chain-spray washing and drying. The silicon wafer then undergoes RCA cleaning and drying: RCA cleaning involves first entering a cleaning tank containing 1% NaOH and 2% hydrogen peroxide solution for the first cleaning to remove additive residues; then entering an acid pickling tank containing 12% HF solution to remove the second doped oxide layer on the back side of the silicon substrate and the first doped oxide layer in the non-preset trench area on the front side; then entering a cleaning tank containing 1% NaOH and 2% H2O2 for the second cleaning; then entering a tank containing 0.5% HCl and 1% HF solution to remove residual metal ions and attached impurities; finally, entering a drying tank to dry the silicon wafer using a high temperature of 90°C and hot air; each of the aforementioned tanks has a water tank before and after it, and the cleaning silicon wafer passes through the residual solution from the previous tank;

[0148] h) Deposit a 4 nm first aluminum oxide layer on both the front and back sides of the silicon substrate;

[0149] i) A first silicon nitride layer is deposited on the front side of a silicon substrate, and a second aluminum oxide layer is formed on the back side of the silicon substrate. The first silicon nitride layer has a thickness of 75 nm and a refractive index of 2.0; the second aluminum oxide layer has a thickness of 125 nm and a refractive index of 2.2.

[0150] j) Electrode printing and sintering are performed on a silicon substrate to obtain a photovoltaic cell; wherein the front side of the photovoltaic cell has N preset slotted areas for removing PN junctions, and N is greater than or equal to 1.

[0151] 2) Testing process for photovoltaic cells:

[0152] I. Preparatory work before testing

[0153] 1. Battery cell cleaning, including:

[0154] Wipe the surface of the battery cells with ultrapure water, ethanol or isopropanol to remove fingerprints, dust and organic residues;

[0155] After drying the solar cells with nitrogen, let them stand for 10 minutes to avoid surface contamination affecting their optical properties.

[0156] 2. Electrode contact inspection, including:

[0157] Use a four-wire probe (such as the Keithley 2400 series) to perform electrical measurements on the solar cells, ensuring that the contact resistance between the metal electrodes of the solar cells and the probe is <0.1Ω;

[0158] Use silver paste or spring probes to secure the battery cells and avoid pressure damage.

[0159] 3. Stabilization treatment, including:

[0160] The solar cells were aged under standard light (1000W / m²) for 1 hour to eliminate light-induced degradation (LID).

[0161] The temperature of the solar cells was maintained at 25℃±0.5℃ using a constant temperature stage to avoid the impact of thermal effects on carrier mobility.

[0162] 4. Equipment calibration, including:

[0163] The light source spectrum was calibrated using a standard reference cell to conform to the AM1.5G standard spectral conditions, with a calibration wavelength range of 300 nm to 1200 nm.

[0164] The irradiance uniformity deviation in the test area does not exceed ±2%, and the measurement error of the temperature sensor used is less than ±0.1℃.

[0165] II. Testing Equipment and Conditions

[0166] 1. Core equipment

[0167] IV tester: Keysight B2900A series, with a voltage resolution of 0.1mV and a current resolution of 0.1μA;

[0168] Solar simulator: Class AAA compliant, with selectable pulsed or steady-state light source (e.g., Wacom WXS-200S-20).

[0169] Temperature control console: Temperature regulation is achieved based on a thermoelectric cooling (TEC) module, with a control accuracy of ±0.2℃;

[0170] Spectral response instrument: equipped with a quantum efficiency (QE) testing system (such as Bentham PVE300).

[0171] D8 reflectometer: PVmeasure D8 reflectometer, xenon lamp light source, based on integrating sphere spectral measurement method, rapidly quantifies texturing effect;

[0172] Ellipsometry: SENTECH SE series, xenon lamp light source.

[0173] 2. Standard Test Conditions (STC)

[0174] Irradiance: 1000W / m² (AM1.5G standard spectrum);

[0175] Temperature: 25℃±1℃ (real-time monitoring via TEC module);

[0176] Light spot uniformity: The uniformity of the light spot covering the effective area of ​​the battery is >95%.

[0177] III. Key Parameter Testing Procedures

[0178] 1. Conversion efficiency (Eta) and IV characteristics (Voc, Isc, FF) testing

[0179] Test equipment: solar simulator, IV tester and four-wire probe.

[0180] step:

[0181] (1) Sample placement: Place the battery cell in the center of the light spot of the simulator, and use a light shield to block the edge of the battery cell by 5mm to avoid light leakage at the edge;

[0182] (2) IV scan: Apply a scan voltage from -0.5V to Voc+0.5V through an IV tester, set the scan step size to 10mV, and record the IV characteristic curve of the battery simultaneously;

[0183] (3) Parameter extraction: Extract the open-circuit voltage Voc (voltage when current = 0) and short-circuit current Isc (current when voltage = 0) from the IV curve;

[0184] (4) Calculation of power and fill factor: Calculate the maximum power point (Pmax = Vmpp × Impp) and fill factor FF = Pmax / (Voc × Isc) on the IV curve;

[0185] (5) Efficiency calculation: The conversion efficiency Eta = (Pmax / Pin) × 100% is calculated, where the incident light power Pin is calibrated by a calibrated standard cell.

[0186] 2. Velvet surface reflectance test

[0187] Test equipment: D8 reflectometer.

[0188] step:

[0189] (1) Power-on warm-up: Turn on the instrument power and warm up for 10-30 minutes until the light source (xenon lamp) and detector are stable;

[0190] (2) Instrument calibration: First, use the standard reflective sheet that comes with the instrument (usually a white board with known high reflectivity, such as Spectralon) for calibration;

[0191] (3) Place the sample: Place the silicon wafer with the textured side down, align it with the test hole of the integrating sphere, and ensure that the sample is flat and completely covers the test hole to prevent stray light from entering;

[0192] (4) Perform the test: Press the test button and the software will display the spectral reflectance curve and the weighted reflectance value;

[0193] (5) Data recording and cleaning: After recording the data, clean the test port with a lint-free cloth to prepare for the next measurement.

[0194] 3. Passivation layer refractive index test

[0195] Test equipment: Ellipsometry.

[0196] step:

[0197] (1) Power-on warm-up: Turn on the light source and detector, and wait for the status to stabilize;

[0198] (2) Substrate calibration: Call the model with known substrate optical constants;

[0199] (3) Establish / select a model: Establish a layer structure model (such as silicon substrate / alumina / silicon nitride) and select a suitable dispersion formula (such as Cauchy model, Tauc-Lorentz model).

[0200] (4) Place the sample: With the film facing upwards, align it with the light path;

[0201] (5) Fitting calculation: The software automatically fits the curve, generates a refractive index curve, and displays the refractive index value and thickness value at a specific wavelength;

[0202] (6) Multi-point testing: Programmable mobile platform to measure on-chip uniformity.

[0203] Example 2:

[0204] 1) The manufacturing process of photovoltaic cells:

[0205] Processes a) to c) are the same as in Example 1;

[0206] d) The first diffusion layer of the preset grooved area is removed in a chain and texturized using a 9% KOH solution and a 1% texturing additive; wherein the texturing additive includes 0.9% polyβ-amino acid, 0.7% polydimethyldiallyl ammonium chloride, 0.3% chitosan, 0.3% polyethylene glycol, and 1.0% glycerol polyoxypropylene polyoxyethylene ether.

[0207] e)~j) The process is the same as in Example 1.

[0208] 2) Testing process for photovoltaic cells:

[0209] Same as Example 1.

[0210] Example 3:

[0211] 1) The manufacturing process of photovoltaic cells:

[0212] Processes a) to c) are the same as in Example 1;

[0213] d) The first diffusion layer of the preset grooved area is removed in a chain and texturized using a 15% KOH solution and a 2% (w / w) texturizing additive; wherein the texturizing additive includes 2% (w / w) polyβ-amino acid, 10% (w / w) polydimethyldiallylammonium chloride, 0.5% (w / w) chitosan, 0.5% (w / w) polyethylene glycol and 2.0% (w / w) glycerol polyoxypropylene polyoxyethylene ether.

[0214] e)~j) The process is the same as in Example 1.

[0215] 2) Testing process for photovoltaic cells:

[0216] Same as Example 1.

[0217] Comparative Example 1:

[0218] 1) The manufacturing process of photovoltaic cells:

[0219] a) A first diffusion layer and a first doped oxide layer are formed on the front side of a textured silicon substrate;

[0220] b) Laser scribing is performed on the first doped oxide layer in the predetermined trench area on the front side of the silicon substrate;

[0221] Among them, a picosecond green laser with a power of 38W is used to laser scribing the first doped oxide layer in the preset groove area, and the groove width of the first doped oxide layer removed by etching is 500um.

[0222] c) The first diffusion layer on the back side of the silicon substrate and the first diffusion layer in the pre-defined groove area on the front side of the silicon substrate are removed by simultaneous alkaline polishing etching and polishing: First, the first doped oxide layer on the back side is removed by 60% HF and then washed and dried by chain spray water; then it enters the alkaline polishing tank; the parameters of the tank etching are as follows: first, it enters the cleaning tank of 1% NaOH and 4% hydrogen peroxide solution for the first cleaning to remove dirt from the surface of the silicon wafer; then, it enters the alkaline polishing tank of 2% NaOH and 1.5% polishing additive to polish the back side of the silicon wafer and polish the first diffusion layer in the laser scribing area on the front side; then, it enters the solution tank of 1% NaOH + 2% H2O2 to clean and remove additive residues; then, it enters the solution tank of 0.5% HCl + 1% HF to remove residual metal ions; each of the above tanks has a water tank before and after it to clean the silicon substrate and remove the residual solution from the previous tank; finally, it enters the drying tank and dries the silicon wafer with a high temperature of 90°C and hot air.

[0223] d) A 0.8 nm dielectric layer and a 110 nm second diffusion layer are sequentially formed on the back side of the silicon substrate;

[0224] e) Remove the second doped oxide layer, the second diffusion layer and the first doped oxide layer in the non-preset trench area on the front side of the silicon substrate, and remove the second doped oxide layer on the back side of the silicon substrate; the implementation method is the same as step g) in Example 1.

[0225] f) Deposit a 4 nm aluminum oxide thin film on the front and back sides of the silicon substrate.

[0226] g) A first passivation layer is deposited on the front side of the silicon substrate, and a second passivation layer is formed on the back side of the silicon substrate. The thickness of the first passivation layer in the non-preset trench area on the front side is 75 nm, and the refractive index is 2.0; the thickness of the first passivation layer in the laser scribing area on the front side is 95 nm, and the refractive index is 2.0; the thickness of the second passivation layer is 125 nm, and the refractive index is 2.2.

[0227] h) Electrode printing and sintering are performed on the silicon substrate to obtain a photovoltaic cell; wherein the front side of the photovoltaic cell has N preset slotted areas for removing PN junctions, and N is greater than or equal to 1.

[0228] 2) Testing process for photovoltaic cells:

[0229] Same as Example 1.

[0230] Based on the above embodiments and comparative examples of the photovoltaic cell preparation process, the same photovoltaic cells obtained in the above embodiments and comparative examples can be used to compare cell performance.

[0231] Table 1 is a comparison table of the electrical performance tests of photovoltaic cells in each embodiment and comparative example:

[0232]

[0233] As shown in Parameter Table 1, comparing Examples 1 to 3 with Comparative Example 1, it can be seen that the photovoltaic cells prepared according to the method described in this application exhibit better performance in terms of open-circuit voltage (Voc), short-circuit current (Isc), fill factor (FF), and photoelectric conversion efficiency (Eta) compared to those prepared using the traditional Topcon process. Furthermore, the photovoltaic cells prepared in this application have lower reflectivity in the scribing and slotting area. This demonstrates that the traditional Topcon process uses groove polishing to remove the first diffusion layer on the back side and the first diffusion layer in the scribing and slotting area on the front side, forming a polished surface in the slotted area. This results in higher reflectivity in the scribing area, affecting light absorption on the front side and thus reducing the short-circuit current. Moreover, during the deposition of the first passivation layer, the polished slotted area has a faster deposition rate, higher film thickness, and lighter color than the non-scribbed area. After such photovoltaic cells are sliced ​​into sectional cells, the front side of the sectional cells is prone to inconsistent brightness and darkness. In this application, a textured surface is formed in both the slotted and non-slotted areas of the photovoltaic cell, ensuring that the deposition rate of the first passivation layer in the slotted and non-slotted areas is basically the same, and the film thickness, color, etc. are also basically the same, thereby ensuring the consistency of the front color of the formed slab cells.

[0234] like Figure 3 As shown, this application also provides an embodiment of a photovoltaic module, which may include:

[0235] The front cover plate 100, the first encapsulating film 200, the battery string layer 300, the second encapsulating film 400 and the back cover plate 500 are stacked in sequence.

[0236] The battery string layer 300 includes a plurality of photovoltaic cells as described in any of the above.

[0237] like Figure 3 As shown, a photovoltaic module is a device that directly converts light energy into electrical energy through the photoelectric effect or photochemical effect. A photovoltaic module is typically a stacked encapsulation structure, comprising at least the following from the light-facing side to the backlighting side: a front cover plate 100, a first encapsulating film 200, a cell string layer 300, a second encapsulating film 400, and a back cover plate 500, as well as a frame surrounding the stacked structure and a junction box located on one side of the back cover plate 500.

[0238] The front cover 100 may be made of a material with excellent light transmittance, impact resistance, corrosion resistance, and weather resistance, and may optionally include at least one of the following materials: tempered glass, plexiglass, transparent ceramics, organic fibers, or polymers. In some embodiments, the front cover 100 may include at least one of an insulating barrier layer, a fluorinated weather-resistant layer, and a transition adhesive layer.

[0239] The back cover 500 typically needs to possess insulation, water resistance, aging resistance, weather resistance, and corrosion resistance. It may optionally include at least one of tempered glass, acrylic glass, metal back cover 500, or composite back cover 500 with PET film as the substrate. The PET-based composite back cover 500 may, depending on the needs of different scenarios, include various types such as composite (e.g., TPT / KPK, TPE / KPE), coated (e.g., TPC, KPC, CPC), and co-extruded (e.g., PO).

[0240] It is understandable that the material selection of the front cover 100 and the back cover 500 does not affect each other, and the same or different materials can be selected according to different application scenarios of the components (such as residential photovoltaics and building-integrated photovoltaics).

[0241] The first encapsulating film 200 and the second encapsulating film 400 may be selected from at least one of ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene coelastomer (POE) film, EVA-POE-EVA co-extruded film (EPE), PVB (polyvinyl butyral), polyethylene terephthalate (PET) film, or liquid silicone. In some embodiments, the first encapsulating film 200 and the second encapsulating film 400 may further include one or more functional additives selected from the group consisting of crosslinking agents, coupling agents, antioxidants, ultraviolet absorbers, etc., to improve the crosslinking degree, weather resistance, adhesive strength, and anti-aging properties of the film. It is understood that the first encapsulating film 200 and the second encapsulating film 400 may be made of the same or different materials.

[0242] The battery string layer 300 includes multiple battery strings, which can be combined in series, parallel, or series-parallel configurations to achieve current collection and output. Further, each battery string is formed by sequentially connecting multiple battery cells via connectors. In some embodiments, at least a portion of the connector is electrically connected to the back electrode of one battery cell, and at least another portion of the connector is electrically connected to the front or back electrode of another battery cell to form a battery string. The connector may optionally include conductive elements such as solder strips, busbars, or metal clips. In some embodiments, to improve welding performance, oxidation resistance, and weather resistance, the connector material may preferably be a highly conductive metal material, such as at least one of silver, copper, tin, and nickel, or an alloy thereof. In some embodiments, to balance conductivity and cost control, the connector material may also be at least one of metal-clad composite materials such as silver-coated copper, copper-coated silver, copper-coated aluminum, aluminum-coated copper, tin-plated copper, or nickel-plated copper. The electrical connection may be selected from one of the following methods: laser welding, spot welding, bonding, ultrasonic welding, resistance welding, or brazing.

[0243] A photovoltaic cell may include a semiconductor substrate, a first emitter of a first conductivity type, and a second emitter of a second conductivity type. It is understood that one of the first and second conductivity types is P-type, and the other is N-type. The semiconductor substrate may include an N-type silicon substrate or a P-type silicon substrate. N-type silicon substrates are typically formed by doping with Group V elements such as phosphorus, arsenic, or antimony, and have the characteristic that the majority carriers are electrons; P-type silicon substrates are typically formed by doping with Group III elements such as boron, gallium, or aluminum, and have the characteristic that the majority carriers are holes.

[0244] The solar cell can employ a grid line design with no main grid (OBB), multiple main grid (MBB), or super-multiple main grid (SMBB). In some embodiments, the grid line material can be selected as at least one of silver-based conductive paste or silver-coated copper composite paste. The paste uses highly conductive metal powder as the conductive substrate, and the substrate can be at least one of silver powder, copper powder, or silver-coated copper composite powder. To improve the ohmic contact performance, conductivity, and long-term weather resistance of the electrodes, a composite functional layer can be formed on the surface of the substrate or in the grid line structure. The functional layer material includes at least one of glass powder, organic carrier, nickel-based barrier layer, tin-based alloy layer, or anti-oxidation and corrosion-resistant coating.

[0245] It is understood that the photovoltaic cell can be at least one of the following commonly used in the field: TOPCon (Tunnel Oxide Passivated Contact) cell, HJT (Heterojunction with Intrinsic Thin-film) cell, BC (Back Contact) cell, perovskite / tandem cell, etc.

[0246] A frame 600 surrounds the periphery of the stacked structure and is typically made of aluminum alloy or steel alloy. In some embodiments, the frame 600 may also be a fiberglass frame or a plastic frame. The inner side of the frame 600 usually has grooves for filling with sealant to achieve a sealed bond with the stacked components formed by the front cover plate 100, the first encapsulating film 200, the battery string layer 300, the second encapsulating film 400, and the back cover plate 500, thereby blocking moisture and buffering external impacts. In some embodiments, the frame 600 can be assembled using corner brackets.

[0247] A junction box 700 is located on one side of the back cover 500 and is electrically connected to the terminals of the bus electrodes in the battery string layer 300 via a lead-out busbar for energy extraction. The junction box 700 typically includes a housing and cover made of weather-resistant insulating material, conductive connecting tabs disposed within the housing, and one or more bypass diodes. The bypass diodes are connected in parallel with sub-units of the battery string. The electrical leads of the junction box 700 include photovoltaic-specific connectors and cables. The cables preferably use cross-linked polyethylene insulating sheaths and tinned copper core wires. In some embodiments, the interior of the junction box 700 may also be filled and encapsulated with potting compound to achieve insulation, thermal conductivity, moisture protection, and fixation.

[0248] like Figure 4 The present application also provides an embodiment of a photovoltaic system 1000, which may include the photovoltaic module 1001 as described above.

[0249] The photovoltaic system 1000 provided in this application can be applied in photovoltaic power plants, such as ground power plants, rooftop power plants, and water-based power plants. It can also be applied to equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings.

[0250] It is understandable that the application scenarios of the PV system 1000 are not limited to this; that is to say, the PV system 1000 can be applied in all fields that require solar power generation. Taking a PV power generation system as an example, the PV system 1000 may include a PV array, a combiner box, and an inverter. The PV array may be an array combination of multiple PV modules. For example, multiple PV modules can form multiple PV arrays. The PV array is connected to the combiner box, which can collect the current generated by the PV array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to realize solar power supply.

[0251] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that the elements inherent in a process, method, article, or apparatus that includes a list of elements are included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Additionally, portions of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0252] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A photovoltaic cell, characterized in that, The photovoltaic cell includes: silicon substrate; A first diffusion layer is disposed in a non-pre-defined trench area on the front side of the silicon substrate; The first passivation layer covers N predetermined slotted areas on the front side of the silicon substrate and the first diffusion layer; wherein the first passivation layer has the same thickness covering the predetermined slotted areas and the first diffusion layer; the predetermined slotted areas are regions with PN junctions removed and having a textured surface structure, and N is greater than or equal to 1; On the back side of the silicon substrate, a dielectric layer, a second diffusion layer, and a second passivation layer are sequentially stacked in a direction away from the silicon substrate. A first electrode is disposed on the front side of the silicon substrate and a second electrode is disposed on the back side; in the thickness direction of the silicon substrate, the first electrode extends through the first passivation layer to the first diffusion layer, and the second electrode extends through the second passivation layer to the second diffusion layer.

2. The photovoltaic cell as described in claim 1, characterized in that, The first passivation layer is any one or more layers of silicon nitride, silicon oxynitride, and silicon oxide. The second passivation layer is any one or more layers of silicon nitride, silicon oxynitride, and silicon oxide.

3. The photovoltaic cell as described in claim 1, characterized in that, The thickness of the first passivation layer is 60 nm to 90 nm; the refractive index is 1.8 to 2.

2. The second passivation layer has a thickness of 100 nm to 150 nm and a refractive index of 2.0 to 2.

4.

4. A method for preparing a photovoltaic cell, characterized in that, include: After texturing the front side of the silicon substrate, a first diffusion layer and a first doped oxide layer are formed; Laser processing is performed on a predetermined groove area on the front side of the silicon substrate to remove the first doped oxide layer in the predetermined groove area; Remove the first doped oxide layer and the first diffusion layer that were deposited around the back side of the silicon substrate; The first diffusion layer in the preset slotted area is removed and texturized; A dielectric layer and a second diffusion layer are sequentially grown on the back side of the silicon substrate; Remove the second doped oxide layer, the second diffusion layer and the first doped oxide layer in the non-preset trench area on the front side of the silicon substrate, and remove the second doped oxide layer on the back side of the silicon substrate; A first passivation layer is deposited on the front side of the silicon substrate, and a second passivation layer is deposited on the back side of the silicon substrate. Electrode printing and sintering are performed on the silicon substrate to obtain a photovoltaic cell; wherein the front side of the photovoltaic cell has N preset slotted areas for removing PN junctions, where N is greater than or equal to 1.

5. The method for preparing a photovoltaic cell as described in claim 4, characterized in that, Laser processing is performed on a predetermined trench area on the front side of the silicon substrate to remove the first doped oxide layer in the predetermined trench area, including: Laser picosecond laser is used to scribing the first doped oxide layer in the preset groove area; wherein the groove width of the first doped oxide layer removed by etching is 240um-600um.

6. The method for preparing a photovoltaic cell as described in claim 4, characterized in that, Removing the first doped oxide layer and the first diffusion layer around the back side of the silicon substrate includes: The first doped oxide layer and the first diffusion layer deposited around the back side of the silicon substrate are removed and polished. The back side of the silicon substrate is purged with ozone to form a silicon oxide layer; A water film layer covering the silicon oxide layer is formed on the back side of the silicon substrate.

7. The method for preparing a photovoltaic cell according to any one of claims 4 to 6, characterized in that, Removing and texturing the first diffusion layer in the preset slotted area includes: The first diffusion layer of the preset grooved area is removed in a chain and texturized by using KOH solution and texturizing additives; wherein the texturizing additives include polyβ-amino acids, polydimethyldiallylammonium chloride, chitosan, polyethylene glycol and glycerol polyoxypropylene polyoxyethylene ether.

8. The method for preparing a photovoltaic cell as described in claim 4, characterized in that, A first passivation layer is deposited on the front side of the silicon substrate, and a second passivation layer is deposited on the back side of the silicon substrate, comprising: A first passivation layer is formed on the front side of the silicon substrate using plasma chemical vapor deposition; A second passivation layer is formed on the back side of the silicon substrate using plasma chemical vapor deposition.

9. A photovoltaic module, characterized in that, It includes a front glass, a front encapsulating film layer, a battery string layer, a back encapsulating film layer, and a backsheet structure stacked in sequence; The battery string layer is formed by connecting segmented battery cells in series and parallel, and the segmented battery cells are formed by cutting and slicing the photovoltaic battery cells as described in any one of claims 1 to 3.

10. A photovoltaic system, characterized in that, Including the photovoltaic module as described in claim 9.

Images