Double-layer photoetching method for semiconductor device with deep groove structure

Abstract

The invention discloses a double-layer photoetching method for a semiconductor device with a deep groove structure, which comprises the following steps of: forming an effect of filling photoresist in a deep groove through a first photoetching process, and continuously performing a second photoetching process on the basis to form a specific etching pattern; and finally, taking the etching pattern formed by the secondary photoetching process as a main etching mask, taking the photoresist in the primary photoetching process as an auxiliary mask and support, and carrying out graphical transfer on a device below. According to the method, two layers of photoresist are arranged on a wafer substrate according to the characteristics that positive photoresist is insoluble in a developing solution before exposure and can be dissolved in the developing solution after exposure and the characteristics that negative photoresist is dissolved in the developing solution before exposure and cannot be dissolved in the developing solution after exposure, and the photoresist close to the wafer substrate is used for supporting; and the other layer of photoresist is used for limiting an etching area. By controlling the optical characteristics (different refractive indexes and absorbance) of the double-layer photoresist, the morphology of the side surface of the groove is improved, the morphology of the photoresist layer is optimized, and the critical dimension deviation is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology and relates to a double-layer photolithography method for semiconductor devices with deep trench structures. Background Technology

[0002] In semiconductor wafer fabrication, especially in the manufacture of memory, power devices, or three-dimensional structures, deep trenches ranging from several micrometers to tens of micrometers are typically formed on the surface of the wafer substrate. During photolithography, it is crucial to ensure that the photoresist completely fills and smoothly covers these trenches to prevent failures in subsequent processes such as etching and ion implantation. Currently, the industry typically uses a single layer of thick photoresist (usually over 10 micrometers thick) to address the deep trench filling problem. However, this thick photoresist has significant technical drawbacks, such as resolution limitations: severe scattering and diffraction of light in thick photoresist leads to decreased imaging contrast, limiting the size of the critical dimension (CD) and preventing miniaturization. Linewidths are typically limited to the micrometer level, severely restricting the precision and integration of product designs. Narrow process windows: the exposure and development windows for thick photoresist are extremely narrow, making them highly sensitive to parameters such as depth of focus and exposure dose, easily leading to pattern defects. Therefore, there is an urgent need in the field for a photolithography method that can simultaneously achieve good trench filling and high-resolution patterning. Summary of the Invention

[0003] The purpose of this invention is to provide a two-layer photolithography method for semiconductor devices with deep trench structures. This method can achieve the critical dimension CD while ensuring that the photoresist perfectly fills and covers the deep trenches on the wafer surface, thereby breaking through product design limitations and improving device performance and integration.

[0004] The technical solution adopted in this invention is a double-layer photolithography method for semiconductor devices with deep trench structures. A first photolithography process creates a deep trench filled with photoresist. A second photolithography process is then performed to form a specific etched pattern. Finally, using the etched pattern formed in the second photolithography process as the primary etch mask and the photoresist from the first photolithography process as an auxiliary mask and support, the underlying device is patterned and transferred. The specific steps are as follows: Step 1: Deposit 100~300nm silicon nitride on a wafer substrate with a deep trench structure using chemical vapor deposition; Step 2: Apply positive or negative photoresist to the upper surface of the wafer by spin coating, with the thickness controlled at 12±0.5μm. Then perform soft baking on a hot plate at a temperature of 90℃~110℃ for 120s~180s. Step 3: Expose the area defined by the first photomask with an exposure dose of 300~500mJ / cm². After exposure, continue baking at a temperature of 90℃~100℃ for 60s~90s. After baking, develop the area with a developer for 90~120s to form the etched area window. Step 4: Coat the wafer developed in Step 3 with a second layer of positive photoresist, with the thickness controlled at 1~5μm. Then bake it on a hot plate at a temperature of 90℃~110℃ for 60s~110s. When the target CD is large, negative photoresist can be used instead. However, negative photoresist has low resolution and cannot achieve the acquisition of smaller CDs, which has a greater limitation. When the target CD is small (<2 micrometers), positive photoresist is the best choice.

[0005] Step 5: Expose the area defined by the second photomask at an exposure dose of 180mJ / cm² to 200mJ / cm², then bake at a temperature of 90℃ to 110℃ for 60s to 110s. After baking, develop the area with a developer for 30 to 90s to form the etched pattern. Step 6: Using the second thin adhesive layer pattern as the main etching mask and the first thick adhesive layer as the auxiliary mask and support, perform deep etching on the underlying silicon nitride substrate.

[0006] In step 3, the first photomask exposes the area to be etched and blocks the light from the rest of the area. In step 5, the second photomask exposes only the pattern to be etched in the area to be etched and blocks the light from the rest of the area.

[0007] The bilayer photolithography method for semiconductor devices with deep trench structures according to the present invention is as follows: Step 1: Deposit 100~300nm silicon nitride on a wafer substrate with a deep trench structure using chemical vapor deposition; Step 2: Apply positive photoresist to the upper surface of the wafer by spin coating, with the thickness controlled at 12±0.5μm. Then, perform general exposure on the photoresist with an exposure dose of 80~100mj². After exposure, bake at a temperature of 90℃~110℃ for 120s~180s. Step 3: Develop the baked photoresist with a developer for 45-60 seconds. Not all of it will be developed away; because the channel photoresist is thicker and the upper layer of photoresist on the steps is thinner, weak exposure and weak development can be used to thin the surface photoresist. Step 4: Spin-coat a second layer of photoresist onto the developed photoresist structure, with the thickness controlled at 1~5μm, and then bake it at a stable temperature of 90℃~110℃ for 60s~110s. After baking, expose the limited exposure area with a third photomask at an exposure dose of 180mJ / cm²~200mJ / cm², and then bake it again at a temperature of 90℃~110℃ for 60s~110s. Step 5: Develop the photoresist baked in Step 4 using a developer solution for 30-90 seconds to form the etched pattern; Step 6: Using the second thin adhesive layer pattern as the main etching mask and the first thick adhesive layer as the auxiliary mask and support, perform deep etching on the underlying silicon nitride substrate.

[0008] The third photomask exposes the pattern to be etched while blocking light from other parts of the image.

[0009] The bilayer photolithography method for semiconductor devices with deep trench structures according to the present invention is as follows: Step 1: Deposit 100~300nm silicon nitride on a wafer substrate with a deep trench structure using chemical vapor deposition; Step 2: Apply negative photoresist to the upper surface of the wafer by spin coating, with the thickness controlled at 12±0.5μm, and then bake it at a temperature of 100℃~110℃ for 90s~110s. Step 3: Develop the baked photoresist with a developer for 45-60 seconds; use a weak development method to thin the photoresist above the step, leaving at least 5-8 micrometers of photoresist in the trench. Step 4: Spin-coat positive photoresist onto the developed photoresist structure, with the thickness controlled at 1~5μm, and then bake it at a stable temperature of 90℃~110℃ for 60s~110s. After baking, expose the limited exposure area with a fourth photomask at an exposure dose of 180mJ / cm²~200mJ / cm², and then bake it again at a temperature of 90℃~110℃ for 60s~110s. Step 5: Develop the photoresist baked in Step 4 using a developer solution for 30-90 seconds to form the etched pattern; Step 6: Using the second thin adhesive layer pattern as the main etching mask and the first thick adhesive layer as the auxiliary mask and support, perform deep etching on the underlying silicon nitride substrate.

[0010] The fourth photomask exposes the pattern to be etched while blocking light from the rest of the pattern.

[0011] The present invention provides a two-layer photolithography method for semiconductor devices with deep trench structures, specifically... Follow these steps: Step 1: Deposit 100~300nm silicon nitride on a wafer substrate with a deep trench structure using chemical vapor deposition; Step 2: Apply positive photoresist to the upper surface of the wafer by spin coating, with the thickness controlled at 12±0.5μm, and then bake it at a temperature of 90℃~110℃ for 120s~180s. Step 3: Expose the area defined by the fifth photomask with an exposure dose of 200~400mJ / cm². After exposure, bake at a temperature of 90℃~110℃ for 60s~110s. Then develop with developer for 90s~120s. Step 4: Spin-coat a second layer of photoresist onto the developed wafer structure, with the thickness controlled at 1~5μm. Then, use a sixth photomask to define the exposure area for exposure, with an exposure dose of 180mJ / cm²~200mJ / cm². After exposure, bake the photoresist at a temperature of 90℃~110℃ for 60s~110s. Step 5: Develop the photoresist baked in Step 4 using a developer solution for 30-90 seconds to form the etched pattern; Step 6: Using the second thin adhesive layer pattern as the main etching mask and the first thick adhesive layer as the auxiliary mask and support, perform deep etching on the underlying silicon nitride substrate.

[0012] In step 3, the fifth photomask blocks the deep trenches of the wafer substrate, causing a protrusion that is higher than the wafer plane. This does not affect the operation and the objective is achieved (trench filling and target CD acquisition are achieved). In step 4, the sixth photomask exposes the pattern to be etched and blocks the light from other parts.

[0013] The beneficial effects of this invention are: (1) Applicable scenarios of the present invention: applicable to substrates with deep trenches (depth ≥ 10 μm, high aspect ratio), such as memory, power devices, etc.

[0014] (2) The present invention utilizes the opposite properties of positive photoresist (soluble after exposure) and negative photoresist (insoluble after exposure) to form functional layers; the photoresist close to the substrate serves as a support layer, and the upper photoresist defines the etching area, thereby achieving separation of process functions and solving the problem of developer penetration and corrosion caused by incomplete filling of deep trenches.

[0015] (3) By controlling the optical properties (different refractive indices and absorbance) of the double-layer photoresist, the morphology of the trench side surface is improved, the morphology of the photoresist layer is optimized, and the critical dimension deviation is reduced. Attached Figure Description

[0016] Figure 1 This is a flowchart of Embodiment 1 of the present invention; Figure 2 This is a flowchart of Embodiment 2 of the present invention; Figure 3 This is a flowchart of embodiment 4 of the present invention. Detailed Implementation

[0017] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0018] Example 1: On a wafer substrate with deep trenches, a first thick photoresist layer (depending on the trench aspect ratio) is coated to fill the trenches, ensuring complete filling and smooth coverage of all deep trenches on the substrate surface. After baking, the first photoresist layer is exposed using a first photomask. The first critical dimension is a larger dimension designed to accommodate thick photoresist lithography (e.g., greater than or equal to 5 micrometers). The exposed first photoresist layer is developed to form a thick photoresist layer with a first pattern, which is mainly used to define the approximate areas requiring subsequent fine processing or to provide support for the structure. A second photoresist layer is coated on the patterned first photoresist layer. This second photoresist layer is significantly thinner than the first layer, preferably 2 micrometers or less, to enable high-resolution patterning. The second photoresist layer is then soft-baked. The second photoresist layer is exposed using a second photomask with a pattern of a second critical dimension, which is smaller than the first critical dimension. The exposed second photoresist layer is developed to form a thin photoresist layer with a second pattern. This second pattern is the final high-precision pattern required. The pattern of the second thin adhesive layer serves as the main mask, and together with the patterned first thick adhesive layer below, they act as an etching barrier layer to simultaneously etch the thin film layer on the wafer substrate, ultimately transferring the high-precision second pattern onto the substrate.

[0019] The core method described above involves a two-layer photolithography process: first applying thicker resist to form a large CD, then applying thinner resist to form a smaller CD. The fine pattern of the thin resist is located within a window defined by the coarser pattern of the thick resist (pattern nesting). Figure 1 As shown, the specific operation steps are as follows: Step 1: Select a GaAs wafer, and form deep trenches with a depth of 15±0.5 micrometers and a width of 5 micrometers on its surface by dry etching. Then, deposit 300nm silicon nitride using PECVD. Step 2: Apply positive thick-film photoresist by spin coating, with the thickness controlled at 12±0.5 micrometers. Then, perform soft baking on a hot plate at a temperature of 90℃~110℃ for 120s~180s. Step 3: The photomask (with a pattern CD of 8 micrometers) is exposed on an i-line stepper lithography machine at an exposure dose of 200 mJ / cm², and then soft-baked on a hot plate at a temperature of 90℃~100℃ for 60s~90s. Subsequently, it is developed using 2.38% TMAH developer for 90 seconds to form the first pattern, which defines the area window requiring high-precision etching. Step 4: Apply a second thin layer of positive photoresist, controlling the thickness to 2 micrometers. Then perform soft baking at 90℃~110℃ for 60s~110s. Expose the second photomask (with a pattern CD of 500nm) on the same i-line lithography machine at an exposure dose of 180~200mJ / cm², followed by soft baking on a hot plate at 90℃~110℃ for 60s~110s. Develop with 2.38% TMAH developer for 60s to form a high-precision second pattern. At this point, the second pattern is precisely located within the window defined by the first pattern.

[0020] Step 5, ICP etching process: using the second thin adhesive pattern as the main etching mask and the first thick adhesive as the auxiliary mask and support, the underlying silicon nitride substrate is deeply etched.

[0021] Example 2 The process involves filling the trench with a thick layer of positive photoresist (depending on the trench aspect ratio), followed by a weak exposure process, and then baking. Development is then used to thin the photoresist thickness at the target location on the higher step. This method utilizes weak exposure and leverages the thickness difference between the photoresist at the trench and the higher step to thin the photoresist at the target location on the higher step while ensuring photoresist filling in the trench. A second thin layer of positive photoresist is then coated and selectively exposed to obtain the target CD. In other words, the process involves filling the trench with a thick layer of positive photoresist, followed by a weak exposure process, development, and thinning the photoresist at the target location on the higher step using the thickness difference between the trench and the higher step. A second thin layer of positive photoresist is then coated and selectively exposed to obtain the target CD. The specific steps are as follows: Step 1: Prepare a GaAs wafer, and form deep trenches with a depth of 15±0.5 micrometers and a width of 5 micrometers on its surface by dry etching. Then, deposit 300nm silicon nitride using PECVD. Step 2: Coat the wafer with positive photoresist, with the thickness controlled at 12±0.5 micrometers. Perform generalized exposure on an i-line stepper lithography machine with an exposure dose of 80~100mj². Then perform soft baking on a hot plate at a baking temperature of 90℃~110℃ for 120s~180s. Step 3: Then develop using 2.38% TMAH developer for 45-60 seconds; Step 4: Spin-coat a second thin layer of positive photoresist onto the above structure, controlling the thickness to 2 micrometers. Then perform soft baking at 90℃~110℃ for 60s~110s. Expose using a photomask (with a pattern CD of 500nm) on the same i-line lithography machine at an exposure dose of 180~200 mJ / cm², followed by soft baking on a hot plate at 90℃~110℃ for 60s~110s. Finally, develop using a standard developer (2.38% TMAH) for a typical time of 60s to form the final pattern. Step 5: ICP etching process, using the second thin adhesive pattern as the main etching mask and the first thick adhesive as the auxiliary mask and support, to perform deep etching on the underlying silicon nitride substrate.

[0022] Example 3 A thick layer of negative photoresist (thickness > trench depth) is used for filling. The photoresist thickness at the target location on the high step is directly reduced by weak development. This method utilizes the solubility of the negative photoresist in the developer when it is not cross-linked. Simultaneously, it leverages the thickness difference between the photoresist at the trench and the high step to reduce the photoresist thickness at the target location on the high step through weak development, while ensuring photoresist filling in the trench. A second thin layer of photoresist is then coated for selective exposure to obtain the target CD. In other words, the above describes using a thick layer of negative photoresist for trench filling, followed by weak development. The thickness difference between the photoresist at the trench and the high step reduces the photoresist thickness at the target location on the high step. A second thin layer of negative photoresist is then coated for selective exposure to obtain the target CD. Figure 2 As shown, the details are as follows: Step 1: Prepare a GaAs wafer, and form deep trenches with a depth of 15±0.5 micrometers and a width of 5 micrometers on its surface by dry etching. Then, deposit 300nm silicon nitride using PECVD.

[0023] Step 2: Coat the wafer with negative adhesive with a thickness controlled at 12±0.5 micrometers, and bake on a hot plate at 100℃~110℃ for 90s~110s.

[0024] Step 3: Then develop the solution (2.38% TMAH) for 45-60 seconds; Step 4: Spin-coat a second thin layer of positive photoresist onto the above structure, controlling the thickness to 2 micrometers. Then perform soft baking at 90℃~110℃ for 60s~110s. Expose using a photomask (with a pattern CD of 500nm) on the same i-line lithography machine at 180~200mJ / cm². Subsequently, perform soft baking on a hot plate at 90℃~110℃ for 60s~110s. Finally, develop using a standard developer (e.g., 2.38% TMAH) for a typical time of 60s to form the final pattern. Step 5: ICP etching process, using the second thin adhesive pattern as the main etching mask and the first thick adhesive as the auxiliary mask and support, to perform deep etching on the underlying silicon nitride substrate.

[0025] Example 4 The process involves filling the trench with a thick layer of positive / negative photoresist (thickness > trench depth), followed by initial selective exposure and development. Using a photomask design, the areas to be filled are exposed and developed (negative photoresist exposed, positive photoresist blocked). This development removes the photoresist at the target location on the high step. This method utilizes the selective exposure property of the high step, where the photoresist is soluble in the developer when it is not cross-linked. Simultaneously, leveraging the thickness difference between the trench and the high step, the photoresist thickness at the target location on the high step is reduced through weak development, while ensuring photoresist filling in the trench. A second thin layer of photoresist is then coated and selectively exposed to obtain the target CD. In other words, after filling with thick photoresist, selective exposure is used with a photomask, followed by development to remove the photoresist at the high step, then a thin layer of photoresist is coated, and the process is repeated to obtain the target CD at the target location. Figure 3 As shown, the specific operation steps are as follows: Step 1: Prepare a GaAs wafer, and form deep trenches with a depth of 15±0.5 micrometers and a width of 5 micrometers on its surface by dry etching. Then, deposit 300nm silicon nitride using PECVD.

[0026] Step 2: On the wafer, a positive thick-film photoresist is coated by spin coating, with the thickness controlled at 12±0.5 micrometers. Then, it is soft-baked on a hot plate at a temperature of 90℃~110℃ for 120s~180s. Step 3: Expose the image using the first photomask (do not expose the grooves in the positive resist pattern, expose the grooves in the negative resist pattern) on a lithography machine at an exposure dose of 200 mJ / cm². Then, perform soft baking on a hot plate at a temperature of 90℃~110℃ for 60s~110s. Subsequently, develop the image using a developer (e.g., 2.38% TMAH) for a typical time of 90 seconds to form the first pattern. Step 4: Spin-coat a second thin layer of positive photoresist onto the above structure, controlling the thickness to 2 micrometers. Bake at 90℃~110℃ for 60s~110s. Expose using a photomask (with a pattern CD of 500nm) on the same i-line lithography machine at an exposure dose of 180~200 mJ / cm², followed by soft baking on a hot plate at 90℃~110℃ for 60s~110s. Develop using a standard developer (e.g., 2.38% TMAH) for a typical time of 60s to form the final pattern. Step 5: ICP etching process, using the second thin adhesive pattern as the main etching mask and the first thick adhesive as the auxiliary mask and support, to perform deep etching on the underlying silicon nitride substrate.

[0027] Example 5 Step 1: Select a GaAs wafer, and form a deep trench with a depth of 15 micrometers and a width of 5 micrometers on its surface by dry etching. Then, use PECVD to deposit 300nm silicon nitride. Step 2: Apply a positive thick-film photoresist by spin coating, controlling the thickness to 120 micrometers. Then, perform soft baking on a hot plate at 100℃ for 160 seconds. Step 3: The photomask (with a pattern CD of 8 micrometers) is exposed on an i-line stepper lithography machine at an exposure dose of 200 mJ / cm², and then soft-baked on a hot plate at 90°C for 80 seconds. Subsequently, it is developed using 2.38% TMAH developer for 90 seconds to form the first pattern, which defines the area window requiring high-precision etching. Step 4: Apply a second thin layer of positive photoresist, controlling the thickness to 2 micrometers. Then perform soft baking at 90℃ for 110 seconds. Expose the second photomask (with a pattern CD of 500nm) on the same i-line lithography machine at an exposure dose of 200mJ / cm², followed by soft baking on a hot plate at 110℃ for 60 seconds. Develop with 2.38% TMAH developer for 60 seconds to form a high-precision second pattern. At this point, the second pattern is precisely located within the window defined by the first pattern.

[0028] Step 5, ICP etching process: using the second thin adhesive pattern as the main etching mask and the first thick adhesive as the auxiliary mask and support, the underlying silicon nitride substrate is deeply etched.

[0029] Example 6 Step 1: Prepare a GaAs wafer, and form deep trenches with a depth of 15 micrometers and a width of 5 micrometers on its surface by dry etching. Then, deposit 300nm silicon nitride using PECVD. Step 2: Coat the wafer with negative adhesive with a thickness controlled at 12±0.5 micrometers, and bake at 110℃ on a hot plate for 100 seconds.

[0030] Step 3: Then develop the solution (2.38% TMAH) for 60 seconds; Step 4: Spin-coat a second thin layer of positive photoresist onto the above structure, controlling the thickness to 2 micrometers. Then perform soft baking at 100°C for 80 seconds. Expose using a photomask (with a pattern CD of 500nm) on the same i-line lithography machine at 190mJ / cm². Follow with soft baking on a hot plate at 100°C for 90 seconds. Then develop using a standard developer (e.g., 2.38% TMAH) for a typical time of 60 seconds to form the final pattern. Step 5: ICP etching process, using the second thin adhesive pattern as the main etching mask and the first thick adhesive as the auxiliary mask and support, to perform deep etching on the underlying silicon nitride substrate.

[0031] The advantages of the present invention are specifically reflected in the following aspects: 1. Balancing deep trench filling and high-resolution graphics By using a dual-layer photoresist structure (a thick layer for support and trench filling, and a thin layer for high-resolution patterning), the contradiction that traditional single-layer photoresist cannot simultaneously satisfy deep trench filling and fine pattern definition is resolved.

[0032] 2. Strong process compatibility It offers multiple process paths (positive adhesive + negative adhesive combination, double positive adhesive, double negative adhesive, etc.), which can be flexibly selected according to the target feature size (CD) and trench depth to adapt to different device requirements. For example: A. When the target CD is < 2μm, positive photoresist should be used first to ensure resolution; B. When the target CD is large, negative adhesive can be used to simplify the process.

[0033] 3. Reduce defects and optimize process window A. The thick photoresist layer (12±0.5μm) is thinned by weak exposure and weak development to avoid complete development and loss of photoresist in the trench, and retains a thickness of 5-8μm as etching support to prevent sidewall collapse or insufficient bottom exposure.

[0034] B. The thin film layer (second layer) has independently controlled exposure dose (180-200mJ / cm²) and baking parameters (90-110℃) to optimize the roughness and resolution of the graphic edge.

[0035] 4. Balancing cost and efficiency No complex equipment is required; it can be achieved using existing photolithography equipment, thus reducing production costs. For example: A. The solutions in Examples 1 and 4 allow for the interchangeability of positive and negative adhesives, reducing material limitations; B. Wide exposure (80-100mJ / cm²) replaces high-precision alignment, simplifying the process.

[0036] 5. Structural adaptability Clearly tolerates process redundancy: The photoresist in the trench can be slightly higher than the wafer plane (protrusion), as long as the etching window is kept open, reducing the dependence on global planarization, which is suitable for non-planar substrates or hard materials such as silicon nitride.

Claims

1. A double-layer photolithography method for semiconductor devices with deep trench structures, characterized in that, The first photolithography process creates a deep trench filled with photoresist. Based on this, a second photolithography process is performed to form a specific etched pattern. Finally, the etched pattern formed by the second photolithography process is used as the main etch mask, and the photoresist in the first photolithography process is used as an auxiliary mask and support to transfer the patterned device below.

2. The double-layer photolithography method for semiconductor devices with deep trench structures according to claim 1, characterized in that, Follow these steps: Step 1: Deposit 100~300nm silicon nitride on a wafer substrate with a deep trench structure using chemical vapor deposition; Step 2: Apply positive or negative photoresist to the upper surface of the wafer by spin coating, with the thickness controlled at 12±0.5μm. Then perform soft baking on a hot plate at a temperature of 90℃~110℃ for 120s~180s. Step 3: Expose the area defined by the first photomask with an exposure dose of 300~500mJ / cm². After exposure, continue baking at a temperature of 90℃~100℃ for 60s~90s. After baking, develop the area with a developer for 90~120s to form the etched area window. Step 4: Coat the wafer after development in Step 3 with a second layer of positive photoresist, with the thickness controlled at 1~5μm. Then bake it on a hot plate at a temperature of 90℃~110℃ for 60s~110s. Step 5: Expose the area defined by the second photomask at an exposure dose of 180mJ / cm² to 200mJ / cm², then bake at a temperature of 90℃ to 110℃ for 60s to 110s. After baking, develop the area with a developer for 30 to 90s to form the etched pattern. Step 6: Using the second thin adhesive layer pattern as the main etching mask and the first thick adhesive layer as the auxiliary mask and support, perform deep etching on the underlying silicon nitride substrate.

3. The double-layer photolithography method for semiconductor devices with deep trench structures according to claim 2, characterized in that, In step 3, the first photomask exposes the area to be etched and blocks the light from the rest of the area. In step 5, the second photomask exposes only the pattern to be etched in the area to be etched and blocks the light from the rest of the area.

4. The double-layer photolithography method for semiconductor devices with deep trench structures according to claim 1, characterized in that, Do it in the following way: Step 1: Deposit 100~300nm silicon nitride on a wafer substrate with a deep trench structure using chemical vapor deposition; Step 2: Apply positive photoresist to the upper surface of the wafer by spin coating, with the thickness controlled at 12±0.5μm. Then, perform general exposure on the photoresist with an exposure dose of 80~100mj². After exposure, bake at a temperature of 90℃~110℃ for 120s~180s. Step 3: Develop the baked photoresist with a developer for 45-60 seconds; Step 4: Spin-coat a second layer of photoresist onto the developed photoresist structure, with a thickness of 1-5 μm, and then bake it at a stable temperature of 90-110℃ for 60-110 seconds. After baking, expose the defined exposure area with a third photomask at an exposure dose of 180-200 mJ / cm², and then bake it at a temperature of 90-110℃ for 60-110 seconds. Step 5: Develop the photoresist baked in Step 4 using a developer solution for 30-90 seconds to form the etched pattern; Step 6: Using the second thin adhesive layer pattern as the main etching mask and the first thick adhesive layer as the auxiliary mask and support, perform deep etching on the underlying silicon nitride substrate.

5. The double-layer photolithography method for semiconductor devices with deep trench structures according to claim 4, characterized in that, The third photomask exposes the pattern to be etched while blocking light from other parts of the image.

6. The double-layer photolithography method for semiconductor devices with deep trench structures according to claim 1, characterized in that, Follow these steps: Step 1: Deposit 100~300nm silicon nitride on a wafer substrate with a deep trench structure using chemical vapor deposition; Step 2: Apply negative photoresist to the upper surface of the wafer by spin coating, with the thickness controlled at 12±0.5μm, and then bake it at a temperature of 100℃~110℃ for 90s~110s. Step 3: Develop the baked photoresist with developer for 45-60 seconds; At least 5-8 micrometers of photoresist should be retained in the trenches; Step 4: Spin-coat positive photoresist onto the developed photoresist structure, with the thickness controlled at 1~5μm, and then bake it at a stable temperature of 90℃~110℃ for 60s~110s. After baking, expose the limited exposure area with a fourth photomask at an exposure dose of 180mJ / cm²~200mJ / cm², and then bake it again at a temperature of 90℃~110℃ for 60s~110s. Step 5: Develop the photoresist baked in Step 4 using a developer solution for 30-90 seconds to form the etched pattern; Step 6: Using the second thin adhesive layer pattern as the main etching mask and the first thick adhesive layer as the auxiliary mask and support, perform deep etching on the underlying silicon nitride substrate.

7. The double-layer photolithography method for semiconductor devices with deep trench structures according to claim 6, characterized in that, The fourth photomask exposes the pattern to be etched while blocking light from the rest of the pattern.

8. The double-layer photolithography method for semiconductor devices with deep trench structures according to claim 1, characterized in that, Follow these steps: Step 1: Deposit 100~300nm silicon nitride on a wafer substrate with a deep trench structure using chemical vapor deposition; Step 2: Apply positive photoresist to the upper surface of the wafer by spin coating, with the thickness controlled at 12±0.5μm, and then bake it at a temperature of 90℃~110℃ for 120s~180s. Step 3: Expose the area defined by the fifth photomask with an exposure dose of 200~400mJ / cm². After exposure, bake at a temperature of 90℃~110℃ for 60s~110s. Then develop with developer for 90s~120s. Step 4: Spin-coat a second layer of photoresist onto the developed wafer structure, with the thickness controlled at 1~5μm. Then, use a sixth photomask to define the exposure area for exposure, with an exposure dose of 180mJ / cm²~200mJ / cm². After exposure, bake the photoresist at a temperature of 90℃~110℃ for 60s~110s. Step 5: Develop the photoresist baked in Step 4 using a developer solution for 30-90 seconds to form the etched pattern; Step 6: Using the second thin adhesive layer pattern as the main etching mask and the first thick adhesive layer as the auxiliary mask and support, perform deep etching on the underlying silicon nitride substrate.

9. The double-layer photolithography method for semiconductor devices with deep trench structures according to claim 8, characterized in that, In step 3, the fifth photomask is used to block the deep trenches of the wafer substrate, and in step 4, the sixth photomask exposes the pattern to be etched, blocking the light from the rest of the area.

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