Low parasitic inductance module structure

By reducing parasitic inductance through a parallel insulating substrate structure and the principle of magnetic phase cancellation, combined with functional partitioning design and precise connection, the problems of inductance, electromagnetic interference and heat dissipation of power modules in high-frequency and high-power-density systems are solved, achieving efficient energy conversion and improved stability.

CN122055024APending Publication Date: 2026-05-15JIANGSU APT SEMICONDUCTOR CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
JIANGSU APT SEMICONDUCTOR CO LTD
Filing Date
2026-02-02
Publication Date
2026-05-15

AI Technical Summary

Technical Problem

In high-frequency, high-power-density power electronic systems, the parasitic inductance problem in existing power modules leads to increased switching losses, aggravated electromagnetic interference, decreased system stability, and increased thermal management pressure. Existing designs struggle to balance low inductance, optimized structural layout, and heat dissipation performance.

Method used

By adopting a parallel insulating substrate structure, the parasitic inductance is reduced by using the principle of magnetic phase cancellation through opposite currents. The current loop is optimized through functional partitioning design and precise connection layout. Combined with the separation of conductivity and heat dissipation functions, the current path is minimized and made more uniform.

Benefits of technology

It significantly reduces parasitic inductance, minimizes voltage and current overlap losses, suppresses electromagnetic noise, improves system stability and heat dissipation efficiency, adapts to high-frequency requirements, reduces production costs, and facilitates mass production.

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Abstract

The invention relates to the technical field of semiconductors, in particular to a low parasitic inductance module structure. The first insulating substrate at least comprises a positive electrode connecting area and an output connecting area which are arranged at an interval; a first metal layer A at the bottom of the first insulating substrate does not participate in electric conduction and is connected with the outside as a heat dissipation carrier; the second insulating substrate comprises a first metal layer B, an insulating layer B and a second metal layer B which are sequentially connected from bottom to top; according to the scheme, the second insulating substrate is parallel to the first insulating substrate; the power chip group comprises an upper bridge chip group and a lower bridge chip group; the number of chips of the upper bridge chip set is equal to that of chips of the lower bridge chip set. Wherein a first electrode of the upper bridge chip group is connected to a positive electrode connecting area of the first insulating substrate, and a second electrode of the upper bridge chip group is connected to a first metal layer of the second insulating substrate; the production and manufacturing cost can be reduced, and large-scale mass production is facilitated.
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