Multilayer ceramic capacitor

Abstract

The invention provides a multilayer ceramic capacitor capable of suppressing wetting and climbing of solder to a surface opposite to a mounting surface during mounting. A laminated ceramic capacitor (10) according to the present invention is provided with: a laminated body having a first surface and a second surface facing each other in a lamination direction, a third surface and a fourth surface facing each other in a first direction orthogonal to the lamination direction, and a fifth surface and a sixth surface facing each other in a second direction orthogonal to the lamination direction and the first direction; a first external electrode disposed on the first surface and the third surface; a second external electrode disposed on the first surface and the fourth surface; a third external electrode disposed on the first surface and the third surface; and a fourth external electrode disposed on the first surface and the fourth surface. The laminate includes a first internal electrode and a second internal electrode. The first external electrode includes: a first base layer connected to the first internal electrode; a first thin film layer disposed on the first surface; and a first surface plating layer. The first external electrode has a first recess located on the inner side of the laminate, and the dimension of the first recess in the second direction is longer than the dimension in the first direction.

Description

Technical Field

[0001] This invention relates to multilayer ceramic capacitors. Background Technology

[0002] In recent years, electronic devices such as portable telephones and portable music players have been continuously miniaturized and made thinner. Along with this, the miniaturization and thinning of multilayer ceramic capacitors incorporated within these miniaturized and thinner electronic devices has also been pursued (see Patent Document 1). In particular, thinner multilayer ceramic capacitors are being developed for use, for example, embedded within a wiring substrate, or even mounted on the surface of a wiring substrate within very narrow gaps.

[0003] Prior art literature

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-101449 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] The multilayer ceramic capacitor described in Patent Document 1, etc., has an approximately square lattice shape and a thinner thickness in the stacking direction. If the thickness in the stacking direction is thinner, the solder used during installation may excessively wet and climb in the direction perpendicular to the mounting surface, thereby wetting and climbing to the side of the multilayer ceramic capacitor opposite to the mounting surface. Corresponding to the amount of solder wetting and climbing, the mounting height may become higher.

[0008] Therefore, the main objective of this invention is to provide a multilayer ceramic capacitor that can suppress solder wetting and creeping onto the surface opposite to the mounting surface during installation.

[0009] Technical solutions for solving the problem

[0010] The multilayer ceramic capacitor of the present invention comprises: a multilayer body having a first and a second surface opposite to each other in the stacking direction, a third and a fourth surface opposite to each other in a first direction orthogonal to the stacking direction, and a fifth and a sixth surface opposite to each other in a second direction orthogonal to the stacking direction and the first direction; a first external electrode disposed on the first and third surfaces; a second external electrode disposed on the first and fourth surfaces; a third external electrode disposed on the first and third surfaces; and a fourth external electrode disposed on the first and fourth surfaces. In the multilayer ceramic capacitor, the multilayer body includes a first internal electrode and a second internal electrode. The first external electrode includes: a first base layer connected to the first internal electrode; a first thin film layer disposed on the first surface; and a first surface coating layer. The first external electrode has a first recess located inside the multilayer body, and the dimension of the first recess in the second direction is longer than the dimension in the first direction.

[0011] According to the multilayer ceramic capacitor of the present invention, the first external electrode includes: a first base layer connected to a first internal electrode; a first thin film layer disposed on a first surface; and a first surface plating layer. The first external electrode has a first recess located inside the multilayer. The dimension of the first recess in a second direction is longer than the dimension in the first direction. Therefore, during installation, the first recess can suppress solder wetting and creeping from the first surface to the external electrode disposed on the opposite surface in the second direction.

[0012] Invention Effects

[0013] According to the present invention, a multilayer ceramic capacitor is provided that can suppress solder wetting and creeping onto the surface opposite to the mounting surface during installation.

[0014] The above-described objects, other objects, features, and advantages of the present invention will become clearer from the following detailed description of specific embodiments with reference to the accompanying drawings. Attached Figure Description

[0015] Figure 1A This is a perspective view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention.

[0016] Figure 1B This is a perspective view of an example of a multilayer ceramic capacitor according to the first embodiment of the present invention, viewed from another direction.

[0017] Figure 2 This is a front view illustrating an example of a multilayer ceramic capacitor according to the first embodiment of the present invention.

[0018] Figure 3 This is a side view illustrating an example of a multilayer ceramic capacitor according to the first embodiment of the present invention.

[0019] Figure 4 yes Figure 1A A schematic cross-sectional view of line IV-IV involved.

[0020] Figure 5 yes Figure 1A A schematic cross-sectional view of line VV involved.

[0021] Figure 6 yes Figure 1A A cross-sectional view of line VI-VI.

[0022] Figure 7 yes Figure 1A A schematic cross-sectional view of line VII-VII.

[0023] exist Figure 8 In the middle, (a) is Figure 6 Part A is an enlarged view, which is an illustrative diagram schematically showing the structure of the basal layer; (b) is... Figure 6 The enlarged view of part A is an illustrative diagram schematically showing the structure of the Sn coating.

[0024] Figure 9A yes Figure 2 A cross-sectional view of line IXA-IXA involved.

[0025] Figure 9B yes Figure 2 A schematic cross-sectional view of line IXB-IXB.

[0026] Figure 10 yes Figure 1A An exploded three-dimensional view of the stacked body shown.

[0027] Figure 11A This is a perspective view of an example of a multilayer ceramic capacitor according to the second embodiment of the present invention, viewed from one direction.

[0028] Figure 11B This is a perspective view of an example of a multilayer ceramic capacitor according to the second embodiment of the present invention, viewed from another direction.

[0029] Figure 12 This is a front view illustrating an example of a multilayer ceramic capacitor according to the second embodiment of the present invention.

[0030] Figure 13 yes Figure 11A A schematic cross-sectional view of line XIII-XIII involved.

[0031] Figure 14 yes Figure 11A A schematic cross-sectional view of line XIV-XIV involved.

[0032] Figure 15 yes Figure 11A A schematic cross-sectional view of the line XV-XV involved.

[0033] Figure 16 yes Figure 11A A schematic cross-sectional view of line XVI-XVI involved.

[0034] Figure 17A yes Figure 12 A schematic cross-sectional view of the line XVIIA-XVIIA involved.

[0035] Figure 17B yes Figure 12 A schematic cross-sectional view of the line XVIIB-XVIIB involved.

[0036] Figure 18 yes Figure 11A An exploded three-dimensional view of the stacked body shown.

[0037] Figure 19A This is a perspective view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention.

[0038] Figure 19B This is a perspective view of an example of a multilayer ceramic capacitor according to the second embodiment of the present invention, viewed from another direction.

[0039] Figure 20 yes Figure 19A A cross-sectional schematic diagram of the line XX-XX involved.

[0040] Figure 21 yes Figure 19A A schematic cross-sectional view of line XXI-XXI involved.

[0041] Figure 22 yes Figure 19A A schematic cross-sectional view of line XXII-XXII involved.

[0042] Figure 23 yes Figure 19A A schematic diagram of the cross-section at point XXIII-XXIII involved. Detailed Implementation

[0043] A. First Implementation

[0044] 1. Multilayer ceramic capacitor

[0045] Next, an example of a multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0046] Figure 1AThis is a perspective view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 1B This is a perspective view of an example of a multilayer ceramic capacitor according to the first embodiment of the present invention, viewed from another direction. Figure 2 This is a front view illustrating an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 3 This is a side view illustrating an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 4 yes Figure 1A A schematic cross-sectional view of line IV-IV involved. Figure 5 yes Figure 1A A schematic cross-sectional view of line VV involved. Figure 6 yes Figure 1A A cross-sectional view of line VI-VI. Figure 7 yes Figure 1A A schematic cross-sectional view of line VII-VII. Figure 8 (a) is Figure 6 Part A of the diagram is an enlarged view, which is a schematic illustration of the structure of the basal layer. Figure 8 (b) is Figure 6 The enlarged view of part A is an illustrative diagram schematically showing the structure of the Sn coating. Figure 9A yes Figure 2 A cross-sectional view of line IXA-IXA involved. Figure 9B yes Figure 2 A schematic cross-sectional view of line IXB-IXB. Figure 10 yes Figure 1A An exploded three-dimensional view of the stacked body shown.

[0047] The multilayer ceramic capacitor 10 has a multilayer body 12 and multiple external electrodes 30.

[0048] (Layered structure)

[0049] The laminate 12 has a first surface 12a and a second surface 12b opposite each other in the lamination direction x, a third surface 12c and a fourth surface 12d opposite each other in the first direction y orthogonal to the lamination direction x, and a fifth surface 12e and a sixth surface 12f opposite each other in the second direction z orthogonal to both the lamination direction x and the first direction y. The direction in which the first surface 12a and the second surface 12b of the laminate 12 are connected to each other is the lamination direction x.

[0050] Furthermore, the laminate 12 preferably has rounded corners and edges. A corner is the intersection of three adjacent faces of the laminate 12, and an edge is the intersection of two adjacent faces of the laminate 12. Additionally, some or all of the third face 12c, fourth face 12d, fifth face 12e, and sixth face 12f may have irregularities or protrusions.

[0051] In addition, the surface of either the first surface 12a or the second surface 12b can be roughened.

[0052] The laminate 12 includes a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 have an inner dielectric layer 14a and an outer dielectric layer 14b. In addition, the internal electrodes 16 have a first internal electrode 16a and a second internal electrode 16b.

[0053] Furthermore, the laminate 12 has an inner layer 18, a first outer layer 20a located on the side of the first surface 12a, and a second outer layer 20b located on the side of the second surface 12b.

[0054] The first outer layer 20a is located on the first surface 12a side of the laminate 12 and is an assembly of multiple outer dielectric layers 14b located between the first surface 12a and the inner electrode 16 closest to the first surface 12a.

[0055] The second outer layer 20b is located on the second surface 12b side of the laminate 12 and is an assembly of multiple outer dielectric layers 14b located between the second surface 12b and the inner electrode 16 closest to the second surface 12b.

[0056] Furthermore, the area sandwiched between the first outer layer 20a and the second outer layer 20b is the inner layer 18.

[0057] The inner layer 18 includes: a first internal electrode 16a, one end of which is exposed on the third surface 12c and the fifth surface 12e, and the other end of which is exposed on the fourth surface 12d and the sixth surface 12f; a second internal electrode 16b, one end of which is exposed on the third surface 12c and the sixth surface 12f, and the other end of which is exposed on the fourth surface 12d and the fifth surface 12e; and an inner dielectric layer 14a.

[0058] The dielectric layer 14 can be formed from a dielectric material, for example. As a dielectric material, a dielectric ceramic containing main components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 can be used. Alternatively, materials with secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds added to these main components can also be used. Furthermore, the inner dielectric layer 14a and the outer dielectric layer 14b can contain the same dielectric material, or different dielectric materials can be included in the inner layer 18 and the outer layers 20a, 20b for functional differentiation. Additionally, at least one of Si, Mg, Ba, Mn, etc., can be added as an additive material.

[0059] Regarding the inner dielectric layer 14a, for example, if it contains a large amount of CaTiO3 or CaZrO3 as a dielectric component, it can reduce the likelihood of insulation breakdown occurring between the first inner electrode 16a and the second inner electrode 16b. Furthermore, it is not limited to this; the inner dielectric layer 14a can also contain SrTiO3 or the like as a main component. In addition, to increase the capacitance of the multilayer ceramic capacitor 10, it is preferable to form it from a material with a high dielectric constant (e.g., BaTiO3). The composition of the outer dielectric layer 14b is preferably the same type of composition as that of the inner dielectric layer 14a.

[0060] The dielectric layer 14 can have multiple grains containing a perovskite-type compound with BaTiO3 as the basic structure.

[0061] When the dielectric layer 14 is thin, the capacitance of the capacitor becomes larger, so the crystal grain size is preferably less than 1 μm.

[0062] The number of stacked dielectric layers 14 is not particularly limited, but it is preferable to have 3 or more and 300 or less, including the first outer layer 20a and the second outer layer 20b. Furthermore, the thickness of the inner dielectric layer 14a is preferably 0.4 μm or more and 2.0 μm or less, and the thickness of the outer dielectric layer 14b is preferably 2.0 μm or more and 100.0 μm or less.

[0063] When the direction opposite to the third face 12c and the fourth face 12d is designated as the first direction y, and the direction opposite to the fifth face 12e and the sixth face 12f is designated as the second direction z, the dimension L in the first direction y and the dimension W in the second direction z of the laminate 12 satisfy the condition 0.85 ≤ L / W ≤ 1.00. That is, the laminate 12 has an approximately square lattice shape.

[0064] (Internal electrodes)

[0065] The internal electrode 16 has a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b. The first internal electrodes 16a and the second internal electrodes 16b are stacked alternately with a dielectric layer 14 between them.

[0066] The first internal electrode 16a is disposed on the surface of the inner dielectric layer 14a. The first internal electrode 16a is opposite to the first surface 12a and the second surface 12b, has a first opposing electrode portion 22a opposite to the second internal electrode 16b, and is stacked in the direction connecting the first surface 12a and the second surface 12b.

[0067] The first internal electrode 16a is led out to the third surface 12c and the fifth surface 12e of the laminate 12 via the first lead-out electrode portion 24a, and is led out to the fourth surface 12d and the sixth surface 12f of the laminate 12 via the second lead-out electrode portion 24b. Furthermore, the width of the first lead-out electrode portion 24a leading to the third surface 12c can be approximately equal to the width leading to the fifth surface 12e, and the width of the second lead-out electrode portion 24b leading to the fourth surface 12d can be approximately equal to the width leading to the sixth surface 12f.

[0068] Furthermore, the first internal electrode 16a is continuously led out to the third surface 12c and the fifth surface 12e of the laminate 12 through the first lead-out electrode portion 24a, and is continuously led out to the fourth surface 12d and the sixth surface 12f of the laminate 12 through the second lead-out electrode portion 24b. However, it is not limited to this and may be led out discontinuously.

[0069] The second internal electrode 16b is disposed on the surface of an inner dielectric layer 14a that is different from the inner dielectric layer 14a on which the first internal electrode 16a is disposed. The second internal electrode 16b is opposite to the first surface 12a and the second surface 12b, has a second opposing electrode portion 22b opposite to the first internal electrode 16a, and is stacked in the direction connecting the first surface 12a and the second surface 12b.

[0070] The second internal electrode 16b is led out to the third surface 12c and the sixth surface 12f of the laminate 12 via the third lead-out electrode portion 24c, and to the fourth surface 12d and the fifth surface 12e of the laminate 12 via the fourth lead-out electrode portion 24d. Furthermore, the width of the third lead-out electrode portion 24c leading to the third surface 12c can be approximately equal to the width leading to the sixth surface 12f, and the width of the fourth lead-out electrode portion 24d leading to the fourth surface 12d can be approximately equal to the width leading to the fifth surface 12e.

[0071] Furthermore, the second internal electrode 16b is continuously led out to the third surface 12c and the sixth surface 12f of the laminate 12 via the third lead-out electrode portion 24c, and is continuously led out to the fourth surface 12d and the fifth surface 12e of the laminate 12 via the fourth lead-out electrode portion 24d. However, it is not limited to this and may be led out discontinuously.

[0072] Furthermore, when viewing the stacked ceramic capacitor 10 from the stacking direction x, the straight line connecting the first lead-out electrode portion 24a and the second lead-out electrode portion 24b of the first internal electrode 16a preferably intersects the straight line connecting the third lead-out electrode portion 24c and the fourth lead-out electrode portion 24d of the second internal electrode 16b.

[0073] In addition, such as Figure 7 As shown, the laminate 12 includes: a side portion (W-spaced) 26a of the laminate 12, located between one end of the second opposing electrode portion 22b of the second internal electrode 16b in the first direction y and the third surface 12c; and a side portion (W-spaced) 26b of the laminate 12, located between the other end of the first opposing electrode portion 22a of the first internal electrode 16a in the first direction y and the fourth surface 12d.

[0074] Furthermore, such as Figure 6 As shown, the laminate 12 includes: an end portion (L-space) 27a of the laminate 12, located between one end of the second opposing electrode portion 22b of the second internal electrode 16b in the second direction z and the fifth surface 12e; and a side portion (L-space) 27b of the laminate 12, located between the other end of the first opposing electrode portion 22a of the first internal electrode 16a in the second direction z and the sixth surface 12f.

[0075] The first internal electrode 16a and the second internal electrode 16b may, for example, contain suitable conductive materials such as metals like Ni, Cu, Ag, Pd, and Au, alloys containing at least one of these metals like Ni-Cu alloys and Ag-Pd alloys, but are not limited thereto. Furthermore, the first internal electrode 16a and the second internal electrode 16b may contain the same conductive material or different conductive materials.

[0076] Furthermore, by including a Sn layer at the interface between the first internal electrode 16a and the second internal electrode 16b and the dielectric layer 14, the concentration of electric field at the interface between the internal electrode 16 and the dielectric layer 14 can be mitigated, thereby improving the reliability under high-temperature loads.

[0077] Furthermore, regarding the number of the first internal electrode 16a and the second internal electrode 16b, it is preferable that the total number is 3 or more and 300 or less. Additionally, the thickness of the first internal electrode 16a and the second internal electrode 16b is not particularly limited, but is preferably, for example, 0.2 μm or more and 2.0 μm or less.

[0078] Alternatively, the stacked body 12 of the multilayer ceramic capacitor 10 may also have the structure described below.

[0079] In the multilayer ceramic capacitor 10, when viewed in the stacking direction x, the third surface 12c to the sixth surface 12f of the multilayer 12 can also be bent into a concave shape toward the center of the multilayer 12. That is, the third surface 12c to the sixth surface 12f of the multilayer 12 can also be warped. In this case, the center of bending and warping is preferably near the center of the third surface 12c to the sixth surface 12f. As a result, the distance between adjacent external electrodes 30 described later can be increased, thereby reducing the risk of conduction between the external electrodes 30.

[0080] Furthermore, when viewed in at least one of the first direction y and the second direction z, the region where the internal electrode 16 is extended on the third surface 12c to the sixth surface 12f preferably has an R-shape from the first surface 12a to the second surface 12b. This increases the exposed area of ​​the internal electrode 16, thereby increasing the contact area between the internal electrode 16 and the external electrode 30.

[0081] (External electrode)

[0082] As shown in Figure 1 to Figure 7 As shown, an external electrode 30 is disposed in the laminate 12.

[0083] The external electrode 30 has a plurality of external electrodes 30 connected to the first internal electrode 16a and the second internal electrode 16b. The external electrode 30 has a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0084] The first external electrode 30a is configured to cover the first lead-out electrode portion 24a of the first internal electrode 16a on the third surface 12c and the fifth surface 12e. Furthermore, the first external electrode 30a is configured to cover a portion of the first surface 12a and a portion of the second surface 12b. The first external electrode 30a is electrically connected to the first lead-out electrode portion 24a of the first internal electrode 16a.

[0085] The second external electrode 30b is configured to cover the second lead-out electrode portion 24b of the first internal electrode 16a on the fourth surface 12d and the sixth surface 12f. Furthermore, the second external electrode 30b is configured to cover a portion of the first surface 12a and a portion of the second surface 12b. The second external electrode 30b is electrically connected to the second lead-out electrode portion 24b of the first internal electrode 16a.

[0086] The third external electrode 30c is configured to cover the third lead-out electrode portion 24c of the second internal electrode 16b on the third surface 12c and the sixth surface 12f. Furthermore, the third external electrode 30c is configured to cover a portion of the first surface 12a and a portion of the second surface 12b. The third external electrode 30c is electrically connected to the third lead-out electrode portion 24c of the second internal electrode 16b.

[0087] The fourth external electrode 30d is configured to cover the fourth lead-out electrode portion 24d of the second internal electrode 16b on the fourth surface 12d and the fifth surface 12e. Furthermore, the fourth external electrode 30d is configured to cover a portion of the first surface 12a and a portion of the second surface 12b. The fourth external electrode 30d is electrically connected to the fourth lead-out electrode portion 24d of the second internal electrode 16b.

[0088] When viewed in the stacking direction x, the external electrode 30 has a first recess 40 extending in the first direction y inside the stack 12. Alternatively, the external electrode 30 may also have a second recess 42 extending in the second direction z inside the stack 12.

[0089] More specifically, when the first external electrode 30a is covered by the first surface 12a, the second surface 12b, the third surface 12c, and the fifth surface 12e, when viewed from the first surface 12a side in the stacking direction x, the first external electrode 30a has a second recess 42a1 extending in the second direction z on the third surface 12c side and a first recess 40a1 extending in the first direction y on the fifth surface 12e side.

[0090] Furthermore, when the first external electrode 30a is covered by the first surface 12a, the second surface 12b, the third surface 12c, and the fifth surface 12e, when viewed from the second surface 12b side in the stacking direction x, the first external electrode 30a has a second recess 42a2 extending in the second direction z on the third surface 12c side and a first recess 40a2 extending in the first direction y on the fifth surface 12e side.

[0091] When viewed from the first surface 12a in the stacking direction x, the dimension of the first recess 40a1 in the first direction y is more than 10% and less than 96.0% of the dimension of the first external electrode 30a on which the first recess 40a1 is formed. More preferably, it is less than 100%. Similarly, when viewed from the second surface 12b in the stacking direction x, the dimension of the first recess 40a2 in the first direction y is more than 10% and less than 96.0% of the dimension of the first external electrode 30a on which the first recess 40a2 is formed. More preferably, it is less than 100%. As a result, excessive wetting and creeping of solder onto the fifth surface 12e can be suppressed. Furthermore, when the first recess 40a1 and the first recess 40a2 are discontinuously arranged, the dimensions of the first recess 40a1 and the first recess 40a2 in the first direction y are defined by their combined length.

[0092] The first recess 40a1 is preferably configured to be at least 0.01 μm and within 10.0 μm of the outermost surface of the fifth surface 12e of the laminate 12. Similarly, the first recess 40a2 is preferably configured to be at least 0.01 μm and within 10.0 μm of the outermost surface of the fifth surface 12e of the laminate 12. That is, the first recess 40a1 and the first recess 40a2 are disposed on the inner side of the laminate 12. As a result, the first recess 40a1 can prevent solder from wetting and creeping from the first surface 12a to the external electrode 30 disposed on the surface opposite to it in the second direction z, or the first recess 40a1 can capture the solder, thus suppressing wetting and creeping to the fifth surface 12e.

[0093] The first recess 40a1 and the second recess 42a1 can also be connected. By connecting the first recess 40a1 and the second recess 42a1, it is also possible to suppress solder wetting and creeping to the portion where two adjacent surfaces intersect. Similarly, the first recess 40a2 and the second recess 42a2 can also be connected. By connecting the first recess 40a2 and the second recess 42a2, it is also possible to suppress solder wetting and creeping to the portion where two adjacent surfaces intersect. When viewed in the first direction y, the distance from the bottom surface of the first recess 40a1 to the vertex of the surface plating layer 36 (described later) located further outward than the first recess 40a1 is preferably 1.0 μm or more.

[0094] When the second external electrode 30b is covered by the first surface 12a, the second surface 12b, the fourth surface 12d, and the sixth surface 12f, when viewed from the first surface 12a side in the stacking direction x, the second external electrode 30b has a second recess 42b1 extending in the second direction z on the fourth surface 12d side and a first recess 40b1 extending in the first direction y on the sixth surface 12f side.

[0095] Furthermore, when the second external electrode 30b is covered by the first surface 12a, the second surface 12b, the fourth surface 12d, and the sixth surface 12f, when viewed from the second surface 12b side in the stacking direction x, the second external electrode 30b has a second recess 42b2 extending in the second direction z on the fourth surface 12d side and a first recess 40b2 extending in the first direction y on the sixth surface 12f side.

[0096] The other structures of the second external electrode 30b are the same as those of the first external electrode 30a.

[0097] When the third external electrode 30c is covered by the first surface 12a, the second surface 12b, the third surface 12c and the sixth surface 12f, when viewed from the first surface 12a side in the stacking direction x, the third external electrode 30c has a second recess 42c extending in the second direction z on the third surface 12c side and a first recess 40b extending in the first direction y on the sixth surface 12f side.

[0098] Furthermore, when the third external electrode 30c is covered by the first surface 12a, the second surface 12b, the third surface 12c, and the sixth surface 12f, when viewed from the second surface 12b side in the stacking direction x, the third external electrode 30c has a second recess 42c2 extending in the second direction z on the third surface 12c side and a first recess 40c2 extending in the first direction y on the sixth surface 12f side.

[0099] The other structures of the third external electrode 30c are the same as those of the first external electrode 30a.

[0100] When the fourth external electrode 30d is covered by the first surface 12a, the second surface 12b, the fourth surface 12d, and the fifth surface 12e, when viewed from the first surface 12a side in the stacking direction x, the fourth external electrode 30d has a second recess 42d extending in the second direction z on the fourth surface 12d side and a first recess 40d extending in the first direction y on the fifth surface 12e side.

[0101] Furthermore, when the fourth external electrode 30d is covered by the first surface 12a, the second surface 12b, the fourth surface 12d, and the fifth surface 12e, when viewed from the second surface 12b side in the stacking direction x, the fourth external electrode 30d has a second recess 42d2 extending in the second direction z on the fourth surface 12d side and a first recess 40d2 extending in the first direction y on the fifth surface 12e side.

[0102] The other structures of the fourth external electrode 30d are the same as those of the first external electrode 30a.

[0103] Within the laminate 12, the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b are opposed to each other across the inner dielectric layer 14a, thereby forming an electrostatic capacitor. Therefore, an electrostatic capacitor can be obtained between the first external electrode 30a and the second external electrode 30b connected to the first internal electrode 16a and the third external electrode 30c and the fourth external electrode 30d connected to the second internal electrode 16b, exhibiting the characteristics of a capacitor.

[0104] The first external electrode 30a, the second external electrode 30b, the third external electrode 30c and the fourth external electrode 30d each have a base layer 32, a thin film layer 34 and a surface coating layer 36.

[0105] In other words, the first external electrode 30a has a first substrate layer 32a, a first thin film layer 34a, and a first surface plating layer 36a. The second external electrode 30b has a second substrate layer 32b, a second thin film layer 34b, and a second surface plating layer 36b. The third external electrode 30c has a third substrate layer 32c, a third thin film layer 34c, and a third surface plating layer 36c. The fourth external electrode 30d has a fourth substrate layer 32d, a fourth thin film layer 34d, and a fourth surface plating layer 36d.

[0106] (Basal layer)

[0107] The substrate layer 32 is disposed on the third surface 12c to the sixth surface 12f. The specific structure of the substrate layer 32 will be described below.

[0108] The first base layer 32a is disposed on the surfaces of the third surface 12c and the fifth surface 12e of the laminate 12, such that the first lead-out electrode portion 24a of the first internal electrode 16a exposed from the third surface 12c and the fifth surface 12e of the laminate 12 is covered.

[0109] The second base layer 32b is disposed on the surfaces of the fourth surface 12d and the sixth surface 12f of the laminate 12, such that it covers the second lead-out electrode portion 24b of the first internal electrode 16a exposed from the fourth surface 12d and the sixth surface 12f of the laminate 12.

[0110] The third base layer 32c is disposed on the surfaces of the third surface 12c and the sixth surface 12f of the laminate 12, such that it covers the third lead-out electrode portion 24c of the second internal electrode 16b exposed from the third surface 12c and the sixth surface 12f of the laminate 12.

[0111] The fourth base layer 32d is disposed on the surfaces of the fourth surface 12d and the fifth surface 12e of the laminate 12, such that it covers the fourth lead-out electrode portion 24d of the second internal electrode 16b exposed from the fourth surface 12d and the fifth surface 12e of the laminate 12.

[0112] Furthermore, the upper end of the first base layer 32a of the first external electrode 30a is preferably connected to the first thin film layer 34a at the ridge formed by the first surface 12a, the third surface 12c, and the fifth surface 12e of the laminate 12. Additionally, the lower end of the first base layer 32a of the first external electrode 30a is preferably connected to the first thin film layer 34a at the ridge formed by the second surface 12b, the third surface 12c, and the fifth surface 12e of the laminate 12. In this case, the first base layer 32a may also be configured to cover the ridge of the third surface 12c and the fifth surface 12e.

[0113] Here, in Figure 8 (a) Taking the first base layer 32a of the first external electrode 30a as an example, its structure will be described in detail. Figure 8 As shown in (a), the distance t1 in the stacking direction x between the front end of the fifth surface 12e of the first substrate layer 32a and the end of the internal electrode 16 closest to the first surface 12a that is exposed on the fifth surface 12e is preferably 3.0 μm or more and 8.1 μm or less. Furthermore, the first substrate layer 32a is preferably configured to extend toward the first surface 12a. In other words, the distance t2 in the stacking direction x between the point P of the outermost surface of the first surface 12a, located 1.0 μm inward from the fifth surface 12e, and the front end of the first substrate layer 32a is preferably 10.0 μm or less.

[0114] Regarding the thickness t3 of the first base layer 32a, it is preferably 3.0 μm or more and 8.1 μm or less away from the end of the internal electrode 16 closest to the first surface 12a that is exposed on the fifth surface 12e in the first direction y.

[0115] The upper end of the second base layer 32b of the second external electrode 30b is preferably connected to the second thin film layer 34b at the ridge formed by the first surface 12a, the fourth surface 12d, and the sixth surface 12f of the laminate 12. Furthermore, the lower end of the second base layer 32b of the second external electrode 30b is preferably connected to the second thin film layer 34b at the ridge formed by the second surface 12b, the fourth surface 12d, and the sixth surface 12f of the laminate 12. Alternatively, the second base layer 32b may be configured to cover the ridge of the fourth surface 12d and the sixth surface 12f.

[0116] The other structures of the second external electrode 30b are the same as those of the first external electrode 30a.

[0117] The upper end of the third base layer 32c of the third external electrode 30c is preferably connected to the third thin film layer 34c at the ridge formed by the first surface 12a, the third surface 12c, and the sixth surface 12f of the laminate 12. Furthermore, the lower end of the third base layer 32c of the third external electrode 30c is preferably connected to the third thin film layer 34c at the ridge formed by the second surface 12b, the third surface 12c, and the sixth surface 12f of the laminate 12. In this case, the third base layer 32c may also be configured to cover the ridge of the third surface 12c and the sixth surface 12f.

[0118] The other structures of the third external electrode 30c are the same as those of the first external electrode 30a.

[0119] The upper end of the fourth base layer 32d of the fourth external electrode 30d is preferably connected to the fourth thin film layer 34d at the ridge formed by the first surface 12a, the fourth surface 12d, and the fifth surface 12e of the laminate 12. Furthermore, the lower end of the fourth base layer 32d of the fourth external electrode 30d is preferably connected to the fourth thin film layer 34d at the ridge formed by the second surface 12b, the fourth surface 12d, and the fifth surface 12e of the laminate 12. In this case, the fourth base layer 32d may also be configured to cover the ridge of the fourth surface 12d and the fifth surface 12e.

[0120] The other structures of the fourth external electrode 30d are the same as those of the first external electrode 30a.

[0121] The substrate layer 32 may contain Cu as the main metallic component. For example, when Ni is used to form the first internal electrode 16a and the second internal electrode 16b, the substrate layer 32 is preferably made of Cu plating which has good adhesion to Ni.

[0122] The substrate layer 32 is formed by growing a coating from the internal electrode 16.

[0123] The thickness of each layer of the substrate 32 is preferably 0.5 μm or more and 10.0 μm or less.

[0124] (Thin film layer)

[0125] The thin film layer 34 has a first thin film layer 34a, a second thin film layer 34b, a third thin film layer 34c, and a fourth thin film layer 34d.

[0126] The first thin film layer 34a covers a portion of the first surface 12a and a portion of the second surface 12b of the laminate 12 on the third surface 12c side and the fifth surface 12e side. The first thin film layer 34a is preferably configured to be connected to the first substrate layer 32a.

[0127] The second thin film layer 34b covers a portion of the first surface 12a and a portion of the second surface 12b of the laminate 12 on the fourth surface 12d side and the sixth surface 12f side. The second thin film layer 34b is preferably configured to be connected to the second substrate layer 32b.

[0128] The third thin film layer 34c covers a portion of the first surface 12a and a portion of the second surface 12b of the laminate 12 on the third surface 12c side and the sixth surface 12f side. The third thin film layer 34c is preferably configured to be connected to the third substrate layer 32c.

[0129] The fourth thin film layer 34d covers a portion of the first surface 12a and the second surface 12b of the laminate 12 on the fourth surface 12d side and the fifth surface 12e side. The fourth thin film layer 34d is preferably configured to be connected to the fourth substrate layer 32d.

[0130] Each of the first thin film layers 34a to the fourth thin film layers 34d is preferably a thin film layer on which metal particles are deposited, formed by sputtering, vapor deposition, or the like. Therefore, the thickness of the first thin film layers 34a to the fourth thin film layers 34d in the direction connecting the first surface 12a and the second surface 12b of the laminate 12 can be set to 1 μm or less, which can sufficiently reduce the dimension of the laminated ceramic capacitor 10 in the lamination direction x, thus enabling the laminated ceramic capacitor 10 to be made shorter.

[0131] Furthermore, the method for measuring the dimensions in the stacking direction x of the first thin film layer 34a to the fourth thin film layer 34d can be as follows: In the case where the thin film layers are formed by the deposition of metal particles, the thickness can be calculated based on the concentration of a given element using a fluorescence X-ray apparatus and a calibration curve method for that metal type. Alternatively, the thickness can be measured by observing the component cross-section obtained through FIB using a scanning microscope and based on the actual observed image.

[0132] Furthermore, when the first thin film layer 34a to the fourth thin film layer 34d are formed by the thin film forming method, these thin film layers preferably contain metals such as Cu and Ni.

[0133] Furthermore, the first thin film layer 34a to the fourth thin film layer 34d can be configured with their respective functions in mind. For example, considering the close contact with the laminate 12, NiCr or NiCu is preferably used as the main component. In addition, the first thin film layer 34a to the fourth thin film layer 34d can be multiple sheets, or it can be a two-layer structure of NiCr and NiCu.

[0134] The thin film layer 34 can also be a thin film layer containing dielectric material and metallic components, formed by screen printing or the like. Accordingly, the ceramic adhesion between the thin film layer 34 and the laminate 12 can be improved, thereby further enhancing the adhesion between the laminate 12 and the external electrode 30. In this case, in addition to the metallic component, it can also contain a ceramic component whose main component is the same as that of the inner dielectric layer 14a. If the thin film layer 34 contains a ceramic component, the difference in thermal expansion coefficients between the laminate 12 and the thin film layer 34 can be reduced, thus alleviating the stress applied to the thin film layer 34. However, the metallic component is not limited to Cu or Ni; other metallic components can also be included, and a glass component can be included in addition to the ceramic component. Examples of glass components include oxides of Ba (barium), Sr (strontium), Si (silicon), Ca (calcium), Zn, Al, or B (boron). Other metallic components may include, for example, Mg, Cr, Sr, Al, Na, Fe, etc. Furthermore, the thin film layer 34 can also have a discontinuous shape. The term "discontinuity" refers to a discontinuity that occurs when viewed from a direction perpendicular to the length dimension.

[0135] For example, in the case where the thin film layer 34 is formed from a ceramic-containing thin film layer, the following methods exist: after cross-sectional grinding, a cross-sectional photograph is obtained using a digital microscope (KEYENCE: VHX-5000), and the thickness is calculated based on the cross-sectional photograph. Alternatively, the following methods exist: a component cross-section is obtained through FIB using a scanning microscope, and the thickness is measured based on the actual observed image.

[0136] (Surface coating)

[0137] The surface plating layer 36 includes a first surface plating layer 36a, a second surface plating layer 36b, a third surface plating layer 36c, and a fourth surface plating layer 36d.

[0138] The first surface coating layer 36a is configured to cover the first thin film layer 34a and the first base layer 32a disposed on the third surface 12c and the fifth surface 12e of the laminate 12.

[0139] The second surface coating layer 36b is configured to cover the second thin film layer 34b and the second base layer 32b disposed on the fourth surface 12d and the sixth surface 12f of the laminate 12.

[0140] The third surface coating layer 36c is configured to cover the third thin film layer 34c and the third base layer 32c disposed on the third surface 12c and the sixth surface 12f of the laminate 12.

[0141] The fourth surface coating layer 36d is configured to cover the fourth thin film layer 34d and the fourth base layer 32d disposed on the fourth surface 12d and the fifth surface 12e of the laminate 12.

[0142] As a surface coating layer 36, it preferably comprises, for example, at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such metal. The coating layer preferably does not contain glass.

[0143] The surface coating 36 can be, for example, only a Sn coating, or a two-layer structure of Ni-Sn coating or Ni-Cu coating.

[0144] The Sn coating is a Ni coating. Specifically, the Sn coating is formed by depositing and growing a Ni coating as a starting point. The thickness of the Sn coating is preferably 1.0 μm or more and 5.0 μm or less. Figure 8 (b) Taking the first surface plating layer 36a of the first external electrode 30a as an example, its structure will be described in detail. Figure 8 As shown in (b), the first surface plating layer 36a constituting the first external electrode 30a includes a Ni plating layer 36a1 and a Sn plating layer 36a2. In this case, the thickness t4 of the Sn plating layer disposed in the first recess 40a (or the second recess 42a) and the thickness t5 of the Sn plating layer disposed at a distance l from the center (1 / 2) of the first surface 12a on the second direction z side of the first external electrode 30a are preferably |t4-t5|≤t5 / 2. The thickness t6 of the Sn plating layer disposed in the first recess 40a (or the second recess 42a) and the thickness t6 in the region 10 μm away from the leading edge of the Sn plating layer disposed on the first surface 12a are preferably |t4-t6|≤t6 / 2.

[0145] The Sn plating layer constituting the second surface plating layer 36b of the second external electrode 30b, the Sn plating layer constituting the third surface plating layer 36c of the third external electrode 30c, and the fourth surface plating layer 36d constituting the fourth external electrode 30d also have the structure constituting the Sn plating layer constituting the first surface plating layer 36a of the first external electrode 30a as described above.

[0146] Furthermore, the thickness of the surface coating 36 is preferably 0.5 μm or more and 10 μm or less.

[0147] The metal content per unit volume of the surface coating is preferably 99% or more.

[0148] The thickness of each layer of the surface coating is preferably 0.5 μm or more and 10.0 μm or less.

[0149] The dimension in the first direction y of the stacked ceramic capacitor 10, which includes the stacked body 12 and the external electrode 30, is set as dimension L; the dimension in the stacking direction x of the stacked ceramic capacitor 10, which includes the stacked body 12 and the external electrode 30, is set as dimension T; and the dimension in the second direction z of the stacked ceramic capacitor 10, which includes the stacked body 12 and the external electrode 30, is set as dimension W.

[0150] Regarding the dimensions of the multilayer ceramic capacitor 10, preferably, the L dimension in the first direction y is 0.2 mm or more and 3.2 mm or less, the T dimension in the stacking direction x is 0.04 mm or more and 0.22 mm or less, and the W dimension in the second direction z is 0.2 mm or more and 3.2 mm or less. The dimensions of the multilayer ceramic capacitor 10 are preferably set to 0.85 ≤ L / W ≤ 1.00. In this way, the stack 12 becomes a substantially square lattice shape, thus increasing the degree of freedom in mounting.

[0151] The multilayer ceramic capacitor 10 shown in FIG1 has a first recess 40 located inside the multilayer body 12. Therefore, during installation, the solder can be suppressed from wetting and creeping from the first surface 12a to the external electrode disposed on the opposite surface in the second direction z through the first recess 40.

[0152] 2. Manufacturing method of multilayer ceramic capacitors

[0153] The manufacturing method of the multilayer ceramic capacitor according to the first embodiment will be described below.

[0154] First, prepare the conductive paste for the dielectric sheet and internal electrodes. The conductive paste for the dielectric sheet and internal electrodes contains an adhesive and a solvent. Known adhesives and solvents can be used.

[0155] Next, conductive paste for the internal electrodes is printed on the dielectric sheet in a given pattern, for example, by inkjet printing, screen printing, or gravure printing. Thus, a dielectric sheet with a pattern of the first internal electrode and a dielectric sheet with a pattern of the second internal electrode are prepared. Then, the sheet with the pattern of the first internal electrode and the sheet with the pattern of the second internal electrode are laminated together to form the inner layer 18.

[0156] Furthermore, for example, in the case where the printing pattern of the internal electrode is formed by gravure printing, by setting the design of the gravure plate used in gravure printing as the graphic pattern of the first internal electrode, and further, by changing the configuration to correspond to the graphic pattern of the second internal electrode, the desired internal electrodes can be formed respectively.

[0157] Furthermore, when forming the printed pattern of the internal electrode layer by screen printing, by setting the design of the screen printing mask to the pattern of the first internal electrode, and by changing it to the configuration corresponding to the pattern of the second internal electrode, the desired internal electrode can be formed.

[0158] Next, a given number of dielectric sheets without printed internal electrode patterns are stacked, thereby forming the first outer layer 20a on the first surface 12a side. Then, the portion prepared above to become the inner layer 18 is stacked, and a given number of dielectric sheets without printed internal electrode patterns are stacked on the inner layer 18, thereby forming the second outer layer 20b on the second surface 12b side. Thus, a laminated sheet is manufactured.

[0159] Next, the laminated sheets are pressed in the stacking direction by means of isostatic pressing to produce a laminated block.

[0160] Next, the laminated block is cut to the given size into smaller laminated pieces. At this point, the corners and edges of the laminated pieces can also be rounded using methods such as tumble grinding.

[0161] Next, the stacked sheets are fired to produce the stack 12. Regarding the firing temperature, although it depends on the materials of the ceramic and the internal electrodes, it is preferably above 900°C and below 1400°C.

[0162] At this time, the first lead-out electrode portion 24a of the first internal electrode 16a and the third lead-out electrode portion 24c of the second internal electrode 16b are exposed from the third surface 12c of the laminate 12. In addition, the second lead-out electrode portion 24b of the first internal electrode 16a and the fourth lead-out electrode portion 24d of the second internal electrode 16b are exposed from the fourth surface 12d of the laminate 12.

[0163] Next, an external electrode 30 is formed on the laminate 12.

[0164] First, a base layer 32 is formed, exposing the internal electrodes 16 covering the surface of the laminate 12. The base layer 32 is a Cu plating layer, formed by electrolytic plating or electroless plating. Then, the laminate 12 after plating is heat-treated to remove residual moisture remaining in the plating film and at the interface between the laminate 12 and the base layer 32.

[0165] Here, after the base layer 32 is formed, for example, given portions of the first surface 12a and the second surface 12b on the third surface 12c side to the sixth surface 12f side are surface-treated by plasma etching, thereby forming regions for forming the first recess 40 and the second recess 42.

[0166] Next, the laminate 12, which forms the base layer 32, is arranged on the worktable, and for example, a thin film layer 34 is formed on the first surface 12a by sputtering.

[0167] Then, a surface plating layer 36 is formed on the substrate layer 32 and the thin film layer 34 disposed on the surface of the laminate 12. More specifically, a Ni plating layer and a Sn plating layer are formed on the substrate layer 32 and the thin film layer 34 as the surface plating layer 36. During the plating process, either electrolytic plating or electroless plating can be used. However, regarding electroless plating, in order to increase the plating deposition rate, pretreatment using a catalyst or the like is required, which complicates the process. Therefore, electrolytic plating is generally preferred. Furthermore, not limited to this, it is also possible to form a recess after the surface plating layer is formed, for example, after the Ni plating layer, and then form the Sn plating layer.

[0168] As described above, it is possible to manufacture the multilayer ceramic capacitor 10 according to the embodiment shown in FIG1.

[0169] B. Second Implementation Method

[0170] 1. Multilayer ceramic capacitor

[0171] An example of a multilayer ceramic capacitor 110 according to the second embodiment of the present invention will be described.

[0172] Figure 11A This is a perspective view of an example of a multilayer ceramic capacitor according to the second embodiment of the present invention, viewed from one direction. Figure 11B This is a perspective view of an example of a multilayer ceramic capacitor according to the second embodiment of the present invention, viewed from another direction. Figure 12 This is a front view illustrating an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. Figure 13 yes Figure 11A A schematic cross-sectional view of line XIII-XIII involved. Figure 14 yes Figure 11A A schematic cross-sectional view of line XIV-XIV involved. Figure 15 yes Figure 11A A schematic cross-sectional view of the line XV-XV involved. Figure 16 yes Figure 11A A schematic cross-sectional view of line XVI-XVI involved. Figure 17A yes Figure 12 A schematic cross-sectional view of the line XVIIA-XVIIA involved. Figure 17B yes Figure 12 A schematic cross-sectional view of the line XVIIB-XVIIB involved. Figure 18 yes Figure 11AThe exploded perspective view of the stacked structure is shown. Additionally, regarding the structures shown in Figures 1 to 12... Figure 7 For identical or equivalent structures, use the same reference numerals and omit detailed descriptions.

[0173] The multilayer ceramic capacitor 110 includes a multilayer body 112 and an external electrode 130.

[0174] (Layered structure)

[0175] The laminate 12 includes a plurality of dielectric layers 114 and a plurality of internal electrodes 116. The dielectric layers 114 have an inner dielectric layer 114a and an outer dielectric layer 114b. In addition, the internal electrodes 116 have a first internal electrode 116a and a second internal electrode 116b.

[0176] Furthermore, the laminate 112 has an inner layer 118, a first outer layer 120a located on the side of the first surface 112a, and a second outer layer 120b located on the side of the second surface 112b.

[0177] The first outer layer 120a is located on the first surface 112a side of the laminate 112 and is an assembly of multiple outer dielectric layers 114b located between the first surface 112a and the inner electrode 116 closest to the first surface 112a.

[0178] The second outer layer 120b is located on the second surface 112b side of the laminate 12, and is an assembly of multiple outer dielectric layers 114b located between the second surface 112b and the inner electrode 116 closest to the second surface 112b.

[0179] Furthermore, the area sandwiched between the first outer layer 120a and the second outer layer 120b is the inner layer 118.

[0180] The inner layer 118 includes: a first internal electrode 116a, one end of which is exposed on the third surface 112c and the other end of which is exposed on the fourth surface 112d; a second internal electrode 116b, one end of which is exposed on the third surface 112c and the other end of which is exposed on the fourth surface 112d; and an inner dielectric layer 114a.

[0181] The material of dielectric layer 114 is the same as that of dielectric layer 14, so its description is omitted.

[0182] (Internal electrodes)

[0183] The internal electrode 116 has a plurality of first internal electrodes 116a and a plurality of second internal electrodes 116b. The first internal electrodes 116a and the second internal electrodes 116b are stacked alternately with a dielectric layer 114 between them.

[0184] The first internal electrode 116a is disposed on the surface of the inner dielectric layer 114a. The first internal electrode 116a is opposite to the first surface 112a and the second surface 112b, and has a first opposing electrode portion 122a opposite to the second internal electrode 116b, and is stacked in the direction connecting the first surface 112a and the second surface 112b.

[0185] The first internal electrode 116a is led out to the third surface 112c of the laminate 112 via the first lead-out electrode portion 124a, and to the fourth surface 112d of the laminate 112 via the second lead-out electrode portion 124b. The first lead-out electrode portion 124a is led out to the fifth surface 112e side of the laminate 112, and the second lead-out electrode portion 124b is led out to the sixth surface 112f side of the laminate 12.

[0186] The second internal electrode 116b is disposed on the surface of an inner dielectric layer 114a that is different from the inner dielectric layer 114a on which the first internal electrode 116a is disposed. The second internal electrode 116b is opposite to the first surface 112a and the second surface 112b, and has a second opposing electrode portion 122b opposite to the first internal electrode 116a, and is stacked in the direction connecting the first surface 112a and the second surface 112b.

[0187] The second internal electrode 116b is led out to the third surface 112c of the laminate 12 via the third lead-out electrode portion 124c, and to the fourth surface 112d of the laminate 112 via the fourth lead-out electrode portion 124d. The third lead-out electrode portion 124c is led out to the sixth surface 112f side of the laminate 112, and the fourth lead-out electrode portion 124d is led out to the fifth surface 112e side of the laminate 112.

[0188] The first internal electrode 116a and the second internal electrode 116b are not exposed on the fifth surface 112e and the sixth surface 112f of the laminate 112.

[0189] Furthermore, when viewing the stacked ceramic capacitor 110 from the stacking direction x, the straight line connecting the first lead-out electrode portion 124a and the second lead-out electrode portion 124b of the first internal electrode 116a preferably intersects the straight line connecting the third lead-out electrode portion 124c and the fourth lead-out electrode portion 124d of the second internal electrode 116b.

[0190] Furthermore, preferably, in the surfaces 112c, 112d, 112e, and 112f of the laminate 112, the first lead-out electrode portion 124a of the first internal electrode 116a and the fourth lead-out electrode portion 124d of the second internal electrode 116b are led out to opposite positions, and the second lead-out electrode portion 124b of the first internal electrode 116a and the third lead-out electrode portion 124c of the second internal electrode 116b are led out to opposite positions.

[0191] In addition, such as Figure 16 As shown, the laminate 112 includes: a side portion (W-spaced) 126a of the laminate 12, located between one end of the second opposing electrode portion 122b of the second internal electrode 116b in the first direction y and the third surface 112c; and a side portion (W-spaced) 126b of the laminate 112, located between the other end of the first opposing electrode portion 122a of the first internal electrode 116a in the first direction y and the fourth surface 112d.

[0192] Furthermore, such as Figure 15 As shown, the laminate 112 includes: an end portion (L-space) 127a of the laminate 112, located between one end of the second opposing electrode portion 122b of the second inner electrode 116b in the second direction z and the fifth surface 112e; and a side portion (L-space) 127b of the laminate 112, located between the other end of the first opposing electrode portion 122a of the first inner electrode 116a in the second direction z and the sixth surface 112f.

[0193] (External electrode)

[0194] like Figures 11A to 16 As shown, an external electrode 130 is disposed in the laminate 12.

[0195] The external electrode 130 has a plurality of external electrodes 130 connected to the first internal electrode 116a and the second internal electrode 116b. The external electrode 130 has a first external electrode 130a, a second external electrode 130b, a third external electrode 130c, and a fourth external electrode 130d.

[0196] The first external electrode 130a is configured to cover the first lead-out electrode portion 124a of the first internal electrode 116a on the third surface 112c. Furthermore, the first external electrode 130a is configured to cover a portion of the first surface 112a and a portion of the second surface 112b. The first external electrode 130a is electrically connected to the first lead-out electrode portion 124a of the first internal electrode 116a.

[0197] The second external electrode 130b is configured to cover the second lead-out electrode portion 124b of the first internal electrode 116a on the fourth surface 112d. Furthermore, the second external electrode 130b is configured to cover a portion of the first surface 112a and a portion of the second surface 112b. The second external electrode 130b is electrically connected to the second lead-out electrode portion 124b of the first internal electrode 116a.

[0198] The third external electrode 130c is configured to cover the third lead-out electrode portion 124c of the second internal electrode 116b on the third surface 112c. Furthermore, the third external electrode 130c is configured to cover a portion of the first surface 112a and a portion of the second surface 112b. The third external electrode 130c is electrically connected to the third lead-out electrode portion 124c of the second internal electrode 116b.

[0199] The fourth external electrode 130d is configured to cover the fourth lead-out electrode portion 124d of the second internal electrode 116b on the fourth surface 112d. Furthermore, the fourth external electrode 130d is configured to cover a portion of the first surface 112a and a portion of the second surface 112b. The fourth external electrode 130d is electrically connected to the fourth lead-out electrode portion 124d of the second internal electrode 116b.

[0200] Furthermore, such as Figure 12 As shown, the external electrode 130 disposed on the fifth surface 112e or the sixth surface 112f where the internal electrode 116 is not brought out is preferably in a "ko" shape covering the short side of either of the sides where the internal electrode 116 is not brought out and the portion from the end of the short side to the middle of the two long sides.

[0201] When viewed in the stacking direction x, the external electrode 130 has a second recess 142 extending in the second direction z inside the stack 112.

[0202] More specifically, when the first external electrode 130a is covered by the first surface 112a, the second surface 112b and the third surface 112c, when viewed from the first surface 112a side in the stacking direction x, the first external electrode 130a has a second recess 142a1 extending in the second direction z on the third surface 112c side.

[0203] Furthermore, when the first external electrode 130a is covered by the first surface 112a, the second surface 112b, and the third surface 112c, when viewed from the second surface 112b side in the stacking direction x, the first external electrode 130a has a second recess 142a2 extending in the second direction z on the third surface 112c side.

[0204] When viewed from the first surface 112a in the stacking direction x, the dimension of the second recess 142a1 in the second direction z is more than 10% and less than 96.0% of the dimension of the first external electrode 130a forming the second recess 140a1 in the second direction z. More preferably, it is less than 100%. Similarly, when viewed from the second surface 112b in the stacking direction x, the dimension of the second recess 142a2 in the second direction z is more than 10% and less than 96.0% of the dimension of the first external electrode 130a forming the second recess 140a2 in the second direction z. More preferably, it is less than 100%. As a result, excessive wetting and creeping of solder onto the third surface 112c can be suppressed. Furthermore, when the second recess 142a1 and the second recess 142a2 are discontinuously arranged, the dimensions of the second recess 142a1 and the second recess 142a2 in the first direction y are defined by their combined length.

[0205] The second recess 142a1 is preferably configured to be at least 0.01 μm and within 10.0 μm of the outermost surface of the third surface 112c of the laminate 112. Similarly, the second recess 142a2 is preferably configured to be at least 0.01 μm and within 10.0 μm of the outermost surface of the third surface 112c of the laminate 112. That is, the second recess 142a1 and the second recess 142a2 are disposed on the inner side of the laminate 112. As a result, the second recess 140a1 can prevent solder from wetting and creeping from the first surface 112a to the external electrode 130 disposed on the surface opposite to it in the second direction z, or the second recess 140a1 can capture the solder, thus suppressing wetting and creeping to the third surface 112c.

[0206] When viewed in the second direction z, the distance from the bottom surface of the second recess 142a1 to the vertex of the surface coating layer 36 (described later) located further outward than the second recess 142a1 is preferably 1.0 μm or more.

[0207] When the second external electrode 130b is covered by the first surface 112a, the second surface 112b and the fourth surface 112d, when viewed from the first surface 112a side in the stacking direction x, the second external electrode 130b has a second recess 142b1 extending in the second direction z on the fourth surface 112d side.

[0208] Furthermore, when the second external electrode 130b is covered by the first surface 112a, the second surface 112b, and the fourth surface 12d, when viewed from the second surface 112b side in the stacking direction x, the second external electrode 130b has a second recess 142b2 extending in the second direction z on the fourth surface 112d side.

[0209] The other structures of the second external electrode 130b are the same as those of the first external electrode 130a.

[0210] When the third external electrode 130c is covered by the first surface 112a, the second surface 112b and the third surface 112c, when viewed from the first surface 112a side in the stacking direction x, the third external electrode 130c has a second recess 142c extending in the second direction z on the third surface 112c side.

[0211] Furthermore, when the third external electrode 130c is covered by the first surface 112a, the second surface 112b, and the third surface 112c, when viewed from the second surface 112b side in the stacking direction x, the third external electrode 130c has a second recess 142c2 extending in the second direction z on the third surface 12c side.

[0212] The other structures of the third external electrode 130c are the same as those of the first external electrode 130a.

[0213] When the fourth external electrode 130d is covered by the first surface 112a, the second surface 112b and the fourth surface 12d, when viewed from the first surface 112a side in the stacking direction x, the fourth external electrode 130d has a second recess 142d extending in the second direction z on the fourth surface 112d side.

[0214] Furthermore, when the fourth external electrode 130d is covered by the first surface 112a, the second surface 112b, and the fourth surface 112d, when viewed from the second surface 112b side in the stacking direction x, the fourth external electrode 130d has a second recess 142d2 extending in the second direction z on the fourth surface 112d side.

[0215] The other structures of the fourth external electrode 130d are the same as those of the first external electrode 130a.

[0216] Within the laminate 112, the first opposing electrode portion 122a of the first internal electrode 116a and the second opposing electrode portion 122b of the second internal electrode 116b are opposed to each other across the inner dielectric layer 114a, thereby forming an electrostatic capacitor. Therefore, an electrostatic capacitor can be obtained between the first external electrode 130a and the second external electrode 130b connected to the first internal electrode 116a, and between the third external electrode 130c and the fourth external electrode 130d connected to the second internal electrode 116b, exhibiting the characteristics of a capacitor.

[0217] The first external electrode 130a, the second external electrode 130b, the third external electrode 130c, and the fourth external electrode 130d preferably have a substrate layer 132, a thin film layer 134, and a surface coating layer 136, respectively.

[0218] (Basal layer)

[0219] The substrate 132 is disposed on the third surface 112c and the fourth surface 112d. The specific structure of the substrate 132 will be described below.

[0220] The first base layer 132a is disposed on the surface of the third surface 112c of the laminate 112, such that the first lead-out electrode portion 124a of the first internal electrode 116a exposed from the third surface 112c of the laminate 112 is covered.

[0221] The second base layer 132b is disposed on the surface of the fourth surface 112d of the laminate 112, such that it covers the second lead-out electrode portion 124b of the first internal electrode 116a exposed from the fourth surface 112d of the laminate 112.

[0222] The third base layer 132c is disposed on the surface of the third surface 112c of the laminate 112, such that it covers the third lead-out electrode portion 124c of the second internal electrode 116b exposed from the third surface 112c of the laminate 112.

[0223] The fourth base layer 132d is disposed on the surface of the fourth surface 112d of the laminate 112, such that it covers the fourth lead-out electrode portion 124d of the second internal electrode 116b exposed from the fourth surface 112d of the laminate 112.

[0224] Regarding the base layer 132, although it still depends on its connection with the internal electrode 116, it is preferably made of a Cu plating layer.

[0225] Furthermore, the upper end of the first base layer 132a of the first external electrode 130a is preferably connected to the first thin film layer 134a at the ridge formed by the first surface 112a and the third surface 112c of the laminate 112. Additionally, the lower end of the first base layer 132a of the first external electrode 130a is preferably connected to the first thin film layer 134a at the ridge formed by the second surface 112b and the third surface 112c of the laminate 112.

[0226] Regarding the first base layer 132a of the multilayer ceramic capacitor 110, similarly to the first base layer 32a of the multilayer ceramic capacitor 10, the distance in the stacking direction x between the front end of the third surface 112c of the first base layer 132a and the end of the internal electrode 116 closest to the first surface 112a that is exposed on the third surface 112c is preferably 3.0 μm or more and 8.1 μm or less. Furthermore, the first base layer 132a is preferably configured to extend toward the first surface 112a. In other words, the distance in the stacking direction x between the point on the outermost surface of the first surface 112a located 1.0 μm inward from the third surface 112c and the front end of the first base layer 132a is preferably 10.0 μm or less.

[0227] Regarding the thickness of the first base layer 132a, it is preferably 3.0 μm or more and 8.1 μm or less away from the end of the internal electrode 116 closest to the first surface 112a that is exposed on the third surface 112c in the first direction y.

[0228] The upper end of the second base layer 132b of the second external electrode 130b is preferably connected to the second thin film layer 134b at the ridge formed by the first surface 112a and the fourth surface 112d of the laminate 112. Furthermore, the lower end of the second base layer 132b of the second external electrode 130b is preferably connected to the second thin film layer 134b at the ridge formed by the second surface 112b and the fourth surface 112d of the laminate 112.

[0229] The other structures of the second external electrode 130b are the same as those of the first external electrode 130a.

[0230] The upper end of the third base layer 132c of the third external electrode 130c is preferably connected to the third thin film layer 134c at the ridge formed by the first surface 112a and the third surface 112c of the laminate 112. Furthermore, the lower end of the third base layer 132c of the third external electrode 130c is preferably connected to the third thin film layer 134c at the ridge formed by the second surface 112b and the third surface 112c of the laminate 112.

[0231] The other structures of the third external electrode 130c are the same as those of the first external electrode 130a.

[0232] The upper end of the fourth base layer 132d of the fourth external electrode 130d is preferably connected to the fourth thin film layer 134d at the ridge formed by the first surface 112a and the fourth surface 112d of the laminate 112. Furthermore, the lower end of the fourth base layer 132d of the fourth external electrode 130d is preferably connected to the fourth thin film layer 34d at the ridge formed by the second surface 112b and the fourth surface 112d of the laminate 112.

[0233] The other structures of the fourth external electrode 130d are the same as those of the first external electrode 130a.

[0234] (Thin film layer)

[0235] The thin film layer 134 has a first thin film layer 134a, a second thin film layer 134b, a third thin film layer 134c, and a fourth thin film layer 134d.

[0236] The first thin film layer 134a covers a portion of the first surface 112a and a portion of the second surface 112b of the laminate 112 on the third surface 112c side and the fifth surface 112e side. The first thin film layer 134a is preferably configured to be connected to the first substrate layer 132a.

[0237] The second thin film layer 134b covers a portion of the first surface 112a and a portion of the second surface 112b of the laminate 112 on the fourth surface 112d side and the sixth surface 112f side. The second thin film layer 134b is preferably configured to be connected to the second substrate layer 132b.

[0238] The third thin film layer 134c covers a portion of the first surface 112a and a portion of the second surface 112b of the laminate 112 on the third surface 112c side and the sixth surface 112f side. The third thin film layer 134c is preferably configured to be connected to the third substrate layer 132c.

[0239] The fourth thin film layer 134d covers a portion of the first surface 112a and a portion of the second surface 112b of the laminate 112 on the fourth surface 112d side and the fifth surface 112e side. The fourth thin film layer 134d is preferably configured to be connected to the fourth substrate layer 132d.

[0240] (Surface coating)

[0241] The surface plating layer 136 includes a first surface plating layer 136a, a second surface plating layer 136b, a third surface plating layer 136c, and a fourth surface plating layer 136d.

[0242] The first surface coating layer 136a is configured to cover the first thin film layer 134a and the first base layer 132a disposed on the third surface 112c of the laminate 112.

[0243] The second surface coating layer 136b is configured to cover the second thin film layer 134b and the second base layer 132b disposed on the fourth surface 112d of the laminate 112.

[0244] The third surface coating layer 136c is configured to cover the third thin film layer 134c and the third base layer 132c disposed on the third surface 112c of the laminate 112.

[0245] The fourth surface coating layer 136d is configured to cover the fourth thin film layer 134d and the fourth substrate layer 132d disposed on the fourth surface 112d of the laminate 112.

[0246] The surface coating 136 can be, for example, only a Sn coating, or a two-layer structure of Ni-Sn coating or Ni-Cu coating.

[0247] The Sn plating layer is coated with a Ni plating layer. Specifically, the Sn plating layer is formed by plating and growing from the Ni plating layer. The thickness of the Sn plating layer is preferably 1.0 μm or more and 5.0 μm or less. Here, the structure of the first surface plating layer 136a of the first external electrode 130a will be described in detail as an example. Similar to the surface plating layer 36 of the multilayer ceramic capacitor 110, the first surface plating layer 136a constituting the first external electrode 130a includes a Ni plating layer and a Sn plating layer. At this time, the relationship between the thickness t4 of the Sn plating layer disposed in the second recess 142a and the thickness t5 of the Sn plating layer disposed at the center position (1 / 2) of the first surface 112a on the second direction z at a distance l from the first surface 112a side of the first external electrode 130a is preferably |t4-t5|≤t5 / 2. The relationship between the thickness of the Sn plating layer disposed in the second recess 142a and the thickness t6 in the region 10 μm away from the front end of the Sn plating layer disposed on the first surface 112a is preferably |t4-t6|≤t6 / 2.

[0248] The Sn plating layer constituting the second surface plating layer 136b of the second external electrode 130b, the Sn plating layer constituting the third surface plating layer 136c of the third external electrode 130c, and the fourth surface plating layer 136d constituting the fourth external electrode 130d also have the structure constituting the Sn plating layer constituting the first surface plating layer 136a of the first external electrode 130a.

[0249] exist Figure 11A The stacked ceramic capacitor 110 shown achieves the same effect as the stacked ceramic capacitor 10 according to the first embodiment.

[0250] 2. Manufacturing method of multilayer ceramic capacitors

[0251] The manufacturing method of the multilayer ceramic capacitor according to the second embodiment will be described below.

[0252] First, prepare the conductive paste for the dielectric sheet and internal electrodes. The conductive paste for the dielectric sheet and internal electrodes contains an adhesive and a solvent. Known adhesives and solvents can be used.

[0253] Next, conductive paste for the internal electrodes is printed on the dielectric sheet in a given pattern, for example, by inkjet printing, screen printing, or gravure printing. Thus, a dielectric sheet with a pattern of the first internal electrode and a dielectric sheet with a pattern of the second internal electrode are prepared. Then, the sheet with the pattern of the first internal electrode and the sheet with the pattern of the second internal electrode are laminated together to form the inner layer 18.

[0254] Next, a given number of dielectric sheets without printed internal electrode patterns are stacked, thereby forming the first outer layer 120a on the first surface 112a side. Then, the portion prepared above to become the inner layer 118 is stacked, and a given number of dielectric sheets without printed internal electrode patterns are stacked on the portion becoming the inner layer 118, thereby forming the second outer layer 120b on the second surface 112b side. Thus, a laminated sheet is manufactured.

[0255] Next, the laminated sheets are pressed in the stacking direction by means of isostatic pressing to produce a laminated block.

[0256] Next, the laminated block is cut to the given size into smaller laminated pieces. At this point, the corners and edges of the smaller laminated pieces can also be rounded using methods such as tumble grinding.

[0257] Next, the stacked sheets are fired to produce the stack 112. Regarding the firing temperature, although it depends on the materials of the ceramic and the internal electrodes, it is preferably above 900°C and below 1400°C.

[0258] At this time, the first lead-out electrode portion 124a of the first internal electrode 116a and the third lead-out electrode portion 124c of the second internal electrode 116b are exposed from the third surface 112c of the laminate 112. In addition, the second lead-out electrode portion 124b of the first internal electrode 116a and the fourth lead-out electrode portion 124d of the second internal electrode 116b are exposed from the fourth surface 112d of the laminate 112.

[0259] Next, an external electrode 130 is formed on the laminate 112.

[0260] First, a base layer 132 is formed, exposing the internal electrodes 116 covering the surface of the laminate 112. The base layer 132 is a Cu plating layer, formed by electrolytic plating or electroless plating. Then, the laminate 112 after plating is heat-treated to remove residual moisture remaining in the plating film and at the interface between the laminate 112 and the base layer 132.

[0261] Here, after the base layer 132 is formed, for example, given portions of the first surface 112a and the second surface 112b on the third surface 112c side to the sixth surface 112f side are surface-treated by plasma etching, thereby forming regions for forming the second recess 142.

[0262] Next, the laminate 112, which forms the base layer 132, is arranged on the worktable, and for example, a thin film layer 134 is formed on the first surface 112a and the second surface 112b by sputtering.

[0263] Then, a surface plating layer 136 is formed on the thin film layer 134 and on the surface of the laminate 112. More specifically, a Ni plating layer and a Sn plating layer are formed on the thin film layer 134 as the surface plating layer 136. During the plating process, either electrolytic plating or electroless plating can be used. However, regarding electroless plating, in order to increase the plating deposition rate, pretreatment using a catalyst or the like is required, which complicates the process. Therefore, electrolytic plating is generally preferred. Furthermore, it is not limited to this; for example, after the surface plating layer is formed, a recess may be formed after the Ni plating layer, and then the Sn plating layer may be formed.

[0264] At this time, the external electrode 130 disposed on the side of the internal electrode 116 that is not led out is formed into a "ko" shape by means of the surface plating layer 136, so that it covers the two short sides of the side of the internal electrode 116 that is not led out and the portion from the ends of the two short sides to the middle part of the two long sides.

[0265] As described above, manufacturing such Figure 13 The stacked ceramic capacitor 110 shown is illustrated.

[0266] C. Third Implementation

[0267] 1. Multilayer ceramic capacitor

[0268] An example of a multilayer ceramic capacitor 210 according to the third embodiment of the present invention will be described.

[0269] Figure 19A This is a perspective view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Figure 19B This is a perspective view of an example of a multilayer ceramic capacitor according to the second embodiment of the present invention, viewed from another direction. Figure 20 yes Figure 19A A cross-sectional schematic diagram of the line XX-XX involved. Figure 21 yes Figure 19A A schematic cross-sectional view of line XXI-XXI involved. Figure 22 yes Figure 19A A schematic cross-sectional view of line XXII-XXII involved. Figure 23 yes Figure 19A A schematic cross-sectional view of line XXIII-XXIII is involved. Additionally, regarding the sections shown in Figures 1 to 12... Figure 7 For identical or equivalent structures, use the same reference numerals and omit detailed descriptions.

[0270] The multilayer ceramic capacitor 210 has a multilayer body 12 and multiple external electrodes 230.

[0271] (Layered structure)

[0272] In the multilayer ceramic capacitor 210 according to the third embodiment, the multilayer body 12 has the same structure as the multilayer body 12 of the first embodiment of the present invention shown in FIG1.

[0273] (Internal electrodes)

[0274] The internal electrode 16 has a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b. The first internal electrodes 16a and the second internal electrodes 16b are stacked alternately with a dielectric layer 14 between them.

[0275] The first internal electrode 16a is disposed on the surface of the inner dielectric layer 14a. The first internal electrode 16a is opposite to the first surface 12a and the second surface 12b, has a first opposing electrode portion 22a opposite to the second internal electrode 16b, and is stacked in the direction connecting the first surface 12a and the second surface 12b.

[0276] (Internal electrodes)

[0277] The first internal electrode 16a is led out to the third surface 12c and the fifth surface 12e of the laminate 12 through the first lead-out electrode portion 24a, and is led out to the fourth surface 12d and the sixth surface 12f of the laminate 12 through the second lead-out electrode portion 24b.

[0278] The second internal electrode 16b is disposed on the surface of an inner dielectric layer 14a that is different from the inner dielectric layer 14a on which the first internal electrode 16a is disposed. The second internal electrode 16b is opposite to the first surface 12a and the second surface 12b, has a second opposing electrode portion 22b opposite to the first internal electrode 16a, and is stacked in the direction connecting the first surface 12a and the second surface 12b.

[0279] The second internal electrode 16b is led out to the third surface 12c and the sixth surface 12f of the laminate 12 through the third lead-out electrode portion 24c, and is led out to the fourth surface 12d and the fifth surface 12e of the laminate 12 through the fourth lead-out electrode portion 24d.

[0280] Furthermore, when viewing the stacked ceramic capacitor 210 from the stacking direction x, the straight line connecting the first lead-out electrode portion 24a and the second lead-out electrode portion 24b of the first internal electrode 16a preferably intersects the straight line connecting the third lead-out electrode portion 24c and the fourth lead-out electrode portion 24d of the second internal electrode 16b.

[0281] Furthermore, preferably, in the surfaces 12c, 12d, 12e, and 12f of the laminate 12, the first lead-out electrode portion 24a of the first internal electrode 16a and the fourth lead-out electrode portion 24d of the second internal electrode 16b are led out to opposite positions, and the second lead-out electrode portion 24b of the first internal electrode 16a and the third lead-out electrode portion 24c of the second internal electrode 16b are led out to opposite positions.

[0282] Furthermore, as shown in FIG27, the laminate 12 includes: a side portion (W-space) 26a of the laminate 12, located between one end of the second opposing electrode portion 22b of the second internal electrode 16b in the first direction y and the third surface 12c; and a side portion (W-space) 26b of the laminate 12, located between the other end of the first opposing electrode portion 22a of the first internal electrode 16a in the first direction y and the fourth surface 12d.

[0283] Furthermore, as shown in FIG26, the laminate 12 includes: an end portion (L-space) 27a of the laminate 12, located between one end of the second opposing electrode portion 22b of the second internal electrode 16b in the second direction z and the fifth surface 12e; and a side portion (L-space) 127b of the laminate 12, located between the other end of the first opposing electrode portion 22a of the first internal electrode 16a in the second direction z and the sixth surface 12f.

[0284] (External electrode)

[0285] like Figures 19A to 23 As shown, an external electrode 230 is disposed in the laminate 12.

[0286] The external electrode 230 has a plurality of external electrodes 230 connected to the first internal electrode 16a and the second internal electrode 16b. The external electrode 230 has a first external electrode 230a, a second external electrode 230b, a third external electrode 230c, and a fourth external electrode 230d.

[0287] The first external electrode 230a is configured to cover the first lead-out electrode portion 24a of the first internal electrode 16a on the third surface 12c and the fifth surface 12e. Furthermore, the first external electrode 230a is configured to cover a portion of the first surface 12a. The first external electrode 230a is electrically connected to the first lead-out electrode portion 24a of the first internal electrode 16a.

[0288] The second external electrode 230b is configured to cover the second lead-out electrode portion 24b of the first internal electrode 16a on the fourth surface 12d and the sixth surface 12f. Furthermore, the second external electrode 230b is configured to cover a portion of the first surface 12a. The second external electrode 230b is electrically connected to the second lead-out electrode portion 24b of the first internal electrode 16a.

[0289] The third external electrode 230c is configured to cover the third lead-out electrode portion 24c of the second internal electrode 16b on the third surface 12c and the sixth surface 12f. Furthermore, the third external electrode 230c is configured to cover a portion of the first surface 12a. The third external electrode 230c is electrically connected to the third lead-out electrode portion 24c of the second internal electrode 16b.

[0290] The fourth external electrode 230d is configured to cover the fourth lead-out electrode portion 24d of the second internal electrode 16b on the fourth surface 12d and the fifth surface 12e. Furthermore, the fourth external electrode 230d is configured to cover a portion of the first surface 12a. The fourth external electrode 230d is electrically connected to the fourth lead-out electrode portion 24d of the second internal electrode 16b.

[0291] When viewed in the stacking direction x, the external electrode 230 has a first recess 240 extending in the first direction y inside the laminate 12. Alternatively, the external electrode 230 may also have a second recess 242 extending in the second direction z inside the laminate 12.

[0292] More specifically, when the first external electrode 230a is covered by the first surface 12a, the third surface 12c, and the fifth surface 12e, when viewed from the first surface 12a side in the stacking direction x, the first external electrode 230a has a second recess 242a1 extending in the second direction z on the third surface 12c side and a first recess 240a1 extending in the first direction y on the fifth surface 12e side.

[0293] When viewed from the first surface 12a in the stacking direction x, the dimension of the first recess 240a1 in the first direction y is more than 10% and less than 96.0% of the dimension of the first external electrode 230a forming the first recess 240a1 in the first direction y. More preferably, it is less than 100%. This suppresses excessive wetting and creeping of solder onto the fifth surface 12e. Furthermore, when the first recesses 240a1 are discontinuously arranged, the dimension of the first recess 240a1 in the first direction y is defined by the total length of the first recesses 240a1.

[0294] The first recess 240a1 is configured such that it is at least 0.01 μm away from the outermost surface of the fifth surface 12e of the laminate 12 and within 10.0 μm. That is, the first recess 240a1 is disposed on the inner side of the laminate 12. As a result, the first recess 240a1 can prevent solder from wetting and creeping from the first surface 12a to the external electrode 230 disposed on the surface opposite to it in the second direction z, or it can capture the solder and thus suppress wetting and creeping to the fifth surface 12e.

[0295] The first recess 240a1 and the second recess 242a1 can also be connected. By connecting the first recess 240a1 and the second recess 242a1, it is also possible to suppress solder wetting and creeping to the intersection of the two adjacent surfaces. When viewed in the first direction y, the distance from the bottom surface of the first recess 240a1 to the vertex of the surface plating layer 36, which is located further outward than the first recess 240a1 and will be described later, is preferably 1.0 μm or more.

[0296] When the second external electrode 230b is covered by the first surface 12a, the fourth surface 12d, and the sixth surface 12f, when viewed from the first surface 12a side in the stacking direction x, the second external electrode 230b has a second recess 242b1 extending in the second direction z on the fourth surface 12d side and a first recess 240b1 extending in the first direction y on the sixth surface 12f side.

[0297] The other structures of the second external electrode 230b are the same as those of the first external electrode 230a.

[0298] When the third external electrode 230c is covered by the first surface 12a, the third surface 12c and the sixth surface 12f, when viewed from the first surface 12a side in the stacking direction x, the third external electrode 230c has a second recess 242c extending in the second direction z on the third surface 12c side and a first recess 240b extending in the first direction y on the sixth surface 12f side.

[0299] The other structures of the third external electrode 230c are the same as those of the first external electrode 230a.

[0300] When the fourth external electrode 230d is covered by the first surface 12a, the fourth surface 12d and the fifth surface 12e, when viewed from the first surface 12a side in the stacking direction x, the fourth external electrode 230d has a second recess 242d extending in the second direction z on the fourth surface 12d side and a first recess 240d extending in the first direction y on the fifth surface 12e side.

[0301] The other structures of the fourth external electrode 230d are the same as those of the first external electrode 230a.

[0302] The first external electrode 230a, the second external electrode 230b, the third external electrode 230c, and the fourth external electrode 230d preferably have a substrate layer 32, a thin film layer 34, and a surface coating layer 36, respectively.

[0303] (Basal layer)

[0304] The substrate layer 32 is disposed on the third surface 12c to the sixth surface 12f. The specific structure of the substrate layer 32 will be described below.

[0305] The first base layer 32a is disposed on the surfaces of the third surface 12c and the fifth surface 12e of the laminate 12, such that the first lead-out electrode portion 24a of the first internal electrode 16a exposed from the third surface 12c and the fifth surface 12e of the laminate 12 is covered.

[0306] The second base layer 32b is disposed on the surfaces of the fourth surface 12d and the sixth surface 12f of the laminate 12, such that it covers the second lead-out electrode portion 24b of the first internal electrode 16a exposed from the fourth surface 12d and the sixth surface 12f of the laminate 12.

[0307] The third base layer 32c is disposed on the surfaces of the third surface 12c and the sixth surface 12f of the laminate 12, such that it covers the third lead-out electrode portion 24c of the second internal electrode 16b exposed from the third surface 12c and the sixth surface 12f of the laminate 12.

[0308] The fourth base layer 32d is disposed on the surfaces of the fourth surface 12d and the fifth surface 12e of the laminate 12, such that it covers the fourth lead-out electrode portion 24d of the second internal electrode 16b exposed from the fourth surface 12d and the fifth surface 12e of the laminate 12.

[0309] Regarding the base layer 32, although it still depends on its connection with the internal electrode 16, it is preferably made of a Cu plating layer.

[0310] In addition, the upper end of the first base layer 32a of the first external electrode 230a is preferably connected to the first thin film layer 34a on the ridge formed by the first surface 12a, the third surface 12c and the fifth surface 12e of the laminate 12.

[0311] Regarding the first base layer 32a of the multilayer ceramic capacitor 210, similarly to the first base layer 32a of the multilayer ceramic capacitor 10, the distance in the stacking direction x between the front end of the third surface 112c of the first base layer 32a and the end of the internal electrode 16 closest to the first surface 12a that is exposed on the third surface 12c is preferably 3.0 μm or more and 8.1 μm or less. Furthermore, the first base layer 32a is preferably configured to extend toward the first surface 12a. In other words, the distance in the stacking direction x between the point on the outermost surface of the first surface 12a located 1.0 μm inward from the third surface 12c and the front end of the first base layer 32a is preferably 10.0 μm or less.

[0312] Regarding the thickness of the first base layer 32a, it is preferably 3.0 μm or more and 8.1 μm or less away from the end of the internal electrode 16 closest to the first surface 12a that is exposed on the third surface 12c in the first direction y.

[0313] The upper end of the second base layer 32b of the second external electrode 230b is preferably connected to the second thin film layer 34b on the ridge formed by the first surface 12a, the fourth surface 12d and the sixth surface 12f of the laminate 12.

[0314] The other structures of the second external electrode 230b are the same as those of the first external electrode 230a.

[0315] The upper end of the third base layer 32c of the third external electrode 230c is preferably connected to the third thin film layer 34c on the ridge formed by the first surface 12a, the third surface 12c and the sixth surface 12f of the laminate 12.

[0316] The other structures of the third external electrode 230c are the same as those of the first external electrode 230a.

[0317] The upper end of the fourth base layer 32d of the fourth external electrode 230d is preferably connected to the fourth thin film layer 34d on the ridge formed by the first surface 12a, the fourth surface 12d and the fifth surface 12e of the laminate 12.

[0318] The other structures of the fourth external electrode 230d are the same as those of the first external electrode 230a.

[0319] (Thin film layer)

[0320] The thin film layer 34 has a first thin film layer 34a, a second thin film layer 34b, a third thin film layer 34c, and a fourth thin film layer 34d.

[0321] The first thin film layer 34a covers a portion of the first surface 12a of the laminate 12 on the third surface 12c side and the fifth surface 12e side. The first thin film layer 34a is preferably configured to be connected to the first substrate layer 32a.

[0322] The second thin film layer 34b covers a portion of the first surface 12a of the laminate 12 on the fourth surface 12d side and the sixth surface 12f side. The second thin film layer 34b is preferably configured to be connected to the second substrate layer 32b.

[0323] The third thin film layer 34c covers a portion of the first surface 12a of the laminate 12 on the third surface 12c side and the sixth surface 12f side. The third thin film layer 34c is preferably configured to be connected to the third substrate layer 32c.

[0324] The fourth thin film layer 34d covers a portion of the first surface 12a of the laminate 12, on the fourth surface 12d side and the fifth surface 12e side. The fourth thin film layer 34d is preferably configured to be connected to the fourth substrate layer 32d.

[0325] (Surface coating)

[0326] The surface plating layer 36 includes a first surface plating layer 36a, a second surface plating layer 36b, a third surface plating layer 36c, and a fourth surface plating layer 36d.

[0327] The first surface coating layer 36a is configured to cover the first thin film layer 34a and the first base layer 32a disposed on the third surface 12c and the fifth surface 12e of the laminate 12.

[0328] The second surface coating layer 36b is configured to cover the second thin film layer 34b and the second base layer 32b disposed on the fourth surface 12d and the sixth surface 12f of the laminate 12.

[0329] The third surface coating layer 36c is configured to cover the third thin film layer 34c and the third base layer 32c disposed on the third surface 12c and the sixth surface 12f of the laminate 12.

[0330] The fourth surface coating layer 36d is configured to cover the fourth thin film layer 34d and the fourth base layer 32d disposed on the fourth surface 12d and the fifth surface 12e of the laminate 12.

[0331] The surface coating 36 can be, for example, only a Sn coating, or a two-layer structure of Ni-Sn coating or Ni-Cu coating.

[0332] The Sn plating layer is coated with a Ni plating layer. Specifically, the Sn plating layer is formed by plating and growing from the Ni plating layer. The thickness of the Sn plating layer is preferably 1.0 μm or more and 5.0 μm or less. Here, the structure of the first surface plating layer 36a of the first external electrode 230a will be described in detail as an example. Similarly to the surface plating layer 36 of the multilayer ceramic capacitor 210, the first surface plating layer 36a constituting the first external electrode 230a includes a Ni plating layer and a Sn plating layer. At this time, the relationship between the thickness t4 of the Sn plating layer disposed in the first recess 240a (or the second recess 242a) and the thickness t5 of the Sn plating layer disposed at the center position (1 / 2) of the first surface 112a at a distance l from the first surface 12a side of the first external electrode 230a is preferably |t4-t5|≤t5 / 2. The relationship between the thickness of the Sn plating layer disposed in the first recess 240a (or the second recess 242a) and the thickness t6 in the region 10 μm away from the front end of the Sn plating layer disposed on the first surface 12a is preferably |t4-t6|≤t6 / 2.

[0333] The Sn plating layer constituting the second surface plating layer 36b of the second external electrode 230b, the Sn plating layer constituting the third surface plating layer 36c of the third external electrode 230c, and the fourth surface plating layer 36d constituting the fourth external electrode 230d also have the structure constituting the Sn plating layer constituting the first surface plating layer 36a of the first external electrode 230a.

[0334] exist Figure 19A The stacked ceramic capacitor 210 according to the third embodiment shown achieves the same effect as the stacked ceramic capacitor 10 described above, and also achieves the following effects.

[0335] That is, according to Figure 19A The third embodiment shown, which involves a multilayer ceramic capacitor 210, is similar to the multilayer ceramic capacitor 10 in FIG1 in that the external electrode 230 is configured to cover only the first surface 12a of the multilayer body 12 and not the second surface 12b, and can provide a low-height multilayer ceramic capacitor without compromising the installability during installation.

[0336] Alternatively, the stacked ceramic capacitor 210 according to the third embodiment can also be configured such that the external electrode 230 is configured to cover a portion of the second surface 12b and not cover the first surface 12a.

[0337] 2. Manufacturing method of multilayer ceramic capacitors

[0338] The manufacturing method of the multilayer ceramic capacitor according to the third embodiment will be described below.

[0339] First, prepare a dielectric sheet, a conductive paste for the internal electrodes, and a conductive paste for the surrounding electrodes. These materials contain an adhesive and a solvent. Known adhesives and solvents can be used.

[0340] Next, conductive paste for the internal electrodes and conductive paste for the surrounding electrodes are printed on the dielectric sheet in a given pattern, for example, by inkjet printing, screen printing, or gravure printing. Thus, a dielectric sheet with patterns of the first internal electrode and the first surrounding electrode, and a dielectric sheet with patterns of the second internal electrode and the second surrounding electrode are prepared. Then, the sheets with the patterns of the first internal electrode and the first surrounding electrode printed on them, and the sheets with the patterns of the second internal electrode and the second surrounding electrode printed on them, are laminated to form the inner layer 18.

[0341] In addition, regarding the printing of patterns formed by each conductive paste, first, the pattern formed by the conductive paste for the internal electrodes is printed, and then the pattern formed by the conductive paste for the surrounding electrodes is printed.

[0342] Next, a given number of dielectric sheets without printed internal electrode patterns and surrounding electrode patterns are stacked to form the first outer layer 20a on the first surface 12a side. Then, the portion prepared above to become the inner layer 18 is stacked, and a given number of dielectric sheets without printed internal electrode patterns and surrounding electrode patterns are stacked on the inner layer 18 to form the second outer layer 20b on the second surface 12b side. Thus, a laminated sheet is manufactured.

[0343] Next, the laminated sheets are pressed in the stacking direction by means of isostatic pressing to produce a laminated block.

[0344] Next, the laminated block is cut to the given size into smaller laminated pieces. At this point, the corners and edges of the laminated pieces can also be rounded using methods such as tumble grinding.

[0345] Next, the stacked sheets are fired to produce the stack 12. Regarding the firing temperature, although it depends on the materials of the ceramic and the internal electrodes, it is preferably above 900°C and below 1400°C.

[0346] At this time, the first lead-out electrode portion 24a of the first internal electrode 16a and the third lead-out electrode portion 24c of the second internal electrode 16b are exposed from the third surface 12c of the laminate 12. In addition, the second lead-out electrode portion 24b of the first internal electrode 16a and the fourth lead-out electrode portion 24d of the second internal electrode 16b are exposed from the fourth surface 12d of the laminate 12.

[0347] Next, an external electrode 230 is formed on the laminate 12.

[0348] First, a base layer 32 is formed, exposing the internal electrodes 16 covering the surface of the laminate 12. The base layer 32 is a Cu plating layer, formed by electrolytic plating or electroless plating. Then, the laminate 12 after plating is heat-treated to remove residual moisture remaining in the plating film and at the interface between the laminate 12 and the base layer 32.

[0349] Here, after the base layer 32 is formed, for example, a given portion of the first surface 12a from the third surface 12c side to the sixth surface 12f side is surface-treated by plasma etching, thereby forming regions for forming the first recess 240 and the second recess 242.

[0350] Next, the laminate 12, which forms the base layer 32, is arranged on the worktable, and for example, a thin film layer 34 is formed on the first surface 12a and the second surface 12b by sputtering.

[0351] Then, a surface plating layer 36 is formed on the thin film layer 34 and on the surface of the laminate 12. More specifically, a Ni plating layer and a Sn plating layer are formed on the thin film layer 34 as the surface plating layer 36. During the plating process, either electrolytic plating or electroless plating can be used. However, regarding electroless plating, in order to increase the plating deposition rate, pretreatment using a catalyst or the like is required, which complicates the process. Therefore, electrolytic plating is generally preferred. Furthermore, it is not limited to this; for example, after the surface plating layer is formed, a recess may be formed after the Ni plating layer, and then the Sn plating layer may be formed.

[0352] Like the above, it is capable of manufacturing Figure 22 The third embodiment shown relates to a multilayer ceramic capacitor 210.

[0353] D. Experimental Example

[0354] Next, in order to confirm the effectiveness of the multilayer ceramic capacitor of the present invention, a solder mounting evaluation was performed on the test specimen according to the manufacturing method described above.

[0355] (1) Specifications of the multilayer ceramic capacitor made from the sample used as an experimental example

[0356] Using the manufacturing method described in the above embodiments, multilayer ceramic capacitors were manufactured as specimens numbered 1 to 15. Additionally, multilayer ceramic capacitors without recesses were also manufactured as existing structure specimens.

[0357] • Construction of multilayer ceramic capacitors: Figure 15 The multilayer ceramic capacitor shown

[0358] • Dimensions (L) of the multilayer ceramic capacitor: 480μm

[0359] • Dimensions of the multilayer ceramic capacitor (W): 480μm

[0360] • Dimensions (T) of multilayer ceramic capacitor: 60μm

[0361] Ceramic material: BaTiO3

[0362] • Material of internal electrodes: Ni

[0363] Construction of external electrodes

[0364] • Substrate: Cu coating

[0365] • Thin film layer: a sputtered film containing at least one of Ni, Cr, and Cu.

[0366] • Surface plating: A two-layer structure consisting of a Ni plating layer and a Sn plating layer.

[0367] (2) Method for solder installation test

[0368] Solder mounting method: An appropriate amount of solder paste was applied to the designated position on the substrate, and the multilayer ceramic capacitors for each sample were mounted on it. Then, the substrate with the multilayer ceramic capacitors mounted was heated to complete the soldering. For existing structure samples without recesses, solder mounting was also performed on the substrate using the same method.

[0369] Evaluation Method: After soldering, the height to the outermost surface of the multilayer ceramic capacitor was measured using a laser microscope or similar instrument, with the substrate surface as a reference. Furthermore, the same measurement was performed on existing structure samples without recesses, and the difference in solder wetting creep was evaluated. Additionally, x in Table 2 represents the ratio of the length of each recess to its dimension in the first direction y or the second direction z of the external electrode.

[0370] (3) Results

[0371] The evaluation results are shown in Table 1 and Table 2.

[0372] Table 1 shows the variation of the difference between the solder wetting creep of each specimen and the solder wetting creep of the existing structural specimen for the change of distance t1.

[0373] Table 2 shows the variation of the difference between the solder wetting creep of each sample and the solder wetting creep of the existing structure sample, for the variation of the ratio of the length of each recess to the dimension in the first direction or the dimension in the second direction of the external electrode.

[0374] [Table 1]

[0375]

[0376] [Table 2]

[0377]

[0378] According to Table 1, in all samples from sample 1 to sample 8, within the range of 1.0 ≤ t1 ≤ 9.0, a reduction in solder wetting creep was confirmed. In particular, in sample 3 to sample 7, within the range of 3.0 ≤ t1 ≤ 8.1, a significant inhibition effect on solder wetting creep was observed.

[0379] Furthermore, according to Table 2, the solder wetting creep was reduced for all specimen numbers. In particular, for specimen numbers 12 to 15, the solder wetting creep was reduced compared to the other specimen numbers within the range of 10.0 ≤ x ≤ 96.0. It was also confirmed that the solder wetting creep was reduced within the range of x ≤ 100.

[0380] Furthermore, as described above, the embodiments of the present invention are disclosed through the above description, but the present invention is not limited thereto.

[0381] That is, various changes can be made to the above-described embodiments regarding mechanism, shape, material, quantity, position or configuration without departing from the technical concept and purpose of the present invention, and these are included in the present invention.

[0382] Explanation of reference numerals in the attached figures

[0383] 10, 110, 210: Multilayer ceramic capacitors;

[0384] 12: Layered body;

[0385] 12a, 112a: Page 1;

[0386] 12b, 112b: Page 2;

[0387] 12c, 112c: Page 3;

[0388] 12d, 112d: Page 4;

[0389] 12e, 112e: Page 5;

[0390] 12f, 112f: Page 6;

[0391] 14, 114: Dielectric layer;

[0392] 14a, 114a: Inner dielectric layer;

[0393] 14b, 114b: outer dielectric layer;

[0394] 16, 116: Internal electrodes;

[0395] 16a, 116a: First internal electrode;

[0396] 16b, 116b: Second internal electrode;

[0397] 18, 118: Inner layer;

[0398] 20a, 120a: First outer layer;

[0399] 20b, 120b: Second outer layer;

[0400] 22a, 122a: First opposing electrode section;

[0401] 22b, 122b: Second opposing electrode section;

[0402] 24a, 124a: First lead-out electrode section;

[0403] 24b, 124b: Second lead-out electrode section;

[0404] 24c, 124c: Third lead-out electrode section;

[0405] 24d, 124d: 4th lead-out electrode section;

[0406] 26a, 26b, 126a, 126b: Sides of the laminate (W-spaced);

[0407] 27a, 27b, 127a, 127b: Ends of the laminate (L-spaces);

[0408] 30, 130, 230: External electrodes;

[0409] 30a, 130a, 230a: First external electrode;

[0410] 30b, 130b, 230b: Second external electrode;

[0411] 30C, 130C, 230C: Third external electrode;

[0412] 30d, 130d, 230d: Fourth external electrode;

[0413] 32, 132: Basal layer;

[0414] 32a: First basal layer;

[0415] 32b: Second basal layer;

[0416] 32c: Third basal layer;

[0417] 32d: Fourth basal layer;

[0418] 34, 134: Thin film layer;

[0419] 34a, 134a: First thin film layer;

[0420] 34b, 134b: Second thin film layer;

[0421] 34c, 134c: the third thin film layer;

[0422] 34d, 134d: The fourth thin film layer;

[0423] 36, 136: Surface coating;

[0424] 36a, 136a: First surface coating;

[0425] 36b, 136b: Second surface coating;

[0426] 36c, 136c: Third surface coating;

[0427] 36d, 136d: Fourth surface coating layer;

[0428] 40, 140, 240: 1st concave part;

[0429] 42, 142, 242: 2nd concave part;

[0430] x: Stacking direction;

[0431] y: 1st direction;

[0432] z: Second direction;

[0433] L: The dimension of the multilayer ceramic capacitor in the first direction;

[0434] W: The dimension of the multilayer ceramic capacitor in the second direction;

[0435] T: Dimensions in the stacking direction of the multilayer ceramic capacitor.

Claims

1. A multilayer ceramic capacitor, comprising: The laminate has a first and a second surface opposite to each other in the lamination direction, a third and a fourth surface opposite to each other in the first direction orthogonal to the lamination direction, and a fifth and a sixth surface opposite to each other in the second direction orthogonal to the lamination direction and the first direction; The first external electrode is disposed on the first surface and the third surface; The second external electrode is disposed on the first surface and the fourth surface; A third external electrode is disposed on the first surface and the third surface; A fourth external electrode is disposed on both the first and fourth surfaces. In the stacked ceramic capacitor The laminate includes a first internal electrode and a second internal electrode. The first external electrode includes: The first base layer is connected to the first internal electrode; A first thin film layer is disposed on the first surface; and First surface coating layer, The first external electrode has a first recess located inside the laminate. The dimension of the first recess in the second direction is longer than the dimension in the first direction.

2. The multilayer ceramic capacitor according to claim 1, wherein, The dimension of the first recess in the first direction is more than 10% and less than 100% of the dimension of the first external electrode in the first direction.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein, The first recess is discontinuously arranged in the first direction.

4. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein, The first recess is continuously arranged in the first direction.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein, The distance in the stacking direction from the innermost end of the first substrate layer to the outermost surface of the first surface coating layer located further outward than the innermost end of the first substrate layer is 3.0 μm or more and 8.1 μm or less.

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