Metastable error detection and BER improvement techniques in pipelined ADC
By introducing an auxiliary path and a delay domain comparator to detect metastable states in a pipelined ADC, the high BER problem of the pipelined ADC under metastable conditions is solved, and a significant reduction in BER and an improvement in signal-to-noise ratio are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TEXAS INSTRUMENTS INC
- Filing Date
- 2024-11-27
- Publication Date
- 2026-05-15
AI Technical Summary
Pipeline analog-to-digital converters (ADCs) have high error rates (BER) under metastable conditions, which affects the signal-to-noise ratio (SNR), especially in applications such as wireless communication, radar, and test and measurement.
An auxiliary path is introduced, which detects the metastability of the flash ADC comparator through a delay domain comparator. When metastability is detected, the residual signal is transferred to the auxiliary path, providing additional time for the flash ADC comparator to stabilize and reducing BER.
The BER was significantly reduced from 3e-4 to 2.8e-15, which improved the signal-to-noise ratio, reduced the probability and magnitude of errors, and enhanced the performance of the ADC.
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Figure CN122055907A_ABST
Abstract
Description
Background Technology
[0001] A pipelined analog-to-digital converter (ADC) converts an analog input signal into a digital output signal. A pipelined ADC has multiple cascaded stages, each resolving a few bits. Each stage of a pipelined ADC may contain a sampler, a sub-ADC (e.g., a flash ADC), a digital-to-analog converter (DAC), a subtractor, and a gain amplifier. The analog input signal is sampled, and the flash ADC in the first stage quantizes the sample into a specific number of bits. Those bits are fed to a DAC of similar size, and the analog output of the DAC is subtracted from the input by the subtractor. This residual is then amplified using a gain amplifier and fed to the next stage. The next stage performs the same operation for a specific number of bits, and so on, until a complete digital sample is produced. The last ADC resolves the final bit. The resolved bit can be time-aligned with a shift register before proceeding to the next stage (e.g., for error correction). This allows different samples to be processed in parallel at each stage. Summary of the Invention
[0002] In at least one example of this specification, a system includes a pipelined analog-to-digital converter (ADC) having a main path and an auxiliary path. The main path includes a first stage having a sampling switch, a flash ADC having an input coupled to the sampling switch, a digital-to-analog converter (DAC) having an input coupled to the output of the flash ADC, and a first amplifier having an output coupled to the DAC and an input coupled to the sampling switch, wherein the first stage is configured to generate samples of the input signal and generate a first residual value. The main path includes a second stage coupled to the inputs of the first stage and the second amplifier, wherein the second stage is configured to generate samples of the first residual value and generate a second residual value. The main path further includes a back-end ADC having an input coupled to the output of the second amplifier, wherein the back-end ADC is configured to generate samples of the second residual value and quantize the second residual value. The auxiliary path includes a plurality of metastable comparators coupled to the flash ADC, wherein each metastable comparator is configured to detect metastability of the comparators in the flash ADC.
[0003] In at least one example of this specification, a pipelined ADC includes a first ADC path. The first ADC path includes a first-stage ADC comprising a flash ADC and a first amplifier coupled to the flash ADC, the first amplifier having an input and an output. The first ADC path further includes a second-stage ADC having an input coupled to the output of the first amplifier and having an output. The first ADC path includes a second amplifier having an input and an output. The first ADC path further includes a third-stage ADC having an input coupled to the output of the second amplifier. The pipelined ADC includes a second ADC path coupled to the input of the first amplifier and having an output. The pipelined ADC includes a metastable comparator having an input coupled to the flash ADC and having an output. The pipelined ADC also includes logic circuitry having an input coupled to the output of the metastable comparator and having an output. The pipelined ADC includes path selection circuitry having a first input coupled to the output of the second-stage ADC, a second input coupled to the output of the second ADC path, a selection input coupled to the output of the logic circuitry, and an output coupled to the input of the second amplifier.
[0004] In at least one example of this specification, a system includes a pipelined ADC having a main path and an auxiliary path. The main path includes a first stage having an input, an output, a sampling switch, a flash ADC coupled to the sampling switch, a digital-to-analog converter (DAC) coupled to the flash ADC, and a first amplifier coupled to the DAC and the sampling switch. The main path also includes a second stage having an input coupled to the output of the first stage and the input of the second amplifier. The main path includes a first back-end ADC having an input coupled to the output of the second amplifier. The auxiliary path includes a plurality of metastable comparators coupled to the flash ADC. The auxiliary path also includes a selection circuit system coupled to the output of the DAC and the plurality of metastable comparators. The auxiliary path includes a buffer having an input and an output, the input being coupled to the output of the selection circuit system. The auxiliary path also includes a second back-end ADC coupled to the output of the buffer. Attached Figure Description
[0005] Figure 1 This is a block diagram of an example pipelined ADC with metastable comparators.
[0006] Figure 2 This is an example timing diagram for the first stage of an ADC.
[0007] Figure 3 This is a block diagram of an example device for metastable state detection.
[0008] Figure 4 This is a schematic diagram of an example metastable comparator.
[0009] Figure 5 This is a block diagram of another example of a pipelined ADC.
[0010] Figure 6 This is a block diagram of another example of a pipelined ADC.
[0011] Figure 7 This is a flowchart of an example method for metastable state detection.
[0012] The same reference numerals or other reference indicators are used in the accompanying drawings to indicate (functionally and / or structurally) the same or similar features. Detailed Implementation
[0013] Pipeline ADCs can suffer from metastability issues caused by sub-ADCs in each stage (e.g., a flash ADC). Metastability occurs when the comparators in a flash ADC do not have enough time to regenerate a small input voltage level into a sufficient digital voltage level. Metastability error (bit error rate (BER)) has two parts: the probability of a metastable event occurring, and the magnitude of the error when metastability occurs. BER is an important metric for many applications, including wireless communication, radar, and test and measurement. Metastability error reduces the signal-to-noise ratio (SNR) of an ADC.
[0014] In the example presented in this paper, a delay domain comparator detects metastability in the flash ADC comparator. Furthermore, the residuals from the first stage of the pipelined ADC are provided to both the main ADC path (e.g., the first ADC path) and an auxiliary path. If no metastability is detected, the residuals are propagated to the main path. If the delay domain comparator detects metastability, the residuals are provided to the auxiliary path, allowing more time for the flash ADC comparator to stabilize. This extra time for stabilization reduces the BER (BER). Several architectures for implementing the auxiliary path are described in this paper.
[0015] Figure 1This is a block diagram of an example pipelined ADC 100. The pipelined ADC 100 includes a first stage 102 (e.g., a first-stage ADC), a second stage 104 (e.g., a second-stage ADC), and a back-end ADC 106 (e.g., a third-stage ADC). In one example, the back-end ADC 106 is the final-stage ADC. In other examples, depending on the bit resolution of the pipelined ADC 100, the pipelined ADC 100 may have more than three stages. The pipelined ADC 100 also includes a timing alignment and digital error correction circuitry system 108. The timing alignment and digital error correction circuitry system 108 includes an output terminal 109. The first stage 102 includes a switch 110, a flash ADC 112, a DAC 114, a capacitor 116, and a gain amplifier 118. The second stage 104 also includes components similar to those in the first stage 102, but those components are... Figure 1 Not shown in the diagram. The back-end ADC 106 also contains components similar to those in the first stage 102, but those components are... Figure 1 The first stage 102, the second stage 104, and the back-end ADC 106 are contained in the main path 120. The pipelined ADC 100 also includes an auxiliary path 122. The auxiliary path 122 contains a metastable comparator 124. An example of the circuitry and logic within the auxiliary path 122 is described below.
[0016] The flash ADC 112 has an input coupled to switch 110 and an output coupled to the input of DAC 114. DAC 114 has an output coupled to a first terminal of capacitor 116. Capacitor 116 has a second terminal coupled to the input of switch 110 and gain amplifier 118. Gain amplifier 118 has an output coupled to the input of the next stage of pipelined ADC 100, which in this example is second stage 104. Second stage 104 has an output coupled to back-end ADC 106. First stage 102, second stage 104, and back-end ADC 106 are each coupled to timing alignment and digital error correction circuitry system 108. Auxiliary path 122 has an input coupled to flash ADC 112 and an output coupled to the second terminal of switch 110 and capacitor 116.
[0017] In the example, stage 102 receives an analog input signal. Switch 110 is a sampling switch for sampling the input signal. In one example, switch 110 is a transistor switch (e.g., a field-effect transistor (FET)). In another example, a sample-and-hold circuit can be used to sample the analog input signal. Flash ADC 112 quantizes the sample into a specific number of bits. In this case, flash ADC 112 produces 4 bits and a residual (e.g., 4+1 bits, where +1 represents the residual or residual value). In one example, these bits are generated using a resistor ladder and comparator in flash ADC 112. The opening and closing, enabling and disabling, and switching on and off of the switches can be controlled by a controller (not shown), which can have any suitable hardware, software, firmware, or combination of implementations.
[0018] In one example, the flash ADC 112 uses 32 comparators to generate the 4+1 bits. These four bits are provided from the flash ADC 112 to a timing alignment and digital error correction circuitry system 108. The remaining bits (e.g., residuals) are provided from the flash ADC 112 to a DAC 114. The DAC 114 generates an analog output that is provided to a capacitor 116. In one example, capacitor 116 is a sampling capacitor, i.e., multiple capacitors connected in parallel. The analog output of the DAC 114 is subtracted from the input signal sample to produce the residual. The residual is provided to a gain amplifier 118, where it is amplified in response to a gain G1 and provided to a second stage 104. In some examples, the gain G1 is between 1.5X and 10X, but in other examples, G1 can use any value.
[0019] The second stage 104 performs a similar function to the first stage 102. In this example, the second stage 104 resolves 3+1 bits (e.g., 3 bits and the residual) to provide to the timing alignment and digital error correction circuitry system 108. The residual from the second stage 104 is provided to the back-end ADC 106. In this example, the back-end ADC 106 resolves 9+1 bits (e.g., 9 bits and the residual). Therefore, in the main path 120, the first stage 102, the second stage 104, and the back-end ADC 106 provide 16 bits of digital data to the timing alignment and digital error correction circuitry system 108. The timing alignment and digital error correction circuitry system 108 can utilize shift registers to align the resolved bits and perform error correction. Therefore, different samples of the input signal can be processed in parallel at each stage. The timing alignment and digital error correction circuitry system 108 includes any hardware, logic, or circuitry system suitable for performing alignment and error correction. The timing alignment circuitry aligns signals from each of the one or more stages (e.g., 102, 104, 106) to produce an aligned digital output signal at output terminal 109. In one example, the timing alignment circuitry uses a shift register. In this example, error correction logic and / or circuitry corrects the state of one or more bits of the digital output signals from one or more stages 102, 104, 106. Any suitable error correction code can be used in various examples, such as Hamming codes, Reed-Solomon codes, Cyclic Redundancy Check codes, Bosch-Chowdhury-Hokungumm (BCH) codes, etc. The timing alignment and digital error correction circuitry 108 produces an aligned and error-corrected digital output signal with an appropriate number of bits at output terminal 109, as described herein.
[0020] In some examples, metastability errors exist. In one example, the first stage 102 performs four functions in one clock cycle before the next clock transition. For example, the analog input signal is sampled at a specific clock rate, where the clock signal is supplied by a suitable clock source (in... Figure 1 (Not shown in the image) is generated. In one example, the pipelined ADC 100 operates at 1.5 gigabits per second (GSPS). The clock rate indicates the rate at which switch 110 samples the analog input signal. For proper operation, each stage in ADC 100 completes its first sample function before switch 110 provides the next sample (e.g., according to the clock rate).
[0021] The four functions include sampling the input signal, quantizing the sample using the flash ADC 112, applying the DAC 114, and amplifying the residual using the gain amplifier 118. These four functions are executed sequentially and require a specific amount of time, as described below. These four functions are completed before the next sample appears. (The following description...) Figure 2An example timing diagram for one stage of the ADC is shown. The flash ADC 112 must complete resolution in a timely manner for subsequent functions (DAC 114 and gain amplifier 118) to proceed on time. If the flash ADC 112 fails to complete resolution in time, metastability errors will occur. Metastability can be prevented by extending the resolution time of the flash ADC 112. Other solutions may involve trade-offs in performance, power consumption, etc.
[0022] In the examples presented herein, one or more metastable comparators 124 determine whether one or more comparators within the flash ADC 112 are metastable. If the flash ADC 112 is metastable, the residual from the first stage 102 is provided to the auxiliary path 122. The residual may also be provided to the second stage 104, and based on the metastable detection result, the output of either the main path or the auxiliary path is passed to the multiplexer. The auxiliary path 122 may contain a back-end ADC (not shown), such as a back-end ADC 106, but does not contain the second stage 104. In one example, the auxiliary path 122 has an output coupled to the input of the timing alignment and digital error correction circuitry system 108 to provide resolved bits. Alternatively, the output of the auxiliary path 122 is coupled to the input of the back-end ADC 106. In both examples, the auxiliary path 122 may resolve 13 bits instead of the 16 bits from the main path 120. The auxiliary path 122 will miss the last 3 bits. Therefore, the error can be ±8 (e.g., 2^3) least significant bits (LSBs). However, if the flash ADC 112 in the first stage 102 is metastable, the error may occur at the 5th bit out of the 16 bits, meaning the error could be 2^11 or 2048 LSBs. Therefore, sending the residual from the first stage 102 to the auxiliary path 122 during metastable conditions can significantly reduce the BER. Further description and architecture for the auxiliary path 122 are described below.
[0023] Figure 2 This is an example timing diagram 200 for the first stage of an ADC. In one example, the first stage is stage 102. Timing diagram 200 includes time ranges 202, 204, 206, 208, 210, 212, and 214. In one example, timing diagram 200 represents one cycle of a clock. In this example, the pipelined ADC 100 operates at 1.5 gigabits per second (GSPS).
[0024] In one example, the pipelined ADC 100 performs four functions in one clock cycle. When operating as expected within this cycle, the pipelined ADC 100 samples the input signal (in time range 202), quantizes the input signal using the flash ADC 112 (in time range 206), applies the DAC 114 (in time range 208), and amplifies the residual using the gain amplifier 118 (in time range 210). As shown in timing diagram 200, for a 1.5 GSPS system, these four functions will be completed within the following timeframes: sampling within approximately 240 picoseconds (ps), flash ADC 112 within 150 ps, DAC 114 within 90 ps, and gain amplifier 118 within 160 ps. Time ranges 206, 208, and 210 will be completed within a total of approximately 400 ps (time range 204) for proper operation. If the fast quantization function is not completed within its allocated time range, metastability may occur.
[0025] If the Flash ADC 112 fails to resolve a bit in time (e.g., within 150 ps), the residual value passed to the next stage of the pipelined ADC 100 may contain errors. Metastability errors occur if the Flash ADC 112 fails to resolve even one bit in time. Metastability can be addressed by providing more resolution time for the Flash ADC 112. Other solutions may involve trade-offs in performance and power consumption.
[0026] Timing diagram 200 shows that if the comparator within the flash ADC 112 fails to make a decision within 160 ps (time range 212), it indicates metastability. The metastable comparator (described below) can detect metastability after time range 212 and then regenerate in time range 214. Regeneration is a process of amplifying the voltage between the comparator inputs and producing the comparator output. In one example, regeneration takes 480 ps.
[0027] Figure 3This is a block diagram 300 of an example device for metastability detection. Block diagram 300 includes a metastability comparator 124 and a master comparator 302. In the example herein, a flash ADC 112 includes several master comparators 302 for producing output bits. In one example, the flash ADC 112 produces 5 bits and therefore has 32 (e.g., 2^5) master comparators 302. Each master comparator 302 is coupled to a metastability comparator 124. In this example, there are 32 metastability comparators 124. Each metastability comparator 124 receives a signal from its associated master comparator 302 indicating whether the master comparator 302 has been resolved. If the master comparator 302 has been resolved, then the metastability comparator 124 can produce a 0 output. If the master comparator 302 has not been resolved, then the metastability comparator 124 can produce a 1 output. If all 32 main comparators 302 resolve in time (e.g., within 160 ps), then the Flash ADC 112 is not metastable and uses the main path 120. If any of the 32 main comparators 302 fails to resolve in time, then the Flash ADC 112 is considered metastable and uses the auxiliary path 122.
[0028] Figure 4 This is a schematic diagram of an example metastable comparator 124. In one example, metastable comparator 124 is a delay-domain comparator. In a delay-domain comparator, the delay time corresponding to the input is compared, rather than the input voltage. The delay-domain comparator produces a 0 or 1 output based on which of the two input signals is received first. Metastable comparator 124 includes transistors 402, 404, 406, 408, 410, 412, 414, and 416. In one example, transistors 402, 404, 406, and 408 are p-type transistors. In one example, transistors 410, 412, 414, and 416 are n-type transistors. In one example, transistors 402, 404, 406, 408, 410, 412, 414, and 416 are field-effect transistors (FETs). In other examples, other types of transistors may be used. Each transistor includes two terminals and one control terminal. For example, the two terminals of an FET are the source and drain, and the control terminal is the gate.
[0029] Metastable comparator 124 also includes a first voltage terminal 418 and a second voltage terminal 420. The first voltage terminal 418 can receive a first voltage (e.g., V). DD The second voltage terminal 420 can receive a second voltage (e.g., ground). The metastable comparator 124 also includes a first input terminal 422, a second input terminal 424, a first output node 426, and a second output node 428. The metastable comparator 124 includes a first output terminal 430 (OUTP) and a second output terminal 432 (OUTM). Figure 4The diagram also shows various signals, such as clock (CLK) 434, COMPOUT_READY 436 (comparator output ready) and REF_DELAY 438 (reference delay).
[0030] Transistor 402 has a gate coupled to the input of CLK 434, a source coupled to the first voltage terminal 418, and a drain coupled to the first output node 426. Transistor 404 has a gate coupled to the gate of transistor 414, a source coupled to the first voltage terminal 418, and a drain coupled to the first output node 426. Transistor 406 has a gate coupled to the gate of transistor 416, a source coupled to the first voltage terminal 418, and a drain coupled to the second output node 428. Transistor 408 has a gate coupled to the input of CLK 434, a source coupled to the first voltage terminal 418, and a drain coupled to the second output node 428.
[0031] Transistor 410 has a gate coupled to the first input terminal 422, a source coupled to the drain of transistor 414, and a drain coupled to the first output node 426. Transistor 412 has a gate coupled to the second input terminal 424, a source coupled to the drain of transistor 416, and a drain coupled to the second output node 428. Transistor 414 has a gate coupled to the gate of transistor 404, a source coupled to the second voltage terminal 420, and a drain coupled to the source of transistor 410. Transistor 416 has a gate coupled to the gate of transistor 406, a source coupled to the second voltage terminal 420, and a drain coupled to the source of transistor 412. Input signal COMPOUT_READY 436 is provided to the first input terminal 422, and input signal REF_DELAY 438 is provided to the second input terminal 424.
[0032] In operation, COMPOUT_READY 436 is a signal from a comparator in the flash ADC 112 indicating that the comparator has provided an output signal and is not metastable. REF_DELAY 438 is a periodic signal that provides pulses at a specific frequency, for example, one pulse every 160 ps. The REF_DELAY 438 signal indicates how much time the comparator in the flash ADC 112 has to produce an output. If COMPOUT_READY 436 arrives at the metastable comparator 124 before REF_DELAY 438, then transistor 410 is turned on before transistor 412, and the first output node 426 is pulled down to the voltage value at the second voltage terminal 420 (e.g., ground). Therefore, the voltage value at the first output terminal 430 (OUTP) is low, and the metastable comparator 124 produces a 0 output at OUTP and OUTM. A 0 output indicates that the comparator in the flash ADC 112 coupled to this metastable comparator 124 is not metastable.
[0033] In another example, if COMPOUT_READY 436 arrives at metastable comparator 124 after REF_DELAY 438 (e.g., after 160 ps), then transistor 412 is turned on before transistor 410, and the second output node 428 is pulled down to the voltage value at the second voltage terminal 420 (e.g., ground). Therefore, the voltage value at the second output terminal 432 (OUTM) is low, and metastable comparator 124 produces a 1 output on both OUTP and OUTM. This 1 output indicates that the comparator in the flash ADC 112 coupled to this metastable comparator 124 has not yet produced an output after 160 ps and is metastable.
[0034] If any metastable comparator 124 produces a 1 output, then the flash ADC 112 is considered metastable, and the pipeline ADC 100 uses auxiliary path 122, as described below. If all metastable comparators 124 produce a 0 output, then each comparator in the flash ADC 112 has been resolved within 160 ps, and the pipeline ADC 100 can use main path 120.
[0035] Figure 5 This is a block diagram of another example of a pipelined ADC 500. The pipelined ADC 500 includes the features described above. Figure 1Some components are described, and similar components are indicated by similar designations. The structure and operation of these similar components are similar to those in the pipelined ADC 100, as described above. The pipelined ADC 500 includes a first stage 102, a second stage 104, and a back-end ADC 106. The first stage 102 includes a switch 110, a flash ADC 112, a DAC 114, a capacitor 116, and a gain amplifier 118. The second stage 104 also contains components similar to those in the first stage 102, but those components are... Figure 5 The output is not shown, except for gain amplifier 502. First stage 102, second stage 104, back-end ADC 106, and gain amplifier 502 are contained in the main path. In some examples, the gain G2 of gain amplifier 502 is between 1.5X and 10X, but in other examples, G2 can use any value. Gain amplifier 502 amplifies the residual from second stage 104 to provide the amplified value to back-end ADC 106. The pipelined ADC 500 also includes auxiliary paths. In this example, the auxiliary paths include metastable comparator 124, selection circuitry 504, buffer 506, switch 508, capacitor 510, voltage terminal 512, and ADC 514.
[0036] The flash ADC 112 has an input coupled to switch 110 and an output coupled to the input of DAC 114. DAC 114 has an output coupled to a first terminal of capacitor 116. Capacitor 116 has a second terminal coupled to the input of switch 110 and gain amplifier 118. Gain amplifier 118 has an output coupled to the input of the next stage of pipelined ADC 100, which in this example is second stage 104. Second stage 104 has an output coupled to back-end ADC 106. First stage 102, second stage 104, back-end ADC 106, and ADC 104 are each coupled to timing alignment and digital error correction circuitry system 108 (in... Figure 5 (Not shown in the image). The input of metastable comparator 124 is coupled to the output of flash ADC 112. The output of metastable comparator 124 is coupled to the input of selection circuit system 504. Selection circuit system 504 is also coupled to the inputs of switch 110 and gain amplifier 118. The output of selection circuit system 504 is coupled to the input of buffer 506. The output of buffer 506 is coupled to switch 508. Switch 508 is also coupled to the first terminal of capacitor 510 and the input of ADC 514. Capacitor 510 has a second terminal coupled to voltage terminal 512, which in one example is ground.
[0037] Metastable comparator 124 determines whether any comparator within the flash ADC 112 is metastable. If none of the comparators in the flash ADC 112 are metastable, then selection circuitry 504 selects the main path of the pipelined ADC 500. In one example, selection circuitry 504 includes one or more transistor switches whose operation can be controlled by a controller. In other examples, any suitable selection circuitry can be used. If one or more comparators in the flash ADC 112 are metastable, then selection circuitry 504 selects an auxiliary path for the pipelined ADC 500. If an auxiliary path is selected, the residual at the input of gain amplifier 118 is provided to buffer 506. Switch 508 samples the signal at the output of buffer 506, and capacitor 510 stores the sampled signal in the auxiliary path to provide the signal to ADC 514. The operation of switch 508 can be similar to that of switch 110 described above. In other examples, switch 508 is implemented using a sample-and-hold circuitry. In one example, capacitor 510 is a sampling capacitor, i.e., multiple capacitors connected in parallel. In one example, the ADC514 is similar to the backend ADC106 and operates in a similar manner to produce 9 digital bits.
[0038] As mentioned above Figure 2 As described, DAC 114 generates an output signal before gain amplifier 118 begins operation. In the operation of pipelined ADC 500, the residual value from flash ADC 112 is provided to gain amplifier 118. Pipeline ADC 500 includes an auxiliary path used when metastability is detected. The auxiliary path includes buffer 506, which in one example is a unity-gain buffer or amplifier. In the main path, the value provided at the input of gain amplifier 118 stabilizes before integration using gain amplifier 118 begins (e.g., DAC 114 generates an output signal before the gain function begins). In the auxiliary path, buffer 506 is faster than gain amplifier 118. This is because the auxiliary path saves approximately 160 ps of gain time used by gain amplifier 118 (e.g., Figure 2 The time range is 210 ps, so an additional 160 ps is available for the flash ADC 112 to complete its operation. The delayed output of the auxiliary path DAC 114 does not produce the problems that occur with the delayed output of the main path DAC 114.
[0039] In this example, the auxiliary path has 4 bits (from the flash ADC 112) plus 9 bits (from the ADC 514), for a total of 13 bits. The main path has 4 bits (from the flash ADC 112), 3 bits from the second-stage ADC 104, and 9 bits from the back-end ADC 106, for a total of 16 bits. In this example, the time constant in the flash ADC 112 is approximately 5.5 ps, so 160 ps provides an additional 28 time constants for the flash ADC 112 to complete its operation. This additional time helps to significantly resolve metastability. With the additional time in the flash ADC 112, the BER improves from 3e-4 to 2.8e-15. However, the auxiliary path provides 13 bits compared to the 16 bits in the main path. The loss of 3 bits results in an error with 8 (e.g., 2^3) least significant bits. However, the BER has two components: the amount of error and the probability of error. Compared to the potential error of 2048 LSBs described above, an error of ±8 least significant bits (LSBs) is acceptable during metastable conditions. In one example, using an auxiliary path, the BER is 2.8e-15, an improvement over other systems.
[0040] Figure 6 This is a block diagram of another example of a pipelined ADC 600. The pipelined ADC 600 includes the features described above. Figure 5 Some components are described, and similar components are indicated by similar numbers. The pipelined ADC 600 includes a first stage 102, a second stage 104, and a back-end ADC 106. The first stage 102 includes a switch 110, a flash ADC 112, a DAC 114, a capacitor 116, and a gain amplifier 118. The second stage 104 also contains components similar to those in the first stage 102, but those components are... Figure 6 Not shown, except for gain amplifier 502. First stage 102, second stage 104, back-end ADC 106, multiplexer 602, and gain amplifier 502 are contained in main path 120 (in...). Figure 1 (As shown in the image). The pipelined ADC 600 also includes auxiliary paths. In this example, the auxiliary paths include a metastable comparator 124, a buffer 506, a switch 508, a capacitor 510, a voltage terminal 512, and an OR gate 604 (e.g., a logic gate or logic circuit).
[0041] The flash ADC 112 has an input coupled to switch 110 and an output coupled to the input of DAC 114. DAC 114 has an output coupled to a first terminal of capacitor 116. Capacitor 116 has a second terminal coupled to the input of switch 110, gain amplifier 118, and buffer 506. Gain amplifier 118 has an output coupled to the input of the next stage of pipelined ADC 100, which in this example is second stage 104. Second stage 104 has an output coupled to a first input of multiplexer 602. Multiplexer 602 has a second input coupled to switch 508. Multiplexer 602 has a selection input coupled to the output of OR gate 604. Multiplexer 602 has an output coupled to gain amplifier 502. Gain amplifier 502 has an output coupled to back-end ADC 106. First stage 102, second stage 104, and back-end ADC 106 are each coupled to timing alignment and digital error correction circuitry system 108 (in... Figure 6 (Not shown in the image). The input of metastable comparator 124 is coupled to the output of flash ADC 112. The output of metastable comparator 124 is coupled to OR gate 604. Buffer 506 has an input coupled to the input of gain amplifier 118 and an output coupled to switch 508. Switch 508 is also coupled to capacitor 510 and the second input of multiplexer 602. Capacitor 510 is also coupled to voltage terminal 512, which in one example is ground.
[0042] In the pipelined ADC 600, multiplexer 602 and OR gate 604 are used to select between the main path and the auxiliary path. Multiplexer 602 is a path selection circuit that includes control inputs or selection inputs. In other examples, the path selection circuit includes circuitry other than the multiplexer (e.g., transistor switches). The pipelined ADC 600 reuses the back-end ADC 106 for both the main path and the auxiliary path, and... Figure 5 Compared to the pipelined ADC 500, this saves some area and power consumption. In the pipelined ADC 600, a metastable comparator 124 detects whether any comparator in the flash ADC 112 is metastable. If none of the comparators in the flash ADC 112 are metastable, then OR gate 604 provides a low output signal to the control input of multiplexer 602. In response to this low signal from OR gate 604 (e.g., control input), multiplexer 602 selects the primary path and couples the secondary stage 104 to gain amplifier 502. If one or more comparators in the flash ADC 112 are metastable, then OR gate 604 provides a high output signal to multiplexer 602. In response to this high signal from OR gate 604, multiplexer 602 selects the secondary path and couples buffer 506 to gain amplifier 502.
[0043] Figure 7 This is a flowchart of an example method 700 for metastability detection. The steps of method 700 can be performed in any suitable order. In some examples, the above regarding... Figure 1 and 3 Method 700 is executed using the hardware components described in -6. In other examples, method 700 is executed using any suitable hardware, software, or digital logic.
[0044] Method 700 begins at 710, where the pipelined ADC receives an input signal. The input signal can be an analog signal that the pipelined ADC converts into a digital signal. Pipeline ADCs 100, 500, or 600 can perform the operations described herein. The pipelined ADC can contain any number of stages and can resolve any number of bits.
[0045] Method 700 continues to 720, where the pipelined ADC provides the input signal to the flash ADC in the first stage of the pipelined ADC. In one example, the flash ADC is flash ADC 112. Flash ADC 112 may contain several flash comparators for performing analog-to-digital conversion. In one example, flash ADC 112 contains 32 flash comparators.
[0046] Method 700 continues to 730, where a metastable comparator determines or detects whether any of the flash comparators is metastable. Each flash comparator may be coupled to a metastable comparator, such as metastable comparator 124. In one example, metastable comparator 124 is a delay domain comparator. If a flash comparator has not produced an output after a certain amount of time has elapsed, then metastable comparator 124 can determine that the flash comparator is metastable.
[0047] If none of the flash comparators are metastable (e.g., each flash comparator has provided an output within a predetermined time range), then method 700 proceeds to 740. At 740, the pipelined ADC provides the residual signal from the first stage to the second stage in the main path of the pipelined ADC. In one example, the residual signal is provided from the first stage 102 to the second stage 104.
[0048] Method 700 continues to 750, where the residual signal from the second stage 104 is provided to a third stage (e.g., a back-end ADC 106) in the main path of the pipelined ADC. The pipelined ADC can contain any number of stages, and the stages can produce any number of digital output bits in the main path.
[0049] If any of the flash comparators at 730 is metastable, then method 700 continues to 760. At 760, the residual signal from the first stage is provided to an auxiliary path in the pipelined ADC. The auxiliary path provides additional time for the flash comparators to resolve, thereby reducing the probability of metastability in the flash comparators. An example of the auxiliary path is... Figure 1 The auxiliary path 122. If one or more flash comparators are metastable, the residual from the first stage 102 is received by the auxiliary path.
[0050] Method 700 continues to 770, where the auxiliary path provides the residual (from stage 102) to the next stage of the pipelined ADC. The next stage could be another auxiliary ADC, for example... Figure 5 The ADC 514 in the pipeline (e.g., a back-end ADC). In another example, the next stage is a stage in the main path of the pipelined ADC, such as... Figure 6 The back-end ADC 106 is shown.
[0051] In the example presented in this paper, a delay domain comparator detects metastability in the flash ADC comparator. The residual from the first stage of the pipelined ADC is provided to either the main path or an auxiliary path of the ADC. If no metastability is detected, the residual is propagated to the main path. If the delay domain comparator detects metastability, the residual is provided to the auxiliary path, giving the flash ADC comparator more time to stabilize. This extra time for stabilization can improve the BER (BER). Several architectures for implementing the auxiliary path are described in this paper.
[0052] In this description, the term "coupled" may encompass a connection, communication, or signaling path that enables the functional relationship to be consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
[0053] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or through a combination thereof.
[0054] The circuits or devices described herein as containing certain components may conversely be coupled to components used to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be coupled to at least some of the passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.
[0055] While some components may be described herein as belonging to a particular process technology, these components may be interchangeable with components from other process technologies. The circuits described herein are reconfigurable to include alternative components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide a certain amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors respectively coupled in parallel between the same nodes. Conversely, a resistor or capacitor shown and described herein as a single component may be multiple resistors or capacitors respectively coupled in series between the same two nodes as a single resistor or capacitor.
[0056] The use of the phrase "grounding" in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means a difference of no more than + / - 10% from the parameter. Within the scope of the claims, the examples may be modified, and other examples are possible.
[0057] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnects or the ends thereof between device elements, circuit elements, integrated circuits, devices, or semiconductor components. Additionally, a voltage rail, or more simply a “rail,” may also be referred to as a voltage terminal and may generally refer to a common node or a set of coupled nodes at the same potential in a circuit.
Claims
1. A system comprising: A pipelined analog-to-digital converter (ADC) having a main path and an auxiliary path, wherein the main path includes: The first stage has a sampling switch, a flash ADC having an input coupled to the sampling switch, a digital-to-analog converter (DAC) having an input coupled to the output of the flash ADC, and a first amplifier having an output coupled to the DAC and an input coupled to the sampling switch, wherein the first stage is configured to generate samples of the input signal and generate a first residual value; The second stage is coupled to the inputs of the first stage and the second amplifier, wherein the second stage is configured to generate a sample of the first residual value and generate a second residual value; as well as A back-end ADC having an input coupled to the output of the second amplifier, wherein the back-end ADC is configured to generate samples of the second residual value and quantize the second residual value; and The auxiliary path includes: Multiple metastable comparators are coupled to the flash ADC, wherein each metastable comparator is configured to detect the metastable state of a comparator in the flash ADC.
2. The system according to claim 1, further comprising: A buffer having the output coupled to the DAC and the input to the sampling switch; A multiplexer having a first input coupled to the output of the buffer and a second input coupled to the second stage, wherein the multiplexer is configured to select between the output of the buffer and the second stage; as well as A logic gate coupled to the plurality of metastable comparators and the multiplexer, wherein the logic gate is configured to control the control input of the multiplexer.
3. The system according to claim 2, wherein the logic gate is an OR gate.
4. The system of claim 2, wherein the multiplexer is configured to select the output of the buffer in response to the metastable comparator detecting a metastable state of the comparator in the flash ADC.
5. The system of claim 2, wherein the auxiliary path includes a sampling capacitor coupled to the output of the buffer.
6. The system of claim 1, wherein the first stage is configured to generate samples of the input signal having a first number of bits, the second stage is configured to generate samples of the first residual value having a second number of bits, and the back-end ADC is configured to generate samples of the second residual value having a third number of bits.
7. The system of claim 1, wherein each metastable comparator is a delay domain comparator.
8. The system according to claim 1, further comprising: A sampling capacitor is located between the output of the DAC and the first amplifier.
9. The system of claim 1, wherein the main path generates samples having a first number of units, and the auxiliary path generates samples having a second number of units, wherein the second number of units is less than the first number of units.
10. A pipelined analog-to-digital converter (ADC), comprising: The first ADC path includes: The first-stage ADC includes a flash ADC and a first amplifier coupled to the flash ADC, the first amplifier having an input and an output; The second-stage ADC has an input coupled to the output of the first amplifier and has an output; The second amplifier has both input and output; as well as A third-stage ADC has an input coupled to the output of the second amplifier; A second ADC path is coupled to the input of the first amplifier and has an output; A metastable comparator having an input coupled to the flash ADC and an output; A logic circuit having an input coupled to the output of the metastable comparator and having an output; as well as A path selection circuit having a first input coupled to the output of the second-stage ADC, a second input coupled to the output of the second ADC path, a selection input coupled to the output of the logic circuit, and an output coupled to the input of the second amplifier.
11. The pipelined ADC of claim 10, wherein the path selection circuit includes a multiplexer having the first, second, and selection inputs.
12. The pipelined ADC of claim 10, wherein the logic circuitry comprises an OR gate having an input coupled to the output of the metastable comparator and an output coupled to the selection input of the path selection circuitry.
13. The pipelined ADC of claim 10, wherein the first-stage ADC comprises: A sampling switch having terminals coupled to the input of the flash ADC and the input of the first amplifier; A digital-to-analog converter (DAC) having an input coupled to the output of the flash ADC and having an output; and A sampling capacitor having a first terminal coupled to the output of the DAC and a second terminal coupled to the input of the first amplifier.
14. The pipelined ADC of claim 10, wherein the second ADC path comprises: A buffer having an input coupled to the input of the first amplifier and having an output; A sampling switch having a first terminal coupled to the output of the buffer and a second terminal coupled to the second input of the path selection circuit; and A sampling capacitor having a terminal coupled to the second input of the path selection circuit.
15. The pipelined ADC of claim 10, wherein the flash ADC includes a comparator, and the metastable comparator is coupled to the comparator.
16. The pipelined ADC of claim 10, wherein the metastable comparator is a delay domain comparator.
17. A system comprising: A pipelined analog-to-digital converter (ADC) having a main path and an auxiliary path, wherein the main path includes: The first stage has an input, an output, a sampling switch, a flash ADC coupled to the sampling switch, a digital-to-analog converter (DAC) coupled to the flash ADC, and a first amplifier coupled to the DAC and the sampling switch; The second stage has an input coupled to the output of the first stage and the input of the second amplifier; as well as A first back-end ADC has an input coupled to the output of the second amplifier; and The auxiliary path includes: Multiple metastable comparators are coupled to the flash ADC; Select the circuit system, which is coupled to the output of the DAC and the plurality of metastable comparators; A buffer having an input and an output, the input being coupled to the output of the selection circuit system; as well as The second back-end ADC is coupled to the output of the buffer.
18. The system of claim 17, wherein the buffer is a unity-gain buffer.
19. The system of claim 17, wherein each metastable comparator is coupled to a comparator in the flash ADC.
20. The system of claim 19, wherein each metastable comparator is a delay domain comparator.