Self-adaptive overtime trigger configuration method based on SPI (Serial Peripheral Interface) signal
By dynamically adjusting the timeout threshold of the SPI clock signal using FPGA, the synchronization difficulties of the SPI communication protocol in non-standardized scenarios are solved, achieving automated locking and stable triggering, thus improving testing efficiency and accuracy.
Patent Information
- Application Number
- CN202610183044.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-09
- Publication Date
- 2026-05-19
AI Technical Summary
In non-standardized scenarios, the existing SPI communication protocol makes it difficult for test and measurement instruments to establish stable trigger synchronization, resulting in low efficiency and a tendency for calculation errors and misjudgments.
An FPGA-based adaptive timeout trigger configuration method is adopted. By measuring the first complete cycle of the SPI clock signal, the timeout threshold is dynamically adjusted. Automatic locking is achieved by using a progressive probing strategy and a closed-loop feedback mechanism. This includes configuring multiple timeout thresholds in the programmable trigger unit and monitoring the stability of the trigger signal, and generating manual configuration prompts when necessary.
It achieves automatic locking of non-standard SPI waveforms, improves the stability and efficiency of SPI communication, and reduces errors and misjudgments caused by manual calculation.
Smart Images
Figure CN122064636A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of hardware resource management technology, and in particular to an adaptive timeout trigger configuration method based on the Serial Peripheral Interface (SPI) signal. Background Technology
[0002] In the verification and debugging of modern embedded systems, signal acquisition and analysis of the Serial Peripheral Interface (SPI) communication protocol constitute a critical step. However, due to the high degree of non-standardization in the physical layer implementation of the SPI protocol—especially in scenarios such as missing chip select (CS) signals, complex slave topologies, or uncertain inter-frame gaps introduced by the master—test and measurement instruments (such as digital oscilloscopes and logic analyzers) struggle to establish stable trigger synchronization. Existing solutions primarily rely on manual calculation and setting of timeouts, a process that is not only inefficient but also highly susceptible to trigger jitter or misjudgment due to calculation errors. Summary of the Invention
[0003] The purpose of this invention is to provide an adaptive timeout trigger configuration method based on the serial peripheral interface (SPI) signal, thereby achieving automatic locking of non-standard SPI waveforms.
[0004] The technical solution adopted in this invention is:
[0005] An adaptive timeout trigger configuration method based on SPI signals of a serial peripheral interface includes the following steps:
[0006] In response to the trigger optimization instruction, the hardware logic circuit in the field programmable gate array (FPGA) is used to measure the input SPI clock signal to obtain the duration T of the first complete clock cycle;
[0007] Based on the duration T and a set of predetermined increments, multiple timeout thresholds are calculated sequentially; and each timeout threshold is calculated, the corresponding timeout threshold is configured to the programmable trigger unit. After each configuration, the stability of the trigger signal output by the programmable trigger unit is monitored. If the timeout threshold can generate a stable trigger signal, the current configuration is locked; otherwise, the next timeout threshold is calculated.
[0008] When it is detected that the timeout thresholds corresponding to all multiples cannot generate a stable trigger signal, a manual configuration prompt is generated to notify the user.
[0009] Furthermore, the specific steps are as follows:
[0010] Step S1: In response to the trigger optimization instruction, the hardware logic circuit in the field programmable gate array (FPGA) is used to measure the input SPI clock signal to obtain the duration T of the first complete clock cycle.
[0011] Step S2: Obtain a set of predetermined multiples that increase sequentially, and select the smallest predetermined multiple as the current predetermined multiple;
[0012] Step S3: The processor calculates the timeout threshold based on the duration T according to the current predetermined multiple;
[0013] Step S4: Configure the timeout threshold to the trigger detection circuit in the FPGA, and monitor the output of the trigger detection circuit after the timeout threshold has elapsed for a specified duration.
[0014] Step S5: Determine if a stable trigger signal has been generated; if yes, lock the current configuration and end; otherwise,
[0015] Step S6: Determine if all preset multiples have been traversed; if so, proceed to step S7; otherwise, select the next level multiple as the current multiple and proceed to step S3.
[0016] Step S7: Output a prompt message indicating a request for manual configuration.
[0017] Furthermore, a set of predetermined multiples that increase sequentially include 1.5, 2.0, 2.5, and 3.0.
[0018] Furthermore, the duration T of the first complete clock cycle is obtained, specifically including:
[0019] The counter is started when the first valid edge of the SPI clock signal is detected;
[0020] The counter stops when the second positive edge of the SPI clock signal is detected.
[0021] The duration T is determined based on the final count value of the counter and the system clock frequency of the FPGA.
[0022] Furthermore, the step of "determining whether a stable trigger signal has been generated" includes:
[0023] Monitor the trigger count of the trigger detection circuit;
[0024] If the trigger count increases within the specified time period of the corresponding CPU, and the rate of increase is within a preset reasonable range, it is determined that a stable trigger signal has been generated.
[0025] Furthermore, an adaptive timeout trigger configuration system based on the Serial Peripheral Interface (SPI) signal includes:
[0026] The Field Programmable Gate Array (FPGA) integrates a period measurement engine and a programmable trigger unit. The period measurement engine measures the duration T of the first complete clock cycle of the SPI clock signal; the programmable trigger unit generates a trigger signal based on a configured timeout threshold.
[0027] An embedded processor, communicating with an FPGA, receives the duration T measured by a period measurement engine; calculates multiple timeout thresholds sequentially based on the duration T and a set of predetermined incrementing factors; configures each calculated timeout threshold sequentially to a programmable trigger unit; monitors the stability of the trigger signal output by the programmable trigger unit after each configuration; locks the current configuration when a certain timeout threshold can generate a stable trigger signal; and generates a manual configuration prompt if the timeout thresholds corresponding to all incrementing factors cannot generate a stable trigger signal.
[0028] Furthermore, the embedded processor communicates with the FPGA via a parallel bus or a PCIe bus.
[0029] Furthermore, the programmable trigger unit includes a reloadable decrementing counter.
[0030] This invention employs the above technical solution, utilizing the high-speed parallel processing capability of an FPGA to perform real-time measurement of the first cycle of the SPI clock signal (SCLK) with nanosecond-level precision. Subsequently, the CPU dynamically adjusts the timeout threshold based on a heuristic algorithm. The system adopts a progressive probing strategy, sequentially applying timeout coefficients of 1.5 times, 2.0 times, 2.5 times, and 3.0 times the clock cycle. A closed-loop feedback mechanism verifies trigger stability, thereby achieving automatic locking of non-standard SPI waveforms. If locking still fails after traversing all coefficients, the system deterministically reverts to the user-interactive mode. Attached Figure Description
[0031] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments;
[0032] Figure 1 This is a flowchart illustrating the adaptive timeout trigger configuration method based on the Serial Peripheral Interface (SPI) signal of the present invention. Detailed Implementation
[0033] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.
[0034] like Figure 1 As shown, this invention discloses an adaptive timeout trigger configuration method based on the Serial Peripheral Interface (SPI) signal, comprising the following steps:
[0035] In response to the trigger optimization instruction, the hardware logic circuit in the field programmable gate array (FPGA) is used to measure the input SPI clock signal to obtain the duration T of the first complete clock cycle;
[0036] Based on the duration T and a set of predetermined increments, multiple timeout thresholds are calculated sequentially; and each timeout threshold is calculated, the corresponding timeout threshold is configured to the programmable trigger unit. After each configuration, the stability of the trigger signal output by the programmable trigger unit is monitored. If the timeout threshold can generate a stable trigger signal, the current configuration is locked; otherwise, the next timeout threshold is calculated.
[0037] When it is detected that the timeout thresholds corresponding to all multiples cannot generate a stable trigger signal, a manual configuration prompt is generated to notify the user.
[0038] Furthermore, the specific steps are as follows:
[0039] Step S1: In response to the trigger optimization instruction, the hardware logic circuit in the field programmable gate array (FPGA) is used to measure the input SPI clock signal to obtain the duration T of the first complete clock cycle.
[0040] Step S2: Obtain a set of predetermined multiples that increase sequentially, and select the smallest predetermined multiple as the current predetermined multiple;
[0041] Step S3: The processor calculates the timeout threshold based on the duration T according to the current predetermined multiple;
[0042] Step S4: Configure the timeout threshold to the trigger detection circuit in the FPGA, and monitor the output of the trigger detection circuit within the time corresponding to the timeout threshold;
[0043] Step S5: Determine if a stable trigger signal has been generated; if yes, lock the current configuration and end; otherwise,
[0044] Step S6: Determine if all preset multiples have been traversed; if so, proceed to step S7; otherwise, select the next level multiple as the current multiple and proceed to step S3.
[0045] Step S7: Output a prompt message indicating a request for manual configuration.
[0046] Furthermore, a set of predetermined multiples that increase sequentially include 1.5, 2.0, 2.5, and 3.0.
[0047] Furthermore, the duration T of the first complete clock cycle is obtained, specifically including:
[0048] The counter is started when the first valid edge of the SPI clock signal is detected;
[0049] The counter stops when the second positive edge of the SPI clock signal is detected.
[0050] The duration T is determined based on the final count value of the counter and the system clock frequency of the FPGA.
[0051] Furthermore, the step of "determining whether a stable trigger signal has been generated" includes:
[0052] Monitor the trigger count of the trigger detection circuit;
[0053] If the trigger count increases within the specified time period of the corresponding CPU, and the rate of increase is within a preset reasonable range, it is determined that a stable trigger signal has been generated.
[0054] Specifically, the optimized process of the present invention is as follows:
[0055] Start / Initialize: The user initiates the "Optimize Settings" command through the interface, and the system enters the initialization state, clearing the old configuration of FPGA 102.
[0056] Measurement cycle: The CPU sends a start measurement command to the FPGA and polls the FLAG_MEASURE_DONE flag. If the measurement is not completed within the timeout period (e.g., 500ms), the process jumps to failure handling.
[0057] Reasonableness check: After reading N_period, the CPU performs a check. If N_period is too small (e.g., <5) or overflows, the signal is considered abnormal, and the process jumps to S311.
[0058] Progressive coefficient trial loop: The algorithm sequentially tries a set of predetermined multiple coefficients (in this embodiment, in the order of 1.5, 2.0, 2.5, 3.0), including the following steps:
[0059] (1.1) Taking 1.5 times as an example: The CPU calculates the timeout threshold N_timeout = N_period × 1.5 and writes it into the timeout configuration register REG_TIMEOUT of the programmable trigger unit PTU of FPGA 102.
[0060] (1.2) Trigger verification: The CPU starts a short-term monitoring timer (e.g., 50ms) and reads the trigger counter TRIGGER_COUNT of PTU 1022 during this period.
[0061] (1.3) Stability judgment: Verification mechanism. If TRIGGER_COUNT increases at a reasonable rate within 50ms (e.g., increases 10 to 500 times), it is judged as a stable trigger; if the count is 0 or does not change, it is judged as no trigger; if the count is extremely high and disordered, it is judged as a false trigger. The latter two cases are considered as failures.
[0062] (1.4) Try the next coefficient: If the current coefficient (e.g., 1.5 times) fails to be verified, the next larger coefficient (e.g., 2.0 times) will be tried automatically, and the configuration and verification process from (1.1) to (1.3) will be repeated.
[0063] Success and Failure Handling: Success: If verification is successful for any coefficient, the algorithm locks the current timeout setting and prompts the user "Optimization successful". Failure: If all preset coefficients fail to pass, the system enters deterministic fallback mode, prompting the user "No correct signal detected, please set manually", and can assist in displaying the measured signal frequency, such as "A signal of approximately 1MHz was detected, it is recommended to try a 5us timeout".
[0064] Furthermore, an adaptive timeout trigger configuration system based on the Serial Peripheral Interface (SPI) signal includes:
[0065] The Field Programmable Gate Array (FPGA) integrates a period measurement engine and a programmable trigger unit. The period measurement engine measures the duration T of the first complete clock cycle of the SPI clock signal; the programmable trigger unit generates a trigger signal based on a configured timeout threshold.
[0066] An embedded processor, communicating with the FPGA, receives the duration T measured by the cycle measurement engine. Based on the duration T and a set of predetermined incrementing factors, it sequentially calculates multiple timeout thresholds. Each calculated timeout threshold is then configured to a programmable trigger unit. After each configuration, the stability of the trigger signal output by the programmable trigger unit is monitored. If a stable trigger signal is generated for a given timeout threshold, the current configuration is locked. If none of the timeout thresholds corresponding to any of the incrementing factors can generate a stable trigger signal, a manual configuration prompt is generated. The embedded processor can arbitrarily modify the value of this register without reprogramming the FPGA bitstream, thereby enabling rate switching in the algorithm.
[0067] Specifically, the system adopts a heterogeneous hardware architecture based on FPGA and embedded processor (CPU). The system includes an analog front-end and digitization module (AFE & ADC), FPGA, CPU, and a high-speed interconnect bus (such as a parallel bus) connecting the FPGA and CPU. The input SPI signal under test (including the SCLK clock signal and MOSI / MISO data signal) is first conditioned and digitized by the digitization module, converted into a digital signal that can be processed by the FPGA. The embedded processor CPU runs an operating system (such as Linux), is responsible for executing adaptive optimization algorithms, and interacts with the FPGA through register read / write operations via the bus. The CPU dynamically rewrites the value of the N_timeout register through the bus, which allows for flexible adjustment of the timeout threshold without restarting the FPGA.
[0068] Specifically, the period measurement engine is designed as a one-shot high-speed counter. The clock source for the period measurement engine is driven by the FPGA's system reference clock. To ensure measurement accuracy, the system clock frequency is typically much higher than the frequency of the signal being measured. For example, the period is 5ns. The measurement flow of the period measurement engine is as follows:
[0069] Reset (IDLE): After power-on or reset, the cycle measurement engine is in an idle state, waiting for the CPU to send the START_MEASURE signal by writing to the control register.
[0070] Pre-trigger (ARMED): Upon receiving the start signal, the cycle measurement engine enters the pre-trigger state and continuously monitors the first valid rising edge of the SPI clock line (SCLK_in).
[0071] The counting function starts a 32-bit high-speed counter after the first rising edge is detected at time t0. This counter is driven by the FPGA's system clock (e.g., 200MHz, period 5ns).
[0072] Latch: When the second rising edge is detected at time t1, the counter is stopped immediately and the count value N_period is latched into the result register REG_PERIOD.
[0073] DONE: Send an interrupt signal to the CPU or set the status flag FLAG_MEASURE_DONE to indicate that the measurement is complete. The CPU can obtain the count value of the first clock cycle by reading REG_PERIOD, and then calculate the actual time length T = N_period × t_sys (where t_sys is the system clock cycle).
[0074] The key to this invention lies in measuring only the first cycle. Unlike traditional frequency meters (which count pulses within a fixed gate time), this invention focuses on instantaneous characteristics. This allows the measurement process to be completed at the nanosecond to microsecond level, with no noticeable delay for the user.14
[0075] Furthermore, the embedded processor communicates with the FPGA via a parallel bus or a PCIe bus.
[0076] Furthermore, the programmable trigger unit includes a reloadable decrementing counter.
[0077] This invention employs the above technical solution, utilizing the high-speed parallel processing capability of an FPGA to perform real-time measurement of the first cycle of the SPI clock signal (SCLK) with nanosecond-level precision. Subsequently, the CPU dynamically adjusts the timeout threshold based on a heuristic algorithm. The system adopts a progressive probing strategy, sequentially applying timeout coefficients of 1.5 times, 2.0 times, 2.5 times, and 3.0 times the clock cycle. A closed-loop feedback mechanism verifies trigger stability, thereby achieving automatic locking of non-standard SPI waveforms. If locking still fails after traversing all coefficients, the system deterministically reverts to the user-interactive mode.
[0078] Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. Without conflict, the embodiments and features in the embodiments of this application can be combined with each other. The components of the embodiments of this application described and illustrated herein can generally be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of this application is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
Claims
1. An adaptive timeout trigger configuration method based on Serial Peripheral Interface (SPI) signals, characterized in that: It includes the following steps: In response to the trigger optimization instruction, the hardware logic circuit in the field programmable gate array (FPGA) is used to measure the input SPI clock signal to obtain the duration T of the first complete clock cycle; Based on the duration T and a set of predetermined increments, multiple timeout thresholds are calculated sequentially. Each timeout threshold is calculated, the corresponding timeout threshold is configured to the programmable trigger unit. After each configuration, the trigger signal output by the programmable trigger unit is monitored to see if it is stable. If the timeout threshold can generate a stable trigger signal, the current configuration is locked; otherwise, the next timeout threshold is calculated. When it is detected that the timeout thresholds corresponding to all multiples cannot generate a stable trigger signal, a manual configuration prompt is generated to notify the user.
2. The adaptive timeout trigger configuration method based on the Serial Peripheral Interface (SPI) signal according to claim 1, characterized in that: The specific steps are as follows: Step S1: In response to the trigger optimization instruction, the hardware logic circuit in the field programmable gate array (FPGA) is used to measure the input SPI clock signal to obtain the duration T of the first complete clock cycle. Step S2: Obtain a set of predetermined multiples that increase sequentially, and select the smallest predetermined multiple as the current predetermined multiple; Step S3: The processor calculates the timeout threshold based on the duration T according to the current predetermined multiple; Step S4: Configure the timeout threshold to the trigger detection circuit in the FPGA, and monitor the output of the trigger detection circuit after the timeout threshold has elapsed for a specified duration. Step S5: Determine whether a stable trigger signal has been generated. If so, lock the current configuration and end; otherwise, Step S6: Determine whether all preset multiples have been traversed; If so, proceed to step S7; Otherwise, select the next predetermined multiple as the current predetermined multiple and proceed to step S3; Step S7: Output a prompt message indicating a request for manual configuration.
3. The adaptive timeout trigger configuration method based on the Serial Peripheral Interface (SPI) signal according to claim 1, characterized in that: A set of predetermined multiples that increase sequentially include 1.5, 2.0, 2.5 and 3.
0.
4. The adaptive timeout trigger configuration method based on the Serial Peripheral Interface (SPI) signal according to claim 1, characterized in that: Obtain the duration T of the first complete clock cycle, specifically including: The counter is started when the first valid edge of the SPI clock signal is detected; The counter stops when the second positive edge of the SPI clock signal is detected. The duration T is determined based on the final count value of the counter and the system clock frequency of the FPGA.
5. The adaptive timeout trigger configuration method based on the Serial Peripheral Interface (SPI) signal according to claim 1, characterized in that: The steps for "determining whether a stable trigger signal has been generated" include: Monitor the trigger count of the trigger detection circuit; If the trigger count increases within the time specified by the CPU, and the rate of increase is within a preset reasonable range, then it is determined that a stable trigger signal has been generated.
6. An adaptive timeout trigger configuration system based on a serial peripheral interface (SPI) signal, comprising the adaptive timeout trigger configuration method based on a serial peripheral interface (SPI) signal as described in any one of claims 1 to 5, characterized in that: The system includes: The field-programmable gate array (FPGA) integrates a period measurement engine and a programmable trigger unit. The period measurement engine is used to measure the duration T of the first complete clock cycle of the SPI clock signal. The programmable trigger unit is used to generate a trigger signal based on a configured timeout threshold; An embedded processor, communicating with an FPGA, receives the duration T measured by a period measurement engine; calculates multiple timeout thresholds sequentially based on the duration T and a set of predetermined incrementing factors; configures each calculated timeout threshold sequentially to a programmable trigger unit; monitors the stability of the trigger signal output by the programmable trigger unit after each configuration; locks the current configuration when a certain timeout threshold can generate a stable trigger signal; and generates a manual configuration prompt if the timeout thresholds corresponding to all incrementing factors cannot generate a stable trigger signal.
7. The adaptive timeout trigger configuration system based on the Serial Peripheral Interface (SPI) signal according to claim 6, characterized in that: Embedded processors communicate with FPGAs via parallel buses or PCIe buses.
8. The adaptive timeout trigger configuration system based on the Serial Peripheral Interface (SPI) signal according to claim 6, characterized in that: The programmable trigger unit contains a reloadable decrementing counter.