Migration method and device for automatic layout and wiring of printed circuit board and storage medium

Abstract

The invention discloses a migration method and device for automatic layout and wiring of a printed circuit board and a storage medium, and relates to the technical field of electronic manufacturing, and the method comprises the steps: responding to a layout and wiring migration instruction, and extracting a relative layout relation between all elements from reference data of a reference circuit board; based on the board frame information, the obstacle constraint information and the electrical netlist data of the to-be-printed circuit board, migrating the element layout structure of the reference printed circuit board into the feasible region of the to-be-printed circuit board according to the relative layout relationship to obtain an element layout result; constructing a plurality of wiring path representations according to wiring association information between the component layout result and the reference data of the reference circuit board; matching a wiring path to generate wiring migration guide information; and performing wiring migration on the component layout result according to the wiring migration guide information to obtain a layout wiring result. Through automatic wiring migration, the problem of low design efficiency of the circuit board is solved, and the efficiency of layout wiring migration is improved.

Description

Technical Field

[0001] This application relates to the field of electronic manufacturing technology, and in particular to a method, apparatus and storage medium for automatic layout and routing of printed circuit boards. Background Technology

[0002] As electronic products develop towards higher speeds, higher integration, and more multifunctionality, the number of components, network size, and wiring layers in modern printed circuit board design continue to increase, placing more stringent demands on the quality of layout and wiring.

[0003] In related technologies, experienced engineers are usually required to combine extensive engineering experience with repeated simulation analysis to complete high-performance layouts. The entire design process relies on the accumulation of human experience and multiple optimizations and adjustments, which makes it difficult to adapt to the design requirements of rapid iteration, resulting in low circuit board design efficiency.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this application is to provide a method, apparatus, and storage medium for automatic placement and routing of printed circuit boards, aiming to solve the technical problem of low efficiency in circuit board design.

[0006] To achieve the above objectives, this application proposes a migration method for automatic placement and routing of printed circuit boards, the method comprising: In response to placement and routing migration instructions, the relative placement relationships between components are extracted from the reference board baseline data to characterize the implicit design layout features; Based on the board outline information, obstacle constraint information and electrical netlist data of the printed circuit board to be printed, the component layout structure of the reference printed circuit board is migrated to the feasible area of ​​the printed circuit board to be printed according to the relative layout relationship to obtain the component layout result. Based on the routing association information between the component layout results and the reference circuit board baseline data, multiple routing path representations are constructed; Match the correspondence between each of the described wiring paths to generate wiring migration guidance information; Based on the routing migration guidance information, routing migration is performed on the component layout result to obtain the layout routing result.

[0007] In one embodiment, in response to the layout and routing migration command, the reference circuit board reference data is parsed to obtain the position coordinates, placement direction, and pin distribution information of each component; Based on the position coordinates, placement direction, and pin distribution information of each component, calculate the relative spacing, orientation relationship, and pin association information between each component. The relative spacing, orientation, and pin association information of each component are associated and integrated to establish a corresponding mapping relationship, and invalid associations are eliminated to obtain the relative layout relationship.

[0008] In one embodiment, based on the board outline information, obstacle constraint information and electrical netlist data of the printed circuit board to be printed, a feasible area for placing components on the printed circuit board to be printed is defined, and constraint parameter data within the feasible area for placing components is determined. Based on the feasible region and the constraint parameter data, and combined with the relative layout relationship between each component, a mapping coordinate system is established between the feasible region of the circuit board to be printed and the layout region of the reference printed circuit board. According to the mapping coordinate system, the component layout structure of the reference printed circuit board is mapped to the feasible area of ​​the printed circuit board to be printed, while keeping the relative spacing, orientation and pin association between each component unchanged, to obtain the preliminary component migration result. The preliminary component migration results are verified for compliance, and issues such as components exceeding the feasible area, conflicting with obstacle areas, and violating component spacing requirements are corrected. The component layout results are then output.

[0009] In one embodiment, based on the preliminary component migration results, the feasible area boundary, obstacle area range, and component spacing design rules of the printed circuit board are compared with each item to check for violations of component positions, and a list of component layout violations including violation type, violation component position, and corresponding rule requirements is obtained. According to the list of component layout violations and component layout rules, the positions of components that exceed the feasible area are adjusted by translation, the avoidance path is planned for components that conflict with the obstacle area, and the spacing is optimized for components that violate the spacing requirements. The intermediate result of the corrected component layout is output. The intermediate results of the revised component layout are then subjected to a comprehensive compliance review based on all design rules until no violations are confirmed, at which point the final component layout result is generated.

[0010] In one embodiment, the component layout results are extracted from the component pin correspondence, circuit connection logic, and key node distribution characteristics contained in the reference circuit board baseline data, and a wiring association information set is generated accordingly. The specific geometric coordinate attributes of the wiring path are stripped from the wiring association information set, and the wiring information of both the reference circuit board and the circuit board to be printed is converted into a topology structure with component nodes, pad nodes and key transition nodes as the core, to obtain wiring topology structure data. Based on node encoding rules and connection relationship description standards, the cabling topology data is standardized and represented to obtain multiple cabling path representations.

[0011] In one embodiment, wiring matching pair data is established between the wiring path representation of the reference circuit board and the wiring path representation of the circuit board to be printed, based on a plurality of the wiring path representations. Verify the consistency of node mapping, connection priority, and path direction logic between the data in the wiring matching pair. Correct the mismatched node correspondence and connection logic according to the wiring matching rules to obtain the wiring path matching relationship. Extract the node mapping relationship, path priority sorting, cabling inflection point reference position and avoidance constraint prompts corresponding to the path migration in the cabling path matching relationship, and integrate them to generate the cabling migration guidance information that can directly guide the cabling migration operation.

[0012] In one embodiment, the node mapping relationship, path priority sorting and avoidance constraint prompts in the routing migration guidance information and the component layout results are parsed to plan the routing migration execution scheme of the printed circuit board to be printed. Based on the routing migration execution scheme, the routing paths are drawn sequentially between the component pins and pad nodes corresponding to the component layout results, according to the path priority, and obstacle areas are avoided, and the preliminary routing migration results are output. The preliminary wiring migration results are subjected to electrical connection integrity verification and comprehensive compliance checks of design rules. Wiring breaks, line short circuits and non-compliant spacing are corrected to generate the layout wiring results.

[0013] In one embodiment, based on the design requirements, performance indicators, and compliance standards uploaded by the user, the electrical connection correctness, layout rationality, wiring compliance, and performance compliance of the layout and wiring results are checked, and a layout and wiring inspection report is generated. Extract key issue information from the layout and routing inspection report, associate it with the original reference data uploaded by the user and the design constraints, sort out the factors related to the migration parameters that caused the problem, and generate feedback data; Based on the feedback data, analyze the weight coefficients and core parameters related to the problem during the migration process, determine the types and magnitudes of parameters that need to be adjusted, and output the parameter adjustment plan; According to the parameter adjustment scheme, the weights and parameters in the migration process are updated, and the layout and routing of the reference circuit board are re-optimized to generate the optimized layout and routing results.

[0014] In addition, to achieve the above objectives, this application also proposes an automatic placement and routing device for printed circuit boards, the automatic placement and routing device for printed circuit boards comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the migration method for automatic placement and routing of printed circuit boards as described above.

[0015] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the automatic placement and routing migration method for printed circuit boards as described above.

[0016] This application provides a method for automatic placement and routing migration of printed circuit boards (PCBs). The method includes extracting the relative placement relationships between components from reference PCB baseline data in response to a placement and routing migration command; migrating the component placement structure of the reference PCB to a feasible area of ​​the PCB according to the relative placement relationships based on the board outline information, obstacle constraint information, and electrical netlist data of the PCB to be printed; constructing multiple routing path representations based on the routing association information between the component placement results and the reference PCB baseline data; generating routing migration guidance information by matching the correspondence between each routing path; and finally performing routing migration on the component placement results based on the routing migration guidance information to obtain the final placement and routing result. This method solves the technical problems of easily confused relative placement relationships, mismatched routing logic, poor compliance of migration results, and low efficiency due to reliance on manual intervention in traditional PCB placement and routing migration processes. It improves the accuracy, automation, and efficiency of PCB placement and routing migration, ensuring the consistency between the migrated placement and routing result and the reference design, as well as compliance with the design constraints of the PCB to be printed.

[0017] In summary, this application solves the technical problem of low efficiency in circuit board design by extracting the relative layout relationship of reference board components, migrating the layout, constructing a routing path representation, and generating guiding information to complete the routing migration, thereby improving the accuracy, automation, and compliance of layout and routing migration. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating the first embodiment of the automatic placement and routing migration method for printed circuit boards according to this application. Figure 2 This is a flowchart illustrating the fourth embodiment of the automatic placement and routing migration method for printed circuit boards according to this application. Figure 3 This is a flowchart of the method in this application; Figure 4 This is a flowchart illustrating the eighth embodiment of the automatic placement and routing migration method for printed circuit boards according to this application. Figure 5 This is a block diagram of the overall system structure of this application; Figure 6 This is a schematic diagram of the automatic layout and routing equipment for printed circuit boards according to this application.

[0021] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0023] In related technologies, experienced engineers are usually required to combine extensive engineering experience with repeated simulation analysis to complete high-performance layouts. The entire design process relies on the accumulation of human experience and multiple optimizations and adjustments, which makes it difficult to adapt to the design requirements of rapid iteration, resulting in low circuit board design efficiency.

[0024] This application provides a solution: First, in response to a placement and routing migration command, the relative placement relationships between components are extracted from reference circuit board baseline data to characterize implicit design layout features. Then, based on the board outline information, obstacle constraint information, and electrical netlist data of the circuit board to be printed, the component placement structure of the reference circuit board is migrated to the feasible area of ​​the circuit board to be printed according to the relative placement relationships to obtain a component placement result. Next, based on the routing association information between the component placement result and the reference circuit board baseline data, multiple routing path representations are constructed. Then, the correspondence between each routing path is matched to generate routing migration guidance information. Finally, based on the routing migration guidance information, routing migration is performed on the component placement result to obtain a placement and routing result.

[0025] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or an automatic placement and routing device for printed circuit boards capable of the above functions. The following description uses an automatic placement and routing device for printed circuit boards as an example to illustrate this embodiment and the subsequent embodiments.

[0026] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0027] This application provides a migration method for automatic placement and routing of printed circuit boards, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the automatic placement and routing migration method for printed circuit boards according to this application.

[0028] In this embodiment, the automatic placement and routing migration method for printed circuit boards includes steps S10 to S50: Step S10: In response to the layout and routing migration instruction, extract the relative layout relationships between components from the reference board baseline data to characterize the implicit design layout features.

[0029] In this embodiment, the placement and routing migration instruction is a trigger signal that initiates the extraction of relative placement relationships of components. The reference board baseline data is a set of basic data containing the position coordinates, orientation, pin distribution, and connection logic of all components on the reference board. Components are electronic device units that constitute the circuit function of the circuit board. Relative placement relationships refer to the relative spacing, orientation, and pin correspondence information between components. Implicit design placement features are the implicit placement logic and structural features in the reference board that reflect expert design experience, including the placement relationship between the reference board and the printed circuit board to be manufactured.

[0030] As an optional implementation, in response to placement and routing migration instructions, the reference circuit board baseline data is first fully parsed to extract the position coordinates, orientation, and pin distribution information of all components, forming a component basic attribute dataset. Then, based on this dataset, the relative spacing, orientation correspondence, and direct and indirect pin relationships between any two components are calculated to obtain a preliminary component relative relationship dataset. Finally, this preliminary dataset is filtered to remove redundant correlation information without practical design significance, retaining key relative layout relationships that characterize core design features, and outputting the final relative layout relationships between all components. This method can preserve the original design details of the reference circuit board to the greatest extent, and the extracted relative layout relationships are highly accurate, providing a high-fidelity reference for subsequent placement migration.

[0031] As an alternative implementation, in response to a placement and routing migration command, the components in the reference circuit board baseline data are first grouped and categorized according to preset component function classification rules, resulting in different functional component groups. Then, the relative placement relationships between components within the same functional component group and the overall relative positional relationships between different functional component groups are extracted to form a grouped relative relationship dataset. Finally, this grouped dataset undergoes topology simplification processing, merging similar related information to generate component relative placement relationships with functional groups as the basic unit, outputting the final relative placement relationships between each component. This method reduces the amount of data computation through group simplification, resulting in higher processing efficiency. It is suitable for processing reference circuit board baseline data with large-scale components and can significantly shorten the overall process time for subsequent placement migration.

[0032] Step S20: Based on the board outline information, obstacle constraint information and electrical netlist data of the circuit board to be printed, the component layout structure of the reference printed circuit board is migrated to the feasible area of ​​the circuit board to be printed according to the relative layout relationship to obtain the component layout result.

[0033] In this embodiment, the board outline information of the printed circuit board to be manufactured refers to the basic shape information of the new board's outer boundary and size range. Obstacle constraint information refers to the areas on the new board that need to be avoided and the corresponding avoidance requirements. Electrical netlist data is a collection of information recording the electrical connection relationships of the pins of each component on the printed circuit board to be manufactured. The component layout structure of the reference printed circuit board is the arrangement and distribution of all components on the reference board and their relative positions. The feasible area is the area on the printed circuit board to be manufactured where components can be placed, meeting the board outline boundary and obstacle avoidance requirements. The component layout result is the final layout state that meets the requirements formed within the feasible area of ​​the printed circuit board to be manufactured after component migration.

[0034] As an optional implementation, based on the board outline information, obstacle constraint information, and electrical netlist data of the printed circuit board to be manufactured, a feasible area is first delineated through boundary resolution and obstacle identification, determining the boundary restrictions, obstacle avoidance range, and pin adaptation requirements within this feasible area. Then, combining the extracted relative layout relationships, core functional components in the reference printed circuit board are selected as positioning anchor points, establishing a mapping relationship between the reference board layout area and the feasible area of ​​the printed circuit board to be manufactured. The reference board component layout structure is then migrated as a whole to the feasible area of ​​the printed circuit board to be manufactured according to the anchor point mapping relationship, simultaneously maintaining the relative spacing, orientation, and pin relationships between each component. Finally, a component-by-component compliance check is performed on the migrated layout to correct minor boundary violations, obtaining the component layout result. This method achieves high fidelity in the relative layout of migrated components, accurately replicating the design logic of the reference board and directly providing a precise layout foundation for subsequent routing migration.

[0035] As an alternative implementation, based on the board outline information, obstacle constraint information, and electrical netlist data of the printed circuit board to be manufactured, the feasible area is first functionally partitioned to determine the component placement type and quantity limits for each partition. Then, combining relative layout relationships, the component layout structure of the reference printed circuit board is functionally decomposed into several component groups. Based on the functional attributes of each component group, the corresponding functional partition of the printed circuit board to be manufactured is matched, and each component group is migrated to its corresponding partition while maintaining the relative layout relationships of the components within the group. Finally, the component layout of each partition is coordinated as a whole, adjusting the spacing and positional adaptability of components between partitions to ensure compliance with the connection logic requirements of the electrical netlist, thus obtaining the component layout result. This method reduces the difficulty of migration calculations through functional partitioning, has high processing efficiency, is suitable for large-scale component layout migration scenarios, shortens the overall process time, and is suitable for scenarios with high migration efficiency requirements.

[0036] Step S30: Based on the wiring association information between the component layout results and the reference circuit board baseline data, construct multiple wiring path representations.

[0037] In this embodiment, the routing association information refers to the corresponding associations between the two types of data mentioned above regarding component pin connection relationships, routing node distribution, and line routing characteristics. The routing path representation is a path model that can be used for matching and migration, formed by standardizing and abstracting the routing information.

[0038] As an optional implementation, based on the routing association information between the component layout results and the reference circuit board baseline data, the component pin connection relationships, routing inflection point positions, key transition node distributions, and routing logic are first extracted from both types of data to form a routing association feature dataset. Then, the specific geometric coordinate attributes of the routing paths are stripped away, and all routing information is converted into a preliminary topology structure centered on component nodes, pad nodes, and transition nodes. Next, unified node encoding rules and connection relationship description standards are defined to standardize and organize the preliminary topology structure, generating multiple routing path representations with topological consistency. The routing path representation constructed by this method has high accuracy, completely retains the core connection logic of the routing, facilitates subsequent path matching, and provides accurate path references for the generation of subsequent routing migration guidance information.

[0039] As an alternative implementation, based on the wiring association information between the component layout results and the reference circuit board baseline data, the wiring association information is first grouped according to the functional attributes of the components, dividing the wiring subsets corresponding to different functional modules. Then, the core connection relationships and critical path features within each wiring subset are extracted, discarding non-critical inflection points and transition nodes in the wiring, and simplifying the wiring information of each subset. Finally, based on the simplified wiring features, multiple wiring path representations are integrated to generate multiple representations based on functional modules. This method significantly reduces the amount of data processing through functional grouping and feature simplification, improves the efficiency of wiring path representation construction, adapts to large-scale wiring information processing scenarios, shortens the data processing time in the early stages of wiring migration, and is suitable for wiring migration scenarios with high requirements for construction efficiency.

[0040] Step S40: Match the correspondence between each of the wiring paths to generate wiring migration guidance information.

[0041] In this embodiment, the correspondence refers to the matching and association relationship between the node mapping, connection logic, and topology of the reference circuit board routing path and the routing path of the circuit board to be printed. Routing migration guidance information refers to a set of guiding data, including node correspondence rules, path priority sorting, and avoidance constraint prompts, used to guide the routing migration operation of the circuit board to be printed.

[0042] As an optional implementation, multi-dimensional matching rules are first defined, including node type matching rules, connection logic matching rules, and topology matching rules. Then, based on these rules, a fine-grained path-by-path matching is performed between the reference circuit board routing path and the routing path of the circuit board to be printed, establishing an initial path correspondence. Next, the consistency of node mapping, connection priority, and path direction logic for each pair of corresponding paths is verified, correcting mismatched node associations and path logic deviations. Finally, key guiding elements for path migration are extracted, including precise node correspondence, path execution priority ranking, routing inflection point reference positions, and obstacle avoidance constraints. These elements are integrated to generate routing migration guidance information. This method offers high path matching accuracy, and the generated guidance information comprehensively covers all the detailed requirements of routing migration, providing precise operational guidance for subsequent routing migration and ensuring the accuracy of the routing migration results.

[0043] As an alternative implementation, all routing paths are first grouped according to functional attributes, dividing them into path subsets corresponding to different functional modules. Then, using functional modules as units, a global correspondence is established between the reference circuit board's functional module path subsets and the circuit board to be printed's functional module path subsets. Next, within each functional module, the core connection logic and key node correspondences of the paths are extracted, discarding non-critical path details. Finally, the path correspondences of each functional module, the execution priority of paths within a module, and the connection requirements for cross-module routing are integrated to generate routing migration guidance information. This method significantly simplifies the matching process through functional grouping, reduces data computation, improves the efficiency of guidance information generation, and shortens the data processing time in the early stages of routing migration, meeting the needs of efficient layout and routing migration.

[0044] Step S50: Based on the routing migration guidance information, perform routing migration on the component layout result to obtain the layout routing result.

[0045] In this embodiment, routing migration is the process of migrating the routing logic of a reference printed circuit board to the component layout of the circuit board to be printed. The layout and routing result is the final overall state of the component layout and routing of the circuit board to be printed after the routing migration is completed.

[0046] As an optional implementation, the method first parses the precise node mapping relationships, path execution priority order, and obstacle avoidance constraints in the routing migration guidance information to plan the routing execution order and node connection rules for each path. Then, routing paths are drawn segment by segment between component pins and pad nodes corresponding to the component placement results, according to priority order, while simultaneously adhering to obstacle avoidance requirements and component spacing design rules. Next, electrical connection integrity verification and initial design rule compliance checks are performed to correct issues such as disconnected routing, short circuits, and spacing violations, resulting in the final placement and routing results. This method offers precise and controllable routing processes, maximally replicating the routing logic of the reference circuit board, ensuring the adaptability of routing and placement, and producing stable and reliable electrical connections with strong compliance, achieving a high level of consistency with the reference design.

[0047] As an alternative implementation, the wiring migration guidance information is first categorized according to functional attributes, dividing it into subsets corresponding to different functional modules to determine the wiring scope and cross-module connection requirements for each module. Then, using functional modules as units, the wiring migration operations within the corresponding areas are completed in batches, simultaneously coordinating the wiring routing and spacing compatibility between modules to avoid cross-module wiring conflicts. Next, an overall compliance check is performed within and across modules to correct wiring connection issues and spacing violations at module boundaries, finally yielding the layout and wiring results. This modular batch processing method significantly simplifies the operation process, reduces data computation, improves the overall efficiency of wiring migration, and shortens the overall process time, making it suitable for layout and wiring scenarios with high migration efficiency requirements.

[0048] For example, in a circuit board layout and routing scenario, in response to a layout and routing migration command, the relative layout relationships between components are extracted from the reference data of a consumer electronics main control reference circuit board containing 200 components. The core chip and surrounding capacitors have a relative spacing of 5mm and are arranged horizontally at 0°, while the capacitors and resistors have a relative spacing of 2mm and are arranged vertically at 90°. Based on the board outline information of a 100mm × 80mm circuit board to be printed, the heat dissipation area obstacle constraint information of a 20mm × 15mm area, and the electrical netlist data containing 120 sets of pin connections, the component layout structure of the reference circuit board is migrated to the feasible area of ​​the circuit board to be printed according to the above relative layout relationships, resulting in a component layout result. Based on the routing association information between the component layout result and the reference circuit board reference data, 20 sets of routing path representations centered on component nodes and pad nodes are constructed. Match the correspondence between each of the routing paths to generate routing migration guidance information that includes node mapping rules and path priority sorting; based on the routing migration guidance information, perform routing migration on the component layout result to obtain a layout and routing result that meets the design requirements of the new board.

[0049] By extracting the relative layout relationships of reference board components, migrating the layout, constructing path representations, and generating guiding information to complete the routing migration, the problem of low efficiency and poor consistency in traditional circuit board layout and routing migration is solved, thus improving the automation and accuracy of layout and routing migration.

[0050] Based on any of the above embodiments, in Embodiment 2 of this application, step S10 includes steps A11 to A13: Step A11: In response to the layout and routing migration command, parse the reference circuit board reference data to obtain the position coordinates, placement direction and pin distribution information of each component.

[0051] In this embodiment, position coordinates are the spatial location identification information of the component on the reference circuit board. Placement direction is the mounting orientation information of the component on the reference circuit board. Pin distribution information includes the number, arrangement order, and positional association information of the component's pins.

[0052] As an optional implementation, in response to the layout and routing migration command, a preset full data parsing protocol is invoked to perform a field-by-field complete scan of the reference circuit board baseline data. This identifies the identification fields used to distinguish different components within the baseline data, and associates these identification fields with corresponding position coordinate records, placement orientation information, and pin distribution information. The extracted information is then normalized to eliminate data redundancy and format differences. Finally, the processed information undergoes integrity verification. After confirming that all three types of information for each component are complete, the position coordinates, placement orientation, and pin distribution information of each component are output. This method offers comprehensive parsing coverage, extracting complete information for all components in the reference circuit board baseline data, providing comprehensive and detailed data support for subsequent extraction of relative layout relationships.

[0053] As an alternative implementation, in response to the placement and routing migration command, the reference circuit board baseline data is scanned in a directional manner according to preset component core feature recognition rules to filter out core feature fields containing component position coordinates, placement orientation, and pin distribution. Through correlation matching of these core feature fields, the position coordinates, placement orientation, and pin distribution information corresponding to each component are directly extracted, and the extracted information is quickly validated for validity. After confirming that the field content conforms to preset specifications, information integration is completed, and the position coordinates, placement orientation, and pin distribution information of each component are output. This method of directional scanning reduces the processing of invalid data, has high parsing efficiency, is suitable for rapid parsing scenarios of large-scale reference circuit board baseline data, improves the efficiency of data preprocessing in the early stages of placement and routing migration, and meets the need for rapid startup of subsequent processes.

[0054] Step A12: Based on the position coordinates, placement direction, and pin distribution information of each component, calculate the relative spacing, orientation relationship, and pin association information between each component.

[0055] In this embodiment, relative spacing refers to the spatial distance between any two components. Orientation relationship refers to the orientation correspondence between any two components. Pin association information refers to the logical connection correspondence between pins of different components.

[0056] As an optional implementation, based on the position coordinates, placement orientation, and pin distribution information of each component, a unified coordinate reference system is first established, and the position coordinates of all components are transformed to this reference system to achieve coordinate normalization. Then, all pairwise combinations of components are traversed, and the relative spacing between components is calculated based on the normalized position coordinates. The orientation parameters of the placement orientation are used to determine the directional relationships between components, and the pin function identifiers in the pin distribution information are used to match the corresponding connection logic between the pins of different components. Subsequently, the calculated relative spacing, directional relationships, and pin association information are integrated, and the consistency and rationality of the information are verified. Logically contradictory associations are corrected, and the final relative spacing, directional relationships, and pin association information between each component are output. This method calculates all component combinations, and the output information has high completeness and accuracy, fully supporting the extraction of subsequent relative layout relationships and providing a detailed data foundation for subsequent layout migration.

[0057] As an alternative implementation, based on the position coordinates, placement orientation, and pin distribution information of each component, all components are first grouped according to their functional attributes, forming different functional component groups. Then, the relative spacing, orientation relationship, and pin association information between components within the same functional component group are calculated. Simultaneously, the position coordinates, placement orientation, and pin distribution information of the core components between different functional component groups are extracted, and the relative spacing, orientation relationship, and pin association information of the core components between groups are calculated. Subsequently, the calculation results of all components within a group and the core components between groups are integrated to form a complete information set, outputting the final relative spacing, orientation relationship, and pin association information between each component. This method significantly reduces the number of component combinations traversed through group calculation, reducing computational load and improving computational efficiency, making it suitable for information calculation scenarios involving large-scale components. The disadvantage is that the information of non-core components between groups is not fully calculated, and the output information granularity is slightly lower than that of the full-scale calculation method. The corresponding effect is that it can significantly shorten the overall information calculation time and quickly output component association information that meets the basic requirements of layout migration.

[0058] Step A13: Associate and integrate the relative spacing, orientation relationship and pin association information between the components to establish a corresponding mapping relationship, and eliminate invalid associations to obtain the relative layout relationship.

[0059] In this embodiment, the mapping relationship is a set of corresponding relationships formed by associating and binding the three elements. Invalid associations are redundant associations that have no practical design significance.

[0060] As an optional implementation, a one-to-one mapping entry for relative spacing, orientation, and pin association information is first established for each group of components. Then, a preset valid association judgment rule is invoked to verify the logical matching degree of the three elements in each mapping entry, filtering out invalid association entries that have no pin connection logic but contain spacing and orientation records. Consistency checks are performed on the filtered valid mapping entries to correct abnormal entries with mismatched spacing and orientation relationships. Finally, all valid mapping entries are integrated to form a complete information set, and the relative layout relationship is output. This method establishes accurate mapping relationships, thoroughly eliminates invalid associations, and outputs a high degree of completeness and reliability in the relative layout relationship. The relative layout relationship accurately reflects the true layout association between components, providing a high-fidelity reference for subsequent layout migration.

[0061] For example, in a circuit board layout and routing scenario, in response to the layout and routing migration command, the KiCad format reference data parsing model is invoked to parse the reference data of a consumer electronics reference circuit board containing 20 components. This yields the position coordinates (50, 60), placement direction 0°, and 16 pins arranged in two parallel rows for the core chip U1; the position coordinates (55, 65), placement direction 0°, and 2 pins symmetrically distributed for the capacitor C1; and the position coordinates (50, 70), placement direction 90°, and 2 pins vertically distributed for the resistor R1. Based on this information, the component association information calculation model is invoked to calculate that the relative distance between U1 and C1 is 7.07mm and their orientation is 45°; the relative distance between U1 and R1 is 10mm and their orientation is 90°; and there are corresponding pin association information for pin 3 of U1 and pin 1 of C1, and pin 5 of U1 and pin 2 of R1. The relative spacing, orientation, and pin association information are mapped one-to-one according to the component combination. The association entries of U1 and diode D5 with no connection are removed by the invalid association filtering rule, resulting in a relative layout relationship containing 18 groups of valid component combination associations.

[0062] By parsing reference board data, calculating component association information, and integrating and eliminating invalid associations, the problem of low efficiency and information redundancy in traditional relative layout relationship extraction is solved, improving the accuracy and efficiency of relative layout relationship extraction and providing reliable data support for subsequent layout migration.

[0063] Based on any of the above embodiments, in Embodiment 3 of this application, step S20 includes steps B11 to B14: Step B11: Based on the board outline information, obstacle constraint information and electrical netlist data of the circuit board to be printed, delineate the feasible area for placing the components of the circuit board to be printed, and determine the constraint parameter data within the feasible area for placing the components.

[0064] In this embodiment, the constraint parameter data is information on the spacing and orientation restrictions for placing components within the feasible area.

[0065] As an optional implementation, based on the board outline information, obstacle constraint information, and electrical netlist data of the printed circuit board to be manufactured, the board outline information is first analyzed to determine the maximum physical placement range of the printed circuit board. Then, the obstacle constraint information is region-marked to determine the location and range of areas to be avoided. Next, combined with the connection requirements of component pins in the electrical netlist data, areas outside the board outline and obstacle areas are excluded, delineating the feasible area for component placement on the printed circuit board. Subsequently, the minimum spacing requirements, orientation restrictions, and pin extension direction restrictions of components within the feasible area are extracted to form preliminary constraint parameter data. Logical verification is performed on this preliminary constraint parameter data, and the final constraint parameter data is determined after confirming that there are no conflicts among the parameters. This method accurately delineates the feasible area, provides comprehensive constraint parameter data without logical contradictions, and can provide a strict and reliable basis for subsequent component layout.

[0066] Step B12: Based on the feasible region, the constraint parameter data, and the relative layout relationship between the components, establish a mapping coordinate system between the feasible region of the circuit board to be printed and the layout region of the reference printed circuit board.

[0067] In this embodiment, the reference printed circuit board layout area is the area of ​​component arrangement on the reference board, and the mapping coordinate system is a coordinate system that establishes the spatial correspondence between the two.

[0068] As an optional implementation, based on the feasible region and the constraint parameter data, and combined with the relative layout relationships between the components, the boundary features and core component position features of the reference printed circuit board layout region are first extracted. Simultaneously, the boundary features of the feasible region of the printed circuit board to be printed is extracted, along with the positional restriction features corresponding to the constraint parameters. The boundary features of the two types of regions are then matched point-to-point. Using the relative layout relationship of the core components as a reference, the reference point and scaling ratio for coordinate mapping are determined, establishing a preliminary mapping coordinate system. The mapping accuracy is then verified through the relative layout relationship of each component, correcting the reference point deviation and scaling ratio error, ultimately determining a stable mapping coordinate system. This method provides high accuracy in mapping the coordinate system, achieving precise correspondence between the spatial positions of the two types of regions and ensuring the consistency of the relative positions of the components after migration.

[0069] As an alternative implementation, the reference printed circuit board layout area is first divided into several functional sub-regions based on relative layout relationships. Simultaneously, the feasible area of ​​the circuit board to be printed is divided into corresponding functional adaptation sub-regions according to constraint parameter data. Representative components are selected as local reference points within each functional sub-region to establish local mapping relationships between sub-regions. Then, the local mapping relationships of all sub-regions are integrated, and a unified coordinate reference is formed to create a global mapping coordinate system. Finally, the mapping rationality at the sub-region junctions is verified using constraint parameter data, junction deviations are corrected, and the final mapping coordinate system is determined. This method simplifies the mapping establishment process through sub-region division, reduces computational load, improves construction efficiency, and is suitable for large-scale component layout scenarios.

[0070] Step B13: Based on the mapping coordinate system, the component layout structure of the reference printed circuit board is mapped to the feasible area of ​​the circuit board to be printed, while keeping the relative spacing, orientation and pin association between each component unchanged, to obtain the preliminary component migration result.

[0071] In this embodiment, the preliminary component migration result is an intermediate layout state formed after component layout mapping that has not undergone final compliance verification.

[0072] As an optional implementation, the component layout structure of the reference printed circuit board is mapped to the feasible area of ​​the circuit board to be printed, based on the mapped coordinate system, while maintaining the relative spacing, orientation, and pin relationships between components, thus obtaining preliminary component migration results. First, the coordinate transformation formula and orientation mapping rules for each component on the reference board are determined based on the mapped coordinate system. Then, the position coordinates of each component on the reference board are converted to coordinates within the feasible area of ​​the circuit board to be printed, simultaneously locking the component placement orientation and pin relationships. Next, the relative spacing of the converted components is checked to ensure it matches the reference board, and the orientation and pin relationships are verified to be without deviation. All verified component coordinates, orientations, and relationships are integrated to form a complete preliminary component migration result. This method accurately restores the layout details of the reference board components, ensures no deviation in the relative relationships of the migrated components, and achieves a high degree of consistency between the preliminary component migration results and the reference board layout, providing a precise intermediate data foundation for subsequent compliance verification.

[0073] Step B14: Perform compliance verification on the preliminary component migration results, correct issues such as components exceeding the feasible area, conflicting with obstacle areas, and violating component spacing requirements, and output the component layout results.

[0074] In this embodiment, compliance verification is a process of checking whether the component layout conforms to the feasible area boundaries, obstacle avoidance, and component spacing requirements. The component spacing requirement is the minimum distance specification that must be maintained between components.

[0075] As an optional implementation, each component in the preliminary component migration results is first traversed, and each component's position is checked individually to see if it exceeds the feasible area boundary, if it overlaps with obstacle areas, and if the spacing between components meets preset requirements. Various violations and their corresponding component identifiers are recorded. Specific correction strategies are developed for different violation types: components exceeding the boundary are shifted, conflicting components are repositioned or fine-tuned, and the arrangement order of components with spacing violations is optimized. After correction, all components undergo a full compliance review again. Once no violations are confirmed, the components are integrated to form the component layout result. This method provides comprehensive verification coverage and precise correction, thoroughly resolving various compliance issues. It boasts extremely high compliance and reliability, providing a stable layout foundation for subsequent wiring migration.

[0076] For example, in the scenario of circuit board layout and routing, based on the board frame information (size 120mm×80mm), obstacle constraint information (20mm×15mm heat dissipation area, coordinate range 30-50mm, 40-55mm), and electrical netlist data (containing 50 sets of component pin connection relationships), the region delineation model is called to delineate the feasible area for component placement on the circuit board to be printed as the entire area within the board frame excluding the heat dissipation area, and to determine constraint parameter data such as minimum component spacing of 2mm, core component orientation of 0°, and non-core component orientation deviation not exceeding 45°. Based on the feasible area and the constraint parameter data, combined with the relative layout relationship between each component (the relative spacing between the core chip and the surrounding capacitor is 5mm, and the orientation is 0°), the coordinate system construction model is called to establish a 1:1.2 scaling mapping coordinate system between the feasible area of ​​the circuit board to be printed and the layout area of ​​the reference circuit board (100mm×60mm), with the reference board reference point (50, 30) corresponding to the reference point of the circuit board to be printed (60, 40). Based on the mapping coordinate system, the layout of 60 components on the reference printed circuit board is mapped to the feasible area of ​​the circuit board to be printed, keeping the relative spacing, orientation, and pin relationships between the components unchanged, thus obtaining preliminary component migration results. A compliance verification model is then used to verify the preliminary component migration results. It is found that capacitor C2 exceeds the feasible area by 2mm and resistor R15 conflicts with the heat dissipation area. C2 is shifted by 2mm, and the orientation of R15 is adjusted to 90°, correcting the three sets of component arrangements that violated the spacing requirements. The final component layout result is then output.

[0077] By defining feasible areas, establishing a mapping coordinate system, migrating layouts, and verifying compliance, the problems of large positioning deviations and poor compliance in traditional circuit board component layout migration have been solved, thus improving the accuracy and efficiency of layout migration.

[0078] Based on any of the above embodiments, in Embodiment 4 of this application, referring to Figure 2 , Figure 2This is a flowchart illustrating the fourth embodiment of the automatic placement and routing migration method for printed circuit boards according to this application. Step B14 includes steps C11 to C13: Step C11: Based on the preliminary component migration results, check the component position violations one by one by comparing the feasible area boundary, obstacle area range and component spacing design rules of the printed circuit board to be printed, and obtain a list of component layout violations including violation type, violation component position and corresponding rule requirements.

[0079] In this embodiment, the obstacle area range refers to the location and size of the area on the printed circuit board that needs to be avoided. The component spacing design rules are design standards that specify the minimum distance between components on the printed circuit board. Violations include components exceeding the boundaries of the feasible area, conflicting with obstacle areas, or violating component spacing requirements. The component layout violation list is a collection of information recording the violation type, the location of the violating component, and the corresponding rule requirements.

[0080] As an optional implementation, the components in the initial component migration results are first divided into several functional component groups based on their functional attributes. Then, using each functional component group as a unit, the overall area of ​​each group is checked to see if it exceeds the feasible area boundary or if there is a large-scale conflict with the obstacle area. Subsequently, a comprehensive spacing rule check is performed on core components within each group, while a sampling method is used to check the spacing of non-core components. Violations identified are categorized and recorded, including the violation type, the location information of the involved components, and the corresponding rule requirements. Finally, the violation records at the group and component levels are integrated to form a list of component layout violations. This method significantly reduces computational load and improves the overall efficiency of violation point checking through grouping and sampling checks. It is suitable for layout checks of large-scale components and shortens the initial process time for compliance verification.

[0081] As an alternative implementation method, the position coordinates and distribution range information of all components in the preliminary component migration results are first extracted. Then, the boundary parameters of the feasible area, the position parameters of the obstacle area, and the standard parameters of the component spacing design rules are retrieved respectively. Each component is checked sequentially according to its component number, examining these three aspects to determine whether it exceeds the feasible area boundary, whether it overlaps with the obstacle area, and whether its spacing with surrounding components does not meet the rule requirements. For components with violations, the violation type, specific location information, and corresponding rule requirement are recorded immediately. Finally, all recorded information is integrated to form a complete list of component layout violations. This method provides comprehensive coverage, highly accurate and complete record of violation information, and can fully reflect various problems in the preliminary migration results, providing a detailed and reliable basis for subsequent precise corrections.

[0082] Step C12: According to the list of component layout violations and component layout rules, perform position translation adjustment for components that exceed the feasible area, plan avoidance paths for components that conflict with obstacle areas, optimize the spacing configuration for components that violate spacing requirements, and output the corrected intermediate result of component layout.

[0083] In this embodiment, component layout rules are design standards that regulate the placement, spacing, and avoidance requirements of components. Position translation adjustment is the operation of moving components that are outside the feasible area to a compliant position. Obstacle area conflict refers to the problem of spatial overlap between component positions and areas requiring avoidance. Avoidance path planning is the operation of designing compliant placement paths for conflicting components. Spacing requirements are the minimum distance specifications that must be maintained between components. Spacing optimization configuration is the operation of adjusting component positions to meet spacing requirements. The intermediate component layout result is a component arrangement state that has been corrected for violations but has not yet been finalized.

[0084] As an optional implementation method, based on the list of component layout violations and the component layout rules, the list of violations is first categorized by violation type, distinguishing between three types of problems: exceeding the feasible area, conflicting with obstacle areas, and spacing violations. Then, a correction plan is developed for each violating component. For components exceeding the feasible area, the minimum translation distance is calculated and the position is adjusted. For components conflicting with obstacle areas, an avoidance path is planned using surrounding empty areas, and the optimal compliant position is selected for adjustment. For components violating spacing requirements, the spacing is optimized by fine-tuning the placement orientation or position coordinates. After each component correction is completed, it is immediately verified against the rules. Only after confirmation of accuracy is the next component processed. Finally, all corrected component position information is integrated, and the corrected component layout intermediate result is output. This method provides precise correction for each component, ensuring that the relative layout relationship of components is not disrupted to the greatest extent. The corrected intermediate result has extremely high compliance, providing high-quality intermediate data support for the subsequent output of the final component layout result.

[0085] Step C13: Perform a comprehensive compliance review of the revised intermediate component layout results again based on all design rules until it is confirmed that there are no violations, and then generate the component layout results.

[0086] In this embodiment, the complete design rules are a set of specifications covering all component placement requirements, including feasible area boundaries of the printed circuit board, obstacle avoidance, component spacing standards, and pin connection logic. The comprehensive compliance review is a verification process that involves thoroughly checking the intermediate results against all the design rules.

[0087] As an optional implementation method, firstly, all clauses of the entire design rules are retrieved, forming a complete verification dimension covering location compliance, spacing compliance, and obstacle avoidance compliance. Then, each component in the intermediate results is checked sequentially according to its component number, verifying whether its position conforms to the feasible area requirements, whether its spacing from surrounding components meets standards, and whether it avoids obstacle areas. Any violations found during the review are immediately corrected. After correction, the full-element review process is restarted, repeating the above operations until all components meet all design rule requirements, finally generating the component layout result. This method reviews all rule clauses and component elements, thoroughly eliminating all explicit and implicit violations, resulting in highly compliant and reliable output results.

[0088] For example, in the scenario of circuit board layout and routing, based on the preliminary component migration results (including the position coordinates and distribution information of 50 components), and referring to the feasible area boundary (120mm×80mm rectangular range), obstacle area range (20mm×20mm heat dissipation area with coordinates 20-40mm, 30-50mm), and component spacing design rules (minimum spacing 2mm), the violation detection model is called to check for violations in component positions item by item, resulting in a list of component layout violations including violation type (exceeding boundary, obstacle conflict, spacing violation), violation component position (capacitor C3 coordinates 122, 45, resistor R20 coordinates 35, 40, inductor L5 spacing 1mm with surrounding components), and corresponding rule requirements. According to the list and component layout rules, C3 is shifted 3mm to the left to complete the position translation adjustment, R20 is moved to the right to avoid a path to coordinates 45, 40, and L5 is finely adjusted to achieve a spacing of 2.5mm to complete the spacing optimization configuration, outputting the corrected intermediate component layout result. The compliance review model is invoked to conduct a comprehensive compliance review of the intermediate results based on all design rules. The first review finds no new violations. After confirming that there are no violations, the component layout result is generated.

[0089] By conducting thorough investigations, precise corrections, and comprehensive re-inspections, the issues of omissions and incomplete corrections in component layout migration violations were resolved, thereby improving the compliance and accuracy of the component layout results.

[0090] Based on any of the above embodiments, in Embodiment 5 of this application, step S30 includes steps D11 to D13: Step D11: Extract the component pin correspondence, circuit connection logic, and key node distribution characteristics contained in the component layout results and the reference circuit board baseline data, and generate a set of wiring association information.

[0091] In this embodiment, the component pin correspondence refers to the connection pairing information between different component pins. The circuit connection logic refers to the conduction sequence and association method of the circuit board circuits. The key node distribution characteristics are the location and distribution attributes of nodes that play a core role in the routing. The routing association information set is a set of associated data for subsequent routing migration formed by associating and integrating the above three types of information.

[0092] As an optional implementation, the component layout results and the reference circuit board baseline data contain the component pin correspondence, circuit connection logic, and key node distribution characteristics. First, a full-dimensional scan and identification of the three types of information in the two types of data is performed, marking the associated component identifiers of each set of pin correspondences, the start and end points and conduction logic of each circuit, and the position attributes of each key node. Then, a one-to-one correspondence mapping relationship of the same type of information between the two types of data is established. Information deviations are corrected through logic consistency verification. Finally, the verified information is classified and integrated according to component combinations to generate a wiring association information set. The advantage of this implementation is that the extracted information is highly complete and the generated set can accurately match the core wiring features of the two types of data. The disadvantage is that the full-dimensional scanning and verification steps are cumbersome, the computational load is large, and the processing time is relatively long. The corresponding effect is that the output wiring association information set can provide comprehensive and accurate data support for the construction of subsequent wiring path representations, ensuring the consistency of wiring migration.

[0093] As an alternative implementation, the component layout results and the reference circuit board baseline data are first divided into several functional modules based on the component functional attributes. Then, for each functional module, the core pin correspondences, main circuit connection logic, and core key node distribution characteristics are extracted, discarding non-core details. Next, an information association mapping relationship is established between modules, and the core information of each module is integrated to form a module-level routing association subset. Finally, all subsets are aggregated and associated to generate a routing association information set. This method reduces invalid information processing through functional module division, significantly improves information extraction and integration efficiency, adapts to large-scale data processing scenarios, and shortens the overall time spent on pre-routing data processing.

[0094] Step D12: Extract the specific geometric coordinate attributes of the wiring path from the wiring association information set, and convert the wiring information of the reference circuit board and the circuit board to be printed into a topology structure with component nodes, pad nodes and key transition nodes as the core to obtain wiring topology structure data.

[0095] In this embodiment, the specific geometric coordinate attributes of the routing path are coordinate information describing the spatial location of the routing path. The routing information of the reference circuit board and the circuit board to be printed are the circuit connection related data corresponding to the two circuit boards respectively. Component nodes, pad nodes, and critical transition nodes are the core node types that play a connecting or transit role in routing. The topology is an abstract structure that represents the connection relationship between nodes. The routing topology data is the transformed abstract routing data with the connection relationship of the core nodes as the core.

[0096] As an optional implementation, this method first traverses all routing information in the routing association information set, identifying and extracting component nodes, pad nodes, and key transition nodes, while removing geometric coordinate data representing specific spatial locations. Then, based on the line connection logic in the routing association information, it establishes connection relationships between the three types of nodes, constructing complete routing topology frameworks for both the reference circuit board and the circuit board to be printed. Next, it verifies the consistency and completeness of node connection relationships in the two topology frameworks, corrects node association deviations, and finally integrates the two topology frameworks to obtain the routing topology structure data. This method provides accurate topology construction, fully preserving the core routing connection logic, and offering a high-fidelity abstract data foundation for subsequent routing path matching.

[0097] Step D13: Based on node encoding rules and connection relationship description standards, the cabling topology data is standardized and represented to obtain multiple cabling path representations.

[0098] In this embodiment, the node coding rule is a specification for assigning unique identifiers to component nodes, pad nodes, and critical transition nodes in the wiring topology. The connection relationship description standard is a unified guideline for defining the association attributes between nodes, such as connection order and connection type.

[0099] As an optional implementation, a unified coding rule covering all node types is first established, assigning a unique and identifiable code to each component node, pad node, and critical transition node. Then, based on the connection relationship description standard, the connection order, connection type, and associated attributes between nodes are clarified. Each path relationship in the routing topology is described item by item according to the coding order, and the description content is logically consistent, correcting issues of code duplication or contradictory connection relationship descriptions. Finally, each path that passes the verification is encapsulated as an independent routing path representation, and these are integrated to form multiple routing path representations. This method provides high standardization and accuracy in characterization results, with clear logical boundaries for each routing path representation, completely and accurately reflecting the core characteristics of the routing topology, providing high-quality data support for subsequent path matching and migration.

[0100] As an alternative implementation, the cabling topology data is first divided into several functional subsets based on the functional attributes corresponding to the cabling. For each subset, appropriate node coding rules and simplified connection relationship description standards are defined. Then, node coding allocation and connection relationship descriptions are completed in batches for each functional subset, focusing on retaining the association features of core paths within the subset while discarding non-critical detailed connection information. Next, the completeness of the representation results within each functional subset is verified, and the compatibility of node coding between subsets is adjusted to avoid coding conflicts. Finally, the representation results of each functional subset are split into independent cabling path representations, resulting in multiple cabling path representations. This method achieves batch processing through functional subset division, reduces computational steps, improves representation efficiency, and is suitable for processing large-scale cabling topology data.

[0101] For example, in the scenario of circuit board layout and routing, the component layout results (including the final arrangement of 60 components) are extracted from the reference circuit board baseline data, along with the component pin correspondence (such as 35 sets of correspondences, including the 4th pin of core chip U1 and the 1st pin of capacitor C1, the 8th pin of U1 and the 2nd pin of resistor R3), the line connection logic (main line conduction sequence, branch line association method), and the key node distribution characteristics (distribution attributes of 20 power nodes and 10 signal relay nodes). A routing information extraction model is then used to generate a routing association information set. The specific geometric coordinate attributes of the routing paths in the set are stripped (such as the reference board line coordinates X1-Y1 to Xn-Yn, and the new board line coordinates A1-B1 to An-Bn). A topology transformation model is then used to convert the routing information of both circuit boards into a topology structure centered on component nodes, pad nodes, and key transition nodes, resulting in routing topology data. Based on the node coding rules of "functional module and serial number" (such as power module node P01, signal module node S02) and the connection relationship description standard (clearly defining the connection order and type), the data is represented by a normalized representation model to obtain 25 wiring path representations.

[0102] By extracting associated cabling information, transforming the topology, and standardizing the representation, the problems of messy cabling information and unclear topological features are solved, improving the standardization and accuracy of cabling path representation and providing reliable data support for subsequent cabling migration matching.

[0103] Based on any of the above embodiments, in Embodiment Six of this application, step S40 includes steps E11 to E13: Step E11: Based on the multiple wiring path representations, establish wiring matching pair data between the wiring path representation of the reference circuit board and the wiring path representation of the circuit board to be printed.

[0104] In this embodiment, the wiring matching pair data is a set of matching data formed after establishing the correspondence between the reference board and the wiring path representation of the printed circuit board to be printed.

[0105] As an optional implementation, the core features of each routing path representation are first extracted, including node encoding sequences, connection relationship types, and path functional attributes. Then, in descending order of feature similarity, the routing path representations of the reference circuit board and the circuit board to be printed are compared path by path, ensuring a unique match between each reference board routing path representation and the corresponding circuit board routing path representation. Next, a deep validation of the feature consistency of each matching pair is performed, correcting matching relationships with significant feature deviations. Finally, all validated matching pairs are integrated to establish routing matching pair data between the routing path representations of the reference circuit board and the circuit board to be printed. This method offers high matching accuracy, achieving a precise one-to-one correspondence between paths, and strong reliability of the matching pair data.

[0106] Step E12: Verify the consistency of node mapping, connection priority, and path direction logic between the data of the wiring matching pairs. Correct the mismatched node correspondence and connection logic according to the wiring matching rules to obtain the wiring path matching relationship.

[0107] In this embodiment, node mapping consistency refers to the degree of uniformity between the corresponding node identifiers and associations in a matching pair. Connection priority consistency refers to the degree of alignment between the path connection order and importance in a matching pair. Path direction logic consistency refers to the degree of consistency between the path connection trend and the association logic in a matching pair. Routing matching rules are the criteria for standardizing the verification and correction operations of routing path matching. Mismatched node correspondences and connection logic are node associations and path connections that do not meet consistency requirements. Routing path matching relationships are the precise path correspondences formed after consistency verification and correction.

[0108] As an optional implementation method, mismatched node correspondences and connection logics are corrected according to cabling matching rules. First, a comprehensive verification index system covering three types of consistency—node mapping consistency, connection priority consistency, and path routing logic consistency—is established. Each cabling matching pair is checked item by item, recording mismatches such as misaligned node mappings, reversed connection priorities, and contradictory path routing logic. Specific correction strategies are developed for different types of mismatches, adjusting node correspondences, resetting connection priority ordering, and optimizing path routing logic. After each correction is completed, a consistency re-check is performed; only after confirming full compliance are the next pair processed. Finally, all corrected matching pairs are integrated to obtain the cabling path matching relationship. This method offers comprehensive verification coverage and precise correction, completely eliminating various mismatches. The output matching relationship has extremely high reliability, providing accurate and stable data support for the generation of subsequent cabling migration guidance information.

[0109] Step E13: Extract the node mapping relationship, path priority sorting, cabling inflection point reference position and avoidance constraint prompts corresponding to the path migration in the cabling path matching relationship, and integrate them to generate the cabling migration guidance information that can directly guide the cabling migration operation.

[0110] In this embodiment, the node mapping relationship refers to the associated information of corresponding nodes in the matching path. The path priority ranking is the order in which the matching paths are divided according to their importance. The wiring inflection point reference position is the reference orientation information of the inflection points in the matching path. The obstacle avoidance constraint prompts are relevant prompts for areas where the matching path needs to avoid obstacles.

[0111] As an optional implementation, the cabling path matching relationships are first analyzed in all dimensions. For each matching path, the node mapping relationship, path priority ranking, cabling inflection point reference position, and avoidance constraint prompts are extracted, and the path identifier to which the information belongs is marked. Then, the extracted information undergoes logical consistency verification to correct issues such as misaligned node mappings, disordered priority ranking, contradictory inflection point positions, and missing avoidance prompts. The verified information is then categorized and integrated according to the path identifiers to form structured information entries. Finally, all entries are summarized to generate cabling migration guidance information that can directly guide cabling migration operations. This method extracts comprehensive and accurate information, and the generated guidance information is highly instructive, accurately covering the migration requirements of all matching paths, providing a comprehensive and reliable operational basis for subsequent cabling migrations.

[0112] As an alternative implementation, the cabling path matching relationship is first divided into several functional path groups based on the path's functional attributes. Within each group, the node mapping relationship, path priority ranking, cabling inflection point reference positions, and avoidance constraint prompts for the core paths are extracted, simplifying the details of inflection point positions and avoidance prompts for non-core paths. Then, the extracted information within each group is validated for correlation to ensure no conflicts between node mapping and priority ranking. Next, the information is integrated by functional path group to form group-level cabling migration guidance subsets. Finally, all subsets are summarized and supplemented with general rules for global path migration, generating the cabling migration guidance information that can directly guide cabling migration operations. This method simplifies the extraction process through grouping, improves information integration efficiency, adapts to large-scale path matching relationship processing scenarios, and shortens the information preparation time in the early stages of cabling migration.

[0113] For example, in a circuit board layout and routing scenario, based on 25 routing path representations (12 for the reference board and 13 for the new board), a routing matching model is invoked to extract core features such as node encoding sequences and functional attributes of each path, establishing 22 sets of routing matching pairs between the routing path representations of the reference circuit board (e.g., P1, P2) and the routing path representations of the circuit board to be printed (e.g., P11, P12). A consistency verification model is invoked to verify the consistency of node mapping, connection priority, and path direction logic among the routing matching pairs. It is found that two matching pairs have misaligned node mappings and one pair has reversed connection priorities. The node correspondence is adjusted and the connection priority sorting is reset according to the routing matching rules to obtain the routing path matching relationship. Extract the node mapping relationship corresponding to the path migration in the matching relationship (such as the reference board node P01 corresponding to the new board node N01), path priority sorting (power path priority 1, signal path priority 2), routing inflection point reference position (such as the reference orientation at the corner), and avoidance constraint prompts (avoid the 20mm×20mm heat dissipation area of ​​the new board), and call the guidance information integration model to integrate and generate the routing migration guidance information that can directly guide the routing migration operation.

[0114] By establishing matching, verification and correction, and information integration, the problems of inaccurate matching and missing guidance information in cabling migration have been solved, improving the accuracy and efficiency of cabling migration and ensuring the compliance of cabling migration.

[0115] Based on any of the above embodiments, in Embodiment Seven of this application, step S50 includes steps F11 to F13: Step F11: Analyze the node mapping relationship, path priority sorting and avoidance constraint prompts in the routing migration guidance information and the component layout results, and plan the routing migration execution scheme of the printed circuit board to be printed.

[0116] In this embodiment, the node mapping relationship refers to the corresponding association information between the routing nodes of the reference board and the printed circuit board to be printed. Path priority ranking is the order of path importance that the routing operation must follow. Avoidance constraint prompts are the relevant requirements for avoiding obstacle areas during the routing process. The routing migration execution plan is a specific operational plan for the routing migration of the printed circuit board to be printed based on the above information and can be directly implemented.

[0117] As an optional implementation, the wiring migration guidance information and the component layout results are first subjected to full-dimensional cross-analysis to extract the component location information corresponding to each node, the priority level of each path, and the corresponding avoidance area. Then, according to the path priority from high to low, detailed wiring start points, direction nodes, inflection point positions, and avoidance and detour schemes are planned for each path, while simultaneously verifying the spatial compatibility between the path direction and the component layout, and correcting any conflicts between the path and component positions. Finally, the operation schemes for all paths are sorted and integrated according to priority to form a clear wiring migration execution scheme. This method has high scheme planning accuracy, can maximize the compliance and rationality of wiring migration, and the output wiring migration execution scheme is detailed, highly operable, and can guide high-precision wiring migration operations.

[0118] As an alternative implementation, all paths are first divided into several functional path groups based on their functional attributes. The core node mapping relationships, priority levels, and global obstacle avoidance constraints of each path group are extracted. Then, an overall routing migration strategy is formulated for each path group, determining the routing sequence within the group, the usage rules for shared nodes, and the connection methods between paths in different groups. Priority is given to ensuring the planning accuracy of core functional path groups, while standardized routing schemes are used for non-core path groups to simplify the planning process. Finally, the strategies of each group are integrated and global operation specifications are supplemented to form a routing migration execution plan. This method significantly reduces computational steps through group planning, improves the efficiency of plan formulation, adapts to large-scale routing migration scenarios, and can quickly output routing migration execution plans that meet production needs, shortening the pre-routing plan preparation cycle.

[0119] Step F12: Based on the routing migration execution scheme, the routing paths are sequentially migrated and drawn between the component pins and pad nodes corresponding to the component layout results, according to the path priority, and obstacle areas are avoided. The preliminary routing migration results are then output.

[0120] In this embodiment, component pins are the conductive connection terminals of components. Pad nodes are the metal areas on the circuit board where component pins are soldered. Routing paths are the traces connecting component pins and pad nodes. Obstacle areas are areas that routing must avoid. The preliminary routing migration result is an intermediate routing state after the routing drawing is completed according to the plan, but before final compliance verification.

[0121] As an optional implementation method, the path priority ranking and avoidance constraints in the routing migration execution plan are first analyzed. Migration drawing is then performed path by path in descending order of priority. For each path, the corresponding pin and pad node connection endpoints are determined, the path direction is planned, and obstacle areas are avoided in real time. During the drawing process, the node connection order and direction parameters of the path are recorded simultaneously. After completing the drawing of one path, it is immediately checked to ensure compliance with the plan requirements before continuing to the next path. Finally, all drawn path information is integrated to output the preliminary routing migration results. This method offers high path drawing accuracy and can ensure the compliance and conflict-free nature of each path to the greatest extent. Its disadvantages are that the step of drawing each path individually is cumbersome, the computational load is large, and the overall processing time is relatively long. However, it provides precise path details, strong compatibility with component placement, and high-quality intermediate data for subsequent compliance verification.

[0122] Step F13: Perform electrical connection integrity verification and comprehensive compliance check of design rules on the preliminary wiring migration results, correct wiring disconnections, line short circuits and non-compliant spacing, and generate the layout wiring results.

[0123] In this embodiment, electrical connection integrity verification is a process of checking whether there are any interruptions or unexpected connections in the wiring path. Comprehensive design rule compliance check verifies whether the wiring path spacing, routing, etc., conform to preset design specifications. A wiring break occurs when the two ends of a line fail to achieve effective continuity. A short circuit occurs when different electrical network lines unexpectedly connect. Non-compliant spacing occurs when the distance between wiring paths does not meet design specification requirements.

[0124] As an optional implementation method, the verification work is first divided into two dimensions: electrical connection and design rules. The continuity of the preliminary wiring migration results is checked path by path to rule out wiring breaks, and the isolation status of different network lines is checked to rule out short circuits. Then, the wiring spacing and path direction of the preliminary wiring migration results are checked path by path to verify whether they meet the design rules requirements, and all violations and their corresponding path identifiers are recorded. Specific correction strategies are developed for different problem types: disconnected lines are supplemented with conductive paths, short-circuit lines are increased with isolation spacing, and non-compliant spacing is adjusted with path direction. After correction, a full-dimensional re-inspection is conducted again. Once it is confirmed that there are no problems, the layout and wiring information are integrated to generate the aforementioned layout and wiring results. This method provides comprehensive verification coverage, high correction accuracy, and can thoroughly solve various explicit and implicit problems, directly supporting subsequent circuit board production and processing.

[0125] For example, refer to Figure 3 , Figure 3This is a flowchart of the method in this application. In the scenario of circuit board placement and routing, the board outline information, obstacle constraint information, and electrical netlist data of the circuit board to be printed and the reference circuit board are first obtained as the basic inputs for the entire process. Next, the relative layout relationships between components are extracted from the baseline data of the reference circuit board to provide a reference for subsequent component placement migration. Then, under the constraints of the circuit board to be printed, the component placement migration is completed based on the relative layout relationships of the components on the reference board, and the migrated component placement result is output as the first intermediate result. After that, the routing migration stage begins. Based on the routing information of the reference circuit board and the migrated component layout, a routing path representation is constructed to provide a standardized path model for routing migration. Then, the routing migration is performed based on the routing path representation, and the migrated routing result is generated as the second intermediate result. Finally, a comprehensive compliance verification is performed on the migrated layout and routing result to correct issues such as disconnected routing, short circuits, and non-compliant spacing, and the final layout and routing result is output. The entire process starts from basic data input, and forms a complete closed loop through component placement migration, routing path construction, routing migration execution, and final compliance verification, realizing accurate migration and compliant output of layout and routing from the reference board to the new board.

[0126] By planning and executing wiring migration and verifying and correcting violations, the problems of low efficiency and poor compliance in wiring migration have been solved, and the accuracy and production adaptability of the layout and wiring of the printed circuit board to be printed have been improved.

[0127] Based on any of the above embodiments, in Embodiment Eight of this application, referring to Figure 4 , Figure 4 This is a flowchart illustrating the eighth embodiment of the automatic placement and routing migration method for printed circuit boards according to this application. Following step S50, steps G11-G14 are also included: Step G11: Based on the design requirements, performance indicators, and compliance standards uploaded by the user, check the electrical connection correctness, layout rationality, wiring compliance, and performance compliance of the layout and wiring results, and generate a layout and wiring inspection report.

[0128] In this embodiment, the design requirements, performance indicators, and compliance standards uploaded by the user are a collection of the user-provided circuit board functional requirements, performance parameters, and compliance guidelines. Layout rationality refers to the rationality of component arrangement in terms of space utilization and heat dissipation. Routing compliance refers to the degree to which wiring spacing, routing, etc., conform to design rules. Performance compliance refers to the degree to which the layout and routing meet preset performance indicators. The layout and routing inspection report is a standardized document that integrates the above inspection results.

[0129] As an optional implementation method, a comprehensive inspection index system covering electrical connections, layout, wiring, and performance is first established. Each line and component location in the layout and wiring results is then checked against the indexes to verify whether electrical connections are broken or short-circuited, whether the layout meets space and heat dissipation requirements, whether wiring conforms to spacing and routing rules, and whether performance meets preset targets. All issues are recorded and their severity is indicated. Corresponding improvement suggestions are generated for each issue. Finally, the inspection results and suggestions are integrated according to the indexes to generate a layout and wiring inspection report. This method provides comprehensive coverage, detailed and accurate report content, and a complete basis for subsequent optimization. It fully reflects the compliance and performance level of the results, providing a highly reliable reference for the final verification and production of the circuit board.

[0130] Step G12: Extract key issue information from the layout and routing inspection report, associate it with the original reference data uploaded by the user and the design constraints, sort out the migration parameter correlation factors that caused the problem, and generate feedback data.

[0131] In this embodiment, key issue information refers to the core violations and performance non-compliance issues reflected in the report. The user-uploaded raw reference data is the original input data containing reference board baseline information. Design constraints are the rules and limitations that the placement and routing must follow, set by the user. Migration parameter correlation factors are parameters related to the occurrence of problems during the placement and routing migration process. Feedback data is structured data that integrates problems, correlation factors, and improvement directions, used to optimize subsequent migration processes.

[0132] As an optional implementation, key issue information is extracted from the layout and routing inspection report. First, the core issues in the report are extracted item by item, and the layout or routing module to which the issue belongs is marked. Then, the original reference data and design constraints uploaded by the user are correlated, and a full-dimensional parameter tracing is performed for each issue. The correlation links between parameters such as node mapping deviations, path priority settings, and avoidance constraint adaptation during the migration process and the issues are identified, recording the specific manifestations and degree of impact of parameter deviations. Finally, the issues, related factors, and improvement suggestions are integrated into structured items to generate feedback data. This method provides accurate correlation analysis, clear and detailed feedback data links, and can directly locate the root cause of the problem, effectively improving the quality and efficiency of layout and routing migration.

[0133] As an alternative implementation, key issue information is extracted from the layout and routing inspection report. These key issues are first categorized into core and secondary issues based on their impact. Core issues are associated with core migration parameters from the original reference data, while secondary issues are associated with non-core migration parameters. The main correlation factors between core issues and core parameters are identified, and a commonality-based induction method is used to simplify the correlation analysis for secondary issues. Issues and correlation factors are then summarized into concise structured entries to generate feedback data. This method significantly reduces analysis steps and improves processing efficiency through hierarchical correlation, adapting to the rapid iteration needs of large-scale projects.

[0134] Step G13: Based on the feedback data, analyze the weight coefficients and core parameters related to the problem during the migration process, determine the types and magnitudes of parameters that need to be adjusted, and output the parameter adjustment plan.

[0135] In this embodiment, the weighting coefficients related to the problem during the migration process are quantified values ​​of the degree of influence of different migration parameters on the problem. Core parameters are those that play a crucial role in the migration process. The types of parameters that need adjustment are the categories of migration parameters that need optimization. The adjustment range is the specific range of changes for parameter optimization. The parameter adjustment plan is an executable plan that clarifies the direction and magnitude of parameter optimization.

[0136] As an optional implementation method, this approach first analyzes the weight coefficients and associated core parameters corresponding to each problem in the feedback data, establishing a quantitative evaluation model for the degree of parameter influence. The influence weights of each core parameter are then ranked to identify the key parameters with the highest weight percentages. Next, based on the severity of the problem, the types of parameters requiring adjustment and the specific adjustment ranges are determined. Detailed optimization rules are formulated for each parameter, and the compatibility of the adjusted parameters with the overall migration process is simultaneously verified, correcting any potential chain reactions. Finally, all parameter adjustment rules are integrated into a structured document, outputting the parameter adjustment plan. This method offers high precision in parameter adjustment, minimizing the occurrence of subsequent problems, accurately locating the root cause of issues, providing a reliable optimization basis for the subsequent migration process, and effectively improving the compliance and efficiency of layout and routing migration.

[0137] As an alternative implementation, based on the feedback data, the problem items in the data are first broken down into their root causes, and the parameter links of the corresponding migration stages are associated to extract all potential impact parameters corresponding to each problem. These parameters are then stratified by their impact level, and by tracing the transmission path of parameters in the migration process, the weight coefficients and core parameters directly related to the problem are analyzed. Next, considering the severity and scope of the problem, the types of parameters that need adjustment are determined. For each parameter type, based on the current value of the parameter and the strength of its association with the problem, a corresponding adjustment range is set, and the chain effect of the adjustment range on other related parameters is simultaneously verified to correct any potential conflicts. Finally, the adjustment types, ranges, and verification results of all parameters are integrated into a structured document to output the parameter adjustment plan. This method offers high accuracy in parameter parsing, strong relevance and compatibility of the adjustment plan, and can solve problems at their root, effectively avoiding similar problems in subsequent migrations and improving the quality and stability of layout and routing migration.

[0138] Step G14: According to the parameter adjustment scheme, update the weights and parameters in the migration process, re-optimize the layout and routing of the reference circuit board, and generate the optimized layout and routing result.

[0139] In this embodiment, the weights and parameters during the migration process are key quantitative indicators and configuration items affecting the placement and routing migration effect. Migration optimization is a process of re-executing the migration based on adjusted parameters to correct the original problems. The optimized placement and routing result is a more compliant and better circuit board placement and routing state formed after parameter adjustment and re-migration.

[0140] As an optional implementation, following the parameter adjustment scheme, the weight coefficients and core parameters that need to be updated are first analyzed one by one, and the corresponding original parameters in the migration process are accurately replaced. Then, the layout and routing migration of the reference circuit board is re-executed according to the complete layout migration and routing migration process. During the migration, the parameter adaptability of each step is verified in real time to ensure that the adjusted parameters fully play their optimization role and correct the problems in the original migration. After the migration is completed, a preliminary compliance check is performed on the overall results, and finally, the optimized layout and routing results are generated. This method has accurate parameter updates and highly targeted migration optimization, which can solve the original problems to the greatest extent.

[0141] As an alternative implementation, according to the parameter adjustment scheme, the weights and parameters to be updated are first categorized and integrated based on the functional modules of the layout and routing, and the original parameters in the migration process of the corresponding functional modules are replaced in batches. Then, the layout and routing of the reference circuit board is re-migrated and optimized in batches by functional module, focusing on ensuring the parameter adaptation and migration effect of core functional modules, while non-core modules are simplified using standardized migration logic. After all modules have been migrated, overall connection verification and problem correction are performed, and finally, the optimized layout and routing results are generated. This method significantly improves optimization efficiency through batch updates and batch migrations, has a small computational load, and is suitable for large-scale circuit board migration and optimization scenarios.

[0142] For example, in a circuit board layout and routing scenario, based on the user-uploaded design requirements (signal transmission rate ≥10Gbps), performance indicators, and compliance standards (wiring spacing ≥3mm, avoiding a 20mm×20mm heat dissipation area), a compliance verification model is invoked to check the electrical connection correctness, layout rationality, wiring compliance, and performance compliance of the layout and routing results (including 60 components and 22 lines). Three electrical connection errors, two instances of non-compliant wiring spacing, and one instance of performance non-compliance are identified, generating a layout and routing inspection report. Key issue information is extracted from the report, and the original reference data (reference board baseline data) uploaded by the user is correlated with the design constraints. An issue tracing model is invoked to analyze migration parameter correlation factors such as node mapping deviations and improper path priority weights, generating feedback data. Based on the feedback data, the weight coefficients (e.g., path priority weight 0.6) and core parameters (node ​​mapping threshold) related to the issues during the migration process are analyzed to determine the types and magnitudes of parameters that need adjustment (weight adjusted to 0.8, threshold optimized by 20%), and a parameter adjustment scheme is output. The migration weights and parameters are updated according to the plan. The migration optimization model is called to re-optimize the layout and routing of the reference circuit board, correct the original problems, and generate the optimized layout and routing results.

[0143] By implementing a closed loop of inspection feedback, parameter adjustment, and re-optimization, the problems of inaccurate traceability and insufficient optimization iteration in layout and routing migration have been resolved, thereby improving layout and routing compliance and optimization efficiency.

[0144] Based on any of the above embodiments, in Embodiment Nine of this application, referring to Figure 5 , Figure 5 This is a block diagram of the overall system structure of this application. The automatic placement and routing migration method for printed circuit boards is applied to an automatic placement and routing system for printed circuit boards, which includes an input module, a placement migration module, a routing migration module, and an output module.

[0145] For example, the system uses a serial layout and routing migration process to ensure the reliability of the migration results in terms of engineering feasibility, design consistency, and performance inheritance. The input module is responsible for uniformly receiving and managing the layout data of the reference printed circuit board (PCB), the board outline information of the PCB to be migrated, obstacle constraint information, and electrical netlist data. The layout data of the reference PCB includes the layout position and orientation information of each component, as well as the original routing path information, which is used to extract the layout and routing features in the expert design. The board outline information of the PCB to be migrated includes the external boundary dimensions and shape information of the PCB to be migrated, which is used to limit the feasible area for layout and routing after migration. The obstacle constraint information includes newly added no-route areas, structural obstacles, or non-placeable areas in the PCB to be migrated, which is used to limit the search space for layout and routing. The electrical netlist data describes the electrical connection relationship between the pins of each component in the PCB to ensure that the electrical function remains consistent before and after migration. The input module formats and uniformly manages these data and uses them as input to the layout migration module. As a crucial pre-processing module of the entire system, the layout migration module's output directly determines the feasibility and quality of subsequent routing migration. This module includes a component relative position relationship extraction unit, a layout migration solution unit, and a layout legalization processing unit. The component relative position relationship extraction unit extracts the relative position relationships between multiple components from the layout data of the reference printed circuit board (PCB) to characterize the layout structure features implicit in the expert design. The layout migration solution unit solves a new component layout scheme based on the extracted component relative position relationships under the constraints of the PCB outline and obstacles, ensuring that the migrated layout results satisfy boundary, spacing, and obstacle constraints while maintaining the original layout characteristics as much as possible. The layout legalization processing unit legalizes the initial layout results obtained from the layout migration solution, ensuring that the final layout of all components meets the requirements of the printed circuit board (PCB) design rules, including component spacing, distance from the board outline boundary, and constraints with obstacle areas. The layout migration module ultimately outputs the migrated component layout results as the direct input to the routing migration module.The routing migration module executes based on the output of the layout migration module and cannot run independently. This module includes a routing path representation construction unit, a routing feature matching unit, and a routing migration guidance unit. The routing path representation construction unit is used to convert the layout results of the reference printed circuit board (PCB) and the PCB to be migrated into routing path representation models that are independent of geometric coordinates, thereby eliminating the coordinate inconsistency problem caused by layout changes. The routing feature matching unit is used to establish the correspondence between the routing path representation model of the reference PCB and the routing path representation model of the PCB to be migrated, and to extract the structural features in the original routing. The routing migration guidance unit generates routing migration guidance information based on the routing feature matching results to guide the automatic routing process of the PCB to be migrated, and finally outputs the routing path results after migration. The output module is used to uniformly output the processing results of the layout migration module and the routing migration module. It includes at least the migrated component layout results and the migrated routing path results. These output results can be used for subsequent printed circuit board (PCB) design rule checks, electromagnetic performance simulations, or manufacturing data generation.

[0146] This application provides an automatic placement and routing device for printed circuit boards. The automatic placement and routing device for printed circuit boards includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the automatic placement and routing migration method for printed circuit boards in the above embodiment 1.

[0147] The following is for reference. Figure 5 This document illustrates a structural schematic diagram of an automated PCB placement and routing device suitable for implementing embodiments of this application. The automated PCB placement and routing device in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, automated PCB placement and routing systems, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), electronic design automation routing devices, etc., as well as fixed terminals such as intelligent PCB placement and routing systems, desktop computers, etc. Figure 5The illustrated automated layout and routing equipment for printed circuit boards is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0148] like Figure 5 As shown, the automated placement and routing equipment for printed circuit boards may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the automated placement and routing equipment. The processing unit 1001, the read-only memory 1002, and the RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the automated PCB placement and routing equipment to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows an automated PCB placement and routing equipment with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented alternatively.

[0149] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from read-only memory 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0150] The automatic placement and routing equipment for printed circuit boards provided in this application employs the migration method for automatic placement and routing of printed circuit boards in the above embodiments, which can solve the technical problem of low efficiency in circuit board design. Compared with the prior art, the beneficial effects of the automatic placement and routing equipment for printed circuit boards provided in this application are the same as the beneficial effects of the migration method for automatic placement and routing of printed circuit boards provided in the above embodiments, and other technical features in this automatic placement and routing equipment are the same as those disclosed in the method of the previous embodiment, and will not be repeated here.

[0151] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0152] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0153] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the automatic layout and routing migration method for printed circuit boards in the above embodiments.

[0154] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, radio frequency (RF), etc., or any suitable combination thereof.

[0155] The aforementioned computer-readable storage medium may be included in an automated placement and routing device for printed circuit boards; or it may exist independently and not be assembled into an automated placement and routing device for printed circuit boards.

[0156] The aforementioned computer-readable storage medium carries one or more programs that, when executed by an automatic placement and routing device for printed circuit boards (PCBs), cause the automatic placement and routing device to: respond to a placement and routing migration command; extract relative placement relationships between components from reference PCB baseline data to characterize implicit design layout features; based on the board outline information, obstacle constraint information, and electrical netlist data of the PCB to be printed, migrate the component placement structure of the reference PCB to the feasible area of ​​the PCB to be printed according to the relative placement relationships, to obtain a component placement result; construct multiple routing path representations based on the routing association information between the component placement result and the reference PCB baseline data; match the correspondence between each routing path to generate routing migration guidance information; and perform routing migration on the component placement result according to the routing migration guidance information to obtain a placement and routing result.

[0157] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0158] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0159] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0160] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described automatic placement and routing migration method for printed circuit boards, thereby solving the technical problem of low efficiency in circuit board design. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the automatic placement and routing migration method for printed circuit boards provided in the above embodiments, and will not be repeated here.

[0161] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A migration method for automatic placement and routing of printed circuit boards, characterized in that, The method includes: In response to placement and routing migration instructions, the relative placement relationships between components are extracted from the reference board baseline data to characterize the implicit design layout features; Based on the board outline information, obstacle constraint information and electrical netlist data of the printed circuit board to be printed, the component layout structure of the reference printed circuit board is migrated to the feasible area of ​​the printed circuit board to be printed according to the relative layout relationship to obtain the component layout result. Based on the routing association information between the component layout results and the reference circuit board baseline data, multiple routing path representations are constructed; Match the correspondence between each of the described wiring paths to generate wiring migration guidance information; Based on the routing migration guidance information, routing migration is performed on the component layout result to obtain the layout routing result.

2. The migration method for automatic placement and routing of printed circuit boards as described in claim 1, characterized in that, The step of extracting the relative layout relationships between components from reference board baseline data to characterize implicit design layout features in response to the layout and routing migration command includes: In response to the layout and routing migration command, the reference circuit board reference data is parsed to obtain the position coordinates, placement direction and pin distribution information of each component; Based on the position coordinates, placement direction, and pin distribution information of each component, calculate the relative spacing, orientation relationship, and pin association information between each component. The relative spacing, orientation, and pin association information of each component are associated and integrated to establish a corresponding mapping relationship, and invalid associations are eliminated to obtain the relative layout relationship.

3. The migration method for automatic placement and routing of printed circuit boards as described in claim 1, characterized in that, The step of migrating the component layout structure of a reference printed circuit board to the feasible area of ​​the printed circuit board according to the relative layout relationship based on the board outline information, obstacle constraint information, and electrical netlist data of the printed circuit board to be printed, to obtain the component layout result, includes: Based on the board outline information, obstacle constraint information and electrical netlist data of the printed circuit board to be printed, the feasible area for placing the components of the printed circuit board to be printed is delineated, and the constraint parameter data within the feasible area for placing the components is determined. Based on the feasible region and the constraint parameter data, and combined with the relative layout relationship between each component, a mapping coordinate system is established between the feasible region of the circuit board to be printed and the layout region of the reference printed circuit board. According to the mapping coordinate system, the component layout structure of the reference printed circuit board is mapped to the feasible area of ​​the printed circuit board to be printed, while keeping the relative spacing, orientation and pin association between each component unchanged, to obtain the preliminary component migration result. The preliminary component migration results are verified for compliance, and issues such as components exceeding the feasible area, conflicting with obstacle areas, and violating component spacing requirements are corrected. The component layout results are then output.

4. The migration method for automatic placement and routing of printed circuit boards as described in claim 3, characterized in that, The steps of performing compliance verification on the preliminary component migration results, correcting issues such as components exceeding the feasible area, conflicting with obstacle areas, and violating component spacing requirements, and outputting the component layout results include: Based on the preliminary component migration results, and in accordance with the feasible area boundary, obstacle area range, and component spacing design rules of the printed circuit board to be printed, the violations of component positions are checked item by item to obtain a list of component layout violations that includes the type of violation, the location of the violating component, and the corresponding rule requirements. According to the list of component layout violations and component layout rules, the positions of components that exceed the feasible area are adjusted by translation, the avoidance path is planned for components that conflict with the obstacle area, and the spacing is optimized for components that violate the spacing requirements. The intermediate result of the corrected component layout is output. The intermediate results of the revised component layout are then subjected to a comprehensive compliance review based on all design rules until no violations are confirmed, at which point the final component layout result is generated.

5. The migration method for automatic placement and routing of printed circuit boards as described in claim 1, characterized in that, The step of constructing multiple routing path representations based on the routing association information between the component layout results and the reference circuit board baseline data includes: Extract the component pin correspondence, circuit connection logic, and key node distribution characteristics contained in the component layout results and the reference circuit board baseline data respectively, and generate a wiring association information set; The specific geometric coordinate attributes of the wiring path are stripped from the wiring association information set, and the wiring information of both the reference circuit board and the circuit board to be printed is converted into a topology structure with component nodes, pad nodes and key transition nodes as the core, to obtain wiring topology structure data. Based on node encoding rules and connection relationship description standards, the cabling topology data is standardized and represented to obtain multiple cabling path representations.

6. The migration method for automatic placement and routing of printed circuit boards as described in claim 1, characterized in that, The step of matching the correspondence between each of the wiring paths and generating wiring migration guidance information includes: Based on multiple wiring path representations, wiring matching pair data is established between the wiring path representation of the reference circuit board and the wiring path representation of the circuit board to be printed. Verify the consistency of node mapping, connection priority, and path direction logic between the data in the wiring matching pair. Correct the mismatched node correspondence and connection logic according to the wiring matching rules to obtain the wiring path matching relationship. Extract the node mapping relationship, path priority sorting, cabling inflection point reference position and avoidance constraint prompts corresponding to the path migration in the cabling path matching relationship, and integrate them to generate the cabling migration guidance information that can directly guide the cabling migration operation.

7. The migration method for automatic placement and routing of printed circuit boards as described in claim 1, characterized in that, The step of performing routing migration on the component placement result based on the routing migration guidance information to obtain the placement and routing result includes: The routing migration guidance information and the node mapping relationship, path priority sorting and avoidance constraint prompts in the component layout results are analyzed to plan the routing migration execution scheme of the printed circuit board to be printed; Based on the routing migration execution scheme, the routing paths are drawn sequentially between the component pins and pad nodes corresponding to the component layout results, according to the path priority, and obstacle areas are avoided, and the preliminary routing migration results are output. The preliminary wiring migration results are subjected to electrical connection integrity verification and comprehensive compliance checks of design rules. Wiring breaks, line short circuits and non-compliant spacing are corrected to generate the layout wiring results.

8. The migration method for automatic placement and routing of printed circuit boards as described in claim 1, characterized in that, After the step of performing routing migration on the component placement result based on the routing migration guidance information to obtain the placement and routing result, the automatic placement and routing migration method for printed circuit boards further includes: Based on the design requirements, performance indicators, and compliance standards uploaded by the user, check the electrical connection correctness, layout rationality, wiring compliance, and performance compliance of the layout and wiring results, and generate a layout and wiring inspection report. Extract key issue information from the layout and routing inspection report, associate it with the original reference data uploaded by the user and the design constraints, sort out the factors related to the migration parameters that caused the problem, and generate feedback data; Based on the feedback data, analyze the weight coefficients and core parameters related to the problem during the migration process, determine the types and magnitudes of parameters that need to be adjusted, and output the parameter adjustment plan; According to the parameter adjustment scheme, the weights and parameters in the migration process are updated, and the layout and routing of the reference circuit board are re-optimized to generate the optimized layout and routing results.

9. An automatic layout and routing device for printed circuit boards, characterized in that, The automatic placement and routing device for printed circuit boards includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the migration method for automatic placement and routing of printed circuit boards as described in any one of claims 1 to 8.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the automatic placement and routing migration method for printed circuit boards as described in any one of claims 1 to 8.

Images