High-voltage release control circuit, flash memory chip and electronic equipment

Abstract

The invention relates to the technical field of flash memory chips, and discloses a high-voltage release control circuit, a flash memory chip and electronic equipment, the high-voltage release control circuit comprises a release current control module, a positive high-voltage first release path, a positive high-voltage second release path, a negative high-voltage first release path and a negative high-voltage second release path; the release current control module controls the release current of the positive high-voltage first release path and the release current of the negative high-voltage first release path to be the same based on the reference current; a first potential detection node included in the positive high-voltage first release path is electrically connected with a first control module, and the first control module controls the positive high-voltage second release path to be opened or closed; a second potential detection node included in the negative high voltage first release path is electrically connected with a second control module, and the second control module controls the negative high voltage second release path to be opened or closed. The release current can be accurately controlled, the abnormal high voltage condition in the release process is avoided, and safety, reliability, accuracy and high release efficiency are considered.

Description

Technical Field

[0001] This disclosure relates to the field of flash memory chip technology, and in particular to a high-voltage release control circuit, a flash memory chip, and an electronic device. Background Technology

[0002] Flash memory chip read, write, and erase operations generally require high-voltage generation circuits, especially write and erase operations, which demand significantly higher voltages, often approaching the device's maximum withstand voltage. During write operations, the positive voltage is typically high, around 10V, while the negative voltage requirement is lower, around -2V. There is little coupling capacitance between the positive and negative voltages, making the release control of these voltages relatively simple. However, during erase operations, both the positive and negative voltages are very high, approaching 10V and -10V respectively. These voltages are very close to the device's maximum withstand voltage, and there is a large coupling capacitance between them.

[0003] Therefore, after the flash memory chip erase operation is completed, the release of the positive and negative high voltages requires careful design. Because the positive and negative high voltages have different loads and are coupled with each other by capacitance, their discharge rates differ during voltage release. During the release process, the positive and negative high voltages may be coupled to higher or more negative voltages, causing erase damage and affecting the reliability of the flash memory chip. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a high-voltage release control circuit, a flash memory chip, and an electronic device. These solutions address the technical issue that existing technologies for establishing positive and negative high-voltage releases for flash memory chip erasure operations cannot adequately balance safety, accuracy, and release efficiency, thus failing to ensure device reliability.

[0005] This disclosure provides a high-voltage release control circuit, including: a release current control module, a positive high-voltage first release path, a positive high-voltage second release path, a negative high-voltage first release path, and a negative high-voltage second release path; The release current control module is electrically connected to the positive high voltage first release path and the negative high voltage first release path respectively. The release current control module controls the release current of the positive high voltage first release path and the release current of the negative high voltage first release path to be the same based on the reference current. The positive high voltage first release path includes a first potential detection node, which is electrically connected to a first control module. The first control module controls the opening or closing of the positive high voltage second release path based on the voltage of the first potential detection node. The negative high voltage first release path includes a second potential detection node, which is electrically connected to a second control module. The second control module controls the opening or closing of the negative high voltage second release path based on the voltage of the second potential detection node.

[0006] Optionally, the release current control module includes a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor; The first PMOS transistor and the second PMOS transistor form the first current mirror. The gate and drain of the first PMOS transistor are shorted together, and the drain of the first PMOS transistor is electrically connected to the reference current source, which provides the reference current. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically connected together, and the source of the first PMOS transistor and the source of the second PMOS transistor are electrically connected to the power supply terminal. The drain of the second PMOS transistor is electrically connected to the source of the first NMOS transistor, the gate and source of the first NMOS transistor are shorted, and the drain of the first NMOS transistor is grounded.

[0007] Further optionally, the positive high voltage first release path includes a second NMOS transistor, a third NMOS transistor, a third PMOS transistor, and a first resistor; The gate of the second NMOS transistor is electrically connected to the first release control signal, the drain of the second NMOS transistor is electrically connected to the source of the third NMOS transistor, and the drain of the third NMOS transistor is grounded; the third NMOS transistor and the first NMOS transistor form a second current mirror, and the gate of the third NMOS transistor is electrically connected to the gate of the first NMOS transistor. The source of the third PMOS transistor is electrically connected to the positive high voltage input terminal, the gate and drain of the third PMOS transistor are shorted, the first resistor is electrically connected between the drain of the third PMOS transistor and the source of the second NMOS transistor, and the source of the second NMOS transistor is the first potential detection node.

[0008] Optionally, the first control module includes a fourth PMOS transistor, a first inverter, and a fourth NMOS transistor; The gate of the fourth PMOS transistor is electrically connected to the first potential detection node, the source of the fourth PMOS transistor is electrically connected to the power supply terminal, and the drain of the fourth PMOS transistor is electrically connected to the input terminal of the first inverter. The fourth NMOS transistor and the first NMOS transistor form the third current mirror. The gate of the fourth NMOS transistor is electrically connected to the gate of the first NMOS transistor. The source of the fourth NMOS transistor is electrically connected to the input terminal of the first inverter. The drain of the fourth NMOS transistor is grounded. The first inverter outputs a first feedback signal, which controls the opening or closing of the second positive high voltage release path.

[0009] Alternatively, the positive high voltage second release path includes a fifth PMOS transistor and a third resistor; The first feedback signal is electrically connected to the gate of the fifth PMOS transistor, controlling the fifth PMOS transistor to turn on or off. The source of the fifth PMOS transistor is electrically connected to the positive high voltage input terminal, and the drain of the fifth PMOS transistor is electrically connected to one end of the third resistor, while the other end of the third resistor is grounded.

[0010] Alternatively, the negative high voltage first release path includes a sixth PMOS transistor, a seventh PMOS transistor, a fifth NMOS transistor, and a second resistor; The gate of the sixth PMOS transistor is electrically connected to the second release control signal, the source of the sixth PMOS transistor is electrically connected to the drain of the seventh PMOS transistor, and the source of the seventh PMOS transistor is electrically connected to the power supply terminal; the seventh PMOS transistor and the first PMOS transistor form the fourth current mirror, and the gate of the seventh PMOS transistor is electrically connected to the gate of the first PMOS transistor. The drain of the fifth NMOS transistor is electrically connected to the negative high voltage input terminal, the gate and source of the fifth NMOS transistor are shorted, the second resistor is electrically connected between the source of the fifth NMOS transistor and the drain of the sixth PMOS transistor, and the drain of the sixth PMOS transistor is the second potential detection node.

[0011] Further optionally, the second control module includes a sixth NMOS transistor, a second inverter, and an eighth PMOS transistor; The gate of the sixth NMOS transistor is electrically connected to the second potential detection node, the drain of the sixth NMOS transistor is grounded, and the source of the sixth NMOS transistor is electrically connected to the input terminal of the second inverter. The eighth PMOS transistor and the first PMOS transistor form the fifth current mirror. The gate of the eighth PMOS transistor and the gate of the first PMOS transistor are electrically connected. The drain of the eighth PMOS transistor is electrically connected to the input terminal of the second inverter. The source of the eighth PMOS transistor is electrically connected to the power supply terminal. The output of the second inverter outputs a second feedback signal, which controls the opening or closing of the negative high voltage second release path.

[0012] Alternatively, the negative high-voltage second release path includes a seventh NMOS transistor and a fourth resistor; The second feedback signal is electrically connected to the gate of the seventh NMOS transistor, controlling the seventh NMOS transistor to turn on or off. The drain of the seventh NMOS transistor is electrically connected to the negative high voltage input terminal, and the source of the seventh NMOS transistor is electrically connected to one end of the fourth resistor, while the other end of the fourth resistor is grounded.

[0013] Based on the same inventive concept, this disclosure also provides a flash memory chip, which includes the above-mentioned high-voltage release control circuit.

[0014] Based on the same inventive concept, this disclosure also provides an electronic device that includes the aforementioned flash memory chip.

[0015] The technical solution provided in this disclosure has the following advantages compared with the prior art: 1. The high-voltage release control circuit provided in this disclosure achieves separate release of positive and negative high voltages through a first positive high voltage release path and a second positive high voltage release path, as well as a first negative high voltage release path and a second negative high voltage release path. The high-voltage release process is staged. At the beginning of the high-voltage release, the release current control module, based on a reference current, precisely controls the positive high voltage release current of the first positive high voltage release path and the negative high voltage release current of the first negative high voltage release path to be equal, ensuring that the positive and negative high voltage release rates are matched and that the positive and negative high voltages are released simultaneously and synchronously. Furthermore, the release current control module can limit the current based on the reference current to avoid excessive release current at the beginning of the release, which could damage the devices. The combination of precise current control and stable release helps to ensure safety at the beginning of the high-voltage release.

[0016] 2. This disclosure further includes a feature where, during the initial high-voltage release process of both the positive and negative high-voltage first release paths, a first control module is electrically connected via a first potential detection node included in the positive high-voltage first release path. This allows the first control module to control the opening of the positive high-voltage second release path after detecting that the voltage at the first potential detection node has decreased to a safe range, thus initiating the second stage of positive high-voltage release. Similarly, a second control module is electrically connected via a second potential detection node included in the negative high-voltage first release path. This allows the second control module to control the opening of the negative high-voltage second release path after detecting that the voltage at the second potential detection node has increased to a safe range, thus initiating the second stage of negative high-voltage release. In other words, during the initial high-voltage release process of both the positive and negative high-voltage first release paths, a potential monitoring and detection mechanism provides real-time feedback on the current release voltage status, ensuring that the second stage of high-current release is only initiated after both positive and negative high voltages have been released to a safe threshold. This eliminates the need for manual intervention, improving the rapid release efficiency of the second stage and ensuring safe and reliable high-voltage release. By employing different release strategies for different release stages, a balance between high-voltage release safety and high efficiency is achieved. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a high-voltage release control circuit provided in an embodiment of this disclosure; Figure 2 This is another schematic diagram of the high-voltage release control circuit provided in the embodiments of this disclosure; Figure 3 This is another schematic diagram of the high-voltage release control circuit provided in the embodiments of this disclosure; Figure 4 yes Figure 3 A schematic diagram of a structure for a second release passage in a positive high-pressure system; Figure 5 yes Figure 3 A schematic diagram of a secondary release pathway for medium- and high-voltage systems. Detailed Implementation

[0020] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0021] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0022] In existing technologies, there are generally two high-voltage release methods: separate release of positive and negative high voltages and offset release of positive and negative high voltages. When the positive and negative high voltages are released separately, they approach the device's limit voltage (positive high voltage is approximately +10V, negative high voltage is approximately -10V). When released directly, the large coupling capacitance between the two leads to the voltage on one side being amplified by coupling, exceeding the limit voltage and causing device damage (the coupling risk may not be reflected in the simulation, but there will be a significant coupling risk in actual use). Furthermore, there is no release current limit. If the instantaneous current is too large during release, it can easily cause circuit burning or device aging. Therefore, although the existing positive and negative high voltage separate release circuit is simple, its reliability is low. Establishing a direct path between positive and negative high voltages for offset release only passively achieves simultaneous voltage release, without controlling the magnitude of the offset current. If the current is uneven, such as at the beginning of release, local overvoltage may still occur. Furthermore, without a voltage detection mechanism, the release progress cannot be judged, potentially leading to incomplete or excessive release. In addition, improperly designed offset paths can cause anomalies such as current backflow and sudden local voltage changes. Furthermore, the offset efficiency decreases as the voltage drops, slowing down the release speed and consequently reducing the overall release efficiency, making it impossible to guarantee release efficiency. Therefore, current technologies for controlling the release of positive and negative high voltages after flash memory chip erase operations only employ a single release mode: either uncontrolled separate release or full offset release, failing to simultaneously address the contradictions of coupled overvoltage, current surge, and release efficiency.

[0023] To address the aforementioned issues, this disclosure proposes a high-voltage release control circuit, a flash memory chip, and electronic devices. These devices can establish positive and negative high-voltage releases for flash memory chip erase operations, effectively balancing safety, accuracy, and release efficiency, thus ensuring device reliability. Specific embodiments of the high-voltage release control circuit, flash memory chip, and electronic devices proposed in this disclosure are detailed below.

[0024] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a high-voltage release control circuit provided in an embodiment of the present disclosure. The high-voltage release control circuit provided in this embodiment includes: a release current control module 10, a positive high voltage first release path 20A, a positive high voltage second release path 20B, a negative high voltage first release path 30A, and a negative high voltage second release path 30B. The release current control module 10 is electrically connected to the positive high voltage first release path 20A and the negative high voltage first release path 30A respectively. The release current control module 10 controls the release current of the positive high voltage first release path 20A and the release current of the negative high voltage first release path 30A to be the same based on the reference current IREF. The positive high voltage first release path 20A includes a first potential detection node VPDET, which is electrically connected to a first control module 40A. The first control module 40A controls the opening or closing of the positive high voltage second release path 20B based on the voltage of the first potential detection node VPDET. The negative high voltage first release path 30A includes a second potential detection node VNDET, which is electrically connected to a second control module 40B. The second control module 40B controls the opening or closing of the negative high voltage second release path 30B based on the voltage of the second potential detection node VNDET.

[0025] Specifically, the high-voltage release control circuit provided in this embodiment can be used to release the positive and negative high voltages established during the erase operation of a flash memory chip. This high-voltage release control circuit includes: a release current control module 10, a first positive high-voltage release path 20A, a second positive high-voltage release path 20B, a first negative high-voltage release path 30A, and a second negative high-voltage release path 30B. That is, the release of the positive high voltage is achieved through the first positive high-voltage release path 20A and the second positive high-voltage release path 20B, and the release of the negative high voltage is achieved through the first negative high-voltage release path 30A and the second negative high-voltage release path 30B. The release current control module 10 is used to control the release current of the first positive high-voltage release path 20A and the first negative high-voltage release path 30A. Specifically, at the beginning of the high-voltage release phase, the positive high-voltage first release path 20A and the negative high-voltage first release path 30A can be opened simultaneously. The release current control module 10 is electrically connected to the positive high-voltage first release path 20A and the negative high-voltage first release path 30A respectively. Based on the reference current IREF, the release current control module 10 controls the release current of the positive high-voltage first release path 20A and the negative high-voltage first release path 30A to be the same or substantially the same. Through the reference current IREF provided by the release current control module 10, the release current of the positive high-voltage first release path 20A and the negative high-voltage first release path 30A can be made the same or substantially the same during the initial stage of high-voltage release. The release current should be as similar as possible. For example, the reference current IREF provided by the release current control module 10 can be copied to the positive high voltage first release path 20A and the negative high voltage first release path 30A respectively, or the reference current IREF provided by the release current control module 10 can be copied to the positive high voltage first release path 20A and the negative high voltage first release path 30A in the same proportion. This ensures that at the beginning of the high voltage release, the release rate of the positive high voltage established by the flash memory chip erase operation through the positive high voltage first release path 20A and the release rate of the negative high voltage established by the flash memory chip erase operation through the negative high voltage first release path 30A are matched consistently, ensuring that the positive and negative high voltages are released synchronously. Furthermore, the release current control module 10 can also limit the release current of the release path. For example, the release current control module 10 can limit the release current of the positive high voltage first release path 20A and the negative high voltage first release path 30A based on the reference current IREF to keep them within a certain current range, avoiding excessive current at the beginning of the release and preventing damage to the device.

[0026] This embodiment also includes a positive high voltage first release path 20A comprising a first potential detection node VPDET, which is electrically connected to a first control module 40A. The first control module 40A controls the opening or closing of the positive high voltage second release path 20B based on the voltage of the first potential detection node VPDET. At the beginning of the high voltage release phase, the reference current IREF provided by the release current control module 10 ensures that the release current of the positive high voltage first release path 20A and the release current of the negative high voltage first release path 30A are precisely current-limited and as similar as possible. Once the positive high voltage first release path 20A releases the positive high voltage to a certain extent, for example, after ensuring it is within a safe range (e.g., the initial positive high voltage value is close to 10V, then when the positive high voltage...), the release current of the positive high voltage second release path 20B is... After the first release path 20A releases 10V to less than 5V (e.g., to 4V), the voltage of the first potential detection node VPDET also decreases according to the decrease in the positive high voltage value. At this time, the first control module 40A can control the second positive high voltage release path 20B to open based on the current voltage of the first potential detection node VPDET, thus starting the second stage of positive high voltage release. Optionally, since the positive high voltage has been reduced to a safe range at this time, the release current of the second positive high voltage release path 20B does not need to be precisely controlled and current limited compared to the first positive high voltage release path 20A. That is, the release current of the second positive high voltage release path 20B can be larger at this time, which can improve the positive high voltage release efficiency while ensuring safe release.

[0027] Similarly, this embodiment also includes a negative high-voltage first release path 30A comprising a second potential detection node VNDET. The second potential detection node VNDET is electrically connected to a second control module 40B. The second control module 40B controls the opening or closing of the negative high-voltage second release path 30B based on the voltage of the second potential detection node VNDET. At the beginning of the high-voltage release, the reference current IREF provided by the release current control module 10 ensures that the release current of the positive high-voltage first release path 20A and the release current of the negative high-voltage first release path 30A are precisely current-limited and as similar as possible. When the negative high-voltage first release path 30A releases the negative high voltage to a certain extent, for example, after ensuring it is within a safe range (e.g., the initial negative high voltage value is close to -10V, then when the negative high voltage... The first release path 30A increases the -10V release to greater than -5V (e.g., after increasing to -4V). The voltage of the second potential detection node VNDET also increases according to the increase in the negative high voltage value. At this time, the second control module 40B can control the second negative high voltage release path 30B to open based on the current voltage NPDET of the second potential detection node VNDET, thus starting the second stage of negative high voltage release. Optionally, since the negative high voltage has been increased to a safe range at this time, the release current of the second negative high voltage release path 30B does not need to be precisely controlled and current limited compared to the first negative high voltage release path 20B. That is, the release current of the second negative high voltage release path 30B can be larger at this time, which can improve the negative high voltage release efficiency while ensuring safe release.

[0028] The high-voltage release control circuit provided in this disclosure achieves separate release of positive and negative high voltages through a first positive high voltage release path 20A and a second positive high voltage release path 20B, and a first negative high voltage release path 30A and a second negative high voltage release path 30B. The high-voltage release process is staged. At the beginning of the high-voltage release, the release current control module 10, based on a reference current, precisely controls the positive high voltage release current of the first positive high voltage release path 20A and the negative high voltage release current of the first negative high voltage release path 30A to be equal, ensuring that the positive and negative high voltage release rates are matched and that the positive and negative high voltages are released simultaneously and synchronously. Furthermore, the release current control module 10 can limit the current based on the reference current to avoid excessive release current at the beginning of the release, which could damage the devices. By combining precise current control with stable release, it is beneficial to ensure safety at the beginning of the high-voltage release.

[0029] Furthermore, this embodiment also includes a configuration where, during the high-voltage release process of the positive high-voltage first release path 20A and the negative high-voltage first release path 30A, the first control module 40A is electrically connected via the first potential detection node VPDET included in the positive high-voltage first release path 20A. This allows the first control module 40A to control the opening of the positive high-voltage second release path 20B after detecting that the voltage of the first potential detection node VPDET has dropped to a safe range, thus initiating the second stage of positive high-voltage release. Similarly, the second control module 40B is electrically connected via the second potential detection node VNDET included in the negative high-voltage first release path 30A. This allows the second control module 40B to detect the second potential... After the voltage of the detection node VNDET is raised to a safe range, the second negative high-voltage release path 30B is opened to initiate the second stage of negative high-voltage release. That is, during the high-voltage release process of the first positive high-voltage release path 20A and the first negative high-voltage release path 30A, a potential monitoring and detection mechanism is used to provide real-time feedback on the current release voltage status. This ensures that the second stage of high-current release is only initiated after both positive and negative high voltages have been released to the safe threshold. No manual intervention is required, which can improve the rapid release efficiency of the second stage, quickly complete the subsequent high-voltage release, and ensure safety and reliability. By adopting different release strategies for different release stages, a balance between high-voltage release safety and high efficiency can be achieved.

[0030] It should be noted that, in this disclosure, positive high voltage refers to a high amplitude voltage that is forward biased relative to the chip reference ground (GND), and negative high voltage refers to a high amplitude voltage that is reverse biased relative to the chip reference ground (GND). Subsequent embodiments will not further explain this.

[0031] In some alternative embodiments, please refer to Figure 2 , Figure 2 This is another structural schematic diagram of the high-voltage release control circuit provided in this embodiment. In this embodiment, the release current control module 10 includes a first PMOS transistor MP1A, a second PMOS transistor MP1B, and a first NMOS transistor MN1A. The first PMOS transistor MP1A and the second PMOS transistor MP1B constitute the first current mirror. The gate and drain of the first PMOS transistor MP1A are shorted together, and the drain of the first PMOS transistor MP1A is electrically connected to the reference current source 101, which provides the reference current IREF. The gate of the first PMOS transistor MP1A and the gate of the second PMOS transistor MP1B are electrically connected together, and the source of the first PMOS transistor MP1A and the source of the second PMOS transistor MP1B are electrically connected to the power supply terminal VCC. The drain of the second PMOS transistor MP1B is electrically connected to the source of the first NMOS transistor MN1A. The gate and source of the first NMOS transistor MN1A are shorted, and the drain of the first NMOS transistor MN1A is grounded to GND.

[0032] This embodiment explains the specific circuit structure that the release current control module 10 can be configured with. The release current control module 10 may include a first PMOS transistor MP1A, a second PMOS transistor MP1B, and a first NMOS transistor MN1A. The first PMOS transistor MP1A and the second PMOS transistor MP1B constitute a first current mirror. The first PMOS transistor MP1A is a reference current mirror transistor used to provide a reference current IREF for the entire release circuit. The second PMOS transistor MP1B is a positive high voltage release current mirror transistor. Optionally, the second PMOS transistor MP1B can replicate or proportionally replicate the reference current IREF of the first PMOS transistor MP1A, thereby achieving precise control of the release current of the positive high voltage first release path 20A within the limit range.

[0033] Optionally, in the release current control module 10 of this embodiment, the first PMOS transistor MP1A and the second PMOS transistor MP1B constitute a first current mirror. The gates of the first PMOS transistor MP1A and the second PMOS transistor are P-tube bias voltage nodes PBIAS. The P-tube bias voltage nodes PBIAS can form a stable replication current or replication voltage in the first current mirror to drive the first PMOS transistor MP1A and the second PMOS transistor MP1B.

[0034] In some alternative embodiments, please refer to Figure 3 , Figure 3 This is another structural schematic diagram of the high-voltage release control circuit provided in this embodiment. In this embodiment, the positive high voltage first release path 20A includes a second NMOS transistor MN4, a third NMOS transistor MN1B, a third PMOS transistor MP2, and a first resistor R1. The gate of the second NMOS transistor MN4 is electrically connected to the first release control signal HVDISCH1. The drain of the second NMOS transistor MN4 is electrically connected to the source of the third NMOS transistor MN1B. The drain of the third NMOS transistor MN1B is grounded to GND. The third NMOS transistor MN1B and the first NMOS transistor MN1A form a second current mirror. The gate of the third NMOS transistor MN1B is electrically connected to the gate of the first NMOS transistor MN1A. The source of the third PMOS transistor MP2 is electrically connected to the positive high voltage input terminal VPOS. The gate and drain of the third PMOS transistor MP2 are shorted. The first resistor R1 is electrically connected between the drain of the third PMOS transistor MP2 and the source of the second NMOS transistor MN4. The source of the second NMOS transistor MN4 is the first potential detection node VPDET.

[0035] This embodiment explains the specific circuit structure that can be configured for the positive high voltage first release path 20A. The positive high voltage first release path 20A may include a second NMOS transistor MN4, a third NMOS transistor MN1B, a third PMOS transistor MP2, and a first resistor R1. The second NMOS transistor MN4 is the switching transistor of the positive high voltage first release path 20A, and its on / off state is controlled by the first release control signal HVDISCH1. When the first release control signal HVDISCH1 is high, the positive high voltage first release path 20A is turned on. The third NMOS transistor MN1B and the first NMOS transistor MN1A constitute a second current mirror. The third NMOS transistor MN1B is a positive high voltage release current mirror transistor, which can replicate or proportionally replicate the reference current of the first NMOS transistor MN1A to control the positive high voltage release current. The first PMOS transistor MP1A and the second PMOS transistor MP1B constitute a first current mirror. Through the proportional relationship between the current mirrors, the release current of the positive high voltage first release path 20A can be precisely controlled.

[0036] Optionally, in this embodiment, in the release current control module 10 and the positive high voltage first release path 20A, the third NMOS transistor MN1B and the first NMOS transistor MN1A constitute the second current mirror. The gates of the third NMOS transistor MN1B and the first NMOS transistor MN1A are the N-transistor bias voltage node NBIAS. The N-transistor bias voltage node NBIAS can form a stable replication current or replication voltage in the second current mirror to drive the third NMOS transistor MN1B and the first NMOS transistor MN1A.

[0037] The third PMOS transistor MP2 and the first resistor R1 in the first positive high voltage release path 20A can realize the real-time detection of the positive high voltage release state of the positive high voltage input terminal VPOS. The third PMOS transistor MP2 is a positive high voltage detection voltage divider. Together with the first resistor R1, it can realize the real-time potential detection during positive high voltage release. The potential of the first potential detection node VPDET is equal to the positive high voltage potential of the positive high voltage input terminal VPOS minus the voltage drop of the third PMOS transistor MP2 and the first resistor R1. The detection potential of the first potential detection node VPDET can be transmitted to the first control module 40A in real time, thereby realizing the first control module 40A to control the opening timing of the second positive high voltage release path 20B based on the detection potential of the first potential detection node VPDET.

[0038] Optional, please continue to refer to Figure 3 The first control module 40A includes a fourth PMOS transistor MP3, a first inverter INV1, and a fourth NMOS transistor MN1C; The gate of the fourth PMOS transistor MP3 is electrically connected to the first potential detection node VPDET, the source of the fourth PMOS transistor MP3 is electrically connected to the power supply terminal VCC, and the drain of the fourth PMOS transistor MP3 is electrically connected to the input terminal of the first inverter INV1. The fourth NMOS transistor MN1C and the first NMOS transistor MN1A form the third current mirror. The gate of the fourth NMOS transistor MN1C is electrically connected to the gate of the first NMOS transistor MN1A. The source of the fourth NMOS transistor MN1C is electrically connected to the input terminal of the first inverter INV1. The drain of the fourth NMOS transistor MN1C is grounded to GND. The first inverter INV1 outputs a first feedback signal VP2Lb, which controls the opening or closing of the positive high voltage second release path 20B.

[0039] Optionally, in the release current control module 10 and the first control module 40A, the fourth NMOS transistor MN1C and the first NMOS transistor MN1A constitute a third current mirror. The gates of the fourth NMOS transistor MN1C and the first NMOS transistor MN1A are N-transistor bias voltage nodes NBIAS. The N-transistor bias voltage nodes NBIAS can form a stable replication current or replication voltage in the third current mirror to drive the fourth NMOS transistor MN1C and the first NMOS transistor MN1A.

[0040] This embodiment explains the circuit structure that the first control module 40A can be configured with, specifically including a fourth PMOS transistor MP3, a first inverter INV1, and a fourth NMOS transistor MN1C. The gate of the fourth PMOS transistor MP3 is connected to the first potential detection node VPDET. When the positive high voltage potential of the positive high voltage input terminal VPOS has not started to be released, the potential of the first potential detection node VPDET follows the positive high voltage potential of the positive high voltage input terminal VPOS and is relatively high. The fourth PMOS transistor MP3 is in the off state. The current driving capability of the controlled fourth PMOS transistor MP3 is less than the current driving capability of the fourth NMOS transistor MN1C controlled by the N-transistor bias voltage node NBIAS. The first feedback signal VP2Lb is at a high potential. At this time, the second positive high voltage release path 20B is not opened.

[0041] As the positive high voltage potential at the positive high voltage input terminal VPOS decreases during the release process, the potential of the first potential detection node VPDET also decreases. When the potential of the first potential detection node VPDET drops to a certain safe potential, the current driving capability of the controlled fourth PMOS transistor MP3 is greater than the current driving capability of the fourth NMOS transistor MN1C controlled by the N-transistor bias voltage node NBIAS. The first feedback signal VP2Lb changes from a high potential to a low potential, which is the timing for the activation of the second positive high voltage release path 20B. In the first control module 40A, the fourth NMOS transistor MN1C and the fourth PMOS transistor MP3 perform current comparison. The fourth PMOS transistor MP3 is a positive high voltage detection current comparator, controlled by the first potential detection node VPDET, and compares the current with the fourth NMOS transistor MN1C. The fourth NMOS transistor MN1C is a positive high voltage detection current comparator, providing the reference current for positive high voltage detection. When the positive high voltage potential at the positive high voltage input terminal VPOS is not released and the potential is high, the potential of the first potential detection node VPDET remains high, and the fourth PMOS transistor MP3 is turned off or the current is small. When the positive high voltage potential at the positive high voltage input terminal VPOS decreases during the release process, the potential of the first potential detection node VPDET also decreases accordingly. The current driving capability for controlling the fourth PMOS transistor MP3 to turn on is greater than the current driving capability for controlling the fourth NMOS transistor MN1C to turn on. The first feedback signal VP2Lb changes from high potential to low potential, which serves as the timing for turning on the second positive high voltage release path 20B.

[0042] In this embodiment, the first control module 40A converts the voltage state into a current signal for comparison, thereby triggering the opening timing of the positive high voltage second release path 20B. This forms a control release current, real-time detection of the positive high voltage potential after release, and feedback adjustment of the opening of the positive high voltage second release path 20B. The entire circuit design does not require a complex voltage sensor, but is implemented only through conventional MOSFETs and resistors, thus balancing detection accuracy and circuit simplicity.

[0043] In some alternative embodiments, please continue to refer to Figure 3 In this embodiment, the negative high voltage first release path 30A includes the sixth PMOS transistor MP4, the seventh PMOS transistor MP1C, the fifth NMOS transistor MN2, and the second resistor R2; The gate of the sixth PMOS transistor MP4 is electrically connected to the second release control signal HVDISCH1B. The source of the sixth PMOS transistor MP4 is electrically connected to the drain of the seventh PMOS transistor MP1C. The source of the seventh PMOS transistor MP1C is electrically connected to the power supply terminal VCC. The seventh PMOS transistor MP1C and the first PMOS transistor MP1A form the fourth current mirror. The gate of the seventh PMOS transistor MP1C is electrically connected to the gate of the first PMOS transistor MP1A. The drain of the fifth NMOS transistor MN2 is electrically connected to the negative high voltage input terminal VNEG. The gate and source of the fifth NMOS transistor MN2 are shorted. The second resistor R2 is electrically connected between the source of the fifth NMOS transistor MN2 and the drain of the sixth PMOS transistor MP4. The drain of the sixth PMOS transistor MP4 is the second potential detection node VNDET.

[0044] This embodiment explains the specific circuit structure that can be configured for the negative high voltage first release path 30A. The negative high voltage first release path 30A may include a sixth PMOS transistor MP4, a seventh PMOS transistor MP1C, a fifth NMOS transistor MN2, and a second resistor R2. The sixth PMOS transistor MP4 is the switching transistor of the negative high voltage first release path 30A. The sixth PMOS transistor MP4 is controlled to turn on or off by the second release control signal HVDISCH1B. When the second release control signal HVDISCH1B is low, the negative high voltage first release path 30A is turned on. The seventh PMOS transistor MP1C and the first PMOS transistor MP1A constitute a fourth current mirror. The seventh PMOS transistor MP1C is a negative high voltage release current mirror transistor, which can replicate or proportionally replicate the reference current of the first PMOS transistor MP1A to control the negative high voltage release current. The first PMOS transistor MP1A and the second PMOS transistor MP1B constitute a first current mirror. Through the proportional relationship between the current mirrors, the release current of the negative high voltage first release path 30A can be precisely controlled.

[0045] Optionally, in this embodiment, in the release current control module 10 and the negative high voltage first release path 20A, the seventh PMOS transistor MP1C and the first PMOS transistor MP1A constitute the fourth current mirror. The gates of the seventh PMOS transistor MP1C and the first PMOS transistor MP1A are P-tube bias voltage nodes PBIAS. The P-tube bias voltage nodes PBIAS can form a stable replication current or replication voltage in the fourth current mirror to drive the seventh PMOS transistor MP1C and the first PMOS transistor MP1A.

[0046] The fifth NMOS transistor MN2 and the second resistor R2 in the first negative high voltage release path 30A can realize the real-time detection of the negative high voltage release state of the negative high voltage input terminal VNEG. The fifth NMOS transistor MN2 is a negative high voltage detection voltage divider, which, together with the second resistor R2, can realize the real-time potential detection during negative high voltage release. The potential of the second potential detection node VNDET is equal to the negative high voltage potential of the negative high voltage input terminal VNEG plus the voltage drop of the fifth NMOS transistor MN2 and the second resistor R2. The detection potential of the second potential detection node VNDET can be transmitted to the second control module 40B in real time, thereby enabling the second control module 40B to control the opening timing of the second negative high voltage release path 30B based on the detection potential of the second potential detection node VNDET.

[0047] Optional, please continue to refer to Figure 3 The second control module 40B includes a sixth NMOS transistor MN3, a second inverter INV2, and an eighth PMOS transistor MP1D; The gate of the sixth NMOS transistor MN3 is electrically connected to the second potential detection node VNDET, the drain of the sixth NMOS transistor MN3 is grounded to GND, and the source of the sixth NMOS transistor MN3 is electrically connected to the input terminal of the second inverter INV2. The eighth PMOS transistor MP1D and the first PMOS transistor MP1A form the fifth current mirror. The gate of the eighth PMOS transistor MP1D and the gate of the first PMOS transistor MP1A are electrically connected. The drain of the eighth PMOS transistor MP1D is electrically connected to the input terminal of the second inverter INV2. The source of the eighth PMOS transistor MP1D is electrically connected to the power supply terminal VCC. The output terminal of the second inverter INV2 outputs a second feedback signal VN2L, which controls the opening or closing of the negative high voltage second release passage 30B.

[0048] Optionally, in the release current control module 10 and the second control module 40B, the eighth PMOS transistor MP1D and the first PMOS transistor MP1A constitute a fifth current mirror. The gates of the eighth PMOS transistor MP1D and the first PMOS transistor MP1A are P-tube bias voltage nodes PBIAS. The P-tube bias voltage nodes PBIAS can form a stable replication current or replication voltage in the fifth current mirror to drive the eighth PMOS transistor MP1D and the first PMOS transistor MP1A.

[0049] This embodiment explains the circuit structure that the second control module 40B can be configured with. Specifically, it can include a sixth NMOS transistor MN3, a second inverter INV2, and an eighth PMOS transistor MP1D. The gate of the sixth NMOS transistor MN3 is connected to the second potential detection node VNDET. When the negative high voltage potential of the negative high voltage input terminal VNEG has not started to release, the potential of the second potential detection node VNDET follows the negative high voltage potential of the negative high voltage input terminal VNEG and is low. The sixth NMOS transistor MN3 is in the off state. The current driving capability of the controlled sixth NMOS transistor MN3 is less than the current driving capability of the eighth PMOS transistor MP1D controlled by the P-tube bias voltage node PBIAS. The second feedback signal VN2L is at a low potential. At this time, the negative high voltage second release path 30B is not turned on.

[0050] As the negative high-voltage input terminal VNEG rises during the release process, the potential of the second potential detection node VNDET also rises. When the potential of the second potential detection node VNDET rises to a certain safe potential, the current driving capability of the controlled sixth NMOS transistor MN3 is greater than the current driving capability of the eighth PMOS transistor MP1D controlled by the P-tube bias voltage node PBIAS. The second feedback signal VN2L changes from a low potential to a high potential, which is the timing for the activation of the second negative high-voltage release path 30B. In the second control module 40B, the eighth PMOS transistor MP1D and the sixth NMOS transistor MN3 perform current comparison. The sixth NMOS transistor MN3 is a negative high-voltage detection current comparator, controlled by the second potential detection node VNDET, and compares the current with the eighth PMOS transistor MP1D. The eighth PMOS transistor MP1D is a negative high-voltage detection current comparator, providing the reference current for negative high-voltage detection. When the negative high voltage potential of the negative high voltage input terminal VNEG is not released and the potential is low, the potential of the second potential detection node VNDET remains low, and the sixth NMOS transistor MN3 is cut off or has a small current. When the negative high voltage potential of the negative high voltage input terminal VNEG rises during the release process, the potential of the second potential detection node VNDET also rises accordingly. The current driving capability of the sixth NMOS transistor MN3 is greater than the current driving capability of the eighth PMOS transistor MP1D controlled by the P-tube bias voltage node PBIAS. The second feedback signal VN2L changes from low potential to high potential, which serves as the turn-on timing for the second negative high voltage release path 30B.

[0051] In this embodiment, the second control module 40B converts the voltage state into a current signal for comparison, thereby triggering the opening of the negative high voltage second release path 30B. This forms a control release current, real-time detection of the negative high voltage potential after release, and feedback adjustment of the opening of the negative high voltage second release path 30B. The entire circuit design does not require a complex voltage sensor, but is implemented only through conventional MOSFETs and resistors, thus balancing detection accuracy and circuit simplicity.

[0052] In some alternative embodiments, please refer to the references. Figure 3 and Figure 4 , Figure 5 , Figure 4 yes Figure 3 A schematic diagram of a structure for the second release path of the neutral high-pressure system. Figure 5 yes Figure 3 A schematic diagram of a secondary release path for medium- and negative high voltage. In this embodiment, the secondary release path 20B for positive high voltage includes a fifth PMOS transistor MP5 and a third resistor R3. The first feedback signal VP2Lb is electrically connected to the gate of the fifth PMOS transistor MP5, controlling the turn-on or turn-off of the fifth PMOS transistor MP5. The source of the fifth PMOS transistor MP5 is electrically connected to the positive high voltage input terminal VPOS, and the drain of the fifth PMOS transistor MP5 is electrically connected to one end of the third resistor R3. The other end of the third resistor R3 is grounded to GND.

[0053] The negative high voltage second release path 30B includes the seventh NMOS transistor MN5 and the fourth resistor R4; The second feedback signal VN2L is electrically connected to the gate of the seventh NMOS transistor MN5, controlling the turn-on or turn-off of the seventh NMOS transistor MN5. The drain of the seventh NMOS transistor MN5 is electrically connected to the negative high voltage input terminal VNEG, and the source of the seventh NMOS transistor MN5 is electrically connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is grounded to GND.

[0054] This embodiment explains the specific circuit structure of the positive high voltage second release path 20B, which may include a fifth PMOS transistor MP5 and a third resistor R3. The fifth PMOS transistor MP5 is the release switch for the second stage of the positive high voltage. After the fifth PMOS transistor MP5 is turned on, it can provide a release path with a large release current for the positive high voltage second release path 20B. The third resistor R3 plays a certain current limiting role, limiting the instantaneous large current during the rapid release of the positive high voltage in the second stage, avoiding large current impact on the chip, and preventing the release current of the positive high voltage second release path 20B from being too large and causing damage to the device in the later stage of release.

[0055] The specific circuit structure of the negative high voltage second release path 30B can include a seventh NMOS transistor MN5 and a fourth resistor R4. The seventh NMOS transistor MN5 is the release switch for the second stage of the negative high voltage. After the seventh NMOS transistor MN5 is turned on, it can provide a release path with a large release current for the negative high voltage second release path 30B. The fourth resistor R4 plays a certain current limiting role, limiting the instantaneous large current during the rapid release of the negative high voltage in the second stage, avoiding large current impact on the chip, and preventing excessive release current of the negative high voltage second release path 30B from causing device damage in the later stages of release.

[0056] In the high-voltage release control circuit of this embodiment, after the first positive high voltage release path 20A releases the positive high voltage to a certain extent, such as ensuring it is within a safe range (e.g., if the initial positive high voltage value is close to 10V, then when the first positive high voltage release path 20A releases 10V to less than 5V, such as to 4V), the voltage of the first potential detection node VPDET also decreases according to the decrease in the positive high voltage value. At this time, the first control module 40A can control the second positive high voltage release path 20B to open based on the current voltage of the first potential detection node VPDET, thereby starting the second stage of positive high voltage release. The source of the fifth PMOS transistor MP5 in the second positive high voltage release path 20B is electrically connected to the positive high voltage input terminal VPOS. Since the positive high voltage has been reduced to a safe range at this time, the potential of the positive high voltage at the positive high voltage input terminal VPOS has been reduced accordingly. Therefore, the release current of the second positive high voltage release path 20B does not require precise current limiting control compared to the first positive high voltage release path 20A. The release current of the second positive high voltage release path 20B can be larger, which can improve the positive high voltage release efficiency while ensuring safe release.

[0057] It is understood that in this embodiment, the first feedback signal VP2Lb output by the first control module 40A is electrically connected to the gate of the fifth PMOS transistor MP5. The first feedback signal VP2Lb and the gate of the fifth PMOS transistor MP5 are not directly connected; there are other control devices in between. This merely indicates that the first feedback signal VP2Lb can control the opening and closing of the fifth PMOS transistor MP5. Similarly, the second feedback signal VN2L output by the second control module 40B is electrically connected to the gate of the seventh NMOS transistor MN5. The second feedback signal VN2L and the gate of the seventh NMOS transistor MN5 are not directly connected; there are other control devices in between. This merely indicates that the second feedback signal VN2L can control the opening and closing of the seventh NMOS transistor MN5.

[0058] In this embodiment, the release current control module 10 achieves complete synchronization of the positive and negative high voltage release speeds through a current mirror. Furthermore, a first control module 40A and a second control module 40B monitor the release voltage values ​​of the positive and negative high voltages in real time to ensure that the activation timing of the second positive high voltage release path 20B and the second negative high voltage release path 30B is within a safe range, requiring no manual intervention. The high voltage release control circuit structure described above in this embodiment is space-saving, and the overall control circuit is small in scale. Therefore, when applied to flash memory chips, it will not occupy too much chip space, which is beneficial for chip miniaturization design. In the initial stage of high voltage release, the current mirror design of the release current control module 10 can precisely control the positive high voltage release current of the first positive high voltage release path 20A and the negative high voltage release current of the first negative high voltage release path 30A to be equal based on a reference current, ensuring matching of the positive and negative high voltage release rates and guaranteeing simultaneous synchronous release of the positive and negative high voltages. Moreover, the release current control module 10 can limit the current based on the reference current to avoid excessive release current at the beginning, which could damage the device. Precise current control combined with stable release helps ensure safety at the start of high voltage release. During the high-voltage release process of the first positive high-voltage release path 20A and the first negative high-voltage release path 30A, the first control module 40A is electrically connected to the first potential detection node VPDET included in the first positive high-voltage release path 20A. This allows the first control module 40A to control the second positive high-voltage release path 20B to open after detecting that the voltage of the first potential detection node VPDET has dropped to a safe range, thus initiating the second stage of positive high-voltage release. Similarly, the second control module 40B is electrically connected to the second potential detection node VNDET included in the first negative high-voltage release path 30A. This allows the second control module 40B to control the second high-voltage release path 20B to open after detecting that the voltage of the second potential detection node VNDET has risen to a safe range. The second negative high-voltage release path 30B is activated to initiate the second stage of negative high-voltage release. During the high-voltage release process of the first positive high-voltage release path 20A and the first negative high-voltage release path 30A, a potential monitoring and detection mechanism is used to provide real-time feedback on the current release voltage status. This ensures that the second stage of high-current release is only initiated after both positive and negative high voltages have been released to the safe threshold. No manual intervention is required, which can improve the rapid release efficiency of the second stage, quickly complete the subsequent high-voltage release, and ensure safety and reliability. By adopting different release strategies for different release stages, a balance is achieved between the stability, safety, and efficiency of high-voltage release, while also considering the release speed. Therefore, when applied to flash memory chips, it can be used without affecting the chip's erasure efficiency.

[0059] In some optional embodiments, this embodiment also provides a flash memory chip, which includes the aforementioned high-voltage release control circuit for releasing the positive and negative high voltages established during the erase operation of the flash memory chip. The flash memory chip provided in this embodiment has the beneficial effects of the high-voltage release control circuit provided in the above embodiments, such as achieving a balance between the stability and safety of high-voltage release and release efficiency, while also considering the release speed, thereby not affecting the erase efficiency of the flash memory chip. For details, please refer to the specific descriptions of the high-voltage release control circuits in the above embodiments; these will not be repeated here.

[0060] In some optional embodiments, this embodiment also provides an electronic device including the aforementioned flash memory chip. When the flash memory chip releases the positive and negative high voltages established during the erase operation, the high-voltage release control circuit provided in the above embodiments can be used. The electronic device provided in this embodiment has the beneficial effects of the high-voltage release control circuit provided in the above embodiments, such as achieving a balance between the stability, safety, and efficiency of high-voltage release, while also considering the release speed, thereby not affecting the erase efficiency of the flash memory chip and ensuring the safety and reliability of the electronic device. For details, please refer to the specific descriptions of the high-voltage release control circuits in the above embodiments; these will not be repeated here.

[0061] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0062] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high-voltage release control circuit, characterized in that, include: Release current control module, positive high voltage first release path, positive high voltage second release path, negative high voltage first release path, negative high voltage second release path; The release current control module is electrically connected to the positive high voltage first release path and the negative high voltage first release path respectively. The release current control module controls the release current of the positive high voltage first release path and the release current of the negative high voltage first release path to be the same based on the reference current. The positive high voltage first release path includes a first potential detection node, which is electrically connected to a first control module. The first control module controls the opening or closing of the positive high voltage second release path based on the voltage of the first potential detection node. The negative high voltage first release path includes a second potential detection node, which is electrically connected to a second control module. The second control module controls the opening or closing of the negative high voltage second release path based on the voltage of the second potential detection node.

2. The high-voltage release control circuit according to claim 1, characterized in that, The release current control module includes a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor; The first PMOS transistor and the second PMOS transistor form a first current mirror. The gate and drain of the first PMOS transistor are shorted together, and the drain of the first PMOS transistor is electrically connected to a reference current source, which provides the reference current. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically connected, and the source of the first PMOS transistor and the source of the second PMOS transistor are electrically connected to a power supply terminal. The drain of the second PMOS transistor is electrically connected to the source of the first NMOS transistor, the gate and source of the first NMOS transistor are shorted, and the drain of the first NMOS transistor is grounded.

3. The high-voltage release control circuit according to claim 2, characterized in that, The positive high voltage first release path includes a second NMOS transistor, a third NMOS transistor, a third PMOS transistor, and a first resistor; The gate of the second NMOS transistor is electrically connected to the first release control signal, the drain of the second NMOS transistor is electrically connected to the source of the third NMOS transistor, and the drain of the third NMOS transistor is grounded; the third NMOS transistor and the first NMOS transistor constitute a second current mirror, and the gate of the third NMOS transistor is electrically connected to the gate of the first NMOS transistor. The source of the third PMOS transistor is electrically connected to the positive high voltage input terminal, the gate and drain of the third PMOS transistor are shorted, the first resistor is electrically connected between the drain of the third PMOS transistor and the source of the second NMOS transistor, and the source of the second NMOS transistor is the first potential detection node.

4. The high-voltage release control circuit according to claim 2, characterized in that, The first control module includes a fourth PMOS transistor, a first inverter, and a fourth NMOS transistor; The gate of the fourth PMOS transistor is electrically connected to the first potential detection node, the source of the fourth PMOS transistor is electrically connected to the power supply terminal, and the drain of the fourth PMOS transistor is electrically connected to the input terminal of the first inverter. The fourth NMOS transistor and the first NMOS transistor form a third current mirror. The gate of the fourth NMOS transistor and the gate of the first NMOS transistor are electrically connected. The source of the fourth NMOS transistor is electrically connected to the input terminal of the first inverter. The drain of the fourth NMOS transistor is grounded. The first inverter outputs a first feedback signal, which controls the opening or closing of the positive high voltage second release path.

5. The high-voltage release control circuit according to claim 4, characterized in that, The positive high voltage second release path includes a fifth PMOS transistor and a third resistor; The first feedback signal is electrically connected to the gate of the fifth PMOS transistor to control the fifth PMOS transistor to turn on or off. The source of the fifth PMOS transistor is electrically connected to the positive high voltage input terminal, and the drain of the fifth PMOS transistor is electrically connected to one end of the third resistor, and the other end of the third resistor is grounded.

6. The high-voltage release control circuit according to claim 2, characterized in that, The negative high voltage first release path includes a sixth PMOS transistor, a seventh PMOS transistor, a fifth NMOS transistor, and a second resistor; The gate of the sixth PMOS transistor is electrically connected to the second release control signal, the source of the sixth PMOS transistor is electrically connected to the drain of the seventh PMOS transistor, and the source of the seventh PMOS transistor is electrically connected to the power supply terminal; the seventh PMOS transistor and the first PMOS transistor constitute a fourth current mirror, and the gate of the seventh PMOS transistor is electrically connected to the gate of the first PMOS transistor. The drain of the fifth NMOS transistor is electrically connected to the negative high voltage input terminal, the gate and source of the fifth NMOS transistor are shorted, the second resistor is electrically connected between the source of the fifth NMOS transistor and the drain of the sixth PMOS transistor, and the drain of the sixth PMOS transistor is the second potential detection node.

7. The high-voltage release control circuit according to claim 2, characterized in that, The second control module includes a sixth NMOS transistor, a second inverter, and an eighth PMOS transistor; The gate of the sixth NMOS transistor is electrically connected to the second potential detection node, the drain of the sixth NMOS transistor is grounded, and the source of the sixth NMOS transistor is electrically connected to the input terminal of the second inverter. The eighth PMOS transistor and the first PMOS transistor constitute the fifth current mirror. The gate of the eighth PMOS transistor and the gate of the first PMOS transistor are electrically connected. The drain of the eighth PMOS transistor is electrically connected to the input terminal of the second inverter. The source of the eighth PMOS transistor is electrically connected to the power supply terminal. The output terminal of the second inverter outputs a second feedback signal, which controls the opening or closing of the negative high voltage second release path.

8. The high-voltage release control circuit according to claim 7, characterized in that, The negative high voltage second release path includes a seventh NMOS transistor and a fourth resistor; The second feedback signal is electrically connected to the gate of the seventh NMOS transistor to control the turning on or off of the seventh NMOS transistor. The drain of the seventh NMOS transistor is electrically connected to the negative high voltage input terminal, and the source of the seventh NMOS transistor is electrically connected to one end of the fourth resistor, while the other end of the fourth resistor is grounded.

9. A flash memory chip, characterized in that, Includes the high-voltage release control circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes the flash memory chip as described in claim 9.

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