Memory performing compute operations

Abstract

The invention relates to a memory performing compute operations. A memory includes: a bit line; first to Nth cell groups (N is an integer of 2 or more), each cell group including a plurality of memory cells connected to a bit line; and first to Nth current supply circuits configured to supply current to the bit line. An amount of current of the first current supply circuit is determined based on a result of sensing a current flowing through the bit line in a state in which an input voltage is supplied to the memory cells of the first cell group. And a current amount of the k-th current supply circuit is determined based on a result of sensing a current flowing through the bit line in a state in which the input voltage is supplied to the memory cells of the first to k-th cell groups and the first to (k-1)-th current supply circuits are activated, where k is any integer ranging from 2 to N.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0164780, filed on November 19, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to memory, and more specifically, to a memory that performs computational operations. Background Technology

[0004] Electronic devices comprise many electronic components, and within electronic devices, computer systems comprise many electronic components made of semiconductors. In the semiconductors that make up a computer system, host devices such as processors or memory controllers perform data communication with the memory. The memory stores data by comprising a large number of storage cells arranged in multiple rows and columns.

[0005] Recently, technologies have been developed to utilize memory for computational operations in order to improve data processing performance. When memory performs computations directly internally without transferring data to the processor, latency caused by data movement can be reduced and energy efficiency can be improved. Summary of the Invention

[0006] In embodiments of this disclosure, a memory may include: a bit line; first to Nth cell groups, where N is an integer of 2 or greater, each cell group including a plurality of memory cells connected to the bit line; and first to Nth current supply circuits configured to supply current to the bit line, wherein the current amount of the first current supply circuit is determined based on the result of sensing the current flowing through the bit line when an input voltage is supplied to the memory cells of the first cell group, and the current amount of the kth current supply circuit is determined based on the result of sensing the current flowing through the bit line when an input voltage is supplied to the memory cells of the first to kth cell groups and the first to (k-1)th current supply circuits are activated, where k is any integer from 2 to N.

[0007] In embodiments of this disclosure, a method of operating a memory may include: applying a first input voltage to memory cells of a first group of cells connected to bit lines; generating a first coarse code by performing coarse analog-to-digital conversion on the current flowing through the memory cells of the first group of cells through the bit lines; supplying a first current corresponding to the first coarse code to the bit lines; applying a second input voltage to memory cells of a second group of cells connected to the bit lines; generating a second coarse code by performing coarse analog-to-digital conversion on the current flowing through the memory cells of the first group of cells, the memory cells of the second group of cells through the bit lines, and the first current; and supplying a second current corresponding to the second coarse code to the bit lines.

[0008] In embodiments of this disclosure, a memory may include: memory cells of a first group of cells connected to a bit line; a first current supply circuit configured to supply current to the bit line to compensate for current absorbed by the memory cells of the first group of cells from the bit line; memory cells of a second group of cells connected to the bit line; and a second current supply circuit configured to supply current to the bit line to compensate for current absorbed by the memory cells of the second group of cells from the bit line. Attached Figure Description

[0009] Figure 1 This demonstrates the mathematical formula for Multiply-Accumulate (MAC) computation, which is the core computation in deep learning.

[0010] Figure 2 This is a diagram illustrating the configuration of a memory according to an embodiment of the present disclosure.

[0011] Figure 3 This is a diagram illustrating the configuration of a memory according to another embodiment of the present disclosure.

[0012] Figures 4A to 4C It is shown in Figure 3 A diagram illustrating the process of performing MAC calculations in the memory. Detailed Implementation

[0013] Various embodiments of this disclosure are intended to provide a technique for improving the accuracy of computational operations of a memory by attenuating the IR voltage drop that occurs in the cell array of the memory.

[0014] According to embodiments of this disclosure, the accuracy of memory computation operations can be improved by attenuating the IR voltage drop that occurs in the cell array of the memory.

[0015] Hereinafter, embodiments based on the technical spirit of this disclosure will be described with reference to the accompanying drawings.

[0016] Figure 1 This demonstrates the mathematical formula for Multiply-Accumulate (MAC) computation, which is the core computation in deep learning.

[0017] The output I of a MAC calculation is defined as the sum of the products of the weights G and the input V. In MAC calculations using memory, the weights are represented by the conductance of the memory cells, hence the sign of the weights is G. The inputs are represented by voltage, hence the sign of the inputs is V. The outputs are represented by current, hence the sign of the outputs is I.

[0018] In the following memory embodiment, since the cell array size is 64×32, the number of inputs V is 64 (V1 to V2). 64 The number of outputs I is 32 (I1 to I). 32 The number of weights G is 2048 (G 1,1To G 32,64 ).

[0019] Figure 2 This is a diagram illustrating the configuration of a memory 200 according to an embodiment of the present disclosure.

[0020] Reference Figure 2 The memory 200 may include word lines WL1 to WL32, bit lines BL1 to BL32, source lines SL1 to SL64, and memory cells MC. 1,1 To MC 32,64 Voltage regulator 210 and analog-to-digital converter (ADC) 220.

[0021] In one embodiment, word lines WL1 to WL32 and bit lines BL1 to BL32 may extend alternately in a first direction. A word line WL and a bit line BL adjacent to each other may form a pair. Source lines SL1 to SL64 may extend in a second direction intersecting the first direction. For example, the second direction may be perpendicular to the first direction. Figure 2 The number of word lines WL1 to WL32, bit lines BL1 to BL32, and source lines SL1 to SL64 shown are merely examples and can be changed according to embodiments.

[0022] In one embodiment, the storage unit MC 1,1 To MC 32,64 It can be connected to one of the bit lines BL1 to BL32 and one of the source lines SL1 to SL64. Memory cell MC 1,1 To MC 32,64 Each of them can be connected to MC 1,1 To MC 32,64 Each connected bit line BL in the memory cell has the same word line number WL. 1,1 To MC 32,64 In the numbers, the first digit corresponds to the bit line BL and word line WL to which the memory cell is connected, and the second digit corresponds to the source line SL to which the memory cell is connected. Memory cell MC 1,1 To MC 32,64 Each of these may include a variable resistor G with a programmable resistance value and a transistor (e.g., an NMOS transistor). According to embodiments, the memory cell may be implemented using a phase-change random access memory (PRAM) cell, a resistive random access memory (RRAM) cell, a magnetic random access memory (MRAM) cell, a ferroelectric random access memory (FRAM) cell, etc.; however, embodiments are not limited thereto. According to embodiments, the variable resistor may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material; however, embodiments are not limited thereto.

[0023] In one embodiment, voltage regulator 210 may apply a constant bit line voltage VBL to the common node CN connected to bit lines BL1 to BL32. Voltage regulator 210 may include operational amplifier 211 and transistor 212. Hereinafter, the level of bit line voltage VBL applied to bit lines BL1 to BL32 during computation operations of memory 200 is shown as 0.1V.

[0024] In one embodiment, the ADC 220 can generate a result code MAC<0:12> by performing an analog-to-digital conversion on the current I. The result code MAC<0:12> can be a code corresponding to... Figure 1 Middle I j The numeric code for the value.

[0025] In one embodiment, the voltage regulator 210 and ADC 220 may not be provided for each bit line BL1 to BL32. That is, the voltage regulator 210 and ADC 220 may be commonly connected to the bit lines BL1 to BL32. Among the bit lines BL1 to BL32, word lines WL1 to WL32 can be used to select the bit line to be sensed by the ADC 220. When one of the word lines WL1 to WL32 is activated, the current flowing through the memory cell MC connected to the bit line BL corresponding to the activated word line WL can be converted (sensed) by the ADC 220. For example, when word line WL2 of the word lines WL1 to WL32 is activated, the current flowing through the turned-on memory cell MC... 2,1 To MC 2,64 A current path is formed between bit line BL2 and source lines SL1 to SL64, while the remaining memory cells MC are turned off. 1,1 To MC 1,64 and MC 3,1 To MC 32,64 No current path is formed between bit lines BL1 and BL3 to BL32 and source lines SL1 to SL64.

[0026] In one embodiment, bit lines BL1 to BL32 are shunt at shunt nodes SN1 to SN64. Figure 2In the diagram, although the number of shunt nodes SN1 to SN64 is shown as equal to the number of source lines SL1 to SL64, the shunt nodes SN can be set at regular intervals. For example, one shunt node SN can be assigned to four source lines SL. The IR voltage drop can be reduced by connecting bit lines BL1 to BL32 in parallel to decrease the resistance in the current path. As mentioned above, the current path between bit lines BL1 to BL32 and source lines SL1 to SL64 is formed only through the memory cell of one bit line BL selected by word line WL from bit lines BL1 to BL32. However, since all bit lines BL1 to BL32 are connected in parallel, the line resistance of bit line BL is reduced. For example, when word line WL7 is activated and a current path is formed between bit line BL7 and source lines SL1 to SL64, the resistance of bit line BL7 can be effectively reduced because bit lines BL1 to BL32 are connected in parallel.

[0027] The following describes the process of performing a MAC calculation operation in memory 200. During this process, word line WL1 is activated, bit line BL1 is selected, and... Figure 1 I1 is manipulated.

[0028] In one embodiment, when word line WL1 is activated, memory cell MC 1,1 To MC 1,64 The transistor can be turned on. Therefore, it can be used through the memory cell MC. 1,1 To MC 1,64 A current path is formed between bit line BL1 and source lines SL1 to SL64. Voltage regulator 210 can apply a bit line voltage VBL of 0.1V to bit line BL1.

[0029] In one embodiment, the input voltage V1' to V can be... 64 Apply to source lines SL1 to SL64. Corresponding to G 1,1 The current of *(0.1-V1') can be drawn from the bit line BL1 to the source line SL1, and corresponds to G 1,2 The current of *(0.1-V2') can be drawn from the bit line BL1 to the source line SL2. That is, corresponding to G... 1,i *(0.1-V i' The current can be absorbed from the bit line BL1 to the source line SLi. Here, G 1,i For storage unit MC 1,i The conductance of the variable resistor, and Figure 1 V in i 'with V i With V i =0.1-V i The relationship.

[0030] Therefore, corresponding to G 1,i *V i The current can flow from bit line BL1 to source lines SL1 to SL64. This current can be connected to... Figure 1 The current flowing from bit line BL1 to source lines SL1 through SL64 can be the same as the current flowing to the common node CN (i.e., Figure 2 The I) is the same. Therefore, the ADC 220 can perform analog-to-digital conversion on the current I and generate a value corresponding to the current I. Figure 1 The result code MAC<0:12> is the value of I1. It can be expected that by activating word lines WL2 through WL32 instead of word line WL1 to perform the same operation, not only will it generate... Figure 1 The value of I1, and also generates the values ​​corresponding to I2 to I 32 The result code is MAC<0:12>.

[0031] In one embodiment, to improve the accuracy of MAC calculations, the voltage level of bit line BL1 needs to be constantly maintained at 0.1V. However, due to the large current, i.e., the 64 memory cells MC... 1,1 To MC 1,64 The sum of the cell currents flows through bit line BL1. Therefore, even if the resistance of bit line BL1 is reduced by shunting nodes SN1 to SN64, it may not be possible to avoid IR voltage drop due to the resistance of bit line BL1. In other words, even if the voltage level at the upper end of bit line BL1 is maintained at 0.1V, this voltage level may not remain at 0.1V, but may gradually decrease towards the lower end of bit line BL1. Because the voltage level of bit line BL1 decreases towards the lower end and is not maintained at 0.1V, the IR voltage drop in memory cell MC... 1,1 To MC 1,64 The unit current may change towards the lower end, resulting in inaccurate MAC calculation results.

[0032] In one embodiment, the inaccuracy of MAC calculation results due to the IR voltage drop of bit line BL occurs not only on bit line BL1, but also when generating corresponding values ​​for I2 to I using other bit lines BL2 to BL32. 32 When the result code MAC<0:12> is displayed.

[0033] Figure 3 This is a diagram illustrating the configuration of a memory 300 according to another embodiment of the present disclosure.

[0034] Reference Figure 3 The memory 300 may include bit lines BL1, word lines WL1, source lines SL1 to SL64, and memory cells MC. 1,1 To MC 1,64The circuit includes current supply circuits 330_1 to 330_8, registers (REG) 340_1 to 340_8, voltage regulator 210, current mirror 350, coarse analog-to-digital converter (CRS ADC) 321, fine analog-to-digital converter (FINE ADC) 325, and result code generation circuit 360.

[0035] Figure 3 Only one word line WL1, one bit line BL1, and the memory cell MC corresponding to word line WL1 and bit line BL1 are shown. 1,1 To MC 1,64 Furthermore, the shunt node SN is not shown. However, the word line WL, bit line BL, memory cell MC, and shunt node SN can be connected with... Figure 2 Configure in the same way.

[0036] In one embodiment, the storage unit MC 1,1 To MC 1,64 It can be divided into multiple unit groups CG1 to CG8. Figure 3 In this context, a cell group can be allocated eight source lines, and the memory cell MC 1,1 To MC 1,64 It can be divided into the first to eighth unit groups CG1 to CG8.

[0037] In one embodiment, current supply circuits 330_1 to 330_8 can compensate for the current absorbed by the memory cells of the corresponding cell group from the bit line BL1. The first current supply circuit 330_1 can supply current to the bit line BL1 to compensate for the current absorbed by the memory cells MC of the first cell group CG1. 1,57 To MC 1,64 The current is drawn from bit line BL1 to source lines SL57 to SL64. The second current supply circuit 330_2 can supply current to bit line BL1 to compensate for the current in the memory cells MC of the second cell group CG2. 1,49 To MC 1,56 Current is drawn from bit line BL1 to source lines SL49 to SL56. Similarly, the third to eighth current supply circuits 330_3 to 330_8 can supply current to bit line BL1 to compensate for the memory cells MC of the third to eighth cell groups CG3 to CG8. 1,1 To MC 1,48 Current is drawn from bit line BL1 to source lines SL1 to SL48.

[0038] In one embodiment, REGs 340_1 to 340_8 may store coarse codes CRS1<0:1> to CRS8<0:1> for controlling the current amounts of current supply circuits 330_1 to 330_8, respectively. For example, the current amount of the first current supply circuit 330_1 may be determined by the first coarse code CRS1<0:1> stored in the first REG 340_1, while the current amount of the fifth current supply circuit 330_5 may be determined by the fifth coarse code CRS5<0:1> stored in the fifth REG 340_5.

[0039] In one embodiment, voltage regulator 210 can apply a bit line voltage VBL to the common node CN to which bit line BL1 is connected. Voltage regulator 210 may include operational amplifier 211 and transistor 212. Voltage regulator 210 can apply a bit line voltage VBL of 0.1V to bit line BL1 during computation operations.

[0040] In one embodiment, the current mirror 350 can mirror the current I flowing through the common node CN, i.e. the current flowing through the bit line BL1, and supply the mirrored current to the CRS ADC 321 and the FINE ADC 325.

[0041] In one embodiment, the CRS ADC 321 can generate coarse codes CRS1<0:1> to CRS8<0:1> by performing a coarse analog-to-digital conversion on the current I mirrored by the current mirror 350. The coarse codes CRS1<0:1> to CRS8<0:1> can be generated sequentially during the computation operation, as detailed below.

[0042] In one embodiment, the FINE ADC 325 can generate the fine code FINE<0:7> by performing a fine analog-to-digital conversion on the current I mirrored by the current mirror 350. The most significant bit of the fine code FINE<0:7> is FINE. <7> It can have binary weights, which are the least significant bits of the coarse code CRS<0:1>. <0> Half of it. Therefore, the least significant bit CRS in the coarse code CRS<0:1> is... <0> It can have a lower least significant bit than the finer code FINE<0:7>. <0> A value that is 256 times larger.

[0043] In one embodiment, the result code generation circuit 360 can generate the result code MAC<0:12> using coarse codes CRS1<0:1> to CRS8<0:1> and fine code FINE<0:7>. The result code generation circuit 360 can generate the lower MAC<0:7> of the result code MAC<0:12> as is, using the fine code FINE<0:7>. The result code generation circuit 360 can also generate the higher MAC<8:12> of the result code MAC<0:12> by adding the coarse codes CRS1<0:1> to CRS8<0:1>.

[0044] Refer to Table 1 below and Figures 4A to 4C Description in Figure 3 The MAC calculation process is performed in memory 300.

[0045] In the following text, the storage unit MC of the first unit group CG1 1,57 To MC 1,64 The current absorbed from bit line BL1 to source lines SL57 to SL64 is 23 μA. The memory cell MC of the second cell group CG2... 1,49 To MC 1,56 The current drawn from bit line BL1 to source lines SL49 to SL56 is 258 μA. The memory cell MC of the third cell group CG3... 1,41 To MC 1,48 The current absorbed from bit line BL1 to source lines SL41 to SL48 is 520μA. The memory cell MC of the fourth cell group CG4... 1,33 To MC 1,40 The current drawn from bit line BL1 to source lines SL33 to SL40 is 15μA. The memory cell MC of the fifth cell group CG5... 1,25 To MC 1,32 The current drawn from bit line BL1 to source lines SL25 to SL32 is 800μA. The memory cell MC of the sixth unit group CG6... 1,17 To MC 1,24 The current absorbed from bit line BL1 to source lines SL17 to SL24 is 300μA. The memory cell MC of the seventh cell group CG7... 1,9 To MC 1,16 The current drawn from bit line BL1 to source lines SL9 to SL16 is 612 μA, while the memory cell MC of the eighth cell group CG8... 1,1 To MC 1,8The current drawn from bit line BL1 to source lines SL1 through SL8 is 90 μA. The CRS ADC 321 is also described as performing analog-to-digital conversion on current I in units of 256 μA, with the current supply circuits 330_1 through 330_8 adjusted to one of 0 μA, 256 μA, 512 μA, and 768 μA. The FINE ADC 325 is also described as performing analog-to-digital conversion on current I in units of 1 μA.

[0046] Table 1

[0047]

[0048] (1) Generation of the first coarse code CRS1<0:1>

[0049] In one embodiment, the input voltage V 57 'To V 64 'The memory cells MC of the first cell group CG1 can be applied via source lines SL57 to SL64.' 1,57 To MC 1,64 (Operation 401). In this case, the same voltage of 0.1V as bit line BL1 can be applied to the memory cells MC of the remaining cell groups CG2 to CG8. 1,1 To MC 1,56 The source lines SL1 to SL56. That is, no current flows from bit line BL1 through the memory cells MC of cell groups CG2 to CG8. 1,1 To MC 1,56 The current flows to source lines SL1 to SL56. A current of 23μA can flow from bit line BL1 through the memory cell MC of the first cell group CG1. 1,57 To MC 1,64 The current is absorbed into the source lines SL57 to SL64, and this current becomes the current I of the bit line BL1.

[0050] In one embodiment, the CRS ADC 321 can generate a first coarse code CRS1<0:1> (operation 403) by performing a coarse analog-to-digital conversion on the current I of the bit line BL1 mirrored by the current mirror 350. Since the current I of the bit line BL1 is 23 μA and the conversion unit of the CRS ADC 321 is 256 μA, the first coarse code CRS1<0:1> can be generated as "00".

[0051] In one embodiment, the first coarse code CRS1<0:1> is stored in the first REG 340_1, and the first current supply circuit 330_1 can supply the current corresponding to the first coarse code CRS1<0:1> to the bit line BL1 (operation 405). Since the first coarse code CRS1<0:1> is "00", the first current supply circuit 330_1 can supply 0μA of current to the bit line BL1.

[0052] (2) Generation of the second coarse code CRS2<0:1>

[0053] Subsequently, the input voltage V 49 'To V 56 'The memory cells MC of the second unit group CG2 can be applied via source lines SL49 to SL56.' 1,49 To MC 1,56 (Operation 407). That is, the input voltage V can be... 49 'To V 64 The source lines SL49 to SL64 of the first cell group CG1 and the second cell group CG2 are applied, and the same voltage of 0.1V as bit line BL1 can be applied to the source lines SL1 to SL48 of the remaining cell groups CG3 to CG8. The memory cell MC of the first cell group CG1... 1,57 To MC 1,64 Storage unit MC of the second unit group CG2 1,49 To MC 1,56 The current absorbed from bit line BL1 and the current supplied by the first current supply circuit 330_1 can flow through bit line BL1. That is, a current I of 281μA (=23+258-0) can flow through bit line BL1.

[0054] The CRS ADC 321 can generate a second coarse code CRS2<0:1> (operation 409) by performing a coarse analog-to-digital conversion on the current I of the bit line BL1, which is mirrored by the current mirror 350. Since the current I of the bit line BL1 is 281μA and the conversion unit of the CRS ADC 321 is 256μA, the second coarse code CRS2<0:1> can be generated as "01".

[0055] The second coarse code CRS2<0:1> is stored in the second REG 340_2, and the second current supply circuit 330_2 can supply the current corresponding to the second coarse code CRS2<0:1> to the bit line BL1 (operation 411). Since the second coarse code CRS1<0:1> is "01", the second current supply circuit 330_2 can supply 256μA of current to the bit line BL1.

[0056] (3) Generation of the third coarse code CRS3<0:1>

[0057] Subsequently, the input voltage V 41 'To V 48 'The memory cell MC of the third unit group CG3 can be applied through source lines SL41 to SL48.' 1,41 To MC 1,48 (Operation 413). That is, the input voltage V can be... 41'To V 64 The source lines SL41 to SL64 of the first to third cell groups CG1 to CG3 are applied, and the same voltage of 0.1V, the same as bit line BL1, can be applied to the source lines SL1 to SL40 of the remaining cell groups CG4 to CG8. The memory cells MC of the first to third cell groups CG1 to CG3... 1,41 To MC 1,64 The current absorbed from bit line BL1 and the current supplied by the first current supply circuit 330_1 and the second current supply circuit 330_2 can flow through bit line BL1. That is, a current I of 545μA (=23+258+520-0-256) can flow through bit line BL1.

[0058] The CRS ADC 321 can generate the third coarse code CRS3<0:1> (operation 415) by performing a coarse analog-to-digital conversion on the current I of the bit line BL1, which is mirrored by the current mirror 350. Since the current I of the bit line BL1 is 545μA and the conversion unit of the CRS ADC 321 is 256μA, the third coarse code CRS3<0:1> can be generated as "10".

[0059] The third coarse code CRS3<0:1> is stored in the third REG 340_3, and the third current supply circuit 330_3 can supply the current corresponding to the third coarse code CRS3<0:1> to the bit line BL1 (operation 417). Since the third coarse code CRS1<0:1> is "10", the third current supply circuit 330_3 can supply 512μA of current to the bit line BL1.

[0060] (4) Generation of the fourth coarse code CRS4<0:1>

[0061] Subsequently, the input voltage V 33 'To V 40 'The memory cells MC of the fourth unit group CG4 can be applied via source lines SL33 to SL40.' 1,33 To MC 1,40 (Operation 419). That is, the input voltage V can be... 33 'To V 64 The source lines SL33 to SL64 of the first to fourth cell groups CG1 to CG4 are applied, and the same voltage of 0.1V, the same as bit line BL1, can be applied to the source lines SL1 to SL32 of the remaining cell groups CG5 to CG8. The memory cells MC of the first to fourth cell groups CG1 to CG4... 1,33 To MC 1,64The current absorbed from bit line BL1 and the current supplied by the first to third current supply circuits 330_1 to 330_3 can flow through bit line BL1. That is, a current I of 48μA (=23+258+520+15-0-256-512) can flow through bit line BL1.

[0062] The CRS ADC 321 can generate the fourth coarse code CRS4<0:1> (operation 421) by performing a coarse analog-to-digital conversion on the current I of the bit line BL1, which is mirrored by the current mirror 350. Since the current I of the bit line BL1 is 48μA and the conversion unit of the CRS ADC 321 is 256μA, the fourth coarse code CRS4<0:1> can be generated as "00".

[0063] The fourth coarse code CRS4<0:1> is stored in the fourth REG 340_4, and the fourth current supply circuit 330_4 can supply the current corresponding to the fourth coarse code CRS4<0:1> to the bit line BL1 (operation 423). Since the fourth coarse code CRS4<0:1> is "00", the fourth current supply circuit 330_4 can supply 0μA of current to the bit line BL1.

[0064] (5) Generation of the fifth coarse code CRS5<0:1>

[0065] Subsequently, the input voltage V 25 'To V 32 'The memory cell MC of the fifth unit group CG5 can be applied via source lines SL25 to SL32.' 1,25 To MC 1,32 (Operation 425). That is, the input voltage V can be... 25 'To V 64 The source lines SL25 to SL64 of the first to fifth cell groups CG1 to CG5 are applied, and the same voltage of 0.1V as bit line BL1 can be applied to the source lines SL1 to SL24 of the remaining cell groups CG6 to CG8. The memory cells MC of the first to fifth cell groups CG1 to CG5... 1,25 To MC 1,64 The current absorbed from bit line BL1 and the current supplied by the first to fourth current supply circuits 330_1 to 330_4 can flow through bit line BL1. That is, a current I of 848μA (=23+258+520+15+800-0-256-512-0) can flow through bit line BL1.

[0066] The CRS ADC 321 can generate the fifth coarse code CRS5<0:1> (operation 427) by performing a coarse analog-to-digital conversion on the current I of the bit line BL1, which is mirrored by the current mirror 350. Since the current I of the bit line BL1 is 848μA and the conversion unit of the CRS ADC 321 is 256μA, the fifth coarse code CRS5<0:1> can be generated as "11".

[0067] The fifth coarse code CRS5<0:1> is stored in the fifth REG 340_5, and the fifth current supply circuit 330_5 can supply the current corresponding to the fifth coarse code CRS5<0:1> to the bit line BL1 (operation 429). Since the fifth coarse code CRS5<0:1> is "11", the fifth current supply circuit 330_5 can supply 768μA of current to the bit line BL1.

[0068] (6) Generation of the sixth coarse code CRS6<0:1>

[0069] Subsequently, the input voltage V 17 'To V 24 'The memory cell MC of the sixth unit group CG6 can be applied via source lines SL17 to SL24.' 1,17 To MC 1,24 (Operation 431). That is, the input voltage V can be... 17 'To V 64 The source lines SL17 to SL64 of the first to sixth cell groups CG1 to CG6 are applied, and the same voltage of 0.1V as bit line BL1 can be applied to the source lines SL1 to SL16 of the remaining cell groups CG7 to CG8. The memory cells MC of the first to sixth cell groups CG1 to CG6... 1,17 To MC 1,64 The current absorbed from bit line BL1 and the current supplied by the first to fifth current supply circuits 330_1 to 330_5 can flow through bit line BL1. That is, a current I of 380μA (=23+258+520+15+800+300-0-256-512-0-768) can flow through bit line BL1.

[0070] The CRS ADC 321 can generate the sixth coarse code CRS6<0:1> (operation 433) by performing a coarse analog-to-digital conversion on the current I of the bit line BL1, which is mirrored by the current mirror 350. Since the current I of the bit line BL1 is 380μA and the conversion unit of the CRS ADC 321 is 256μA, the sixth coarse code CRS6<0:1> can be generated as "01".

[0071] The sixth coarse code CRS6<0:1> is stored in the sixth REG 340_6, and the sixth current supply circuit 330_6 can supply the current corresponding to the sixth coarse code CRS6<0:1> to the bit line BL1 (operation 435). Since the sixth coarse code CRS6<0:1> is "01", the sixth current supply circuit 330_6 can supply 256μA of current to the bit line BL1.

[0072] (7) Generation of the seventh coarse code CRS7<0:1>

[0073] Subsequently, the input voltage V9' to V 16 'The memory cell MC of the seventh unit group CG7 can be applied via source lines SL9 to SL16.' 1,9 To MC 1,16 (Operation 437). That is, the input voltage V9' can be changed to V... 64 The source lines SL9 to SL64 of the first to seventh cell groups CG1 to CG7 are applied, and the same voltage of 0.1V as bit line BL1 can be applied to the source lines SL1 to SL8 of the eighth cell group CG8. The memory cells MC of the first to seventh cell groups CG1 to CG7... 1,9 To MC 1,64 The current absorbed from bit line BL1 and the current supplied by the first to sixth current supply circuits 330_1 to 330_6 can flow through bit line BL1. That is, a current I of 736μA (=23+258+520+15+800+300+612-0-256-512-0-768-256) can flow through bit line BL1.

[0074] The CRS ADC 321 can generate the seventh coarse code CRS7<0:1> (operation 439) by performing a coarse analog-to-digital conversion on the current I of the bit line BL1, which is mirrored by the current mirror 350. Since the current I of the bit line BL1 is 736 μA and the conversion unit of the CRS ADC 321 is 256 μA, the seventh coarse code CRS7<0:1> can be generated as "10".

[0075] The seventh coarse code CRS7<0:1> is stored in the seventh REG 340_7, and the seventh current supply circuit 330_7 can supply the current corresponding to the seventh coarse code CRS7<0:1> to the bit line BL1 (operation 441). Since the seventh coarse code CRS7<0:1> is "10", the seventh current supply circuit 330_7 can supply 512μA of current to the bit line BL1.

[0076] (8) Generation of the eighth coarse code CRS8<0:1>

[0077] Subsequently, input voltages V1' to V8' can be applied to the memory cell MC of the eighth cell group CG8 via source lines SL1 to SL8. 1,1 To MC 1,8 (Operation 443). That is, the input voltage V1' to V... 64 'Source lines SL1 to SL64 can be applied to the first to eighth unit groups CG1 to CG8. Storage units MC of the first to eighth unit groups CG1 to CG8 1,1 To MC 1,64 The current absorbed from bit line BL1 and the current supplied by the first to seventh current supply circuits 330_1 to 330_7 can flow through bit line BL1. That is, a current I of 314μA (=23+258+520+15+800+300+612+90-0-256-512-0-768-256-512) can flow through bit line BL1.

[0078] The CRS ADC 321 can generate the eighth coarse code CRS8<0:1> (operation 445) by performing a coarse analog-to-digital conversion on the current I of the bit line BL1, which is mirrored by the current mirror 350. Since the current I of the bit line BL1 is 314μA and the conversion unit of the CRS ADC 321 is 256μA, the eighth coarse code CRS8<0:1> can be generated as "01".

[0079] The eighth coarse code CRS8<0:1> is stored in the eighth REG 340_8, and the eighth current supply circuit 330_8 can supply the current corresponding to the eighth coarse code CRS8<0:1> to the bit line BL1 (operation 447). Since the eighth coarse code CRS8<0:1> is "01", the eighth current supply circuit 330_8 can supply 256μA of current to the bit line BL1.

[0080] (9) Generation of fine code FINE<0:7> and result code MAC<0:12>

[0081] Subsequently, the storage units MC of the first to eighth unit groups CG1 to CG8 1,1 To MC 1,64 The current absorbed from bit line BL1 and the current supplied by the first to eighth current supply circuits 330_1 to 330_8 can flow through bit line BL1. That is, a current I of 58μA (=23+258+520+15+800+300+612+90-0-256-512-0-768-256-512-256) can flow through bit line BL1.

[0082] The FINE ADC 325 can generate the fine code FINE<0:7> (operation 449) by performing a fine analog-to-digital conversion on the current I of the bit line BL1, which is mirrored by the current mirror 350. Since the current I of the bit line BL1 is 58 μA and the conversion unit of the FINE ADC 325 is 1 μA, the fine code FINE<0:7> can be generated as "00111010".

[0083] The result code generation circuit 360 generates the result code MAC<0:12> using the first to eighth coarse codes CRS1<0:1> to CRS8<0:1> and the fine code FINE<0:7> (operation 451). The fine code FINE<0:7> can be generated as is the low-order MAC<0:7> of the result code MAC<0:12>. Therefore, the low-order MAC<0:7> of the result code MAC<0:12> can be “00111010”. The high-order MAC<8:12> of the result code MAC<0:12> can be generated by adding all the first to eighth coarse codes CRS1<0:1> to CRS8<0:1>. Therefore, the high-order MAC<8:12> of the result code MAC<0:12> can be generated as “01010”. As a result, the result code MAC<0:12> can be generated as “0101000111010”, and this value can correspond to Figure 1 The value of I1 in the table.

[0084] Based on the MAC calculation process described in (1) to (9) above, during the calculation operation, the storage units MC of cell groups CG1 to CG8... 1,1 To MC 1,64 The current drawn from bit line BL1 can be compensated by the current supplied by current supply circuits 330_1 to 330_8. Therefore, the current I in bit line BL1 will not increase significantly. Since the current flowing through bit line BL1 does not increase significantly, almost no IR voltage drop occurs in bit line BL1. As a result, the voltage level of bit line BL1 can be kept constant at 0.1V during the calculation operation. That is, the MAC calculation operation can be performed accurately.

[0085] Although it has been described that by using the memory cell MC connected to bit line BL1 1,1 To MC 1,64 calculate Figure 1 The I1 process, but it can be expected, Figure 1 I2 to I 32 The memory cells MC connected to parts 330_1 to 330_8, 340_1 to 340_8, 210, 350, 321, 325 and 360 can be used via bit lines BL2 to BL32. 2,1 To MC 32,64 To calculate.

[0086] Although embodiments based on the technical concept of this disclosure have been described above with reference to the accompanying drawings, this is merely for describing embodiments according to the concept of this disclosure, and this disclosure is not limited to the above embodiments. Those skilled in the art to which this disclosure pertains can make various types of substitutions, modifications, and changes to the embodiments without departing from the technical concept of this disclosure as defined in the following claims, and it should be understood that such substitutions, modifications, and changes fall within the scope of this disclosure. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A memory, comprising: Bit line; The first unit group to the Nth unit group, each unit group includes multiple storage units connected to the bit line, where N is an integer of 2 or greater; as well as The first current supply circuit to the Nth current supply circuit supplies current to the bit line. Wherein, the current quantity of the first current supply circuit is determined based on the result of sensing the current flowing through the bit line while the input voltage is supplied to the memory cell of the first cell group, and The current quantity of the k-th current supply circuit is determined based on the result of sensing the current flowing through the bit line when the input voltage is supplied to the memory cells of the first to the k-th cell groups and the first to the (k-1)-th current supply circuits are activated, where k is any integer from 2 to N.

2. The memory according to claim 1, further comprising: A voltage regulator that applies a constant voltage to the bit line; A current mirror that reflects the current flowing through the bit line; as well as A coarse analog-to-digital converter, which: performs analog-to-digital conversion on the current mirrored by the current mirror, and generates first coarse code to Nth coarse code for controlling the first current supply circuit to the Nth current supply circuit.

3. The memory according to claim 2, further comprising: A fine analog-to-digital converter, wherein, with an input voltage supplied to the storage cells of the first to the Nth cell groups and the first to the Nth current supply circuits activated, fine code is generated by performing analog-to-digital conversion on the current mirrored by the current mirror; and The result code generation circuit generates result code based on the first coarse code to the Nth coarse code and the fine code.

4. The memory according to claim 3, wherein, The result code generation circuit generates the high-order bits of the result code by adding the first coarse code to the Nth coarse code, and generates the low-order bits of the result code by adding the fine code.

5. The memory according to claim 1, further comprising: Multiple source lines are connected to the memory cells of the first unit group to the Nth unit group and input the input voltage.

6. The memory according to claim 1, wherein, Each of the plurality of storage cells has a variable resistor.

7. The memory according to claim 6, wherein, Each of the plurality of memory cells further includes a transistor for controlling the electrical connection of the source line corresponding to the variable resistor in response to the voltage level of the word line.

8. A method of operating a memory, the method comprising: A first input voltage is applied to the memory cell connected to the first group of bit lines; The first coarse code is generated by performing a coarse analog-to-digital conversion on the current flowing through the bit line in the storage cell of the first unit group; A first current corresponding to the first coarse code is supplied to the bit line; A second input voltage is applied to the memory cell connected to the second group of cells of the bit line; The second coarse code is generated by performing coarse analog-to-digital conversion on the current flowing through the bit line in the storage cells of the first unit group and the storage cells of the second unit group and the first current; as well as A second current corresponding to the second coarse code is supplied to the bit line.

9. The operating method according to claim 8, further comprising: An input voltage is applied to the memory cell connected to the kth cell group of the bit lines; The kth coarse code is generated by performing coarse analog-to-digital conversion on the current flowing through the bit lines of the memory cells from the first unit group to the kth unit group and the first current to the (k-1)th current. as well as Supply the bit line with the k-th current corresponding to the k-th coarse code. Specifically, the input voltage is repeatedly applied to the storage cell of the k-th cell group, the k-th coarse code is generated, and the k-th current is supplied to the bit line by increasing the value of k from 3 to N, where N is an integer greater than 3.

10. The operating method according to claim 9, further comprising: Fine code is generated by performing fine analog-to-digital conversion on the current flowing through the bit lines of the memory cells from the first group to the Nth group and the first current to the Nth current.

11. The operating method according to claim 10, further comprising: The high-order bits of the resulting code are generated by adding the first to the Nth coarse codes; as well as The fine code is generated as the low-order bits of the resulting code.

12. The operating method according to claim 9, wherein, Each memory cell in the first to Nth cell groups draws current from the bit line, the current being determined by the input voltage input to each memory cell and the programming resistance value of each memory cell.

13. A memory comprising: The first group of memory cells is connected to the bit lines; First current supply circuit, Specifically: a first current is supplied to the bit line to compensate for the current absorbed by the memory cells of the first cell group from the bit line; The storage cells of the second unit group are connected to the bit lines; as well as The second current supply circuit supplies a second current to the bit line to compensate for the current absorbed by the memory cells of the second cell group from the bit line.

14. The memory according to claim 13, further comprising: The storage units of the third unit group to the Nth unit group are connected to the bit line, where N is an integer greater than 3; as well as From the third current supply circuit to the Nth current supply circuit, Specifically, a third to Nth current is supplied to the bit line to compensate for the current absorbed by the memory cells of the third to Nth cell groups from the bit line.

15. The memory according to claim 14, further comprising: A voltage regulator that applies a constant voltage to the bit line; A current mirror that reflects the current flowing through the bit line; A coarse analog-to-digital converter that performs coarse analog-to-digital conversion on the current mirrored by the current mirror; as well as A fine analog-to-digital converter that performs fine analog-to-digital conversion on the current mirrored by the current mirror.

16. The memory according to claim 15, wherein, The current supply circuit of the kth current is controlled by the kth coarse code, where k is any integer from 2 to N. The k-th coarse code is generated by the coarse analog-to-digital converter when the storage cells of the first unit group to the k-th unit group are activated and the first current supply circuit to the (k-1)-th current supply circuit is activated, wherein when k is 1, all current supply circuits are deactivated.

17. The memory according to claim 16, further comprising: The result code generation circuit generates result code based on the first coarse code to the Nth coarse code and the fine code generated by the fine analog-to-digital converter.

18. The memory according to claim 17, wherein, The result code generation circuit generates the high-order bits of the result code by adding the first coarse code to the Nth coarse code, and generates the low-order bits of the result code by adding the fine code.

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