High-frequency pulse DC power supply output stability control device

Abstract

The application discloses a high-frequency pulse DC power output stability control device and belongs to the technical field of power supply control. The device proposes a state zeroing-knowledge injection control paradigm for the contradiction between overshoot and slow response after reset of the traditional controller in the pulse mode due to integral memory. At the starting moment of each pulse period, a pulse opening instruction is generated and a reset signal is generated with a delay, the integral capacitor is forced to discharge to make its output zero, and the overshoot risk is eliminated; according to the load current steady-state value collected during the last pulse off period and the current target duty cycle, a feedforward control value is determined; in the same control period when the integral value is zeroed, the feedforward value and the integral output value are added to generate a drive control signal, and finally the drive power switch output pulse current is modulated. Through the cooperation of physical state forced zeroing and system knowledge cross-period prediction injection, the application realizes the rapid and non-overshoot establishment of the pulse current, and effectively solves the dynamic performance bottleneck of the high-frequency pulse power supply.

Description

Technical Field

[0001] This application relates to the field of power control technology, and in particular to a high-frequency pulse DC power supply output stabilization control device. Background Technology

[0002] High-frequency pulsed DC power supplies are core equipment in fields such as electrochemical machining, material surface treatment, and special electroplating. Their performance directly depends on the quality of the output pulse current waveform, especially requiring a fast rise time and a stable flat top without overshoot at the moment the pulse starts. To achieve this goal, traditional control methods mainly rely on the classic proportional-integral-derivative (PID) controller or its simplified form, the proportional-integral (PI) controller.

[0003] However, applying this type of controller, designed for continuous systems, to pulse operating mode exposes inherent and irreconcilable contradictions. First, overshoot is significant. The integrator's presence gives it a memory function, continuously accumulating historical control errors. After a pulse cycle ends, the control output of the integrator does not return to zero but remains at a residual value. When a new pulse cycle begins, this historical residual value, representing the state of the previous cycle, is superimposed on the new error signal and acts on the power switch, often causing severe current overshoot at the moment the new pulse starts. This not only reduces process accuracy but may also damage the load equipment. To eliminate this overshoot, one direct approach is to reset the integrator to zero at the beginning of each pulse cycle; however, this immediately leads to a second problem: deteriorated response speed. After resetting, the integrator re-integrates from zero, failing to provide sufficient control at the initial stage of the pulse, resulting in a slow pulse current rise and poor dynamic response. For high-frequency pulse applications, the pulse width is extremely narrow, and the slow rise will severely compress the effective current flattening time, significantly reducing power supply efficiency and usability.

[0004] Existing technologies have proposed various improvement schemes to address the aforementioned contradictions, but all have significant limitations. For example, while simple feedforward open-loop control can accelerate the response, its control accuracy depends entirely on model accuracy, making it unable to adapt to load changes and exhibiting poor robustness. Using complex algorithms such as adaptive or predictive control, although theoretically able to balance performance, suffers from high algorithm complexity, high computational resource consumption, high implementation costs, and dynamic response speed constrained by algorithm convergence time, making it difficult to meet the stringent real-time requirements of high-frequency pulse control. Therefore, in the field of high-frequency pulse DC power supply control, how to fundamentally resolve the sharp contradiction between "eliminating overshoot" and "ensuring rapid response" at the pulse initiation moment, caused by the integrator's memory characteristics, especially under complex operating conditions with dynamically changing load and duty cycle, has become a long-standing and unresolved core technical bottleneck. Summary of the Invention

[0005] In order to overcome the above-mentioned defects of the prior art, embodiments of this application provide a high-frequency pulse DC power supply output stabilization control device to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the high-frequency pulse DC power supply output stabilization control device provided in this application specifically includes:

[0007] The instruction generation unit is configured to generate a pulse start instruction at the beginning of each pulse cycle;

[0008] A reset signal generation unit, whose input terminal is connected to the instruction generation unit, is configured to generate a reset signal after a hardware protection time delay in response to the pulse turn-on instruction, wherein the hardware protection time is greater than the response time of the integral control and reset unit and less than the turn-on delay time of the power switching device.

[0009] An integral control and reset unit, whose reset terminal is connected to the reset signal generation unit, is configured to discharge its integral capacitor under the control of the reset signal, so that the integral output value is reset to zero.

[0010] The feedforward control unit is configured to determine the feedforward control value based on the steady-state current value of the power supply acquired and latched during the previous pulse turn-off period and the target duty cycle of the current pulse period.

[0011] A signal synthesis unit, whose first input terminal is connected to the output terminal of the integral control and reset unit to obtain the integral output value, and whose second input terminal is connected to the output terminal of the feedforward control unit to obtain the feedforward control value, is configured to add the feedforward control value and the integral output value in the same control cycle when the integral output value is reset to zero, so as to generate a drive control signal;

[0012] A pulse width modulation and driving unit, connected to the signal synthesis unit, is configured to generate a pulse width modulation signal based on the driving control signal and drive the power switching device of the power supply to turn on to output a pulse current.

[0013] Optionally, the instruction generation unit is configured to generate a pulse start instruction at the beginning of each pulse cycle, specifically including: generating an enable signal with a fixed width at the beginning of each pulse cycle according to preset pulse frequency and duty cycle parameters, as the pulse start instruction.

[0014] Optionally, a reset signal generation unit, with its input connected to the instruction generation unit, is configured to generate a reset signal in response to the pulse enable instruction after a hardware protection time delay, wherein the hardware protection time is greater than the response time of the integral control and reset unit and less than the turn-on delay time of the power switching device, including:

[0015] The pulse activation command is delayed by a preset hardware protection time to generate a reset signal for the integral controller. The hardware protection time is greater than the response time of the integral controller and less than the turn-on delay time of the power switching device. The hardware protection time is determined based on the response characteristics of the integral controller and the switching speed of the power switching device.

[0016] Optionally, the hardware protection time in the reset signal generation unit is determined based on the response characteristics of the integral controller and the switching speed of the power switching device. Specifically, the duration of the reset signal is adjusted according to the integral time constant of the integral controller. For an integral controller with a large time constant, the duration of the reset signal is extended; for an integral controller with a small time constant, the duration of the reset signal is shortened. The hardware protection time is adjusted accordingly to ensure that the reset process is completed before the power switching device is turned on.

[0017] Optionally, the integral control and reset unit, with its reset terminal connected to the reset signal generation unit, is configured to discharge its integral capacitor under the control of the reset signal, thereby resetting the integral output value to zero. Specifically, this includes:

[0018] The reset signal is applied to the control terminal of the discharge switch device to turn on the discharge switch device, which is connected in parallel with the integrating capacitor;

[0019] The discharge circuit of the integrating capacitor is formed by the conducting discharge switching device, so that the charge stored on the integrating capacitor is released.

[0020] During the continuous conduction of the discharge circuit, the voltage across the integrating capacitor is monitored. When the voltage drops below the reset threshold voltage, it is determined that the integrated output value has been reset to zero, and the discharge switching device is turned off to disconnect the discharge circuit.

[0021] Optionally, the feedforward control unit is configured to determine a feedforward control value based on the steady-state current value of the power supply acquired and latched during the previous pulse turn-off period and the target duty cycle of the current pulse period, including:

[0022] During the previous pulse shutdown period, the output current of the power supply is continuously monitored. When it is determined that the rate of change of the output current is lower than the stability threshold, the current value at this moment is latched as the steady-state value of the current.

[0023] Using the latched steady-state current value and the target duty cycle as joint query inputs, a preset two-dimensional parameter mapping table is retrieved, and the corresponding feedforward control value is directly output.

[0024] Optionally, the step of obtaining the steady-state value of the current includes:

[0025] During the previous pulse turn-off period, multiple instantaneous values ​​of the output current are continuously acquired at a sampling frequency higher than the pulse frequency;

[0026] Calculate the rate of change of output current between adjacent sampling points;

[0027] When the absolute value of the rate of change is less than the stability judgment threshold for N consecutive sampling periods, the current output current value is latched as the steady-state current value.

[0028] Where N is an integer greater than 2, and the stability judgment threshold is preset based on the rated output current and load characteristics of the power supply.

[0029] Optionally, the two-dimensional parameter mapping table is established through the following offline calibration steps:

[0030] S21. Connect the power supply to the test load;

[0031] S22. Set the load current value and duty cycle value;

[0032] S23. After the pulse is turned on, adjust the feedforward injection amount until there is no overshoot on the rising edge of the pulse current and the setup time is the shortest. Record the feedforward injection amount at this time as the feedforward control value.

[0033] S24. Change the impedance of the test load, the load current value and the duty cycle value, and repeat steps S22 to S23 to obtain data points under different operating conditions.

[0034] S25: Organize all data points into the two-dimensional parameter mapping table indexed by the steady-state value of the load current and the target duty cycle.

[0035] Optionally, when the steady-state current value or the target duty cycle exceeds the index range of the two-dimensional parameter mapping table, the feedforward control value is calculated using an extrapolation algorithm based on the nearest neighbor index: the feedforward control value is based on the index point in the two-dimensional parameter mapping table that is closest to the two-dimensional query point formed by the steady-state current value and the target duty cycle;

[0036] Based on the direction and magnitude of the deviation between the two-dimensional query point and the nearest neighbor index point, the final feedforward control value is calculated according to a preset linear or nonlinear adjustment coefficient.

[0037] Optionally, a pulse width modulation and driving unit, connected to the signal synthesis unit, is configured to generate a pulse width modulation signal based on the driving control signal and drive the power switching device of the power supply to turn on to output a pulse current, specifically including:

[0038] The drive control signal is input to the first input terminal of a pulse width modulation comparator, and a periodic carrier signal is input to the second input terminal of the pulse width modulation comparator.

[0039] In the pulse width modulation comparator, the level of the drive control signal is compared with the instantaneous level of the periodic carrier signal to generate the pulse width modulation signal for controlling the on / off state of the power switching device;

[0040] The pulse width modulation signal is input to the input terminal of the drive circuit, and the drive circuit generates a drive level signal that matches the control terminal characteristics of the power switching device.

[0041] The power switching device is driven by the driving level signal, so that it is turned on and off according to the duty cycle of the pulse width modulation signal, thereby generating the pulse current at the output terminal of the power supply.

[0042] Compared with the prior art, this application has the following beneficial effects:

[0043] First, this invention fundamentally resolves the inherent contradiction between overshoot and response speed, achieving high-quality pulse current output. By forcibly resetting the physical state (integrating capacitor voltage) of the integrator controller to zero at the beginning of each pulse cycle, this invention completely eliminates residual control quantities caused by accumulated historical errors, eradicating the physical root cause of overshoot at the hardware level. Simultaneously, it creatively proposes a new paradigm of state zeroing-knowledge injection. Within the same control cycle, the feedforward control value, determined jointly by the previous cycle's load characteristic "snapshot" and the current target duty cycle, is synthesized with the zeroed integral output value. This feedforward value is essentially a cross-cycle predictive compensation, precisely providing the initial drive quantity required to match the current operating condition. This allows the pulse current to obtain strong drive in the first switching cycle, achieving instantaneous and rapid establishment, perfectly compensating for the response delay caused by integrator reset.

[0044] Secondly, it significantly improves the system's adaptability and overall robustness under dynamic operating conditions. This invention utilizes the system's silent period during pulse shutdown for lossless current sampling. The obtained steady-state current value purely reflects the real-time impedance characteristics of the load, ensuring the accuracy of the feedforward knowledge source. Based on this real-time load information and the target command, a pre-calibrated mapping relationship is jointly queried, enabling feedforward compensation to quickly adapt to load changes and duty cycle adjustments. The entire scheme solves complex dynamic optimization problems by combining offline calibration with online table lookup. While ensuring excellent dynamic performance (fast and without overshoot), it avoids complex online calculations, has a simple structure, and responds quickly, making it particularly suitable for high-frequency pulse application scenarios. Attached Figure Description

[0045] Figure 1 This is a flowchart illustrating a high-frequency pulsed DC power supply output stabilization control device provided in an embodiment of this application.

[0046] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0047] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” used in the embodiments of this invention are also intended to include the plural forms, and “multiple” generally includes at least two unless the context clearly indicates otherwise.

[0050] Depending on the context, the words “if” or “suppose” as used here can be interpreted as “when” or “in response to determination” or “in response to detection.” Similarly, depending on the context, the phrases “if determination” or “if detection (of the stated condition or event)” can be interpreted as “when determination” or “in response to determination” or “when detection (of the stated condition or event)” or “in response to detection (of the stated condition or event).”

[0051] Furthermore, the timing of the steps in the following embodiments is merely an example and not a strict limitation.

[0052] In practice, the server-side equipment deployed by the high-frequency pulsed DC power supply output stabilization control device may consist of one or more devices. This high-frequency pulsed DC power supply output stabilization control device can be implemented as a service instance, a virtual machine, or a hardware device. For example, the high-frequency pulsed DC power supply output stabilization control device can be implemented as a service instance deployed on one or more devices in a cloud node. Simply put, the high-frequency pulsed DC power supply output stabilization control device can be understood as software deployed on a cloud node, used to provide high-frequency pulsed DC power supply output stabilization control to each user terminal. Alternatively, the high-frequency pulsed DC power supply output stabilization control device can also be implemented as a virtual machine deployed on one or more devices in a cloud node. This virtual machine contains application software for managing each user terminal. Alternatively, the high-frequency pulsed DC power supply output stabilization control device can also be implemented as a server composed of numerous identical or different types of hardware devices, with one or more hardware devices configured to provide high-frequency pulsed DC power supply output stabilization control to each user terminal.

[0053] In terms of implementation, the high-frequency pulse DC power supply output stabilization control device and the user terminal are mutually compatible. That is, if the high-frequency pulse DC power supply output stabilization control device is implemented as an application installed on a cloud service platform, then the user terminal is implemented as a client that establishes a communication connection with the application; or if the high-frequency pulse DC power supply output stabilization control device is implemented as a website, then the user terminal is implemented as a webpage; or if the high-frequency pulse DC power supply output stabilization control device is implemented as a cloud service platform, then the user terminal is implemented as a mini-program in an instant messaging application.

[0054] like Figure 1 The figure shown is a system architecture diagram of a high-frequency pulse DC power supply output stabilization control device provided in an embodiment of the present invention.

[0055] The high-frequency pulsed DC power supply output stabilization control device 100 of this invention can be installed in a cloud server. In terms of implementation, it can be used as one or more service devices, or as an application installed in the cloud (e.g., a mobile service operator's server, server cluster, etc.), or it can be developed into a website. Depending on the functions implemented, the high-frequency pulsed DC power supply output stabilization control device 100 may include an instruction generation unit 101, a reset signal generation unit 102, an integral control and reset unit 103, a feedforward control unit 104, a signal synthesis unit 105, and a pulse width modulation and driving unit 106. The module described in this invention can also be called a unit, referring to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, stored in the memory of the electronic device.

[0056] In this embodiment of the invention, each of the above-mentioned modules in the high-frequency pulse DC power supply output stabilization control device can be implemented independently and called upon other modules. This "calling" can be understood as a module connecting to multiple modules of another type and providing corresponding services to those connected modules. For example, the sharing and evaluation module can call the same information acquisition module to obtain the information collected by that module. Based on the above characteristics, the high-frequency pulse DC power supply output stabilization control device provided in this embodiment of the invention can adjust the applicability of the high-frequency pulse DC power supply output stabilization control device architecture by adding modules and directly calling them without modifying the program code, achieving cluster-based horizontal expansion to quickly and flexibly expand the high-frequency pulse DC power supply output stabilization control device. In practical applications, the above-mentioned modules can be set in the same device or different devices, or they can be set in a virtual device, such as a service instance in a cloud server.

[0057] The following describes the components and specific workflow of the high-frequency pulse DC power supply output stabilization control device, using specific embodiments as examples:

[0058] The instruction generation unit 101 is configured to generate a pulse start instruction at the beginning of each pulse cycle.

[0059] In some embodiments, the instruction generation unit is configured to generate a pulse start instruction at the beginning of each pulse cycle, specifically including: generating an enable signal with a fixed width at the beginning of each pulse cycle according to preset pulse frequency and duty cycle parameters, as the pulse start instruction.

[0060] In this embodiment of the application, the instruction generation unit is configured to generate a pulse start instruction at the beginning of each pulse cycle.

[0061] In the embodiments of this application, the pulse period is the repetition time unit of the power supply output pulse current, which consists of a high-level pulse turn-on period and a low-level pulse turn-off period; the pulse turn-on command is a digital logic signal, and its effective edge marks the formal start of the energy output phase within the current pulse period.

[0062] In this embodiment, the implementation of this step relies on the timer module in the digital controller. Specifically, two key parameters are first set according to the target output waveform: the pulse repetition frequency and the pulse duty cycle. The pulse repetition frequency determines the total duration of the pulse cycle, and the pulse duty cycle determines the proportion of the pulse-on period within a pulse cycle. A timer inside the controller is set to a free-running mode synchronized with the pulse frequency, and the total duration of the pulse cycle is set by configuring the timer's period register. Simultaneously, a dedicated comparison register is set to a fixed value much smaller than the period value. When the timer's count value increments from zero, during the extremely short period when the count value is less than the comparison register value, the timer's output pin continuously outputs a high-level logic signal. The rising edge of this high-level signal occurs at the instant the timer's count value reaches zero, i.e., the absolute start point of each pulse cycle, and its falling edge is determined by the value of the comparison register, thus forming a narrow pulse with a fixed width. This narrow pulse, automatically generated by the hardware timer at the start of the cycle, is the pulse-on instruction. For example, if the desired pulse frequency is 10kHz, then the pulse period is 100 microseconds. The timer's period register is set to correspond to 100 microseconds, and the compare register is set to generate a pulse with a width of 1 microsecond. Thus, at the 0 microsecond of each 100 microsecond period, the timer hardware will automatically output a high-level signal that lasts for 1 microsecond, which serves as a precise pulse start instruction.

[0063] In the embodiments of this application, the pulse start command provides a precise and stable time reference for the entire control sequence. This command is the unified trigger origin for all subsequent control actions, especially the reset and feedforward injection coordinated operation, ensuring that the system can start working from a definite and consistent time point in each pulse cycle. This is the time synchronization prerequisite for solving the periodic overshoot problem.

[0064] In this embodiment, the connection between this step and subsequent steps is that its output directly drives the reset signal generation unit. The edge of the pulse start command is fed to the next unit as a trigger condition for starting the hardware protection delay and generating the reset signal, thereby transmitting the time information of the start of the cycle to the entire control chain.

[0065] The reset signal generation unit 102 has its input terminal connected to the instruction generation unit and is configured to generate a reset signal after a hardware protection time delay in response to the pulse turn-on instruction. The hardware protection time is greater than the response time of the integral control and reset unit and less than the turn-on delay time of the power switching device.

[0066] In some embodiments, a reset signal generating unit, whose input terminal is connected to the instruction generating unit, is configured to generate a reset signal after delaying for a hardware protection time in response to the pulse start instruction, where the hardware protection time is greater than the response time of the integral control and reset unit and less than the turn-on delay time of the power switch device, and includes:

[0067] Delay the pulse start instruction for a preset hardware protection time and then generate a reset signal for the integral controller. The hardware protection time is greater than the response time of the integral controller and less than the turn-on delay time of the power switch device, and the hardware protection time is determined according to the response characteristics of the integral controller and the switching speed of the power switch device.

[0068] In the embodiments of the present application, the reset signal generating unit is connected to the output terminal of the instruction generating unit and is configured to receive the pulse start instruction and correspondingly generate a reset signal for controlling the integral controller.

[0069] In the embodiments of the present application, the pulse start instruction is a periodic trigger signal provided by the instruction generating unit. The reset signal is an active logic level signal, and the duration of its effective level is designed to control the discharge circuit of the integral capacitor inside the integral controller to force it to be cleared. The hardware protection time is a preset time delay parameter, and the setting of this parameter aims to ensure a correct and safe timing relationship between the reset action of the integral controller and the driving action of the power switch device, thereby avoiding the control competition state at the hardware level.

[0070] In the embodiments of the present application, the core of implementing this step lies in a digital logic circuit or a dedicated delay chip with programmable delay function. After detecting the rising edge or falling edge of the pulse start instruction, the reset signal generating unit does not immediately output the reset signal, but starts an internal timing, and the length of this timing is the preset hardware protection time. Specifically, the value of the hardware protection time must satisfy a key timing inequality, that is, t_d>t_res and t_d<t_sw, where t_d represents the hardware protection time, t_res represents the response time of the integral controller, and t_sw represents the turn-on delay time of the power switch device. The response time t_res of the integral controller refers to the longest time required for the voltage of the internal integral capacitor to truly discharge to zero from when a valid signal is received at its reset terminal, which depends on the capacitance value of the integral capacitor and the impedance of the discharge circuit. The turn-on delay time t_sw of the power switch device refers to the time period from when the turn-on instruction is issued by the drive circuit to when the device is fully turned on and the main circuit current starts to be established.

[0071] For example, if the discharge time constant of the integrator controller is measured to be approximately 1 microsecond, then t_res can be set to 1.5 microseconds; if the delay from the gate voltage of the MOSFET power transistor rising to its threshold to full conduction is 3 microseconds, then t_sw can be set to 3 microseconds. According to the inequality, the hardware protection time t_d must be set between 1.5 microseconds and 3 microseconds, and a feasible value is 2 microseconds. The programmable delay logic in the reset signal generation unit is configured with a 2-microsecond delay. Therefore, when the pulse enable command arrives, the unit will wait for 2 microseconds before generating and outputting a valid reset signal with a certain pulse width. This delay operation ensures that when the reset signal takes effect and the integrator is forcibly cleared, the power switch drive signal ultimately caused by the pulse enable command has not yet turned on the main power transistor, thus completely eliminating the possibility of instantaneous overshoot caused by the residual historical value of the integrator directly acting on the already turned-on power transistor at the beginning of a new cycle.

[0072] In the embodiments of this application, the technical effect of generating a reset signal is to establish a safe control timing barrier. By forcibly inserting a waiting period that is longer than the time required for the integrator to reset but shorter than the power transistor turn-on delay, this step ensures that the critical operation of the integrator "returning to zero" can be completed 100% before the power output is established. This physically eliminates the path of overshoot caused by the intervention of historical states in the new cycle, which is the fundamental guarantee for achieving the goal of "no overshoot".

[0073] In this embodiment, the connection between this step and the preceding and following steps is that it plays a role in coordinating the timing. It receives a unified start time signal from the instruction generation unit and, by introducing a precise delay, converts this time signal into a safe reset trigger signal and outputs it to the subsequent integral control and reset unit. The setting of this delay is directly related to the dynamic characteristics of the two core components, the integral controller and the power switching device, so that the reset action and the power drive action of the entire system are decoupled in time and executed sequentially.

[0074] In some embodiments, the hardware protection time in the reset signal generation unit is determined based on the response characteristics of the integral controller and the switching speed of the power switching device. Specifically, the duration of the reset signal is adjusted according to the integral time constant of the integral controller. For an integral controller with a large time constant, the duration of the reset signal is extended; for an integral controller with a small time constant, the duration of the reset signal is shortened. The hardware protection time is adjusted accordingly to ensure that the reset process is completed before the power switching device is turned on.

[0075] In this embodiment, the specific value of the hardware protection time preset by the reset signal generation unit is determined based on the response characteristics of the integral controller and the switching speed of the power switching device. One of the core determination principles is to dynamically adjust it based on the integral time constant of the integral controller.

[0076] In the embodiments of this application, the integral time constant is a key physical parameter describing the dynamic response speed of the integral controller. It reflects how quickly the integrator output accumulates the input error signal. In hardware, it is mainly determined by the product of the integral resistor and the integral capacitor. The duration of the reset signal refers to the length of time that the reset signal remains at an effective level to drive the discharge circuit to conduct. It must ensure that the integral capacitor has enough time to complete the discharge.

[0077] In this embodiment, the specific implementation of this adjustment principle relies on prior measurements or model analysis of the integral controller hardware circuit. The implementation process does not employ a fixed delay value, but rather establishes a parameterized configuration mechanism. First, the integral time constant τ (τ = R_int × C_int, where R_int is the integrating resistor and C_int is the integrating capacitor) of the integral controller is determined by measurement or from the component datasheet. A larger integral time constant τ means a larger integrating capacitor or a higher discharge circuit impedance, resulting in a longer time required to discharge to zero voltage. Therefore, the hardware protection time t_d and the effective duration t_width of the reset signal need to be positively correlated with it. In practical operation, the measured τ value can be input into the control unit during the system initialization or parameter configuration phase. The control unit stores a preset mapping relationship or calculation formula, such as setting t_width=k×τ+t_margin, where k is a coefficient greater than 1 to ensure full discharge, and t_margin is a time margin. For an integral controller with a large time constant τ, the calculated t_width is longer, and the reset signal generation unit generates a wider effective pulse accordingly; conversely, for a controller with a smaller τ, a narrower effective pulse is generated.

[0078] For example, if an integral controller has a τ of 100 microseconds, and k = 1.2 and t_margin = 10 microseconds, then t_width = 130 microseconds is calculated. The reset signal will remain valid for 130 microseconds to ensure the large capacitor is fully discharged. However, if another integral controller has a τ of 10 microseconds, then t_width is only 22 microseconds. Simultaneously, the hardware protection time t_d itself needs to be coordinated with the adjusted total reset operation time to ensure that the entire reset process (including delay and discharge) is completely completed before the power switch is turned on. This adjustment can be accomplished using a variable counter in a programmable logic device or a configurable timer in a microcontroller.

[0079] In the embodiments of this application, the technical effect of adjusting the duration of the reset signal according to the integral time constant is to achieve precision and adaptability in the reset operation. It avoids two risks associated with using a fixed time: for slow integrators, insufficient reset time leads to incomplete capacitor discharge, with residual voltage becoming a potential overshoot risk in the next cycle; for fast integrators, excessively long reset time unnecessarily occupies valuable control time, potentially delaying subsequent control actions. Through adaptive adjustment, it ensures that the "state to zero" operation is thorough and efficient under any integrator characteristic, fundamentally consolidating the reliability of overshoot elimination.

[0080] In this embodiment, the connection between this adjustment principle and the overall control scheme lies in incorporating the physical characteristics of the integral controller into the timing design. It is no longer an isolated delay setting, but rather feeds back the dynamic performance parameters of the "integral control and reset unit" to the configuration logic of the "reset signal generation unit," ensuring that the preceding step (generating a reset) accurately adapts to the actual needs of the subsequent step (performing a reset). This reflects the collaborative design among the various components of the system, jointly serving the core objective of achieving a complete zeroing of the integral state within a safe timing range.

[0081] The integral control and reset unit 103, whose reset terminal is connected to the reset signal generation unit, is configured to discharge its integral capacitor under the control of the reset signal, so that the integral output value is reset to zero.

[0082] In some embodiments, the integral control and reset unit, with its reset terminal connected to the reset signal generation unit, is configured to discharge its integral capacitor under the control of the reset signal, thereby resetting the integral output value to zero. Specifically, this includes:

[0083] The reset signal is applied to the control terminal of the discharge switch device to turn on the discharge switch device, which is connected in parallel with the integrating capacitor;

[0084] The discharge circuit of the integrating capacitor is formed by the conducting discharge switching device, so that the charge stored on the integrating capacitor is released.

[0085] During the continuous conduction of the discharge circuit, the voltage across the integrating capacitor is monitored. When the voltage drops below the reset threshold voltage, it is determined that the integrated output value has been reset to zero, and the discharge switching device is turned off to disconnect the discharge circuit.

[0086] In this embodiment, the reset terminal of the integral control and reset unit receives a reset signal from the reset signal generation unit and performs a key operation under the control of the signal, namely, discharging the internal integral capacitor, thereby forcibly restoring the integral output value to zero.

[0087] In this embodiment, the integrating capacitor is the core physical component in the integrating controller that performs mathematical integration operations. The voltage value corresponding to the amount of charge stored at its two ends directly represents the integrated output value. The discharge switching device is a semiconductor switching element controlled by an external logic signal, such as a MOSFET transistor. The discharge circuit is a low-impedance current path provided by the conducting discharge switching device. The reset threshold voltage is a preset voltage reference value close to zero potential, used to determine whether the discharge process is complete.

[0088] In this embodiment, the implementation of this step involves a specific analog circuit structure and its control logic. The core of the integral control and reset unit is an analog integrator consisting of an operational amplifier, an integrating resistor, and an integrating capacitor. The integrating capacitor is connected in parallel to a MOSFET, which serves as a discharge switching device. The source and drain of the MOSFET are connected to the two ends of the integrating capacitor, respectively, and its gate serves as the control terminal to receive a reset signal. When the reset signal is valid, for example, it becomes high, and this high-level signal is applied to the gate of the MOSFET, causing the MOSFET to switch from the off state to the fully on state. Since the MOSFET exhibits extremely low on-resistance between its source and drain when it is on, a near-short-circuit low-impedance discharge loop is instantaneously established across the integrating capacitor. The charge stored on the integrating capacitor is rapidly released through this loop, and the voltage across it begins to drop rapidly.

[0089] To ensure complete discharge and avoid unnecessary power consumption, this embodiment also includes a voltage monitoring circuit. A high-input-impedance voltage comparator is connected across the integrating capacitor to continuously monitor its voltage. The other input of the comparator is connected to a reference source representing the reset threshold voltage, such as 0.1V. During the continuous conduction of the discharge circuit, the monitoring circuit continuously compares the capacitor voltage with this threshold. Once the capacitor voltage is detected to drop below 0.1V, the comparator output state flips, generating an indication signal. This indication signal is sent to the control logic, which then drives the reset signal to an invalid level (pull-down to low), thereby turning off the MOSFET switching device and actively disconnecting the discharge circuit. For example, if the integrating capacitor value is 1nF and the MOSFET on-resistance is 10 ohms, the time constant of the discharge circuit is only 10 nanoseconds. With the reset signal duration being several microseconds, the capacitor voltage can be pulled down to far below 0.1V in a very short time, and the switch is then turned off promptly.

[0090] In the embodiments of this application, the technical effect of discharging the integrating capacitor to reset the output to zero is to achieve an absolute reset of the physical state of the controller. This operation physically clears all the charge accumulated on the integrating capacitor due to historical errors, thereby completely erasing the "memory" of the integrator. This directly eliminates the root cause of output overshoot caused by the control residue of the previous cycle intervening in the new cycle, and is the decisive physical action to solve the "no overshoot" problem.

[0091] In this embodiment, this step is a specific implementation of the "state reset" stage in the entire control paradigm. It is directly controlled by the reset signal with protection timing generated by the preceding steps, ensuring that the reset action is performed within a safe time window. Its output result—the integral output value after reset—is a key input for the subsequent signal synthesis step. It provides a clean, zero-starting-from-zero reference platform for the injection of feedforward control values, enabling "knowledge injection" to take effect accurately in a state free from historical interference. The two work together to solve the response speed problem.

[0092] The feedforward control unit 104 is configured to determine the feedforward control value based on the steady-state current value of the power supply acquired and latched during the previous pulse turn-off period and the target duty cycle of the current pulse period.

[0093] In some embodiments, the feedforward control unit is configured to determine a feedforward control value based on the steady-state current value of the power supply acquired and latched during the previous pulse turn-off period and the target duty cycle of the current pulse period, including:

[0094] During the previous pulse shutdown period, the output current of the power supply is continuously monitored. When it is determined that the rate of change of the output current is lower than the stability threshold, the current value at this moment is latched as the steady-state value of the current.

[0095] Using the latched steady-state current value and the target duty cycle as joint query inputs, a preset two-dimensional parameter mapping table is retrieved, and the corresponding feedforward control value is directly output.

[0096] In this embodiment, the feedforward control unit is configured to perform a critical computational task, namely, to determine a feedforward control value based on the steady-state value of the power supply output current acquired and latched during the previous pulse turn-off period, combined with the target duty cycle of the current pulse period.

[0097] In this embodiment, the steady-state value of the power supply's output current specifically refers to a stable value that the current flowing through the load circuit reaches and remains stable during the pulse turn-off period when the power switching device is completely off and there is no power output at the power supply output terminal. This value is determined solely by the reference voltage source inside the power supply and the real-time impedance of the load, and is a pure electrical reflection of the load characteristics. The target duty cycle is the proportion of the desired on-time set by the user or the upper-level system for the pulse cycle that is about to begin. The feedforward control value is a pre-calculated control quantity whose purpose is to directly provide a drive signal close to the desired output at the moment the pulse is turned on, in order to compensate for the inertia of the system.

[0098] In the embodiments of this application, the implementation of this step is divided into two consecutive stages: obtaining the steady-state value of the current and calculating the feedforward control value by looking up a table.

[0099] In the first stage, during the off-peak period of the previous pulse cycle, the control unit initiates a high-speed sampling process. The analog-to-digital converter continuously samples the power supply's output current signal at a rate much higher than the pulse repetition frequency, for example, at 100kHz, ten times the pulse frequency. Each time a new sample value I[n] is obtained, the control unit immediately calculates the difference between it and the previous sample value I[n-1]. Based on the sampling frequency and the change in output current, the rate of change of the output current is calculated. This rate of change is compared with a preset stability threshold, which is typically set as a small percentage of the power supply's rated output current. A counter is installed within the control unit. When the absolute value of the rate of change ΔI calculated for multiple consecutive sampling cycles (e.g., 5 consecutive times) is less than this stability threshold, the logic circuit determines that the current has entered a stable state. At this time, the control unit triggers a latch to capture and save the current sample value I[n] at the current moment. This value is then recognized as the steady-state current value used for this calculation. .

[0100] In the second phase, at the start of the current pulse cycle, the control unit synchronously acquires two inputs: the one stored in the latch. and preset These two parameters form a join query key-value pair. , The system internally stores a two-dimensional parameter mapping table generated through offline experimental calibration. This table establishes a path from different "current-duty cycle" combinations to the optimal "feedforward control value". The correspondence between the key and value pairs, and the calculation logic of the control unit, such as a lookup table function, uses these key-value pairs as indexes to directly access the corresponding positions in the mapping table. This is due to the actual operating conditions... , The result may not be exactly equal to the discrete index points in the table. The system will use an interpolation algorithm, such as bilinear interpolation, to calculate the final result based on the four nearest neighbor entries. Where V_ref is the base, and R_load is... Indirectly, this is reflected in the calibration of different loads R_load and duty cycles through numerous experiments. The optimal And thus obtained.

[0101] In the embodiments of this application, the technical effect of determining the feedforward control value is to realize the "retention and reuse of system knowledge". It uses the system quiescent period (pulse turn-off period) to detect and lock the real-time impedance characteristics of the load without loss, and combined with the new control command, predicts the optimal initial thrust required for the system to quickly reach a new steady state. This directly compensates for the "historical information" lost due to the integrator being reset to zero, thereby solving the problem of slow system response and long rise time caused by reset.

[0102] In this embodiment, this step is the core of the "knowledge injection" stage in the entire control paradigm. The steady-state current value it relies on comes from the observation of the system state in the previous cycle, which reflects the knowledge transfer across cycles. The feedforward control value it outputs will be combined with the zeroed integral output value in the signal synthesis unit. This design enables the system to have a driving signal dominated by the accurate prediction value at the beginning of each cycle, thereby realizing a fast dynamic response without overshoot. Together with the "state zeroing" step, it solves the core contradiction in the background technology.

[0103] In some embodiments, the step of obtaining the steady-state value of the current includes:

[0104] During the previous pulse turn-off period, multiple instantaneous values ​​of the output current are continuously acquired at a sampling frequency higher than the pulse frequency;

[0105] Calculate the rate of change of output current between adjacent sampling points;

[0106] When the absolute value of the rate of change is less than the stability judgment threshold for N consecutive sampling periods, the current output current value is latched as the steady-state current value.

[0107] Where N is an integer greater than 2, and the stability judgment threshold is preset based on the rated output current and load characteristics of the power supply.

[0108] In this embodiment, the steady-state value of the current is obtained through a closed-loop process that includes high-speed sampling, dynamic calculation, and condition judgment.

[0109] In this embodiment, the instantaneous value of the output current is a discrete current data point acquired by a current sensor and an analog-to-digital converter at a specific moment; the stability judgment threshold is a boundary value used to distinguish whether the current signal has entered a stable state; N is a preset integer greater than 2, which specifies the continuous consistency condition required to judge the stable state.

[0110] In this embodiment, the implementation of this step first relies on the establishment of a hardware sampling link and the execution of a software judgment algorithm. After determining the start of the shutdown period in the previous pulse cycle, the control unit enables a high-speed analog-to-digital converter, which continuously samples the output current at a fixed frequency f_s, where f_s must be higher than the pulse repetition frequency f_p to ensure that sufficient dynamic details can be captured during the shutdown period. For example, f_s = 10 × f_p is set. Each time a new sample value I[k] is obtained, the control unit immediately reads the previous sample value I[k-1] from the memory and calculates the instantaneous rate of change of the current according to the sampling frequency and the formula ΔI[k] = I[k] - I[k-1]. At the same time, a preset stability judgment threshold ΔI_th is invoked. This threshold is usually set according to the rated output current I_rated of the power supply and the dynamic range of a typical load. For example, ΔI_th = 1% × I_rated. A counter is initialized to zero. For each calculated ΔI[k], its absolute value |ΔI[k]| is compared with ΔI_th. If |ΔI[k]| < ΔI_th, the counter is incremented; otherwise, the counter is cleared. Only when the counter accumulates to a preset integer N (e.g., N=5) does the control logic determine that the output current has stabilized for a sufficiently long time, and finally latches the current sampled value I[k] as the steady-state current value. This mechanism ensures that the latched current value is not an accidental quiet point, but the true electrical steady state reached by the system during the turn-off period, effectively filtering out turn-off transients or noise interference. For example, for a power supply with I_rated=10A and ΔI_th set to 0.1A, if the current change at 5 consecutive sampling points is less than 0.1A, it is determined to be stable, and the current value at the 5th point (e.g., 5.02A) is latched.

[0111] In this embodiment of the application, the technical effect of obtaining the steady-state current value in the manner described above is to ensure that the extracted load characteristic "snapshot" has high accuracy and reliability. Through high-frequency sampling and multi-cycle continuous judgment of the rate of change, this method can accurately capture the true steady-state current of the load circuit after the pulse is turned off. This current value directly and purely reflects the key system parameter of load impedance, laying a reliable data foundation for the accurate calculation of the feedforward value, thereby ensuring the effectiveness of "knowledge injection".

[0112] In this embodiment, this step is the first and crucial step in the feedforward control value determination process. It provides real-time and accurate load impedance information input for the entire cross-cycle predictive compensation mechanism, and the obtained value will be compared with the target duty cycle. Together, they act as a joint key to retrieve the pre-stored system knowledge base (two-dimensional mapping table), thereby driving the generation of accurate feedforward control values. The successful execution of this step provides indispensable real-time system status information for solving the problem of slow response after integrator reset.

[0113] In some embodiments, the two-dimensional parameter mapping table is established through the following offline calibration steps:

[0114] S21. Connect the power supply to the test load;

[0115] S22. Set the load current value and duty cycle value;

[0116] S23. After the pulse is turned on, adjust the feedforward injection amount until there is no overshoot on the rising edge of the pulse current and the setup time is the shortest. Record the feedforward injection amount at this time as the feedforward control value.

[0117] S24. Change the impedance of the test load, the load current value and the duty cycle value, and repeat steps S22 to S23 to obtain data points under different operating conditions.

[0118] S25: Organize all data points into the two-dimensional parameter mapping table indexed by the steady-state value of the load current and the target duty cycle.

[0119] In this embodiment of the application, the two-dimensional parameter mapping table is pre-established through a systematic offline calibration process, which aims to determine the optimal feedforward control value for the power supply under various load and command conditions.

[0120] In this embodiment, the test load is an electronic load device whose impedance value can be precisely set and adjusted to simulate various load conditions that the power supply may encounter in actual operation; the feedforward injection is an experimental variable that is manually or automatically adjusted during the calibration process, and its physical meaning is the same as the feedforward control value used in the final control, representing the control voltage or digital quantity directly applied to the pulse width modulation stage.

[0121] In this embodiment of the application, the implementation of the offline calibration step relies on a complete test system that includes a power supply to be calibrated, a programmable test load, a high-speed data acquisition device, and a control computer.

[0122] In step S21, the output of the power supply to be calibrated is connected to a programmable electronic load. In step S22, the operator sets two target parameters through a control computer: one is the desired steady-state value of the load current, which is achieved by setting the electronic load to constant current mode and assigning its current value; the other is the target duty cycle, which is input to the controller of the power supply to be calibrated. Step S23 is the core optimization step: the control computer instructs the power supply to start pulse output with the set duty cycle. At the same time, the computer captures the rising edge waveform of the pulse current in real time through a high-speed data acquisition card. The computer automatically or the operator manually adjusts the feedforward injection parameter fed into the power supply controller. The goal of the adjustment is to make the captured current waveform simultaneously meet two criteria: first, during the rise and after reaching the target value, the current absolutely does not exceed the positive overshoot of the target value; second, the settling time required for the current to rise from 10% to 90% of the target value is as short as possible. This is an iterative optimization process. When the unique feedforward injection quantity meets the two conditions of "no overshoot" and "shortest settling time", it is recorded as the optimal feedforward control value under that specific operating condition (current load current, current duty cycle); Step S24 aims to cover the entire operating range: systematically change the impedance value of the electronic load to generate different steady-state load current values, while traversing the possible range of target duty cycle values ​​(e.g., from 10% to 90%). For each new combination of "(steady-state load current value, target duty cycle)", the optimization recording process of steps S22 and S23 is repeated to obtain a large number of data points covering the entire operating plane; Step S25 performs data processing: sort and grid all the recorded data points with the steady-state load current value as one dimension and the target duty cycle as another dimension to form a structured lookup table, namely the two-dimensional parameter mapping table, which will be burned into the non-volatile memory of the power controller for online querying.

[0123] In this embodiment of the application, the technical effect of establishing a two-dimensional parameter mapping table through the offline calibration step is to construct a high-fidelity "system knowledge base". This knowledge base stores in advance the exact feedforward compensation amount required for the power supply to achieve optimal dynamic performance (i.e., fast and no overshoot) under various specific operating conditions in the form of experimental data. This ensures that during online control, the feedforward control unit can quickly retrieve a near-optimal solution based on real-time operating conditions, thereby fundamentally guaranteeing the accuracy and effectiveness of "knowledge injection" and enabling the system to have strong robustness and adaptability.

[0124] In this embodiment, the offline calibration step is a necessary preparation and foundation for realizing online high-performance control. The mapping table it establishes is the basis for real-time querying by the feedforward control unit during online operation. The quality of the mapping table directly determines the accuracy of the feedforward value in online control, and thus determines whether the response delay caused by the integrator reset can be reliably compensated. Therefore, this offline process is closely integrated with the online control process, and together they serve the core goal of resolving the contradiction between speed and no overshoot.

[0125] In some embodiments, when the steady-state current value or the target duty cycle exceeds the index range of the two-dimensional parameter mapping table, the feedforward control value is calculated using an extrapolation algorithm based on the nearest neighbor index: the feedforward control value is based on the index point in the two-dimensional parameter mapping table that is closest to the two-dimensional query point composed of the steady-state current value and the target duty cycle;

[0126] Based on the direction and magnitude of the deviation between the two-dimensional query point and the nearest neighbor index point, the final feedforward control value is calculated according to a preset linear or nonlinear adjustment coefficient.

[0127] In this embodiment, the two-dimensional query point is a two-dimensional coordinate point composed of the real-time acquired steady-state current value and the target duty cycle. The nearest neighbor index point is the known index point in the two-dimensional parameter mapping table whose coordinate value has the smallest Euclidean distance to the coordinate value of the two-dimensional query point in two-dimensional space. The extrapolation coefficient is a scaling factor pre-set according to the system characteristic model or boundary experimental data, used to convert the deviation outside the index point into the adjustment amount of the feedforward control value.

[0128] In this embodiment, the extrapolation algorithm comprises three specific steps: distance calculation, deviation evaluation, and numerical adjustment. First, the algorithm needs to determine the nearest neighbor index point. It will use the two-dimensional query point... With all index points in the mapping table Perform a traversal comparison. Calculate the Euclidean distance. Select to make The smallest index point and its corresponding feedforward control value As the basis for computation; next, the algorithm calculates the deviation between the two-dimensional query point and the nearest neighbor index point in two dimensions, i.e. and Then, adjustments are made according to preset rules. A typical linear extrapolation is implemented as follows: based on the direction (positive or negative) and magnitude of the deviation, multiply by a preset extrapolation coefficient in each dimension; the final feedforward control value... From the formula The calculation shows that, and These are the linear extrapolation coefficients for the current dimension and the duty cycle dimension, respectively. These coefficients can be determined by analyzing the gradient of the boundary data of the mapping table or by conducting a small number of extended calibration experiments.

[0129] For example, if the two-dimensional query point is ( The maximum current index of the mapping table is 10A, and the nearest neighbor index point is... ,but If preset Then it can be calculated that For nonlinear relationships, the adjustment term may include the square of the deviation or use other nonlinear functions. 0.1V.

[0130] In the embodiments of this application, the technical effect of using the extrapolation algorithm to calculate the feedforward control value is to extend the reliable operating boundary of the control system and enhance its adaptability. It ensures that even when the load or command condition slightly exceeds the pre-calibrated typical range, the system can still generate a reasonable feedforward value inferred from existing knowledge, rather than completely failing or using the default value. This maintains the continuity of the "knowledge injection" mechanism, so that under non-standard conditions, the system can still achieve rapid establishment and suppress overshoot as much as possible, thereby improving the robustness of the overall scheme.

[0131] In this embodiment, the extrapolation algorithm is a crucial fault-tolerant and extension module in the feedforward control value determination step. It serves as a powerful supplement to the two-dimensional parameter mapping table lookup function, seamlessly integrating with the lookup operation. When the query is successful, it directly outputs the value from the table; when the query overflows, it performs a reasonable deduction based on the most relevant knowledge (nearest neighbor points) within the table. This ensures that the feedforward control unit can output an effective control quantity under any real-time operating condition, thus working in conjunction with the integral reset operation to continuously and stably address the core technical problem of rapid, overshoot-free establishment.

[0132] The signal synthesis unit 105 has its first input terminal connected to the output terminal of the integral control and reset unit to obtain the integral output value, and its second input terminal connected to the output terminal of the feedforward control unit to obtain the feedforward control value. It is configured to add the feedforward control value and the integral output value in the same control cycle when the integral output value is reset to zero, so as to generate a drive control signal.

[0133] In this embodiment of the application, the signal synthesis unit has two input terminals, which are respectively connected to the output terminal of the integral control and reset unit and the output terminal of the feedforward control unit. The unit is configured to perform a key arithmetic and logic operation, that is, in the same control cycle in which the integral output value is reset to zero, the acquired feedforward control value and the integral output value are added together to generate the final drive control signal.

[0134] In the embodiments of this application, the drive control signal is an analog voltage or digital quantity that directly determines the duty cycle of the output of the pulse width modulation unit, and is the final instruction to control the operation of the power switching device; the same control cycle refers to a complete and fixed time segment in the digital control system from reading the input signal, executing the control algorithm to updating the output register.

[0135] In this embodiment, the core of this step lies in precise timing control and an arithmetic addition operation. The signal synthesis unit can be an adder circuit composed of operational amplifiers in hardware, or an arithmetic logic unit performing addition operations in a digital controller, its operation triggered by a strict time sequence. After the start of each pulse cycle, following a hardware protection time delay, the reset signal takes effect, and the integral capacitor in the integral control and reset unit is forcibly discharged. Almost simultaneously, the feedforward control unit, based on the steady-state current value of the previous cycle and the target duty cycle of the current cycle, outputs the feedforward control value through table lookup or calculation. The signal synthesis unit first samples at its first input terminal, and the integral output value obtained at this time... The value has been ensured to be zero; next, the feedforward control value is obtained at its second input; subsequently, within a very short and defined time window—that is, within the "same control cycle"—addition is performed, because... The result is zero, therefore the actual calculation result is This calculation and result update must be completed before the end of the current control cycle.

[0136] For example, in a digital control interrupt service routine with a period of 1 microsecond, the program sequentially performs the following operations: read (0V), Read (For example, 1.48V), perform addition 0 + 1.48 = 1.48, and write the result 1.48V to the drive control signal register. The entire "read-calculate-write" process must be completed before the end of this 1-microsecond interrupt, so as to ensure that from the next switching cycle, the PWM comparator uses the duty cycle driven by this synthesized signal.

[0137] In this embodiment, the technical effect of completing signal synthesis within the same control cycle is to achieve "seamless switching" and "instantaneous establishment" of the control state. Simultaneously with the physical clearing of the integrator's historical state, a feedforward control quantity precisely matching the current operating condition is immediately injected as the driving basis. This avoids the slow integral ramp-up process of the integrator starting from zero, allowing the pulse current to obtain a strong drive close to the final steady-state value in the first switching cycle, thereby greatly accelerating the response speed. Simultaneously, since the integrator starts from zero, overshoot is completely eliminated. This operation is the core action that directly resolves the contradiction between "speed" and "no overshoot."

[0138] In this embodiment, this step is the convergence point and final manifestation of the entire "state zeroing-knowledge injection" control paradigm. It directly receives and processes the "zeroing state" ( ) and "system knowledge" from the feedforward control unit ( By strictly synchronizing in time (same control cycle) and directly synthesizing mathematically, it merges two decoupled solutions that separately address overshoot and slow response into a unified, high-performance drive command. The output drive control signal directly determines the operation of the power stage.

[0139] The pulse width modulation and driving unit 106 is connected to the signal synthesis unit and is configured to generate a pulse width modulation signal based on the driving control signal and drive the power switching device of the power supply to turn on to output a pulse current.

[0140] In some embodiments, a pulse width modulation and driving unit, connected to the signal synthesis unit, is configured to generate a pulse width modulation signal based on the driving control signal and drive the power switching device of the power supply to turn on to output a pulse current, specifically including:

[0141] The drive control signal is input to the first input terminal of a pulse width modulation comparator, and a periodic carrier signal is input to the second input terminal of the pulse width modulation comparator.

[0142] In the pulse width modulation comparator, the level of the drive control signal is compared with the instantaneous level of the periodic carrier signal to generate the pulse width modulation signal for controlling the on / off state of the power switching device;

[0143] The pulse width modulation signal is input to the input terminal of the drive circuit, and the drive circuit generates a drive level signal that matches the control terminal characteristics of the power switching device.

[0144] The power switching device is driven by the driving level signal, so that it is turned on and off according to the duty cycle of the pulse width modulation signal, thereby generating the pulse current at the output terminal of the power supply.

[0145] In this embodiment, the pulse width modulation and driving unit is connected to the signal synthesis unit. This unit is configured to perform the final stage of power conversion, that is, to generate the corresponding pulse width modulation signal based on the driving control signal, and to control the power switching device of the power supply to be turned on through the driving circuit, so as to finally form the required pulse current at the output terminal.

[0146] In the embodiments of this application, the pulse width modulation signal is a digital pulse waveform with a variable duty cycle; the periodic carrier signal is a periodic analog waveform with a fixed frequency, such as a triangular wave or a sawtooth wave; the drive level signal is a signal whose voltage and current capabilities are fully matched to the electrical requirements of the control terminal (such as the gate) of the power switching device after level conversion and power amplification.

[0147] In this embodiment, this step is implemented sequentially by four sub-steps: comparison, conversion, amplification, and power execution. First, the drive control signal output by the signal synthesis unit is... (For example, an analog voltage of 1.48V or its corresponding digital value) is connected to the non-inverting input of a pulse width modulation comparator; simultaneously, a periodic carrier signal generated by an oscillator (for example, a triangular wave with an amplitude of 0 to 3.3V and a frequency of 100kHz) is input to the inverting input of the comparator. In the pulse width modulation comparator, its internal circuitry continuously... The instantaneous level value is compared with the instantaneous voltage value of the triangular wave in real time. According to the working principle of the comparator, when When the voltage level is higher than the instantaneous level of the triangular wave, the comparator outputs a high-level logic signal (e.g., 3.3V); otherwise, it outputs a low-level signal (e.g., 0V). Since the voltage of the triangular wave changes linearly with time, the duration of the comparator's high-level output is related to the voltage level of the triangular wave. The voltage magnitude is directly proportional, thus generating a duty cycle. The modulated PWM pulse sequence is the pulse width modulation signal. This PWM signal is then fed into a dedicated driver circuit. The primary function of this driver circuit is level conversion, such as converting the 3.3V logic level output from the controller to the +12V and -5V levels required by the power switching devices to ensure rapid and reliable turn-on and turn-off. The driver circuit may also provide electrical isolation to protect the control side. Finally, the high-voltage drive level signal output from the driver circuit is directly applied to the control terminal (gate) of the power switching device (such as a MOSFET or IGBT). When the drive level is high, the power switching device quickly turns on, the main power circuit of the power supply is connected, and current begins to flow to the load. When the drive level is low, the power switching device quickly turns off, cutting off the current. In this way, the power switching device strictly follows the duty cycle of the PWM signal for high-speed switching, thus forming a pulse current waveform with an amplitude corresponding to the duty cycle after the power supply's output filter network. For example, if... With a voltage of 1.48V and a peak value of 3.3V for the triangular wave, the generated PWM signal has a duty cycle of approximately 45%. The power switching device operates with a duty cycle of 45%, outputting the corresponding average current.

[0148] In the embodiments of this application, the technical effect of the pulse width modulation and driving steps is to ultimately convert precise digital or analog control quantities into precise physical power output. This is because the driving control signal... It is synthesized from a precise feedforward value and a zero-reset integral value. Therefore, the PWM signal modulated by it has an ideal duty cycle command that enables the output current to establish quickly and without overshoot from the beginning of the pulse period. Through the faithful execution of the power stage, a high-quality pulse current waveform with no overshoot and fast establishment is finally achieved on the load, which directly solves the core contradiction in the background technology.

[0149] In this embodiment, this step is the final execution link of the entire control chain. It receives high-performance drive instructions from the signal synthesis unit and physically implements them through standard PWM modulation and power drive mechanisms. The fast and accurate execution of this step ensures that the technical effects of all preceding steps (instruction generation, reset, feedforward calculation, signal synthesis) are accurately reflected in the final output current, thus completing the closed loop from control algorithm to excellent output performance.

[0150] In the embodiments provided in this application, it should be understood that the disclosed system can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and there may be other division methods in actual implementation.

[0151] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0152] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0153] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application.

[0154] The embodiments of this application can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence is the theory, system, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0155] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application.

Claims

1. A high-frequency pulse DC power supply output stabilization control device, characterized in that, The device includes: The instruction generation unit is configured to generate a pulse start instruction at the beginning of each pulse cycle; A reset signal generation unit, whose input terminal is connected to the instruction generation unit, is configured to generate a reset signal after a hardware protection time delay in response to the pulse turn-on instruction, wherein the hardware protection time is greater than the response time of the integral control and reset unit and less than the turn-on delay time of the power switching device. An integral control and reset unit, whose reset terminal is connected to the reset signal generation unit, is configured to discharge its integral capacitor under the control of the reset signal, so that the integral output value is reset to zero. The feedforward control unit is configured to determine the feedforward control value based on the steady-state current value of the power supply acquired and latched during the previous pulse turn-off period and the target duty cycle of the current pulse period. A signal synthesis unit, whose first input terminal is connected to the output terminal of the integral control and reset unit to obtain the integral output value, and whose second input terminal is connected to the output terminal of the feedforward control unit to obtain the feedforward control value, is configured to add the feedforward control value and the integral output value in the same control cycle when the integral output value is reset to zero, so as to generate a drive control signal; A pulse width modulation and driving unit, connected to the signal synthesis unit, is configured to generate a pulse width modulation signal based on the driving control signal and drive the power switching device of the power supply to turn on to output a pulse current.

2. The high-frequency pulse DC power supply output stabilization control device as described in claim 1, characterized in that, The instruction generation unit is configured to generate a pulse start instruction at the beginning of each pulse cycle, specifically including: generating an enable signal with a fixed width at the beginning of each pulse cycle according to preset pulse frequency and duty cycle parameters, as the pulse start instruction.

3. The high-frequency pulse DC power supply output stabilization control device as described in claim 1, characterized in that, A reset signal generation unit, whose input is connected to the instruction generation unit, is configured to generate a reset signal in response to the pulse enable instruction after a hardware protection time delay, wherein the hardware protection time is greater than the response time of the integral control and reset unit and less than the turn-on delay time of the power switching device, including: The pulse activation command is delayed by a preset hardware protection time to generate a reset signal for the integral controller. The hardware protection time is greater than the response time of the integral controller and less than the turn-on delay time of the power switching device. The hardware protection time is determined based on the response characteristics of the integral controller and the switching speed of the power switching device.

4. The high-frequency pulse DC power supply output stabilization control device as described in claim 3, characterized in that, The hardware protection time in the reset signal generation unit is determined based on the response characteristics of the integral controller and the switching speed of the power switching device. Specifically, the duration of the reset signal is adjusted according to the integral time constant of the integral controller. For an integral controller with a large time constant, the duration of the reset signal is extended, and for an integral controller with a small time constant, the duration of the reset signal is shortened. The hardware protection time is adjusted accordingly to ensure that the reset process is completed before the power switching device is turned on.

5. The high-frequency pulse DC power supply output stabilization control device as described in claim 1, characterized in that, An integral control and reset unit, whose reset terminal is connected to the reset signal generation unit, is configured to discharge its integral capacitor under the control of the reset signal, thereby resetting the integral output value to zero. Specifically, this includes: The reset signal is applied to the control terminal of the discharge switch device to turn on the discharge switch device, which is connected in parallel with the integrating capacitor; The discharge circuit of the integrating capacitor is formed by the conducting discharge switching device, so that the charge stored on the integrating capacitor is released. During the continuous conduction of the discharge circuit, the voltage across the integrating capacitor is monitored. When the voltage drops below the reset threshold voltage, it is determined that the integrated output value has been reset to zero, and the discharge switching device is turned off to disconnect the discharge circuit.

6. The high-frequency pulse DC power supply output stabilization control device as described in claim 2, characterized in that, The feedforward control unit is configured to determine feedforward control values ​​based on the steady-state current value of the power supply acquired and latched during the previous pulse turn-off period and the target duty cycle of the current pulse period, including: During the previous pulse shutdown period, the output current of the power supply is continuously monitored. When it is determined that the rate of change of the output current is lower than the stability threshold, the current value at this moment is latched as the steady-state value of the current. Using the latched steady-state current value and the target duty cycle as joint query inputs, a preset two-dimensional parameter mapping table is retrieved, and the corresponding feedforward control value is directly output.

7. The high-frequency pulse DC power supply output stabilization control device as described in claim 6, characterized in that, The steps for obtaining the steady-state value of the current include: During the previous pulse turn-off period, multiple instantaneous values ​​of the output current are continuously acquired at a sampling frequency higher than the pulse frequency; Calculate the rate of change of output current between adjacent sampling points; When the absolute value of the rate of change is less than the stability judgment threshold for N consecutive sampling periods, the current output current value is latched as the steady-state current value. Where N is an integer greater than 2, and the stability judgment threshold is preset based on the rated output current and load characteristics of the power supply.

8. The high-frequency pulse DC power supply output stabilization control device as described in claim 6, characterized in that, The two-dimensional parameter mapping table is established through the following offline calibration steps: S21. Connect the power supply to the test load; S22. Set the load current value and duty cycle value; S23. After the pulse is turned on, adjust the feedforward injection amount until there is no overshoot on the rising edge of the pulse current and the setup time is the shortest. Record the feedforward injection amount at this time as the feedforward control value. S24. Change the impedance of the test load, the load current value and the duty cycle value, and repeat steps S22 to S23 to obtain data points under different operating conditions. S25: Organize all data points into the two-dimensional parameter mapping table indexed by the steady-state value of the load current and the target duty cycle.

9. The high-frequency pulse DC power supply output stabilization control device as described in claim 6, characterized in that, When the steady-state current value or the target duty cycle exceeds the index range of the two-dimensional parameter mapping table, the feedforward control value is calculated using an extrapolation algorithm based on the nearest neighbor index: the feedforward control value is based on the index point in the two-dimensional parameter mapping table that is closest to the two-dimensional query point formed by the steady-state current value and the target duty cycle; Based on the direction and magnitude of the deviation between the two-dimensional query point and the nearest neighbor index point, the final feedforward control value is calculated according to a preset linear or nonlinear adjustment coefficient.

10. The high-frequency pulse DC power supply output stabilization control device as described in claim 1, characterized in that, A pulse width modulation and driving unit, connected to the signal synthesis unit, is configured to generate a pulse width modulation signal based on the driving control signal and drive the power switching device of the power supply to turn on to output a pulse current, specifically including: The drive control signal is input to the first input terminal of a pulse width modulation comparator, and a periodic carrier signal is input to the second input terminal of the pulse width modulation comparator. In the pulse width modulation comparator, the level of the drive control signal is compared with the instantaneous level of the periodic carrier signal to generate the pulse width modulation signal for controlling the on / off state of the power switching device; The pulse width modulation signal is input to the input terminal of the drive circuit, and the drive circuit generates a drive level signal that matches the control terminal characteristics of the power switching device. The power switching device is driven by the driving level signal, so that it is turned on and off according to the duty cycle of the pulse width modulation signal, thereby generating the pulse current at the output terminal of the power supply.

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