Digital-to-analog converter and successive approximation analog-to-digital converter

Abstract

The invention provides a digital-to-analog converter and a successive approximation type analog-to-digital converter. The digital-to-analog converter comprises a capacitor array which comprises a plurality of capacitor units. Each capacitor unit comprises a first electrode plate, a second electrode plate and a third electrode plate. In the sampling stage, the first electrode plate of each capacitor unit is connected with an input analog voltage signal, and the second electrode plate and the third electrode plate of each capacitor unit are connected with a common-mode voltage signal. In the quantization stage, the second electrode plate of each capacitor unit in at least part of the capacitor units is connected with one of a logic low level and a logic high level, and the third electrode plate is connected with the other one of the logic low level and the logic high level. And a first electrode plate of the capacitor unit is suspended and is used for outputting an analog voltage signal after digital-to-analog conversion. Therefore, by defining a new capacitor unit, a lower unit capacitance value can be obtained.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, and in particular to a digital-to-analog converter and a successive approximation analog-to-digital converter. Background Technology

[0002] Analog-to-digital converters (ADCs) bridge the gap between analog and digital signals. Successive Approximation Register (SAR) ADCs are widely used due to their simple structure and ease of manufacturing. Charge Redistribution Digital-to-Analog Converters (CDACs) are the core module of SAR ADCs in pursuit of low power consumption and high accuracy. Designing a CDAC requires an exponentially increasing capacitor array. However, due to limitations in manufacturing processes, the metal width cannot be zero, resulting in a minimum size and capacitance value for metal-oxide-semiconductor (MOM) capacitors manufactured using specific processes. This minimum capacitance value can be considered the unit capacitance. In other words, traditional MOM capacitors are limited by the inability to infinitely shrink the metal width, resulting in a larger layout area and an inability to achieve extremely low unit capacitance values. If the traditional method of paralleling unit capacitors is used to double the capacitance, the capacitor array in an N-bit successive approximation analog-to-digital converter would use 2... N Each unit capacitor requires a large layout area. Furthermore, the area of ​​the most significant bit (MSB) capacitor will be twice the area of ​​the least significant bit (LSB) capacitor. N-1 It is susceptible to capacitance mismatch due to process deviations.

[0003] Therefore, it is necessary to propose a new technical solution to address the above problems. Summary of the Invention

[0004] One of the objectives of this invention is to provide a digital-to-analog converter and a successive approximation analog-to-digital converter that defines a new capacitor unit that can achieve a lower unit capacitance value.

[0005] According to one aspect of the present invention, a digital-to-analog converter (DAC) is provided, comprising: a capacitor array including a plurality of capacitor units, each capacitor unit including a first electrode plate, a second electrode plate, and a third electrode plate, wherein a first sub-capacitor is formed between the first electrode plate and the second electrode plate, and a second sub-capacitor is formed between the first electrode plate and the third electrode plate, the capacitance values ​​of the first sub-capacitor and the second sub-capacitor being different; in a sampling phase, the first electrode plate of each capacitor unit is connected to an input analog voltage signal, and the second and third electrode plates of each capacitor unit are connected to a common-mode voltage signal; in a quantization phase, the second electrode plate of at least some of the plurality of capacitor units is connected to either a logic low level or a logic high level, and the third electrode plate is connected to the other of either a logic low level or a logic high level, wherein the first electrode plate of the capacitor unit is left floating and used to output the analog voltage signal after digital-to-analog conversion.

[0006] According to one aspect of the present invention, a successive approximation analog-to-digital converter is provided, comprising: two digital-to-analog converters as described above, a successive approximation logic unit, a comparator, and a sampling control switch.

[0007] Compared with the prior art, the present invention can achieve a lower unit capacitance value by defining a new capacitor unit. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0009] Figure 1 This is a three-dimensional structural diagram of the capacitor unit in one embodiment of the present invention;

[0010] Figure 2 This is a top view of a portion of the capacitor units in the capacitor array of the digital-to-analog converter in this invention, in one embodiment.

[0011] Figure 3 This is a top view of one embodiment of the successive approximation analog-to-digital converter of the present invention. Detailed Implementation

[0012] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0013] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that excludes other embodiments. Unless otherwise specified, the terms "connected," "linked," and "connected" used herein to indicate electrical connection refer to direct or indirect electrical connection.

[0014] This invention provides a novel charge redistribution digital-to-analog converter (CDAC) that employs new capacitor cells in its capacitor array, thereby achieving extremely low unit capacitance values ​​and realizing capacitance doubling with a smaller layout area. The CDAC can be applied to successive approximation analog-to-digital converters. However, in other embodiments, the CDAC is not limited to successive approximation analog-to-digital converters and can be used in other applicable applications.

[0015] like Figure 1 and 2 As shown, the digital-to-analog converter includes a capacitor array. The capacitor array includes multiple capacitor units. , , , , Wait. In Figure 2 The illustrated embodiment shows five capacitor units, but in practice, there can be more capacitor units, such as 8 or 16, or fewer, such as 4. Each capacitor unit can be a MOM capacitor.

[0016] In one embodiment, such as Figure 2 As shown, each capacitor unit (e.g.) , , , , The device includes a first electrode plate 110, a second electrode plate 120, and a third electrode plate 130. A first sub-capacitor is formed between the first electrode plate 110 and the second electrode plate 120, and a second sub-capacitor is formed between the first electrode plate 110 and the third electrode plate 130. The capacitance values ​​of the first sub-capacitor and the second sub-capacitor are different.

[0017] During the sampling phase, the first electrode plate 110 of each capacitor unit is connected to the input analog voltage signal, and the second electrode plate 120 and the third electrode plate 130 of each capacitor unit are connected to the common-mode voltage signal V. cm Connected. Preferably, the input analog voltage signal can be the analog signal that the successive approximation analog-to-digital converter needs to convert to digital.

[0018] During the quantization phase, in at least some of the capacitor cells, the second electrode plate of each capacitor cell is connected to either a logic low level or a logic high level, and the third electrode plate is connected to the other logic low level or a logic high level. The first electrode plate of the capacitor cell is left floating and used to output the analog voltage signal after digital-to-analog conversion. Preferably, the logic low level or logic high level is obtained based on the digital switching signal generated by the successive approximation logic unit in the successive approximation analog-to-digital converter.

[0019] Thus, some or all of the capacitor cells whose second and third electrode plates are connected to a logic low or logic high level are enabled or used. During the quantization phase, the second and third electrode plates of each of the unused or enabled capacitor cells remain connected to the common-mode voltage signal.

[0020] Each digital switch signal corresponds to one capacitor cell, and multiple digital switch signals correspond to multiple capacitor cells. These multiple digital switch signals form a digital code. In one example, when the digital switch signal corresponding to a capacitor cell is 0, it indicates that the corresponding capacitor cell is not used. In this case, both the second and third electrodes of the capacitor cell are connected to the common-mode voltage signal. When the digital switch signal corresponding to a capacitor cell is 1, it indicates that the corresponding capacitor cell is used. In this case, the second electrode of the capacitor cell is connected to either a logic low level or a logic high level, and the third electrode is connected to the other logic low level or a logic high level. In another example, a digital switch signal of 0 can indicate that the corresponding capacitor cell is used, and a digital switch signal of 1 can indicate that the corresponding capacitor cell is not used.

[0021] In another embodiment, the digital switch signal corresponding to a capacitor unit also includes a bit used to indicate which of the second and third electrode plates of the capacitor unit is connected to a logic low level or a logic high level. For example, when the bit is 0, it can indicate that the second electrode plate is connected to a logic low level and the third electrode plate is connected to a logic high level. When the bit is 1, it can indicate that the second electrode plate is connected to a logic high level and the third electrode plate is connected to a logic low level.

[0022] Preferably, the first electrode plates 110 of each capacitor unit in the capacitor array are interconnected.

[0023] The digital-to-analog converter (DAC) works by utilizing the principle that the voltage difference across a capacitor cell cannot change abruptly. During the quantization stage, the voltage value of the first electrode cell is changed by altering the voltage values ​​of the second / third electrode plates. This effectively converts the digital switch signal into an analog voltage signal. Because the DAC contains multiple capacitor cells, it receives multiple digital switch signals, such as "10101101".

[0024] One of the advantages, features, or benefits of this invention is that the capacitance value of the capacitor unit is determined based on the difference between the capacitance value of the first sub-capacitor and the capacitance value of the second sub-capacitor. This allows the capacitance value of the capacitor unit with the smallest capacitance value (i.e., the unit capacitance value) to be designed to be very small, breaking through the process limitations in the prior art and achieving the function of doubling the capacitance value with a smaller layout area.

[0025] In one embodiment, such as Figure 1 , 2 As shown, the first electrode plate 110 is frame-shaped, and the second electrode plate 120 and the third electrode plate 130 are located within the frame-shaped first electrode plate. The second electrode plate 120 and the third electrode plate 130 are strip-shaped, with the length of the second electrode plate 120 greater than the length of the third electrode plate 130. Because the length of the second electrode plate 120 is greater than the length of the third electrode plate 130, the relative area of ​​the electrodes of the second and first electrode plates is greater than the relative area of ​​the electrodes of the third and first electrode plates, resulting in the capacitance value of the first sub-capacitor being greater than the capacitance value of the second sub-capacitor. The capacitance value of the capacitor unit is equal to the difference between the capacitance values ​​of the first and second sub-capacitors. By controlling the difference between the lengths of the second electrode plate 120 and the third electrode plate 130, the capacitance value of the capacitor unit can be controlled, thus allowing the capacitance value of the capacitor unit to be designed to be as small as possible.

[0026] In an alternative embodiment, the first electrode plate 110 may also be elongated, with the second electrode plate 120 and the third electrode plate 130 located on one or both sides of the elongated first electrode plate. In another alternative embodiment, the first electrode plate 110 may also be L-shaped. Furthermore, the second electrode plate 120 and the third electrode plate 130 may be frame-shaped, L-shaped, or other matching shapes. By setting the relative shapes and positions of the first electrode plate 110, the second electrode plate 120, and the third electrode plate 130, the relative area of ​​the electrodes of the second electrode plate and the first electrode plate is greater than the relative area of ​​the electrodes of the third electrode plate and the first electrode plate, thereby making the capacitance value of the first sub-capacitor greater than the capacitance value of the second sub-capacitor. By controlling the difference between the capacitance values ​​of the first and second sub-capacitors, the capacitance value of the capacitor unit can be controlled, thus allowing the unit capacitance value to be designed to be as small as possible.

[0027] like Figure 2 As shown, the 0th capacitor unit among the plurality of capacitor units The capacitance value is the smallest, and can be called the unit capacitance, with a capacitance of Cr. The capacitance value of the nth capacitor unit in the plurality of capacitor units is 2 times that of Cr. n The multiple, where n is the index of the capacitor unit, ranging from 0 to N, where N is a natural number greater than or equal to 1, and N+1 is the total number of capacitor units. For example, the first capacitor unit... The capacitance value is 2 of Cr 1 2Cr; the second capacitor unit The capacitance value is 2 of Cr 2 4Cr, the third capacitor unit. The capacitance value is 2 of Cr 3 10 times, i.e., 8Cr, the 4th capacitor unit The capacitance value is 2 of Cr 4 The number of times is 16Cr, and so on.

[0028] More specifically, such as Figure 2 As shown, the difference between the length of the second electrode plate 120 and the length of the third electrode plate 130 of the 0th capacitor unit is 2Δ, that is, the length of the second electrode plate 120 of the 0th capacitor unit is greater than that of the common-mode capacitor unit C. m The reference electrode plate 180 is Δ in length, where Δ is the unit length increment; the third electrode plate 130 of the 0th capacitor unit is compared with the common-mode capacitor unit C. m The reference electrode plate is 180 short Δ, that is, the difference between the length of the second electrode plate and the length of the third electrode plate of the 0th capacitor unit is 2Δ.

[0029] Thus, the capacitance value of the 0th capacitor unit for:

[0030] ;

[0031] ；

[0032] ;

[0033] Where C0 is the capacitance value of the first sub-capacitor of the 0th capacitor unit, and C0' is the capacitance value of the second sub-capacitor of the 0th capacitor unit. m For common-mode capacitor unit C m The capacitance value, C Δ This represents the capacitance value between the unit length increment Δ and the first electrode plate 110. The smaller Δ is, the greater C is. ΔThe smaller the value, the closer it can be to 0. However, excessively small unit capacitance can lead to significant noise effects, thus requiring a compromise design. m This term is canceled out during differential calculation, and therefore does not affect the effective capacitance value of the capacitor cell.

[0034] like Figure 2 As shown, the difference between the length of the second electrode plate 120 and the length of the third electrode plate 130 of the first capacitor unit is 4Δ, that is, the length of the second electrode plate 120 of the first capacitor unit is greater than that of the common-mode capacitor unit C. m The reference electrode plate 180 is 2Δ long; the third electrode plate 130 of the first capacitor unit is compared with the common-mode capacitor unit C. m The reference electrode plate is 180° shorter than 2Δ, meaning the difference between the length of the second electrode plate and the length of the third electrode plate of the first capacitor unit is 4Δ.

[0035] Thus, the capacitance value of the first capacitor unit for:

[0036] ;

[0037] ；

[0038] ;

[0039] Where C1 is the capacitance value of the first sub-capacitor of the first capacitor unit, and C1' is the capacitance value of the second sub-capacitor of the first capacitor unit. m For common-mode capacitor unit C m The capacitance value.

[0040] The difference between the length of the second electrode plate 120 and the length of the third electrode plate 130 of the second capacitor unit is 8Δ, that is, the length of the second electrode plate 120 of the second capacitor unit is greater than that of the common-mode capacitor unit C. m The reference electrode plate 180 is 4Δ long; the third electrode plate 130 of the second capacitor unit is larger than that of the common-mode capacitor unit C. m The reference electrode plate is 180° shorter than 4Δ, meaning the difference between the length of the second electrode plate and the length of the third electrode plate of the second capacitor unit is 8Δ.

[0041] Thus, the capacitance value of the second capacitor unit for:

[0042] ;

[0043] ；

[0044] ;

[0045] Where C2 is the capacitance value of the first sub-capacitor of the second capacitor unit, and C2' is the capacitance value of the second sub-capacitor of the second capacitor unit. m For common-mode capacitor unit C m The capacitance value.

[0046] In this way, subsequent capacitor units (i.e., higher-order capacitor units) can be increased proportionally by adding C. Δ The coefficients are realized (e.g.) = 8C Δ , = 16C Δ (etc.), forming a linearly growing effective capacity sequence.

[0047] In the above capacitor unit, different effective capacitance values ​​are achieved by scaling the lengths of the second and third electrode plates.

[0048] In the quantization phase, the first plate is left floating, the second plate is connected to a logic high level, and the third plate is connected to a logic low level. Therefore, the actual effective capacitance value is the difference between the first and second sub-capacitors, C. m The parasitic effects of the second and third electrode plates on the shielding layer are also canceled out during this process. Common-mode voltage signal V cm The parasitic effect of the first electrode plate on the shielding layer will be canceled out in the differential CDAC structure (e.g., Figure 3 The first CDAC and the second CDAC in the process.

[0049] When designing a multi-bit CDAC using the above structure, the effective capacitance of the capacitor unit is the difference between the capacitance value of the first sub-capacitor and the capacitance value of the second sub-capacitor. This effective capacitance can be designed to be an extremely small value; however, because of C... m The presence of this (which will be a large value) will affect the effective input range of the CDAC. If all the capacitor cells in the capacitor array are implemented using only the length scaling of the second and third electrode plates, for example, in a 14-bit SAR ADC, each of the 14 different bits would require an exceptionally long MOM capacitor, resulting in a huge total capacitance (the total capacitance is the sum of all C...). m and C Δ The sum of these values ​​makes them difficult to use. Therefore, the low-order capacitor cells in the CDAC utilize the length scaling of the second and third electrode plates to multiply the capacitance value (e.g., ...). Figure 2 shown The capacitor unit is formed by using a scheme of long and short second electrode plates. The high-order portion of the CDAC uses the maximum effective capacitance connected in parallel to multiply the capacitance value (e.g., ...). Figure 2 shown It consists of two Formed in parallel, Figure 2The middle only shows If there are higher-order capacitor units, multiple units can also be used. (Formed in parallel), achieving a good compromise in total capacity, area, and matching.

[0050] Specifically, in this invention, the difference between the length of the second electrode plate and the length of the third electrode plate of the nth capacitor unit in the (1-M)th capacitor unit is 2. n *2Δ, where M is a natural number greater than or equal to 1 and less than or equal to N. Figure 2 In the embodiment shown, M is 3, that is Different effective capacitance values ​​are achieved by scaling the lengths of the second and third electrode plates. This type of capacitor unit can form an effective capacitance through the length difference between the second and third electrode plates, without being limited by the minimum width of the manufacturing process, thus achieving extremely low unit capacitance. When n is greater than M, the nth capacitor unit is formed by connecting multiple (n-1)th capacitor units in parallel, where M is a natural number greater than or equal to 1 and less than or equal to N. It is important to note that the nth capacitor unit formed by connecting multiple (n-1)th capacitor units in parallel is still considered a single capacitor unit, not multiple capacitor units.

[0051] In one embodiment, each capacitor unit includes multiple capacitor sub-units, each capacitor sub-unit being formed in a metal layer. For example... Figure 1 As shown, each capacitor sub-unit includes a first sub-electrode plate 111, a second sub-electrode plate 121, and a third sub-electrode plate 131. The first sub-electrode plates 111 of different capacitor sub-units in each capacitor unit are interconnected via metal vias 151 to form a first electrode plate 110; the second sub-electrode plates 121 of different capacitor sub-units in each capacitor unit are interconnected via metal vias 151 to form a second electrode plate 120; and the third sub-electrode plates 131 of different capacitor sub-units in each capacitor unit are interconnected via metal vias 151 to form a third electrode plate 130. This increases the capacitance per unit area.

[0052] like Figure 1 As shown, each capacitor unit further includes a shielding layer 160. The shielding layer is formed in a metal layer. The second sub-electrode plates 121 of different capacitor sub-units in each capacitor unit are connected to the first signal connection line 141 via metal vias 152, and the third sub-electrode plates 131 of different capacitor sub-units in each capacitor unit are connected to the second signal connection line 142 via metal vias 152. The first signal connection line 141 and the second signal connection line 142 are formed in a metal layer and / or a polysilicon layer.

[0053] exist Figure 1In the example shown, the capacitor sub-unit comprises two capacitor sub-units, one located in the Xth metal layer and the other located in the (X-1)th metal layer. In other embodiments, three or more capacitor sub-units may be provided. Of course, a single capacitor sub-unit may also be used. Figure 1 In the example shown, the shielding layer 160 is located between the metal layer containing the first and second signal connection lines and the metal layer containing the bottommost capacitor sub-unit. The shielding layer 160 is located in the (X-3)th metal layer, and the first signal connection line 141 and the second signal connection line 142 are located in the first metal layer. That is, the first metal layer is a digital switch signal transmission layer. When the first signal connection line 141 is connected to a logic low level, the second signal connection line 142 is connected to a logic high level; when the first signal connection line 141 is connected to a logic high level, the second signal connection line 142 is connected to a logic low level.

[0054] Preferably, the shielding layers in each capacitor unit of the capacitor array are interconnected to form a larger shielding layer, thereby achieving shielding of digital switching signals and analog voltage signals.

[0055] In one embodiment, there is a spaced metal layer between the metal layer containing the shielding layer 160 and the metal layer containing the bottommost capacitor sub-unit. Figure 1 In the example shown, the X-2 metal layer is a spaced, empty metal layer between the metal layer where the shielding layer 160 is located and the metal layer where the lowest capacitor sub-unit is located. The empty X-2 metal layer can reduce the parasitic effect of the MOM capacitor body structure formed by the higher metal layers on the X-3 metal shielding layer.

[0056] Figure 1 The first electrode plate, which can be referred to as the upper electrode plate of the MOM capacitor, is connected to the analog voltage signal input to the CDAC; the second and third electrode plates, which can be referred to as the lower electrode plates of the MOM capacitor, are used to connect digital switching signals. The presence of the shielding layer 160 isolates the analog voltage signal input to the CDAC connected to the first electrode plate from the digital switching signals connected to the second and third electrode plates, providing good shielding. Furthermore, the first metal layer containing the first signal connection line 141 and the second signal connection line 142 does not occupy additional layout area during placement and routing. Jumpers can also be made using a polysilicon layer without adversely affecting the main structure of the MOM capacitor, offering high flexibility and reducing the matching difficulty of large-scale capacitor array placement and routing.

[0057] According to another aspect of the present invention, a successive approximation analog-to-digital converter (SAR ADC) is provided. Figure 3This is a top view of one embodiment of the successive approximation analog-to-digital converter of the present invention.

[0058] The successive approximation analog-to-digital converter includes: two digital-to-analog converters 310-1 and 310-2; a successive approximation logic unit 320; a comparator 330; and a sampling control switch 340.

[0059] Each digital-to-analog converter (DAC) 310-1 and 310-2 can be a charge redistribution type DAC as described above. The shielding layers 370 of the two DACs are interconnected, and the two DACs are respectively designated as the first DAC 310-1 and the second DAC 310-2. The first and second signal connection lines of each capacitor unit in each DAC 310-1 and 310-2 are labeled 360. Connection lines 350 in each DAC 310-1 and 310-2 are used for time-division multiplexing of the analog voltage signal input to the CDAC and the analog voltage signal after digital-to-analog conversion output from the CDAC.

[0060] like Figure 3 As shown, during the sampling phase, the sampling control switch 340 connects the input first differential analog voltage signal to the first electrode plate of each capacitor unit of the first digital-to-analog converter 310-1 via the connection line 350, and connects the input second differential analog voltage signal to the first electrode plate of each capacitor unit of the second digital-to-analog converter 310-2 via the connection line 350. The successive approximation logic 320 generates digital switching signals for the sampling phase, controlling the second and third electrode plates of each capacitor unit of the first digital-to-analog converter 310-1 to connect to the common-mode voltage signal Vcm, and controlling the second and third electrode plates of each capacitor unit of the second digital-to-analog converter 310-1 to connect to the common-mode voltage signal Vcm.

[0061] During the quantization phase, the sampling control switch 340 disconnects the input first differential analog voltage signal from the first electrode plate of each capacitor unit of the first digital-to-analog converter (DAC) and disconnects the input second differential analog voltage signal from the first electrode plate of each capacitor unit of the second DAC. The successive approximation logic unit 320 generates a digital switching signal for the quantization phase. Based on this digital switching signal, the second electrode plate of at least a portion of the capacitor units in the first DAC 310-1 is connected to either a logic low level or a logic high level, and the third electrode plate is connected to the other of the logic low level or logic high level, via the first signal connection line and the second signal connection line 360. Similarly, based on the digital switching signal generated by the successive approximation logic unit 320, the second electrode plate of at least a portion of the capacitor units in the second DAC 310-2 is connected to either a logic low level or a logic high level, and the third electrode plate is connected to the other of the logic low level or logic high level, via the first signal connection line and the second signal connection line 360. One input terminal of the comparator 330 is connected to the first electrode plate of each capacitor unit of the first digital-to-analog converter, and the other input terminal of the comparator 330 is connected to the first electrode plate of each capacitor unit of the second digital-to-analog converter. The comparator 330 generates a comparison signal and provides it to the successive approximation logic unit 320.

[0062] It should be noted that the specific working principle of the successive approximation analog-to-digital converter is well known to those skilled in the art and is not the focus of this invention, so it will not be described in detail here.

[0063] Typical SAR ADCs using a standard CDAC structure have around 10 bits. When the bit depth increases further, capacitor bridging is used to reduce the number of capacitors, which can further increase the bit depth. However, the resulting parasitic effects and mismatch risks significantly increase placement and routing complexity, even affecting product yield. Due to the use of a novel capacitor unit, the SAR ADC in this invention can increase the bit depth to 14 bits while reducing placement and routing complexity. This structure can form an effective capacitor through the length difference between the two lower plates, overcoming the limitations of minimum process width and achieving extremely low unit capacitance. The metal shielding layer effectively separates analog voltage signals and digital switching signals, achieving excellent shielding and improved placement and routing flexibility.

[0064] One of the advantages, key points, and benefits of this invention is:

[0065] 1) Traditional MOM capacitors are limited by the fact that the metal width cannot be infinitely reduced, resulting in a large layout area and an inability to obtain extremely low unit capacitance values. This invention defines a custom MOM capacitor structure that can obtain the extremely low unit capacitance value required in SAR ADC design, achieving the function of doubling the capacitance value with a smaller layout area.

[0066] 2) Large-scale capacitor arrays, especially those involving both analog and digital signals, experience significant mutual interference between analog and digital signals during digital signal switching and capacitor charging and discharging due to parasitic capacitance between the wiring metals. Therefore, achieving good wiring and shielding is quite difficult. By utilizing a shielding layer structure in the custom MOM capacitor structure of this invention, shielding between analog and digital signals is achieved, thereby making the layout and wiring design of large-scale capacitor arrays more efficient and reliable, and reducing the matching difficulty of layout and wiring of large-scale capacitor arrays.

[0067] It should be noted that any modifications made by those skilled in the art to the specific embodiments of the present invention do not depart from the scope of the claims. Accordingly, the scope of the claims is not limited to the foregoing specific embodiments.

Claims

1. A digital-to-analog converter, characterized in that, It includes: A capacitor array includes multiple capacitor units, each capacitor unit including a first electrode plate, a second electrode plate and a third electrode plate, wherein a first sub-capacitor is formed between the first electrode plate and the second electrode plate, and a second sub-capacitor is formed between the first electrode plate and the third electrode plate, and the capacitance value of the first sub-capacitor and the capacitance value of the second sub-capacitor are different. During the sampling phase, the first electrode plate of each capacitor unit is connected to the input analog voltage signal, and the second and third electrode plates of each capacitor unit are connected to the common-mode voltage signal. During the quantization stage, the second electrode plate of each capacitor unit in at least some of the plurality of capacitor units is connected to one of the logic low level or logic high level, and the third electrode plate is connected to the other of the logic low level or logic high level. The first electrode plate of the capacitor unit is left floating and used to output the analog voltage signal after digital-to-analog conversion.

2. The digital-to-analog converter according to claim 1, characterized in that, The capacitance value of the capacitor unit is determined based on the difference between the capacitance value of the first sub-capacitor and the capacitance value of the second sub-capacitor. The relative area of ​​the second electrode plate and the first electrode plate of each capacitor unit is greater than the relative area of ​​the third electrode plate and the first electrode plate.

3. The digital-to-analog converter according to claim 2, characterized in that, The capacitance value of the 0th capacitor unit among the plurality of capacitor units is the smallest, which is Cr. The capacitance value of the nth capacitor unit among the plurality of capacitor units is 2 times that of Cr. n The multiple, n is the serial number of the capacitor unit, the value of n ranges from 0 to N, N is a natural number greater than or equal to 1, and N+1 is the number of the multiple capacitor units.

4. The digital-to-analog converter according to claim 3, characterized in that, When n is greater than M, the nth capacitor unit is formed by multiple (n-1)th capacitor units connected in parallel, where M is a natural number greater than or equal to 1 and less than or equal to N.

5. The digital-to-analog converter according to claim 3, characterized in that, The second and third electrode plates are strip-shaped. The length of the second electrode plate is greater than the length of the third electrode plate. The difference between the length of the second electrode plate and the length of the third electrode plate of the 0th capacitor unit is 2Δ. The difference between the length of the second electrode plate and the length of the third electrode plate of the nth capacitor unit in the 1-M capacitor unit is 2. n *2Δ, where M is a natural number greater than or equal to 1 and less than or equal to N.

6. The digital-to-analog converter according to claim 5, characterized in that, The first electrode plate is frame-shaped, and the second and third electrode plates are located inside the frame-shaped first electrode plate.

7. The digital-to-analog converter according to claim 1, characterized in that, Each capacitor unit comprises multiple capacitor sub-units, and each capacitor sub-unit is formed in a metal layer. Each capacitor sub-unit includes a first sub-electrode plate, a second sub-electrode plate, and a third sub-electrode plate. The first sub-electrode plates of different capacitor sub-units in each capacitor cell are interconnected by via metal holes to form the first electrode plate. The second sub-electrode plates of different capacitor sub-units in each capacitor cell are interconnected by via metal holes to form the second electrode plate. The third sub-electrode plates of different capacitor sub-units in each capacitor unit are interconnected by via metal to form the third electrode plate.

8. The digital-to-analog converter according to claim 7, characterized in that, Each capacitor cell also includes a shielding layer formed within a metal layer. The second sub-electrode plates of different capacitor sub-units in each capacitor unit are connected to the first signal connection line through via metal holes. The third sub-electrode plate of each capacitor sub-unit in each capacitor unit is connected to the second signal connection line through a via metal hole. The first signal connection line and the second signal connection line are formed in a metal layer and / or a polysilicon layer. The shielding layer is located between the metal layer containing the first and second signal connection lines and the metal layer containing the bottommost capacitor sub-unit. The shielding layers in each capacitor unit are interconnected.

9. The digital-to-analog converter according to claim 8, characterized in that, There is a spaced metal layer between the metal layer containing the shielding layer and the metal layer containing the bottommost capacitor sub-unit.

10. The digital-to-analog converter according to claim 1, characterized in that, The first electrode plates of the plurality of capacitor units are interconnected. During the quantization phase, the second and third electrode plates of each of the unused portions of the capacitor cells remain connected to the common-mode voltage signal.

11. A successive approximation analog-to-digital converter, characterized in that, It includes: Two digital-to-analog converters as described in any one of claims 1-10; Successive approximation of logic units; Comparator; Sampling control switch.

12. The successive approximation analog-to-digital converter according to claim 11, characterized in that, The shielding layers of the two digital-to-analog converters are interconnected. The two digital-to-analog converters are referred to as the first digital-to-analog converter and the second digital-to-analog converter, respectively. During the sampling phase, the sampling control switch connects the input first differential analog voltage signal to the first electrode plate of each capacitor unit of the first digital-to-analog converter and the input second differential analog voltage signal to the first electrode plate of each capacitor unit of the second digital-to-analog converter. The successive approximation logic generates digital switching signals for the sampling phase. Based on the digital switching signals generated by the successive approximation logic unit, the second and third electrode plates of each capacitor unit of the first digital-to-analog converter are connected to the common-mode voltage signal, and the second and third electrode plates of each capacitor unit of the second digital-to-analog converter are connected to the common-mode voltage signal. During the quantization phase, the sampling control switch disconnects the input first differential analog voltage signal from the first electrode plate of each capacitor unit of the first digital-to-analog converter (DAC) and disconnects the input second differential analog voltage signal from the first electrode plate of each capacitor unit of the second DAC. The successive approximation logic unit generates a digital switching signal for the quantization phase. Based on the digital switching signal generated by the successive approximation logic unit, the second electrode plate of each capacitor unit in at least a portion of the capacitor units of the first DAC is connected to either a logic low level or a logic high level, and the third electrode plate is connected to the other of the logic low level or logic high level. Based on the digital switching signal, the second electrode plate of each capacitor unit in at least a portion of the capacitor units of the second DAC is connected to either a logic low level or a logic high level, and the third electrode plate is connected to the other of the logic low level or logic high level. One input terminal of the comparator is connected to the first electrode plate of each capacitor unit of the first DAC, and the other input terminal of the comparator is connected to the first electrode plate of each capacitor unit of the second DAC. The comparator generates a comparison signal and provides it to the successive approximation logic unit.

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