Dual-channel SI detection and hot switching method and system based on shared FFT

Abstract

The invention discloses a dual-channel SI detection and hot switching method and system based on shared FFT (Fast Fourier Transform). According to the method, FFT is only executed once on OFDM symbols in the same transmission mode, frequency domain output is provided for a main path and a detection path to extract subcarriers according to different spectrum configuration parameters at the same time, and the two paths are subjected to parallel decoding and CRC verification through an independent channel estimator and a system information decoder; when the CRC of the main path does not pass and the CRC of the detection path passes, writing spectrum configuration parameters of the detection path into a configuration register of the main path, and only executing directional reset on modules influenced by spectrum configuration changes without resetting an FFT processing unit and a frame synchronization module; and the detection path is closed after the consistency of the spectrum mode indexes is judged and locked through a voting confirmation mechanism, and the receiver is switched to a single-path mode. According to the method, FFT repeated calculation and frame synchronization recapture of traditional trial and error search are avoided, and the frequency spectrum configuration switching time delay is remarkably reduced.

Description

Technical Field

[0001] This invention relates to the field of OFDM digital broadcast receiver technology, and in particular to a dual-channel SI detection and hot-switching method and system based on shared FFT. Background Technology

[0002] The CDR (China Digital Radio) system is a digital audio broadcasting standard (GY / T 268.1-2013) based on OFDM modulation in the FM band. This standard defines six effective spectrum modes (indexed as 1, 2, 9, 10, 22, and 23), divided into two main categories: Class A and Class B. Class A spectrum modes use subcarriers in the DA subband, with active subcarriers concentrated in the central region of the OFDM symbol spectrum. Class B spectrum modes use subcarriers in the DB subband, with active subcarriers distributed on both sides of the spectrum, avoiding the bandwidth occupied by analog FM signals in the middle. The subcarrier index ranges are completely different for the different spectrum categories.

[0003] The standard also defines two configurations for the interleaving number NI=1 and NI=2. NI=2 provides a wider signal bandwidth and utilizes more subcarriers. The combination of spectrum category and NI constitutes the spectrum configuration parameters. The receiver must know the spectrum configuration parameters currently used by the transmitter in order to extract pilot and system information at the correct subcarrier positions.

[0004] According to Section 4.6 of GY / T 268.1-2013, the System Information (SI) has a 48-bit structure, including a 42-bit data payload and a 6-bit CRC-6 checksum, where the generator polynomial of the CRC-6 is G6(x) = x. 6 +x 5 +x³+x²+x+1, the initial register state is all 1s (0x3F). The system information carries key parameters such as the spectrum mode index, and the receiver obtains the current spectrum configuration information by decoding SI.

[0005] The standard also specifies that, under the same transmission mode (transmission modes 1 and 3 use a 2048-point FFT, and transmission mode 2 uses a 1024-point FFT), the number of points N in the FFT is determined solely by the transmission mode and is unaffected by the spectrum class or the number of interleaving points. This means that Class A and Class B spectrum modes use the same size FFT transform under the same transmission mode.

[0006] In existing technologies, when the receiver is unsure of the spectrum configuration parameters currently used by the transmitter, a trial-and-error serial search method is typically employed: SI decoding is initiated by assuming a spectrum class (e.g., Class A); if CRC continues to fail, it switches to another spectrum class (e.g., Class B) and tries again. This method has the following drawbacks:

[0007] First, each spectrum class switch requires re-performing the FFT transformation on the OFDM symbols, and the FFT is one of the most computationally expensive modules in an OFDM receiver, with a computational complexity of O(N log N). In fact, since Class A and Class B use the same size FFT in the same transmission mode, the FFT output can be reused. Trial-and-error serial search leads to unnecessary repeated FFT calculations.

[0008] Second, if the SI decoding failures caused by incorrect assumptions exceed the threshold (such as 20 consecutive CRC failures), the frame synchronization module will be triggered to re-enter the acquisition state, and the entire receiving link will be rebuilt from scratch. After entering the tracking state, it will also need to go through a grace period (such as 40 subframes, i.e. 6.4 seconds) before the normal CRC failure count can be restored. The total delay of spectrum configuration switching can reach several seconds to more than ten seconds.

[0009] Third, during the serial search process, if the current spectrum category is assumed to be correct but encounters short-term channel degradation (such as deep fading) causing the CRC to temporarily fail, improperly switching to another spectrum category will lead to longer periods of incorrect decoding, further exacerbating the reception interruption.

[0010] In existing literature, EP2281377A1 discloses a shared FFT method for processing multiple carriers, but this method is geared towards multi-carrier aggregation scenarios, encompassing the spectra of multiple component carriers in a single large FFT. Its purpose is to reduce the hardware complexity of multi-carrier systems, which differs from the scenario described in this invention where subcarriers are extracted based on different spectrum configurations within a single carrier. Furthermore, it does not involve parallel SI decoding, CRC decision-making, or directional module reset. EP1879344B1 discloses a TPS-based frame synchronization method, employing a sequential sliding window mechanism for serial search, which differs from the dual-path parallel decoding architecture of this invention. US20080225995A1 discloses a DVB-H TPS parameter blind detection method for accelerating service discovery, but it uses a serial trial-and-error parameter search, requiring receiver reconfiguration for each attempt, which differs from the shared FFT parallel detection and directional reset mechanism of this invention. Summary of the Invention

[0011] To address the technical problems of repeated FFT calculations, frame synchronization re-acquisition, and excessively long spectrum configuration switching delays caused by trial-and-error serial search in existing technologies, this invention provides a dual-channel SI detection and hot-switching method and system based on shared FFT.

[0012] The technical solution of the present invention is as follows:

[0013] A dual-channel SI detection and hot-switching method based on shared FFT, applied to a receiver receiving OFDM digital broadcast signals containing multiple possible spectral configurations, includes the following steps:

[0014] S1 Shared FFT and Dual Subcarrier Extraction Steps: After frame synchronization is completed, the FFT processing unit performs an N-point Fast Fourier Transform on the current OFDM symbol and writes the frequency domain data into the FFT output buffer memory; the subcarrier extraction module extracts two sets of subcarrier data from the same set of frequency domain data according to two different spectrum configuration parameters. The N-point FFT is performed only once for different spectrum categories.

[0015] S2 Dual-Path Parallel System Information Decoding Steps: The first channel estimator and the first system information decoder perform channel estimation, equalization, SI decoding, and CRC verification on the first group of subcarrier data; when the main path CRC fails, the probe is active, and the spectrum mode is not locked, the second channel estimator and the second system information decoder perform independent channel estimation, equalization, SI decoding, and CRC verification on the second group of subcarrier data.

[0016] S3 CRC decision and orientation module hot-switching steps: When the probe path CRC passes, the spectrum configuration parameters of the probe path are replaced with the main path configuration, and orientation reset is performed only on the affected processing modules, without resetting the FFT processing unit and frame synchronization module.

[0017] S4 Voting Confirmation and Probe Closure Steps: Perform consistency voting on the spectrum mode index that passes through CRC multiple times consecutively. After reaching the preset number of times, lock the confirmation and close the probe path, switching from dual-path mode to single-path mode.

[0018] The present invention also provides a corresponding OFDM digital broadcast receiver system, including an FFT processing unit, a dual-subcarrier extraction module, a main path processing chain, a probe path processing chain, a CRC check unit, a mode switching controller, a directional reset controller, and a voting confirmation module.

[0019] The beneficial effects of this invention include:

[0020] First, the computational resource reuse effect: Under the same transmission mode, only one FFT transformation is performed for each OFDM symbol, and the subcarrier extraction of the probe path is only an index reading operation of the FFT output buffer. The computational overhead is negligible, which reduces the FFT computation by half compared to trial-and-error serial search.

[0021] Second, the switching latency reduction effect: during hot switching, only the processing modules affected by the spectrum configuration change are reset in a targeted manner. There is no need to re-execute FFT transformation and frame synchronization capture, avoiding the 40 subframe forgiveness period (6.4 seconds) after frame synchronization re-enters the capture state in the traditional scheme. The spectrum configuration switching can be completed within one subframe period (160 milliseconds).

[0022] Third, the effectiveness of protection against false positives: The voting confirmation mechanism requires multiple consecutive CRC checks to pass and the spectrum mode index to be consistent before locking the configuration. The false positive rate of CRC-6 is approximately 2⁻. 6 That is, 1.6%, reducing the probability of three consecutive false positives to approximately 4 × 10⁻ 6 This effectively prevents spectral mode jitter caused by CRC false positives.

[0023] Fourth, adaptive computing power effect: After the spectrum mode is confirmed and locked, the subcarrier extraction, channel estimation and SI decoding of the probe path are turned off, and the receiver is reduced from dual-path mode to single-path mode, eliminating the computing power overhead of continuous probe. Attached Figure Description

[0024] Figure 1 This is a receiver system architecture block diagram provided for an embodiment of the present invention.

[0025] Figure 2 The flowchart of dual-channel SI detection and hot-switching provided in the embodiments of the present invention.

[0026] Figure 3 This is a timing diagram comparing the spectrum configuration switching delay of the traditional solution and the present invention.

[0027] Figure 4 This is a schematic diagram of the directional reset module range provided in an embodiment of the present invention. Detailed Implementation

[0028] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] I. System Architecture

[0030] like Figure 1 As shown, the OFDM digital broadcast receiver provided in this embodiment of the invention includes the following functional modules: an FFT processing unit 101, an FFT output buffer memory 102, a subcarrier extraction module 103, a first channel estimator 104, a second channel estimator 105, a first system information decoder 106, a second system information decoder 107, a CRC check unit 108, a mode switching controller 109, a directional reset controller 110, a voting confirmation module 111, a pilot generator 112, a continuous pilot reference module 113, a service description information processor 114, a signal-to-interference ratio estimator 115, a frame synchronization module 116, and a main path spectrum configuration register 117.

[0031] The FFT processing unit 101 receives OFDM symbols from the time-domain sampling after timing synchronization by the frame synchronization module 116, and performs an N-point Fast Fourier Transform. The value of N is determined by the current transmission mode: N=2048 for transmission modes 1 and 3, and N=1024 for transmission mode 2. The FFT processing unit 101 uses FFTW3 single-precision forward FFT, and the transformed N-point frequency domain data is written to the FFT output buffer memory 102.

[0032] The subcarrier extraction module 103 reads frequency domain data from the FFT output buffer memory 102. In dual-path mode, the subcarrier extraction module 103 extracts subcarriers from the same set of N-point frequency domain data according to two different spectrum configuration parameters. Taking transmission mode 1 as an example, the subcarrier index range for Class A spectrum configuration is negative frequency -497 to -5 and positive frequency 5 to 497. For Class B spectrum configuration, the subcarrier index range is negative frequency -623 to -503 and positive frequency 503 to 623 when NI=1, and negative frequency -623 to -381 and positive frequency 381 to 623 when NI=2. The subcarrier extraction operation only involves reading the index of array elements in the FFT output buffer memory 102 and does not involve any multiplication or addition operations.

[0033] The first channel estimator 104 and the first system information decoder 106 constitute the main path processing chain. The first channel estimator 104 performs LS estimation and IIR time-domain smoothing on the first group of subcarrier data based on the pilot positions determined by the first spectrum configuration parameters, and eliminates common phase errors and sampling frequency offsets through CPE and SFO differential tracking. Finally, it performs frequency-domain linear interpolation and equalization on all active subcarriers. The first system information decoder 106 extracts system information symbols from the equalized subcarrier data according to the SI column positions and performs Viterbi decoding.

[0034] The second channel estimator 105 and the second system information decoder 107 constitute the probe path processing chain. The second channel estimator 105 is an independent instance of the first channel estimator 104, using the pilot position determined by the second spectrum configuration parameters to maintain independent channel frequency response estimates, CPE phase accumulation, and SFO slope. The second system information decoder 107 is also independent of the first system information decoder 106.

[0035] The CRC check unit 108 performs CRC-6 checks on the 48-bit data output by the first system information decoder 106 and the second system information decoder 107 respectively. The specific implementation of the CRC-6 check is as follows: using the generator polynomial G6(x) = x... 6 +x 5+x³+x²+x+1, with an initial register value of 0x3F, calculates the CRC value bit by bit for the first 42 bits of data payload, and compares it with the CRC field received in the last 6 bits. If they match, the verification is considered successful.

[0036] The mode switching controller 109 is the core decision-making unit. During the processing cycle of each subframe, the mode switching controller 109 executes the following decision logic: First, it checks the CRC check result of the main path (first system information decoder 106); if the main path CRC passes and the voting confirmation module 111 has locked the spectrum mode, the probe path is closed; if the main path CRC fails, the probe path is active and the spectrum mode has not been locked, the decoding process of the probe path processing chain is started; if the probe path CRC passes, the second spectrum configuration parameter is written to the main path spectrum configuration register 117, triggering the directional reset controller 110 to perform a directional reset and close the probe path.

[0037] After the mode switching controller 109 completes the spectrum configuration parameter replacement, the directional reset controller 110 sends reset commands to the following affected processing modules: the layout parameters of the subcarrier extraction module 103, the pilot generator 112, the first channel estimator 104, the continuous pilot reference module 113, the first system information decoder 106, the service description information processor 114, and the signal-to-interference ratio estimator 115. The directional reset controller 110 does not send reset commands to the FFT processing unit 101 and the frame synchronization module 116 because the number of points N in the FFT is determined by the transmission mode and is not affected by changes in the spectrum category; similarly, the timing and frequency offset estimation of frame synchronization are independent of the spectrum category.

[0038] The voting confirmation module 111 maintains a candidate spectrum pattern index and a corresponding continuous consistency counter. Whenever a CRC check passes, the voting confirmation module 111 compares the decoded spectrum pattern index with the current candidate value: if they are the same, the counter is incremented; if they are different, the candidate value is replaced with the new value and the counter is reset to 1. When the counter reaches the confirmation threshold L=3, the candidate value is locked as the confirmation value and written to the spectrum pattern confirmation register. This voting mechanism effectively prevents false positives in CRC leading to misjudgments of the spectrum pattern. The single false detection rate of CRC-6 is approximately 1.6%, and the probability of three consecutive false detections is reduced to approximately 4×10⁻⁻⁻⁶. 6 .

[0039] Pilot generator 112 generates discrete pilot sequences based on a linear feedback shift register (LFSR). The polynomial of the LFSR is x¹¹+x. 9 +1, initial register value is 0x052A. Pilot position is related to spectrum type and NI, therefore it needs to be reinitialized when switching spectrum configurations.

[0040] The continuous pilot reference module 113 generates a 108-point reference signal by re-encoding (convolutional coding, interleaving, QPSK mapping) the decoded 48-bit SI, which is used to assist the channel estimator in extracting common phase errors. The SI column positions change with the spectrum category, so they need to be reinitialized when the spectrum configuration is switched.

[0041] II. Dual-channel SI detection and hot-switching process

[0042] like Figure 2 As shown, the workflow of the dual-channel SI detection and hot-switching method in this embodiment of the invention is as follows:

[0043] Step 1: After powering on, the receiver enters the automatic spectrum configuration detection mode. The initially assumed spectrum class (e.g., Class A) is used as the first spectrum configuration parameter for the primary path, and the alternative spectrum class (e.g., Class B) is used as the second spectrum configuration parameter for the detection path. The second channel estimator 105 and the second system information decoder 107 are initialized, and the detection activation flag is set to true.

[0044] Step 2: After the frame synchronization module 116 completes the OFDM symbol timing synchronization, the FFT processing unit 101 performs an N-point FFT transformation on the current OFDM symbol and writes the N-point frequency domain data into the FFT output buffer memory 102.

[0045] Step three: The subcarrier extraction module 103 extracts two sets of subcarrier data from the same set of frequency domain data in the FFT output buffer memory 102, according to the first spectrum configuration parameters and the second spectrum configuration parameters respectively. Specifically, for each OFDM symbol, after the FFT transform is performed once, the first set of subcarrier data is first read from the FFT output buffer memory 102 according to the first subcarrier index range according to the first spectrum configuration parameters and written into the first subcarrier buffer. Then, the second set of subcarrier data is read from the same FFT output buffer memory 102 according to the second subcarrier index range according to the second spectrum configuration parameters and written into the second subcarrier buffer. The data in the FFT output buffer memory 102 is not modified between the two reads.

[0046] Step four: The first channel estimator 104 performs channel estimation and equalization on the first group of subcarrier data. The first system information decoder 106 extracts SI symbols from the equalized subcarrier data. The first system information decoder 106 attempts four rotation phases (0°, 90°, 180°, and 270°) for the SI symbols, performing concatenated processing of QPSK soft demapping to generate log-likelihood ratio (LLR), deinterleaving, Viterbi decoding, and CRC-6 checksum under each rotation phase. When the CRC-6 checksum passes under any rotation phase, the decoding result corresponding to that rotation phase is output as the SI, and the frame synchronization module 116 is notified of CRC success.

[0047] Step 5, the mode switching controller 109 checks the triple gating conditions: (i) the probe activation flag is true; (ii) the first system information decoder 106 in step 4 did not obtain a CRC pass result for any of the four rotating phases; and (iii) the spectrum mode confirmation register in the voting confirmation module 111 has no valid lock value. When all three conditions are met, the mode switching controller 109 starts probe path decoding.

[0048] Step six: The second channel estimator 105 performs independent channel estimation and equalization on the second group of subcarrier data based on the pilot positions determined by the second spectrum configuration parameters. The second system information decoder 107 also attempts four rotating phases for SI decoding and CRC-6 verification.

[0049] Step 7: The CRC check unit 108 determines the CRC result of the probe path. If the probe path CRC passes, proceed to step 8 (hot switching); if the probe path CRC also fails, return to step 2 to process the next subframe.

[0050] Step 8 (hot switching): The mode switching controller 109 writes the second spectrum configuration parameter into the main path spectrum configuration register 117, replacing the first spectrum configuration parameter. The directional reset controller 110 performs a reset on the affected modules in the following order: (1) the subcarrier extraction module 103 updates the subcarrier index range to the range corresponding to the new spectrum category; (2) the pilot generator 112 reinitializes the LFSR pilot sequence and pilot position according to the new spectrum category and NI; (3) the first channel estimator 104 clears the historical IIR smoothing value, CPE accumulation and SFO slope, and reconstructs the channel estimation reference point according to the new pilot position; (4) the continuous pilot reference module 113 clears the current reference signal, marks it as inactive, and regenerates the 108-point reference signal after the new SI CRC passes; (5) the first system information decoder 106 reinitializes according to the SI column position of the new spectrum category, and the voting counter is reset to zero; (6) the service description information processor 114 reinitializes according to the column mapping of the new spectrum category and NI; (7) the signal-to-interference ratio estimator 115 reinitializes the power measurement interval according to the subcarrier range of the new spectrum category and NI. The mode switching controller 109 sets the probe activation flag to false and closes the probe path.

[0051] Step nine: Regardless of whether the main path passes the CRC check automatically or after a hot switch, the voting confirmation module 111 performs a consistency check on the spectrum mode index carried in the SI that has passed the CRC check. Valid spectrum mode indices are 1, 2, 9, 10, 22, and 23. The voting confirmation module 111 maintains candidate spectrum mode indices and a continuous consistency counter: if the new decoded value is the same as the candidate value, the counter is incremented by 1; if they are different, the candidate value is replaced and the counter is reset to 1. When the counter reaches 3, the spectrum mode index is locked as the confirmation value.

[0052] Step 10: After the spectrum mode index is locked and confirmed, if the probe path is still active, the mode switching controller 109 shuts down the extraction of the second group of subcarrier data and the probe path processing chain. The receiver then performs single-path subcarrier extraction for each OFDM symbol only, no longer calling the dual-path demodulation function, thus eliminating the continuous computational overhead of the probe path.

[0053] Step 11: After the spectrum mode index is locked and confirmed, if the number of interleaving NI corresponding to the confirmed spectrum mode is not less than 2, the frequency domain zeroing bandwidth of the FM canceller needs to be reduced to the preset protection bandwidth (e.g., 200kHz) so that the frequency domain zeroing boundary does not exceed the starting subcarrier index corresponding to the second interleaving block, thus avoiding the FM canceller from accidentally deleting valid digital signal subcarriers.

[0054] III. Closed-loop exits automatically confirmed by the main path

[0055] In addition to the aforementioned path that corrects spectrum configuration through hot switching, when the initially assumed spectrum category is correct, the first system information decoder 106 of the main path will pass the CRC check multiple times consecutively. The voting confirmation module 111 locks the confirmation value after three consecutive CRC checks and the spectrum mode index is consistent. At this point, the mode switching controller 109 directly closes the probe path and does not perform the hot switching step. This is another normal exit point for the closed loop.

[0056] IV. CRC consecutive failure fallback protection

[0057] When both the main path and the probe path experience continuous CRC failures (e.g., extremely poor channel conditions), the frame synchronization module 116 counts the number of consecutive CRC failures, with the consecutive failure count based on the CRC check result of the first system information decoder 106. When the number of consecutive failures reaches 20, the frame synchronization module 116 re-enters the acquisition state, and the receiver starts the frame synchronization search from the beginning. The threshold is selected based on the following: each subframe period is 160 milliseconds, and 20 failures correspond to a tolerance window of 3.2 seconds. This duration is sufficient to cover the typical deep fading duration in mobile channels (Rayleigh fading coherence time in urban multipath environments is typically on the order of hundreds of milliseconds), avoiding unnecessary frame synchronization re-acquisition due to short-term channel degradation; at the same time, this threshold is not too large, ensuring that backoff can be triggered within an acceptable time when the spectrum configuration is indeed incorrect. After the frame synchronization module 116 re-enters the tracking state from the acquisition state, the first 40 subframes (6.4 seconds) are a grace period, during which CRC check failures are not counted in the consecutive failure count. The value of the grace period is based on the following: after frame synchronization re-enters the tracking state, the IIR adaptive smoothing filter of the first channel estimator 104 requires several subframes to converge to a steady state. 40 subframes provide sufficient convergence margin for channel estimation, preventing CRC failures before channel estimation stabilizes from being mistakenly counted as spectrum configuration errors. This back-off protection mechanism ensures that the receiver can still recover under extreme channel conditions.

[0058] V. Time Delay Comparison between Traditional Solutions and the Invention

[0059] like Figure 3 As shown, the switching latency of the traditional trial-and-error serial search scheme and the scheme of this invention are compared in the case of spectrum configuration error:

[0060] Traditional approach: The receiver initiates reception assuming a Class A spectrum configuration, with continuous SI CRC failures. After 20 consecutive CRC failures, frame synchronization reacquisition is triggered (20 × 160 ms = 3.2 seconds). Upon re-entering the acquisition state, frame synchronization is searched (approximately 1-2 seconds). After entering the tracking state, a 40-subframe forgiveness period (6.4 seconds) occurs. Assuming Class B, SI decoding restarts, and confirmation is achieved after 3 consecutive successful CRC attempts (0.48 seconds). The total delay is approximately 11-12 seconds.

[0061] The present invention employs a receiver that simultaneously extracts subcarriers and decodes SI in parallel using both Class A and Class B configurations. While the main path (Class A) CRC fails, the probe path (Class B) CRC passes. Hot handover can be triggered within the first subframe period (160 milliseconds). After a directional reset of the seven affected modules, reception resumes with the correct Class B configuration. Confirmation is achieved after three consecutive successful CRC passes (0.48 seconds). The total delay is approximately 0.64 seconds.

[0062] The total latency of spectrum configuration switching in this invention is reduced by approximately 94% compared to traditional solutions.

[0063] VI. Scope of Targeted Reset Modules

[0064] like Figure 4 As shown, the directional reset triggered by hot switching in this invention only covers modules affected by changes in spectrum configuration parameters, specifically including the following 7 modules and their reset reasons:

[0065] (1) Layout parameters of subcarrier extraction module 103: The range of positive and negative frequency subcarrier indexes varies with the spectrum category, and the effective subcarrier distribution areas of Class A and Class B are different.

[0066] (2) Pilot generator 112: The position of the discrete pilot and the length of the LFSR sequence vary with the spectrum category and NI. The pilot sequence length is 62×NI points in transmission mode 1 / 3 and 32×NI points in transmission mode 2.

[0067] (3) First channel estimator 104: The change in pilot position causes the reference point of LS estimation to change. The historical IIR smoothing value, CPE phase accumulation and SFO slope are all related to the old spectrum configuration and need to be cleared.

[0068] (4) Continuous pilot reference module 113: The position of the SI column changes with the spectrum category, and the 108-point reference signal needs to be regenerated under the new configuration. In transmission mode 1 / 3, the SI column positions of Class A are {11,55,75,103} and {144,164,192,228}, while the SI column positions of Class B are different.

[0069] (5) First system information decoder 106: The row and column positions of SI symbols in the subcarrier matrix change with the spectrum category, and the voting counter is reset to zero to avoid error accumulation across configurations.

[0070] (6) Service Description Information Processor 114: The column mapping of SDIS symbols varies with spectrum category and NI.

[0071] (7) Signal-to-interference ratio estimator 115: The subcarrier range for power measurement varies with spectrum category and NI.

[0072] The following modules will not be reset:

[0073] (1) FFT processing unit 101: The number of FFT points N is determined by the transmission mode (transmission mode 1 / 3 uses N=2048, transmission mode 2 uses N=1024). The spectrum category and NI do not change the FFT size, so the FFT plan does not need to be rebuilt and the FFT transformation does not need to be re-executed.

[0074] (2) Frame synchronization module 116: Frame timing and carrier frequency offset estimation do not depend on spectrum category and NI, and spectrum configuration switching does not affect the time domain positioning of OFDM symbols.

[0075] All operations of the directional reset are parameter updates (modifying the subcarrier index range, reinitializing the LFSR register, clearing IIR historical values, etc.), and do not involve the search or iterative convergence process, which can be completed in a single processing cycle.

Claims

1. A dual-channel SI detection and hot-switching method based on shared FFT, applied in a receiver receiving OFDM digital broadcast signals containing multiple possible spectrum configurations, the receiver comprising a frame synchronization module, an FFT processing unit, an FFT output buffer memory, a subcarrier extraction module, a first channel estimator, a second channel estimator, a first system information decoder, a second system information decoder, a CRC check unit, a mode switching controller, a directional reset controller, and a voting confirmation module, characterized in that, Includes the following steps: S1 Shared FFT and Dual Subcarrier Extraction Steps: After the frame synchronization module completes the OFDM symbol timing synchronization, the FFT processing unit performs an N-point fast Fourier transform on the current OFDM symbol and writes the N-point frequency domain data obtained by the transform into the FFT output buffer memory; wherein, the value of N is determined by the current transmission mode. The subcarrier extraction module extracts a first set of subcarrier data from the same set of N-point frequency domain data in the FFT output buffer memory, according to the first subcarrier index range determined by the first spectrum configuration parameters, and writes it into the first subcarrier buffer. Simultaneously, it extracts a second set of subcarrier data from the same set of N-point frequency domain data according to the second subcarrier index range determined by the second spectrum configuration parameters and writes it into the second subcarrier buffer. The first spectrum configuration parameters and the second spectrum configuration parameters correspond to different spectrum categories, and the subcarrier index ranges under different spectrum categories are different. However, the N-point fast Fourier transform is performed only once for different spectrum categories under the same transmission mode. S2 Dual-Path Parallel System Information Decoding Steps: The first channel estimator performs channel estimation and equalization on the first group of subcarrier data based on the pilot symbols in the first subcarrier buffer. The first system information decoder extracts system information symbols from the equalized first group of subcarrier data and performs Viterbi decoding. The CRC check unit performs CRC check on the data bits output by the first system information decoder. The mode switching controller initiates system information decoding of the probe path when the following three conditions are met: (i) the extraction of the second group of subcarrier data is active; (ii) the CRC check of the current subframe of the first system information decoder fails; and (iii) the spectrum mode of the first system information decoder has not been confirmed and locked by voting. The second channel estimator performs independent channel estimation and equalization on the second group of subcarrier data based on the pilot positions in the second subcarrier buffer determined by the second spectrum configuration parameters. The second system information decoder extracts system information symbols from the equalized second group of subcarrier data and performs Viterbi decoding. The CRC check unit performs CRC check on the data bits output by the second system information decoder. S3 CRC Decision and Orientation Module Hot Switching Procedure: When the CRC check of the second system information decoder passes, the mode switching controller writes the second spectrum configuration parameter into the main path spectrum configuration register to replace the first spectrum configuration parameter. The directional reset controller only performs directional reset on processing modules affected by the changes in the spectrum configuration parameters. The directional reset does not include the reset of the FFT processing unit or the frame synchronization module. The reason why the FFT processing unit is not reset is that the number N of the N-point fast Fourier transform is determined by the transmission mode and is not affected by the changes in the spectrum category. S4 Voting Confirmation and Detection Closure Steps: The voting confirmation module performs consistency voting on the spectrum mode index carried by the system information that has passed CRC verification in multiple consecutive subframes. When the decoding results of a preset number of consecutive times all point to the same spectrum mode index, the spectrum mode index is locked as the confirmation value and written into the spectrum mode confirmation register. After the spectrum mode index is locked and confirmed, the mode switching controller shuts down the extraction of the second group of subcarrier data and the processing flow of the second channel estimator and the second system information decoder, and the receiver switches from dual-subcarrier extraction mode to single-subcarrier extraction mode.

2. The method according to claim 1, characterized in that, The processing modules in S3 affected by the changes in the spectrum configuration parameters include: a subcarrier extraction and layout module, a pilot generator, a channel estimator, a continuous pilot reference module, a system information decoder, a service description information processor, and a signal-to-interference ratio estimator.

3. The method according to claim 1, characterized in that, In step S2, the first system information decoder and the second system information decoder each attempt four rotation phases for the system information symbols: 0°, 90°, 180°, and 270°. Under each rotation phase, constellation demapping, deinterleaving, Viterbi decoding, and CRC-6 verification are performed sequentially. When the CRC-6 verification passes under any rotation phase, the decoding result corresponding to that rotation phase is used as the system information output.

4. The method according to claim 1, characterized in that, The specific determination of the three conditions in S2 is as follows: (i) the detection activation flag is true; (ii) the first system information decoder does not obtain the CRC check result for the four rotation phases in the current subframe; (iii) there is no valid lock value in the spectrum mode voting confirmation register.

5. The method according to claim 1, characterized in that, The preset number of times in S4 is 3 times; the specific process of the consensus voting is as follows: maintain a candidate spectrum mode index and a corresponding continuous consensus counter. When the newly decoded spectrum mode index is the same as the current candidate value, increment the counter. When they are different, replace the candidate value with the newly decoded spectrum mode index and reset the counter to 1. When the counter reaches 3, lock the candidate value as the confirmation value.

6. The method according to claim 1, characterized in that, After the spectrum mode index is locked and confirmed in S4, if the number of interleaving NI corresponding to the confirmed spectrum mode is not less than 2, the frequency domain zeroing bandwidth of the FM canceller is reduced to the preset protection bandwidth so that the boundary of the frequency domain zeroing does not exceed the starting subcarrier index corresponding to the second interleaving block.

7. The method according to claim 1, characterized in that, Once the CRC check of the first system information decoder passes and the spectrum mode is confirmed by voting, the mode switching controller directly shuts down the extraction of the second group of subcarrier data and the processing flow of the second channel estimator and the second system information decoder, without executing the hot switching step in S3.

8. The method according to claim 1, characterized in that, When the first system information decoder fails CRC check 20 times consecutively, the frame synchronization module re-enters the capture state; and the first 40 subframes after the frame synchronization module enters the tracking state from the capture state are a grace period, during which CRC check failures are not counted in the consecutive failure count.

9. A dual-channel SI detection and hot-switching system based on shared FFT, characterized in that, include: The frame synchronization module is used to perform symbol timing synchronization on the received OFDM signals; The FFT processing unit is used to perform an N-point fast Fourier transform on the OFDM symbols after the frame synchronization module has completed timing synchronization, and write the N-point frequency domain data into the FFT output buffer memory, wherein the value of N is determined by the current transmission mode. The dual-path subcarrier extraction module is used to extract a first set of subcarrier data and a second set of subcarrier data from the same set of N-point frequency domain data in the FFT output buffer memory, according to two different subcarrier index ranges determined by the first spectrum configuration parameter and the second spectrum configuration parameter, and write them into the corresponding subcarrier buffers respectively; wherein the first spectrum configuration parameter and the second spectrum configuration parameter correspond to different spectrum categories. The first channel estimator and the first system information decoder constitute the main path processing chain, which is used to perform channel estimation, equalization, system information extraction and Viterbi decoding on the first group of subcarrier data. The second channel estimator and the second system information decoder constitute the probe path processing chain, which is used to perform independent channel estimation, equalization, system information extraction and Viterbi decoding on the second group of subcarrier data. The CRC check unit is used to perform CRC checks on the data bits output by the first system information decoder and the second system information decoder, respectively. The mode switching controller is used to start the decoding process of the probe path processing chain when the CRC check of the current subframe of the first system information decoder fails, the extraction of the second group of subcarrier data is active, and the spectrum mode has not been locked, and to write the second spectrum configuration parameter into the main path spectrum configuration register when the CRC check of the second system information decoder passes. A directional reset controller is used to send reset commands only to the processing modules affected by the changes in spectrum configuration parameters after the mode switching controller has completed the replacement of spectrum configuration parameters, and not to send reset commands to the FFT processing unit and the frame synchronization module. The voting confirmation module is used to perform consistency voting on the spectrum mode index carried by the system information that has passed CRC verification in multiple consecutive subframes. When the decoding results of a preset number of consecutive times all point to the same spectrum mode index, it is locked as the confirmation value, and the mode switching controller is triggered to shut down the extraction of the second group of subcarrier data and the detection path processing chain.

10. The system according to claim 9, characterized in that, The system also includes a spectrum configuration register group. After the mode switching controller writes the second spectrum configuration parameters into the spectrum configuration register group, the directional reset controller reads the updated value of the register group and sends a directional reset instruction to the subcarrier extraction layout module, pilot generator, channel estimator, continuous pilot reference module, system information decoder, service description information processor, and signal-to-interference ratio estimator, without sending a reset instruction to the FFT processing unit and frame synchronization module.

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